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lvttl lvcmos-to-differential Datasheet PDF File

For lvttl lvcmos-to-differential Found Datasheets File :: 2000 Search Time::1.36ms
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				Integrated Device Technology, Inc.
Part No.	8N3PGDAMBKI-025LF 8N3PGDAMBKI-025LFT
OCR Text	...ed for normal operation. lvcmos/lvttl interface levels. 2 reserved reserve reserved pin. 3v ee power negative supply pin. 4 nclk input pullup/ pulldown inverting differential clock input. v cc /2 default when left floating 5 clk input pulld...
Description	LOW SKEW CLOCK DRIVER, PBCC10 5 X 7 MM, 1 MM HEIGHT, ROHS COMPLIANT, VFQFN-10
File Size	673.49K / 20 Page	View it Online	Download Datasheet

				MAXIM - Dallas Semiconductor MAXIM[Maxim Integrated Products] Maxim Integrated Products, Inc.
Part No.	MAX9206 MAX9208 MAX9208EAI MAX9206EAI
OCR Text	...16MHz) o 10-Bit Parallel LVCMOS/lvttl Output o Up to 600Mbps Throughput (MAX9208) o Programmable Output Strobe Edge o Pin Compatible to DS92LV1212A and DS92LV1224 General Description The MAX9206/MAX9208 deserializers transform a highspe...
Description	10-Bit Bus LVDS Deserializers
File Size	176.14K / 12 Page	View it Online	Download Datasheet

				ICS
Part No.	M2026
OCR Text	...as well as single-ended LVCMOS, lvttl Loss of Lock (LOL) output pin; Narrow Bandwidth control input (NBW pin) AutoSwitch (AUTO pin) - automatic (non-revertive) reference clock reselection upon clock failure Acknowledge pin (REF_ACK pin) ...
Description	SAW PLL for Frequency Translation with automatic reference clock reselection, Loss of Lock indicator, and Hitless Switching options
File Size	333.73K / 12 Page	View it Online	Download Datasheet

				ON Semiconductor
Part No.	NB7L14MNTXG NB7L14MNG
OCR Text	...as lvpecl, cml, lvds, lvcmos or lvttl logic levels. the v refac reference output can be used to rebias capacitor ? coupled differential or single ? ended input signals. the 1:4 fanout design was optimized for low output skew applications. ...
Description	2.5V / 3.3V 7GHz/10Gbps Differential 1:4 LVPECL Fanout Buffer 2.5V / 3.3V 7GHz/10Gbps Differential 1:4 LVPECL Fanout Buffer
File Size	141.81K / 9 Page	View it Online	Download Datasheet

				NS
Part No.	DS90C385AM
OCR Text	...ter converts 28 bits of LVCMOS/ lvttl data into four LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over the fifth LVDS link. Every cycle of the transmi...
Description	3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display Link-87.5 MHz
File Size	628.65K / 14 Page	View it Online	Download Datasheet

				ON Semiconductor
Part No.	NB7L14
OCR Text	...as lvpecl, cml, lvds, lvcmos or lvttl logic levels. the v refac reference output can be used to rebias capacitor ? coupled differential or single ? ended input signals. the 1:4 fanout design was optimized for low output skew applications. ...
Description	2.5V / 3.3V 7GHz/10Gbps Differential 1:4 LVPECL Fanout Buffer
File Size	170.46K / 9 Page	View it Online	Download Datasheet

				austriamicrosystems AG
Part No.	AS1153-T AS1153V2
OCR Text	... input 5gnd ground 6out2 lvcmos/lvttl receiver output 7out1 lvcmos/lvttl receiver output 8vcc power-supply input. bypass v cc to gnd with 0.1f and 0.001f ceramic capacitors. vcc out1 out2 gnd in1- in1+ in2+ in2- as1153/57 1 2 3 4 8 7 6 5 ...
Description	Dual LVDS Receiver
File Size	400.20K / 16 Page	View it Online	Download Datasheet

				Integrated Circuit Syst... ICST[Integrated Circuit Systems]
Part No.	ICS5310AI31L ICS85310I-31 ICS85310AYI31 ICS85310AYI-31 ICS85310AYI-31LF ICS85310AYI-31LFT ICS85310AYI-31T
OCR Text	...chronizing clock enable. LVCMOS/lvttl interface levels. Inver ting differential clock input. Synchronizing clock enable. LVCMOS/lvttl interface levels. Inver ting differential clock input. Negative supply pin. Output supply pins. Differenti...
Description	LOW SKEW, DUAL, 1-TO-5 2.5V/3.3V DIFFERENTIAL-TO-ECL/LVPECL FANOUT BUFFER
File Size	190.43K / 16 Page	View it Online	Download Datasheet

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