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Cypress
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| Part No. |
CY7C1323BV25-100BZXC
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| OCR Text |
...d C) account for clock skew and flight time mismatching * Separate Port Selects for depth expansion * Synchronous internally self-timed writes * 2.5V core power supply with HSTL Inputs and Outputs * Variable drive HSTL output buffers * Expa... |
| Description |
18-Mbit 4-Word Burst SRAM with DDR-I Architecture
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| File Size |
259.39K /
18 Page |
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it Online |
Download Datasheet
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DATA DEVICE CORP
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| Part No. |
DSC-10510-323Q
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| OCR Text |
...processor based systems such as flight simulators, flight instrumentation, fire control systems, and flight data computers. ? 1986, 1999 data device corporation ddc custom monolithics utilized in this product are copyright under the semico... |
| Description |
DIGITAL TO SYNCHRO OR RESOLVER, DMA40
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| File Size |
200.62K /
14 Page |
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it Online |
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CYPRESS SEMICONDUCTOR CORP
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| Part No. |
CY7C1414JV18-267BZC
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| OCR Text |
...c ) to minimize clock skew and flight time mismatches echo clocks (cq and cq ) simplify data capture in high speed systems single multiplexed address i nput bus latches address inputs for both read and write ports separate port select... |
| Description |
36-Mbit QDR™-II SRAM 2-Word Burst Architecture
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| File Size |
967.62K /
26 Page |
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it Online |
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CYPRESS SEMICONDUCTOR CORP
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| Part No. |
CY7C1418AV18-267BZC
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| OCR Text |
...c ) to minimize clock skew and flight time mismatches echo clocks (cq and cq ) simplify data capture in high speed systems synchronous internally self timed writes 1.8v core power supply with hstl inputs and outputs variable drive hs... |
| Description |
36-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V
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| File Size |
917.70K /
27 Page |
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it Online |
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Cypress Semiconductor, Corp.
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| Part No. |
CY7C1420BV18-250BZC
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| OCR Text |
...c ) to minimize clock skew and flight time mismatches echo clocks (cq and cq ) simplify data capture in high speed systems synchronous internally self-timed writes ddr ii operates with 1.5 cycle read latency when dll is enabled ope... |
| Description |
36-Mbit DDR-II SRAM 2-Word Burst Architecture 1M X 36 DDR SRAM, 0.45 ns, PBGA165
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| File Size |
916.18K /
27 Page |
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it Online |
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