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Arizona Microtek, Inc.
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| Part No. |
AZP94 AZP94NAG AZP94XP
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| OCR Text |
... 5.5v operation ? selectable divide ratio ? selectable enable polarity and threshold (cmos/ttl or pecl) ? tristate compatible outputs ? input buffer powers down when disabled ? selectable input biasing ? high bandwidth f... |
| Description |
ECL/PECL ±1, ±2 Clock Generation Chip with Tristate Compatible Outputs
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| File Size |
140.55K /
8 Page |
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IDT[Integrated Device Technology]
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| Part No. |
IDT5T2110NLI IDT5T2110 IDT5T2110BBI IDT5T2110NLI8 IDT5T2110BBI8
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| OCR Text |
...ace 3-level inputs for feedback divide selection with multiply ratios of(1-6, 8, 10, 12) Selectable HSTL, eHSTL, 1.8V/2.5V LVTTL, or LVEPECL input interface Selectable differential or single-ended inputs and six differential outputs PLL byp... |
| Description |
2.5V ZERO DELAY PLL DIFFERENTIAL CLOCK DRIVER TERACLOCK
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| File Size |
158.62K /
23 Page |
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Download Datasheet |
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IDT[Integrated Device Technology]
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| Part No. |
IDT5T2010NLI IDT5T2010 IDT5T2010BBI IDT5T2010BBI8 IDT5T2010NLI8
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| OCR Text |
...ace 3-level inputs for feedback divide selection with multiply ratios of(1-6, 8, 10, 12) Selectable HSTL, eHSTL, 1.8V/2.5V LVTTL, or LVEPECL input interface Selectable differential or single-ended inputs and ten singleended outputs PLL bypa... |
| Description |
2.5V ZERO DELAY PLL CLOCK DRIVER TERACLOCK
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| File Size |
154.51K /
23 Page |
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it Online |
Download Datasheet |
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IDT[Integrated Device Technology]
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| Part No. |
IDT5V994PFI IDT5V994 IDT5V994JI IDT5V994PFGI IDT5V994PFI8
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| OCR Text |
... 1tU 2tU 3tU 4tU Skew (Pair #3) Divide by 2 -6tU -4tU -2tU Zero Skew 2tU 4tU 6tU Divide by 4 Skew (Pair #4) Divide by 2 -6tU -4tU -2tU Zero Skew 2tU 4tU 6tU Inverted (2)
NOTES: 1. LL disables outputs if TEST = MID and sOE = HIGH. 2. When... |
| Description |
3.3V Programmable Skew PLL Clock Driver TurboClock Plus
3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK-TM PLUS
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| File Size |
65.67K /
9 Page |
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it Online |
Download Datasheet |
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IDT[Integrated Device Technology]
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| Part No. |
IDT5V995PFI IDT5V995 IDT5V995PFGI
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| OCR Text |
...rol 3-level inputs for feedback divide selection multiply / divide ratios of (1-6, 8, 10, 12) / (2, 4) PLL bypass for DC testing External feedback, internal loop filter 12mA balanced drive outputs Low Jitter: <100ps cycle-to-cycle Power-dow... |
| Description |
3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK
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| File Size |
71.68K /
10 Page |
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it Online |
Download Datasheet |
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ICST[Integrated Circuit Systems]
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| Part No. |
ICS8442I ICS8442AYI ICS8442AYILF ICS8442AYILFT ICS8442AYIT
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| OCR Text |
...sitions from LOW-to-HIGH. The M divide and N output divide values are latched on the HIGH-toLOW transition of S_LOAD. If S_LOAD is held HIGH, data at the S_DATA input is passed directly to the M divider and N output divider on each rising e... |
| Description |
From old datasheet system
700MHZ, CRYSTAL OSCILLATOR-TO-DIFFERENTIAL LVDS FREQUENCY SYNTHESIZER
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| File Size |
168.92K /
15 Page |
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it Online |
Download Datasheet |
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