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Part No. |
IBM041841QLAD-6
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OCR Text |
...he sram is in high-z. write and deselect operations will synchronously switch the sram into and out of high-z, therefore, triggering an update. the user may choose to invoke asynchronous g updates by providing a g setup and hold about the k... |
Description |
256K X 18 STANDARD SRAM, 3 ns, PBGA119
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File Size |
171.10K /
23 Page |
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it Online |
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INTEGRATED SILICON SOLUTION INC
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Part No. |
IS61LPS25632T-200TQI
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OCR Text |
... (i/o) auto power-down during deselect single cycle deselect snooze mode for reduced-power standby jtag boundary scan for pbga package t version (three chips selects) d version (two chips selects) j version (pbga package with ... |
Description |
256K X 32 CACHE SRAM, 3.1 ns, PQFP100
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File Size |
176.18K /
29 Page |
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it Online |
Download Datasheet |
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ALLIANCE SEMICONDUCTOR CORP
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Part No. |
AS7C33128NTD36A-100BC AS7C33128NTD36A-166TQC
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OCR Text |
...in pipelined mode, a two-cycle deselect latency allows pending read or write operations to be completed. use the adv/ld (burst advance) input to perform burst read, write, and deselect operations. when adv/ld is high, external addresse... |
Description |
128K X 36 ZBT SRAM, 12 ns, PQFP100 128K X 36 ZBT SRAM, 9 ns, PQFP100
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File Size |
161.04K /
10 Page |
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it Online |
Download Datasheet |
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Price and Availability
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