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				NXP Semiconductors N.V. Philips Semiconductors
Part No.	PDI1394L21BP PDI1394L21BE PDI1394L21
OCR Text	...d control and status registers. Write enable. When asserted (LOW) in conjunction with HIF CS_N, a write to the PDI1394L21 internal registers...through 0. Byte-wide interface to the AV layer 1. External application clock. Rising edge active. Th...
Description	1394 full duplex AV link layer controller 1 CHANNEL(S), 400M bps, SERIAL COMM CONTROLLER, PQFP100
File Size	354.74K / 52 Page	View it Online	Download Datasheet

				Cypress
Part No.	CY7C2263KV18-450BZXI CY7C2263KV18-550BZXI CY7C2265KV18-400BZXI CY7C2265KV18-450BZC CY7C2265KV18-550BZXC
OCR Text	... separate independent read and write data ports ? supports concurrent transactions 550 mhz clock for high bandwidth four-word burst for r...through a common address bus. addresses for read and write addresses are latched on alternate rising...
Description	36-Mbit QDRII SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT
File Size	636.59K / 32 Page	View it Online	Download Datasheet

				Cypress
Part No.	CY7C2245KV18-450BZXI
OCR Text	... separate independent read and write data ports ? supports concurrent transactions 450 mhz clock for high bandwidth four-word burst for r...through a common address bus. addresses for read and write addresses are latched on alternate risin...
Description	36-Mbit QDRII SRAM Four-Word Burst Architecture (2.0 Cycle Read Latency) with ODT
File Size	643.20K / 28 Page	View it Online	Download Datasheet

				Cypress
Part No.	CY7C2163KV18-450BZXI CY7C2163KV18-550BZXI CY7C2165KV18-450BZC CY7C2165KV18-550BZC
OCR Text	... separate independent read and write data ports ? supports concurrent transactions 550-mhz clock for high bandwidth four-word burst for r...through a common address bus. addresses for read and write addresses are latched on alternate rising...
Description	18-Mbit QDRII SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT
File Size	626.68K / 30 Page	View it Online	Download Datasheet

				Cypress
Part No.	CY7C1020CV33-15ZSXE
OCR Text	...by taking chip enable (ce ) and write enable (we ) inputs low. if byte low enable (ble ) is low, then data from i/o pins (i/o 1 through i/o 8 ), is written into the location specified on the address pins (a 0 through a 14 ). if byte high ...
Description	512 K (32 K 16) Static RAM
File Size	400.24K / 16 Page	View it Online	Download Datasheet

				NXP Semiconductors N.V.
Part No.	PDI1394L11 PDI1394L11BA
OCR Text	...ata path to internal registers. Write enable. When asserted (LOW) in conjunction with HIF CS_N, a write to the PDI1394L11 internal registers...through 0. Byte-wide interface to the AV layer. External application clock. Rising edge active. Star...
Description	1394 AV Link Layer Controller(AV锛??棰?瑙??锛???ュ??у??? 1394 AV Link Layer Controller(AV（音视频）链接层控制 1394影音链路层控制器（视听（音频/视频）链接层控制器）
File Size	304.80K / 46 Page	View it Online	Download Datasheet

				NXP Semiconductors
Part No.	PCF85102C-2T PCF85103C-2T PCF85102C-2P PCF85103C-2P
OCR Text	...ansfer Device addressing Remark Write operations Byte/word write Page write Read operations Remark 9 10 11 12 13 14 14.1 14.2 14.2.1 14.2.2 ...Through-hole mount packages Soldering by dipping or by solder wave Manual soldering Surface mount pa...
Description	256 x 8-bit CMOS EEPROMs with I2C-bus interface
File Size	103.54K / 20 Page	View it Online	Download Datasheet

				Vitesse Semiconductor Corporation
Part No.	VSC880TY
OCR Text	...s timed to the wen signal. wen write enable i 62.5mb/s ttl if cen is low, this signal provides a synchronization pulse for loading switch...through parallel interface cdata[7:0]. csel chip select i 62.5mb/s ttl this signal allows several s...
Description	High performance 16x16 serial crosspoint switch. Dual 3.3V/2.5V or 3.3V/2.0V power supply
File Size	376.05K / 28 Page	View it Online	Download Datasheet

				Cypress Semiconductor
Part No.	CY7C1514AV18 CY7C1514AV18-167BZC CY7C1514AV18-167BZI CY7C1514AV18-167BZXC CY7C1514AV18-167BZXI CY7C1514AV18-200BZC CY7C1514AV18-200BZI CY7C1514AV18-200BZXC CY7C1510AV18-167BZC CY7C1510AV18-167BZXC CY7C1510AV18-167BZXI CY7C1510AV18-200BZC CY7C1510AV18-167BZI CY7C1510AV18-200BZI CY7C1510AV18-200BZXC CY7C1510AV18-200BZXI CY7C1525AV18-167BZC
OCR Text	... Separate independent read and write data ports Supports concurrent transactions 250 MHz clock for high bandwidth 2-word burst on all acce...through a common address bus. Addresses for read and write addresses are latched on alternate rising...
Description	72-Mbit QDR?II SRAM 2-Word Burst Architecture 72-Mbit QDR?II SRAM 2-Word Burst Architecture
File Size	414.91K / 28 Page	View it Online	Download Datasheet

For write-through Found Datasheets File :: 23012 Search Time::2.219ms
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