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?2002 integrated device technology, inc. dsc-5647/1 1

true dual-ported memory cells which allow simultaneous access of the same memory location high-speed clock to data access ? commercial: 7.5/9/12ns (max.) ? industrial: 9ns (max.) low-power operation ? idt709369l active: 1.2w (typ.) standby: 2.5mw (typ.) flow-through or pipelined output mode on either port via the ft /pipe pins counter enable and reset features dual chip enables allow for depth expansion without additional logic full synchronous operation on both ports ? 4ns setup to clock and 0ns hold on all control, data, and address inputs ? data input, address, and control registers ? fast 7.5ns clock to data out in the pipelined output mode ? self-timed write allows fast cycle time ? 12ns cycle time, 83mhz operation in pipelined output mode separate upper-byte and lower-byte controls for multiplexed bus and bus matching compatibility ttl- compatible, single 5v (10%) power supply industrial temperature range (?40c to +85c) is available for selected speeds available in a 100-pin thin quad flatpack (tqfp) package high-speed 16k x 18 synchronous pipelined dual-port static ram idt709369l 0a 1a 0b 1b 0/1 ab i/o control 1 0/1 0 ft /pipe r r/ w r ub r lb r ce 0r oe r ce 1r memory array counter/ address reg. 5647 drw 01 a 13r a 0r clk r ads r cnten r cntrst r i/o 9l -i/o 17l i/o 0l -i/o 8l i/o 9r -i/o 17r i/o 0r -i/o 8r a 0l clk l ads l a 13l cnten l cntrst l counter/ address reg. r/ w l ub l lb l ce 0l oe l ce 1l 1 0/1 0 1b 0b 1a 0a 0/1 ba i/o control ft /pipe l preliminary
6.42 idt709369l high-speed 16k x 18 synchronous pipelined dual-port static ram industrial and commercial temperature rang es 2 preliminary index 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 1009998 979695 94 9392 9190 8988 8786 8584 8382 81 8079 7877 76 ft /pipe r oe r r/ w r cntrst r ce 1r ce 0r gnd a 12r a 13r a 11r a 10r a 9r nc i / o 1 0 r i/o 11r i/o 12r i/o 13r i/o 14r i/o 15r gnd ub r lb r 5647 drw 02 i/o 15l ft /pipe l oe l r/ w l cntrst l ce 1l ce 0l vcc a 13l a 12l a 11l a 10l a 9l i/o 10l i/o 11l i/o 12l i/o 13l i/o 14l ub l lb l gnd i / o 5 r i / o 4 r i / o 3 r i / o 2 r i / o 0 r i / o 0 l g n d i / o 2 l i / o 4 l i / o 5 l i / o 6 l i / o 7 l i / o 3 l i / o 1 r i / o 7 r g n d i / o 8 r i / o 9 r i / o 8 l i / o 9 l i / o 6 r a 7 r a 8 l a 7 l a 6 r a 5 r a 4 r a 3 r a 2 r a 1 r a 0 r c l k r c n t e n r c l k l c n t e n l a 0 l a 2 l a 3 l a 5 l a 6 l a 1 l a 4 l a 8r g n d v c c i / o 1 l v c c g n d 709369pf pn100-1 (4) 100-pin tqfp top view (5) nc nc i/o 16r i/o 17r i/o 17l i/o 16l a d s l a d s r . nc 05/13/02 notes: 1. all v cc pins must be connected to power supply. 2. all gnd pins must be connected to ground. 3. package body is approximately 14mm x 14mm x 1.4mm 4. this package code is used to reference the package diagram. 5. this text does not indicate orientation of the actual part-marking.
the idt709369 is a high-speed 16k x 18 bit synchronous dual-port ram. the memory array utilizes dual-port memory cells to allow simultaneous access of any address from both ports. registers on control, data, and address inputs provide minimal setup and hold times. the timing latitude provided by this approach allows systems to be designed with very short cycle times. with an input data register, the idt709369 has been optimized for applications having unidirectional or bidirectional data flow in bursts. an automatic power down feature, controlled by ce 0 and ce 1, permits the on-chip circuitry of each port to enter a very low standby power mode. fabricated using idt?s cmos high-performance technology, these devices typically operate on only 1.2w of power.
6.42 idt709369l high-speed 16k x 18 synchronous pipelined dual-port static ram industrial and commercial temperature r anges 3 preliminary notes: 1. "h" = v ih, "l" = v il, "x" = don't care. 2. ads , cnten , cntrst = x. 3. oe is an asynchronous input signal. !"!#$%&'() '* # oe clk ce 0 ce 1 ub lb r/ w upper byte i/o 9-1 7 lower b yte i/o 0-8 mode x h x x x x high-z high-z deselected ? power down x x l x x x high-z high-z deselected ? power down x l h h h x high-z high-z both bytes deselected x lhlhl data in high-z write to upper byte only x lhhll high-z data in write to lower byte only x lhlll data in data in write to both bytes l lhlhhdata out high-z read upper byte only l lhhlh high-zdata out read lower byte only l lhllhdata out data out read both bytes h x l h l l x high-z high-z outputs disabled 5647 tbl 02 + left port right port names ce 0l , ce 1l ce 0r , ce 1r chip enables (2 ) r/ w l r/ w r read/write enable oe l oe r output enable a 0l - a 13l a 0r - a 13r address i/o 0l - i/o 17l i/o 0r - i/o 17r data input/output clk l clk r clock ub l ub r upper byte select (1 ) lb l lb r lower byte select (1 ) ads l ads r address strobe cnten l cnten r counter enable cntrst l cntrst r counter reset ft /pipe l ft /pipe r flow-through/pipeline v cc power gnd ground 5647 tbl 01 notes: 1. lb and ub are single buffered regardless of state of ft /pipe. 2. ce o and ce 1 are single buffered when ft /pipe = v il , ce o and ce 1 are double buffered when ft /pipe = v ih , i.e. the signals take two cycles to deselect.
6.42 idt709369l high-speed 16k x 18 synchronous pipelined dual-port static ram industrial and commercial temperature rang es 4 preliminary &
'', ! '- ./ &
'', ' notes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. v term must not exceed v cc + 10% for more than 25% of the cycle time or 10ns maximum, and is limited to < 20ma for the period of v term > v cc + 10%. # 0& notes: 1. these parameters are determined by device characterization, but are not production tested. 2. 3dv references the interpolated capacitance when the input and output switch from 0v to 3v or from 3v to 0v. 3. c out also references c i/o .

! 1234156 7 notes: 1. industrial temperature: for specific speeds, packages and powers contact your sales office. 2. this is the parameter t a . this is the "instant on" case temperature. notes: 1. v term must not exceed v cc + 10%. 2. v il > -1.5v for pulse width less than 10ns. grade ambient temperature (2 ) gnd vcc commercial 0 o c to +70 o c0v 5.0v + 10% industrial -40 o c to +85 o c0v 5.0v + 10% 5647 tbl 04 symbol parameter min. typ. max. unit v cc supply voltage 4.5 5.0 5.5 v gnd ground 0 0 0 v v ih inp ut high vo ltage 2.2 ____ 6.0 (1 ) v v il input low voltage -0.5 (2 ) ____ 0.8 v 5647 tbl 05 symbol parameter conditions (2 ) max. unit c in input capacitance v in = 3dv 9 pf c out (3 ) output capacitance v out = 3dv 10 pf 5647 tbl 07 symbol rating commercial & industrial unit v te rm (2) terminal voltage with respect to gnd -0.5 to +7.0 v t bias temperature unde r bias -55 to +125 o c t stg storage temperature -65 to +150 o c i out dc output current 50 ma 5647 tbl 06 notes: 1. "h" = v ih, "l" = v il, "x" = don't care. 2. ce 0 , lb , ub , and oe = v il ; ce 1 and r/ w = v ih . 3. outputs configured in flow-through output mode: if outputs are in pipelined mode the data out will be delayed by one cycle. 4. ads and cntrst are independent of all other signals including ce 0 , ce 1 , ub and lb . 5. the address counter advances if cnten = v il on the rising edge of clk, regardless of all other signals including ce 0 , ce 1 , ub and lb . 6. while an external address is being loaded ( ads = v il ), r/ w = v ih is recommended to ensure data is not written arbitrarily. !"!#$$%'' 8 address previous address addr used clk (6 ) ads cnten cntrst i/o (3 ) mode an x an l (4 ) xhd i/o (n) external address used xanan + 1 h l (5 ) hd i/o (n+1) counter enabled ? internal address generation x an + 1 an + 1 hh hd i/o (n+1) external address blocked ? counter disabled (an + 1 reused) xxa 0 xx l (4 ) d i/o (0) counter reset to address 0 5647 tb l 0 3
6.42 idt709369l high-speed 16k x 18 synchronous pipelined dual-port static ram industrial and commercial temperature r anges 5 preliminary notes: 1. at f = f max , address and control lines (except output enable) are cycling at the maximum frequency clock cycle of 1/t cyc , using "ac test conditions" at input levels of gnd to 3v. 2. f = 0 means no address, clock, or control lines change. applies only to input at cmos level standby. 3. port "a" may be either left or right port. port "b" is the opposite from port "a". 4. vcc = 5v, ta = 25 c for typ, and are not production tested. i cc dc (f=0) = 150ma (typ). 5. ce x = v il means ce 0x = v il and ce 1x = v ih ce x = v ih means ce 0x = v ih or ce 1x = v il ce x < 0.2v means ce 0x < 0.2v and ce 1x > v cc - 0.2v ce x > v cc - 0.2v means ce 0x > v cc - 0.2v or ce 1x < 0.2v "x" represents "l" for left port or "r" for right port. *

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,9", ! '- ./ & / 13/:; *

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,9", ! - ./ & / 135/:; note: 1. at vcc < 2.0v input leakages are undefined. symbol parameter test conditions 709369l unit min. max. |i li | input leakage current (1 ) v cc = 5.5v, v in = 0v to v cc ___ 5a |i lo | output leakage current ce 0 = v ih or ce 1 = v il , v out = 0v to v cc ___ 5a v ol output low voltage i ol = +4ma ___ 0.4 v v oh output high voltage i oh = -4ma 2.4 ___ v 5647 tbl 08 709369l7 com'l only 709369l9 com'l & ind 709369l12 com'l only symbol parameter test condition version typ. (4 ) max. typ. (4 ) max. typ. (4 ) max. unit i cc dynamic op erating current (bo th po rts active) ce l and ce r = v il outputs disabled f = f max (1 ) com'l l 275 465 250 400 230 355 ma ind l ____ ____ 300 430 ____ ____ i sb1 standby current (bo th po rts - ttl le v e l in p u ts ) ce l = ce r = v ih f = f max (1 ) com'l l 95 150 80 135 70 110 ma ind l ____ ____ 95 160 ____ ____ i sb2 standby current (one port - ttl le v e l in p u ts ) ce "a" = v il and ce "b" = v ih (3 ) active port outputs disabled, f=f max (1 ) com'l l 200 295 175 275 150 240 ma ind l ____ ____ 195 295 ____ ____ i sb3 full standby current (bo th po rts - cmos level inputs) both ports ce r and ce l > v cc - 0.2v v in > v cc - 0.2v o r v in < 0.2v, f = 0 (2 ) com'l l 0.5 3 0.5 3.0 0.5 3 ma ind l ____ ____ 0.5 6.0 ____ ____ i sb4 full standby current (one port - cmos level inputs) ce "a" < 0.2v and ce "b" > v cc - 0.2v (5 ) v in > v cc - 0.2v o r v in < 0.2v, active port outputs disabled, f = f max (1 ) com'l l 190 290 170 270 140 225 ma ind l ____ ____ 190 290 ____ ____ 5647 tbl 09
6.42 idt709369l high-speed 16k x 18 synchronous pipelined dual-port static ram industrial and commercial temperature rang es 6 preliminary ! ' figure 1. ac output test load. figure 2. output test load (for t cklz , t ckhz , t olz , and t ohz ). *including scope and jig. figure 3. typical output derating (lumped capacitive load). input pulse levels input rise/fall times input timing reference levels output reference levels output load gnd to 3.0v 3ns max. 1.5v 1.5v figures 1,2 and 3 5647 tbl 10 5647 drw 0 5 893 ? 30pf 347 ? 5v data out 893 ? 5pf* 347 ? 5v data out 5647 drw 04 1 2 3 4 5 6 7 8 20 40 100 60 80 120 140 160 180 200 tcd 1 , tcd 2 (typical, ns) capacitance (pf) 5647 drw 0 6 -1 0 - 10pf is the i/o capacitance of this device, and 30pf is the ac test load capacitance
6.42 idt709369l high-speed 16k x 18 synchronous pipelined dual-port static ram industrial and commercial temperature r anges 7 preliminary notes: 1. transition is measured 0mv from low or high-impedance voltage with the output test load (figure 2). this parameter is guarant eed by device characteriza- tion, but is not production tested. 2. the pipelined output parameters (t cyc2 , t cd2 ) to either the left or right ports when ft /pipe = v ih . flow-through parameters (t cyc1 , t cd1 ) apply when ft /pipe = v il for that port . 3. all input signals are synchronous with respect to the clock except for the asynchronous output enable ( oe ), ft /pipe r and ft /pipe l. *

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! / 13/:;!14 2<4 709369l7 com'l only 709369l9 com'l & ind 709369l12 com'l only symbol parameter min. max. min. max. min. max. unit t cyc1 clock cycle time (flow-through) (2 ) 22 ____ 25 ____ 30 ____ ns t cyc2 clock cycle time (pipelined) (2 ) 12 ____ 15 ____ 20 ____ ns t ch1 clock high time (flow-through) (2 ) 7.5 ____ 12 ____ 12 ____ ns t cl 1 clock low time (flow-through) (2 ) 7.5 ____ 12 ____ 12 ____ ns t ch2 clock high time (pipelined) (2 ) 5 ____ 6 ____ 8 ____ ns t cl 2 clock low time (pipelined) (2 ) 5 ____ 6 ____ 8 ____ ns t r clock rise time ____ 3 ____ 3 ____ 3ns t f clock fall time ____ 3 ____ 3 ____ 3ns t sa address setup time 4 ____ 4 ____ 4 ____ ns t ha address hold time 0 ____ 1 ____ 1 ____ ns t sc chip enable setup time 4 ____ 4 ____ 4 ____ ns t hc chip enable hold time 0 ____ 1 ____ 1 ____ ns t sb byte enable setup time 4 ____ 4 ____ 4 ____ ns t hb byte enable hold time 0 ____ 1 ____ 1 ____ ns t sw r/ w setup time 4 ____ 4 ____ 4 ____ ns t hw r/ w hold time 0 ____ 1 ____ 1 ____ ns t sd inp ut data s e tup tim e 4 ____ 4 ____ 4 ____ ns t hd inp ut data ho ld tim e 0 ____ 1 ____ 1 ____ ns t sad ads setup time 4 ____ 4 ____ 4 ____ ns t ha d ads hold time 0 ____ 1 ____ 1 ____ ns t scn cnten setup time 4 ____ 4 ____ 4 ____ ns t hcn cnten hold time 0 ____ 1 ____ 1 ____ ns t srst cntrst setup time 4 ____ 4 ____ 4 ____ ns t hrst cntrst hold time 0 ____ 1 ____ 1 ____ ns t oe o utp ut e nab le to data valid ____ 9 ____ 12 ____ 12 ns t olz o utp ut e nab le to o utp ut lo w-z (1 ) 2 ____ 2 ____ 2 ____ ns t ohz o utp ut e nab le to o utp ut hig h-z (1 ) 17 17 17ns t cd1 clock to data valid (flow-through) (2 ) ____ 18 ____ 20 ____ 25 ns t cd2 clock to data valid (pipelined) (2 ) ____ 7.5 ____ 9 ____ 12 ns t dc data output hold after clock high 2 ____ 2 ____ 2 ____ ns t ckhz clock high to output high-z (1 ) 292929ns t cklz clo c k hig h to o utp ut lo w-z (1 ) 2 ____ 2 ____ 2 ____ ns port-to-port delay t cwdd write port clock high to read data delay ____ 28 ____ 35 ____ 40 ns t ccs clock-to-clock setup time ____ 10 ____ 15 ____ 15 ns 5647 tbl 11
6.42 idt709369l high-speed 16k x 18 synchronous pipelined dual-port static ram industrial and commercial temperature rang es 8 preliminary ! )9 &'.
=>!" ", ft ($* ?@? 1/ $a < ! )9 &'.
', ft ($* ?@? 1/ $6 < notes: 1. transition is measured 0mv from low or high-impedance voltage with the output test load (figure 2). 2. oe is asynchronously controlled; all other inputs are synchronous to the rising clock edge. 3. ads = v il , cnten and cntrst = v ih . 4. the output is disabled (high-impedance state) by ce 0 = v ih , ce 1 = v il , ub = v ih , or lb = v ih following the next rising edge of the clock. refer to truth table 1. 5. addresses do not have to be accessed sequentially since ads = v il constantly loads the address on the rising edge of the clk; numbers are for reference use only. 6. if ub or lb was high, then the upper byte and/or lower byte of data out for qn + 2 would be disabled (high-impedance state). 7. "x" here denotes left or right port. the diagram is with respect to that port. an an + 1 an + 2 an + 3 t cyc1 t ch1 t cl1 r/ w address data out ce 0 clk oe t sc t hc t cd1 t cklz qn qn + 1 qn + 2 t ohz t olz t oe t ckhz 5647 drw 07 (1) (1) (1) (1) (2) ce 1 ub , lb t sb t hb t sw t hw t sa t ha t dc t dc (5) t sc t hc t sb t hb an an + 1 an + 2 an + 3 t cyc2 t ch2 t cl2 r/ w address ce 0 clk ce 1 ub , lb (4) data out oe t cd2 t cklz qn qn + 1 qn + 2 t ohz t olz t oe 5647 drw 08 (1) (1) (1) (2) t sc t hc t sb t hb t sw t hw t sa t ha t dc t sc t hc t sb t hb (5) (1 latency) (6) (6)
6.42 idt709369l high-speed 16k x 18 synchronous pipelined dual-port static ram industrial and commercial temperature r anges 9 preliminary ! )9 )=" > > =>!" "&' b3< notes: 1. b1 represents bank #1; b2 represents bank #2. each bank consists of one idt709369 for this waveform, and are setup for depth expansion in this example. address (b1) = address (b2) in this situation. 2. ub , lb , oe , and ads = v il ; ce 1(b1) , ce 1(b2) , r/ w , cnten , and cntrst = v ih . 3. transition is measured 0mv from low or high-impedance voltage with the output test load (figure 2). 4. ce 0 , ub , lb , and ads = v il ; ce 1 , cnten , and cntrst = v ih . 5. oe = v il for the right port, which is being read from. oe = v ih for the left port, which is being written to. 6. if t ccs < maximum specified, then data from right port read is not valid until the maximum specified for t cwdd . if t ccs > maximum specified, then data from right port read is not valid until t ccs + t cd1 . t cwdd does not apply in this case. 7. all timing is the same for both left and right ports. port "a" may be either left or right port. port "b" is the opposite fro m port "a". ! )9 -
'&' t sc t hc ce 0(b1) address (b1) a 0 a 1 a 2 a 3 a 4 a 5 t sa t ha clk 5647 drw 09 q 0 q 1 q 3 data out(b1) t ch2 t cl2 t cyc2 (3) address (b2) a 0 a 1 a 2 a 3 a 4 a 5 t sa t ha ce 0(b2) data out(b2) q 2 q 4 t cd2 t cd2 t ckhz t cd2 t cklz t dc t ckhz t cd2 t cklz (3) (3) t sc t hc (3) t ckhz (3) t cklz (3) t cd2 a 6 a 6 t dc t sc t hc t sc t hc data in "a" clk "b" r/ w "b" address "a" r/ w "a" clk "a" address "b" no match match no match match valid t cwdd t cd1 t dc data out "b" 5647 drw 10 valid valid t sw t hw t sa t ha t sd t hd t hw t cd1 t ccs t dc t sa t sw t ha (6) (6)
6.42 idt709369l high-speed 16k x 18 synchronous pipelined dual-port static ram industrial and commercial temperature rang es 10 preliminary ! )9 '&'> >)> >&' oe 1/ $a ! )9 '&'> >)> >&' oe ' notes: 1. transition is measured 0mv from low or high-impedance voltage with the output test load (figure 2). 2. output state (high, low, or high-impedance) is determined by the previous cycle control signals. 3. ce 0 , ub , lb , and ads = v il ; ce 1 , cnten , and cntrst = v ih . "nop" is "no operation". 4. addresses do not have to be accessed sequentially since ads = v il constantly loads the address on the rising edge of the clk; numbers are for reference use only. 5. "nop" is "no operation." data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity. r/ w address an an +1 an + 2 an + 2 an + 3 an + 4 data in dn + 2 ce 0 clk 5647 drw 11 qn qn + 3 data out ce 1 ub , lb t cd2 t ckhz t cklz t cd2 t sc t hc t sb t hb t sw t hw t sa t ha t ch2 t cl2 t cyc2 read nop read t sd t hd (4) (2) (1) (1) t sw t hw write (5) r/ w address an an +1 an + 2 an + 3 an + 4 an + 5 data in dn + 3 dn + 2 ce 0 clk 5647 drw 12 data out qn qn + 4 ce 1 ub , lb oe t ch2 t cl2 t cyc2 t cklz (1) t cd2 t ohz (1) t cd2 t sd t hd read write read t sc t hc t sb t hb t sw t hw t sa t ha (4) (2) t sw t hw
6.42 idt709369l high-speed 16k x 18 synchronous pipelined dual-port static ram industrial and commercial temperature r anges 11 preliminary ! )9 =>!" "&'> >)> >&' oe 1/ $a ! )9 =>!" "&'> >)> >&' oe ' notes: 1. transition is measured 0mv from low or high-impedance voltage with the output test load (figure 2). 2. output state (high, low, or high-impedance is determined by the previous cycle control signals. 3. ce 0 , ub , lb , and ads = v il ; ce 1 , cnten , and cntrst = v ih . "nop" is "no operation". 4. addresses do not have to be accessed sequentially since ads = v il constantly loads the address on the rising edge of the clk; numbers are for reference use only. 5. "nop" is "no operation." data in memory at the selected address may be corrupted and should be re-written to guarantee data i ntegrity. r/ w address an an +1 an + 2 an + 2 an + 3 an + 4 data in dn + 2 ce 0 clk 5647 drw 13 qn data out ce 1 ub , lb t cd1 qn + 1 t ch1 t cl1 t cyc1 t sd t hd t cd1 t cd1 t dc t ckhz qn + 3 t cd1 t dc t sc t hc t sb t hb t sw t hw t sa t ha read nop read t cklz (4) (2) (1) (1) t sw t hw write (5) r/ w address an an +1 an + 2 an + 3 an + 4 an + 5 (4) data in dn + 2 ce 0 clk 5647 drw 14 qn data out ce 1 ub , lb t cd1 t ch1 t cl1 t cyc1 t sd t hd t cd1 t dc qn + 4 t cd1 t dc t sc t hc t sb t hb t sw t hw t sa t ha read write read t cklz (2) dn + 3 t ohz (1) (1) t sw t hw oe t oe
6.42 idt709369l high-speed 16k x 18 synchronous pipelined dual-port static ram industrial and commercial temperature rang es 12 preliminary ! )9 '&'="'' '9
! )9 =>!" "&'="'' '9
notes: 1. ce 0 , oe , ub , and lb = v il ; ce 1 , r/ w , and cntrst = v ih . 2. if there is no address change via ads = v il (loading a new address) or cnten = v il (advancing the address), i.e. ads = v ih and cnten = v ih , then the data output remains constant for subsequent clocks. address an clk data out qx - 1 (2) qx qn qn + 2 (2) qn + 3 ads cnten t cyc2 t ch2 t cl2 5647 drw 15 t sa t ha t sad t had t cd2 t dc read external address read with counter counter hold t sad t had t scn t hcn read with counter qn + 1 address an clk data out qx (2) qn qn + 1 qn + 2 qn + 3 (2) qn + 4 ads cnten t cyc1 t ch1 t cl1 5647 drw 16 t sa t ha t sad t had read external address read with counter counter hold t cd1 t dc t sad t had t scn t hcn read with counter
6.42 idt709369l high-speed 16k x 18 synchronous pipelined dual-port static ram industrial and commercial temperature r anges 13 preliminary ! )9 )="'' '9
=>!" " ', ! )9 & ', notes: 1. ce 0 , ub , lb , and r/ w = v il ; ce 1 and cntrst = v ih . 2. ce 0 , ub , lb = v il ; ce 1 = v ih . 3. the "internal address" is equal to the "external address" when ads = v il and equals the counter output when ads = v ih . 4. addresses do not have to be accessed sequentially since ads = v il constantly loads the address on the rising edge of the clk; numbers are for reference use only. 5. output state (high, low, or high-impedance) is determined by the previous cycle control signals. 6. no dead cycle exists during counter reset. a read or write cycle may be coincidental with the counter reset cycle. 7. cnten = v il advances internal address from ? an ? to ? an +1 ? . the transition shown indicates the time required for the counter to advance. the ? an +1 ? address is written to during this cycle. address an clk data in dn dn + 1 dn + 1 dn + 2 ads cnten t ch2 t cl2 t cyc2 5647 drw 17 internal (3) address an (7) an + 1 an + 2 an + 3 an + 4 dn + 3 dn + 4 t sa t ha t sad t had write counter hold write with counter write external address write with counter t sd t hd address an d 0 t ch2 t cl2 t cyc2 q 0 q 1 0 clk data in r/ w cntrst 5647 drw 18 internal (3) address ads cnten t srst t hrst t sd t hd t sw t hw counter reset write address 0 read address 0 read address 1 read address n qn an + 1 an + 2 read address n+1 data out t sa t ha 1 an an + 1 (5) (6) ax (4) (6) .
6.42 idt709369l high-speed 16k x 18 synchronous pipelined dual-port static ram industrial and commercial temperature rang es 14 preliminary 5647 drw 19 idt709369 ce 0 ce 1 ce 1 ce 0 ce 0 ce 1 a 14 ce 1 ce 0 v cc v cc idt709369 idt709369 idt709369 control inputs control inputs control inputs control inputs cntrst clk ads cnten r/ w lb , ub oe

the idt709369 provides a true synchronous dual-port static ram interface. registered inputs provide minimal set-up and hold times on address, data, and all critical control inputs. all internal registers are clocked on the rising edge of the clock signal, however, the self-timed internal write pulse is independent of the low to high transition of the clock signal. an asynchronous output enable is provided to ease asynchronous bus interfacing. counter enable inputs are also provided to stall the operation of the address counters for fast interleaved memory appli- cations. ce 0 = v ih or ce 1 = v il for one clock cycle will power down the internal circuitry to reduce static power consumption. multiple chip enables allow easier banking of multiple idt709369's for depth expansion configurations. when the pipelined output mode is enabled, two cycles are required with ce 0 = v il and ce 1 = v ih to re-activate the outputs. " ')'"*0 the idt709369 features dual chip enables (refer to truth table i) in order to facilitate rapid and simple depth expansion with no requirements for external logic. figure 4 illustrates how to control the various chip enables in order to expand two devices in depth. the idt709369 can also be used in applications requiring expanded width, as indicated in figure 4. since the banks are allocated at the discretion of the user, the external controller can be set up to drive the input signals for the various devices as required to allow for 36-bit or wider applications. figure 4. depth and width expansion with idt709369
6.42 idt709369l high-speed 16k x 18 synchronous pipelined dual-port static ram industrial and commercial temperature r anges 15 preliminary ,' $ note: 1. contact your local sales office for industrial temp range for other speeds, packages and powers. a power 99 speed a package a process/ temperature range blank i (1) commercial (0 cto+70 c) industrial (-40 cto+85 c) pf 100-pin tqfp (pn100-1) 7 9 12 xxxxx device type idt speed in nanoseconds 5647 drw 20 l low power 709369 288k (16k x 18-bit) synchronous dual-port ram commercial only commercial & industrial commercial only "
6 . 5/13/02: initial public release corporate headquarters for sales: for tech support: 2975 stender way 800-345-7015 or 408-727-611 6 831-754-4613 santa clara, ca 95054 fax: 408-492-8674 dualporthelp@idt.com www.idt.com the idt logo is a registered trademark of integrated device technology, inc. ."c definition "preliminary" datasheets contain descriptions for products that are in early release.

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