ESD5342N will semiconductor ltd. 1 revision 1. 4 , 201 7 /0 7 / 2 4 esd 53 4 2 n 2 - line s , un i - d irectional, l ow capacitance trans ient voltage suppressor descriptions the ESD5342N is a low capacitance tvs (tran sient voltage suppressor) designed to protect high speed data interfaces. it has been specifically designed to protec t sensitive electronic components which are connected to data and transmission lines from over - stress caused by esd (e lectro s tatic d ischarge ). the ESD5342N incorporates two pairs of low capacitance steering diodes plus a tvs diode. the ESD5342N may be use d to provide esd protection up to 2 0 k v (contact discharge ) according to iec61000 - 4 - 2 , and withstand peak pulse current up to 4 a ( 8/20 s ) according to iec61000 - 4 - 5. the esd53 42n is available in dfn1006 - 3 l package. standard products are pb - free and halogen - free. features ? stand - off voltage: 5v max. ? transient protection for each line according to iec61000 - 4 - 2 (esd): 20kv ( contact discharge) iec61000 - 4 - 4 (eft): 40a (5/50ns ) iec61000 - 4 - 5 (surge): 4 a (8/20 s) ? l ow capacitance: c j = 1.0 pf typ. ? ultra - low leakage current: i r <1na typ. ? l ow clamping voltage: v cl = 17.5 v @ i pp = 16a (tlp) ? solid - state silico n technology applications ? usb interface ? hdmi interface ? dvi ? portable electronics ? notebooks h ttp // : www. sh - willsemi.com dfn1006 - 3 l (bottom v iew) circuit d iagram 3 = device code * = month code ( a~z) marking (top view) order i nformation device package shipping ESD5342N - 3/tr dfn1006 - 3 l 10 000/tape&reel 2 1 3 1 3 2 3 * .
ESD5342N will semiconductor ltd. 2 revision 1. 4 , 201 7 /0 7 / 2 4 absolute m aximum r ating s electrical characteristics ( t a = 25 o c, unless otherwise noted ) notes: 1) tlp parameter: z 0 = 50 , t p = 100ns, t r = 2n s, averaging window from 60ns to 80ns. r dyn is calculated from 4a to 16a. 2) non - repetitive current pulse, according to iec61000 - 4 - 5. parameter symbol rating unit peak pulse power ( t p = 8/20 s) p pk 60 w peak pulse current (t p = 8/20 s) i pp 4 a esd according to iec61000 - 4 - 2 air discharge v esd 2 0 kv esd according to iec61000 - 4 - 2 contact discharge 2 0 j unction t emperature t j 1 25 o c operating temperature t op - 40 ~ 85 o c lead temperature t l 260 o c storage temperature t stg - 55~150 o c parameter symbol condition min. typ. max. unit rever se maximum working voltage v rwm 5.0 v reverse leakag e current i r v rwm = 5v <1 100 n a reverse breakdown voltage v br i t = 1ma 7.0 8.0 9.0 v forward voltage v f i t = 1 0ma 0.6 0.9 1.2 v clamping voltage 1) v cl i pp = 16a, t p = 100ns 1 7.5 v dynamic resistance 1) r dyn 0. 5 5 clamping voltage 2 ) v cl i pp = 1a, t p = 8/20s 1 1 v i pp = 4 a, t p = 8/20s 1 5 v junction capacitance c j v r = 0v, f = 1mhz pin1 or 2 to pin3 1.0 1.4 pf v r = 0v, f = 1mhz between pin1 and pin2 0.5 0.7 pf
ESD5342N will semiconductor ltd. 3 revision 1. 4 , 201 7 /0 7 / 2 4 typical characteristics ( t a = 25 o c, unless otherwise noted ) 8/20 s w aveform per iec61000 - 4 - 5 clamping voltage vs. peak pulse current non - repetitive peak pulse p ower vs. pulse time contact discharge current waveform per iec61000 - 4 - 2 capacitance vs. rever se voltage power derating vs. ambient t emperature 0 1 2 3 4 5 0.4 0.6 0.8 1.0 1.2 between pin1 and pin2 pin1 or 2 to pin3 f = 1mhz c j - junction capacitance (uniformization) v r - reverse voltage (v) 1 10 100 1000 1 10 100 1000 peak pulse power (w) pulse time ( ? s) 0 25 50 75 100 125 150 0 20 40 60 80 100 % of rated power t a - ambient temperature ( o c) 0 1 2 3 4 5 8 10 12 14 pulse waveform: t p = 8/20 ? s v c - clamping voltage (v) i pp - peak pulse current (a) t 60ns 30ns t r = 0.7~1ns 10 90 100 current (%) time (ns) 0 0 100 20 90 50 10 t 2 t 1 front time: t 1 = 1.25 ? ? t = 8 ? s time to half-value: t 2 = 20 ? s peak pulse current (%) time ( ? s) t
ESD5342N will semiconductor ltd. 4 revision 1. 4 , 201 7 /0 7 / 2 4 typical characteristics ( t a = 25 o c, unless otherwise noted ) esd clamping ( +8kv contact discharge per iec61000 - 4 - 2) tlp measurement esd c lamping ( - 8kv contact discharge per iec61000 - 4 - 2 ) 0 2 4 6 8 10 12 14 16 18 20 22 -2 0 2 4 6 8 10 12 14 16 18 20 z 0 = 50 ? t r = 2ns t p = 100ns tlp current (a) tlp voltage (v)
ESD5342N will semiconductor ltd. 5 revision 1. 4 , 201 7 /0 7 / 2 4 application information the esd534 2n is designed to protect two high speed lines against esd. fig1 is shown the connection and fig2 is shown pcb layout guide for usb interface esd protection fig1 fig2 v b u s d m d p i d g n d v b u s d m d p i d g n d
ESD5342N will semiconductor ltd. 6 revision 1.4, 2017/07/24 package outline dimensions dfn1006-3l e2 e1 l l e d b2 b1 top view bottom view side view a1 a l1 ( ) ( ) ( ) ( ) recommend pcb layout (unit: mm) symbol dimensions in millimeters min. typ. max. a 0.36 - 0.50 a1 0.00 - 0.05 d 0.95 1.00 1.05 e 0.55 0.60 0.65 b1 0.10 0.15 0.20 b2 0.40 0.50 0.60 l 0.20 0.25 0.30 l1 0.20 0.30 0.40 e1 0.35 bsc e2 0.65 bsc notes: this recommended land pattern is for reference purposes only. please consult your manufacturing group to ensure your pcb design guidelines are met. 0.45 0.45 0.20 0.25 0.25 0.70
ESD5342N will semiconductor ltd. 7 revision 1.4, 2017/07/24 tape and reel information reel dimensions tape dimensions w p1 quadrant assignments for pin1 orientation in tape q1 q2 q4 q3 q1 q2 q4 q3 rd reel dimension w overall width of the carrier tape 1 p1 pitch between successive cavity centers pin1 pin1 quadrant rd 7inch 13inch 2mm 4mm 8mm q1 q2 q3 q4 8mm 12mm 16mm
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