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data sheet low skew, 1-to-10 differential-to-3.3v, 2.5v lvpecl/ecl fanout buffer 85310i-11 85310i-11 rev f 7/8/15 1 ?2015 integrated device technology, inc. clk0 nclk0 q0nq0 q1 nq1 q2 nq2 q3 nq3 q4 nq4 q5 nq5 q6 nq6 q7nq7 q8nq8 q9nq9 0 1 clk1 nclk1 clk_sel clk_en pulldown pullup pulldown pulldown pulluppullup d le q general description the 85310i-11 is a low skew, high performance 1-to-10 differential-to-2.5v/3.3v ecl/l vpecl fanout buffer. the clkx, nclkx pairs can accept most standar d differential input levels. the 85310i-11 is characterized to operate from either a 2.5v or a 3.3v power supply. guaranteed output and part-to-part skew characteristics make the 85310i-11 ideal for those clock distribution applications demanding well defined performance and repeatability. features ten differential 2.5v, 3.3v lvpecl/ecl output pair two selectable differential input pairs differential clkx, nclkx pairs can accept the following interface levels: lvpecl, lvds, lvhstl, sstl, hcsl maximum output frequency: 700mhz translates any single ended input signal to 3.3v lvpecl levels with resistor bias on nclk input output skew: 30ps (typical) part-to-part skew: 140ps (typical) propagation delay: 2ns (typical) additive phase jitter, rms: <0.13ps (typical) lvpecl mode operating voltage supply range: v cc = 2.375v to 3.8v, v ee = 0v ecl mode operating voltage supply range: v cc = 0v, v ee = -3.8v to -2.375v -40c to 85c ambient operating temperature available in lead-free rohs compliant package pin assignment 85310i-11 32-lead lqfp 7mm x 7mm x 1.4mm package body y package top view block diagram 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 12 3 4 56 7 8 2423 22 21 2019 18 17 v cc clk_sel clk0 nclk0 clk_en clk1 nclk1 v ee q3 nq3 q4 nq4 q5nq5 q6 nq6 v cco nq9 q9 nq8 q8 nq7 q7 v cco q0 nq0 q1nq1 q2 nq2 v cco v cco
low skew, 1-to-10 differential-to-3.3v, 2.5v lvpecl/ecl fanout buffer 2 rev f 7/8/15 85310i-11 data sheet table 1. pin descriptions note: pullup and pulldown refer to internal input resistors. see table 2, pin characteristics, for typical values. table 2. pin characteristics number name type description 1v cc power positive supply pin. 2 clk_sel input pulldown clock select input. when high, selects clk1, nclk1 inputs. when low, selects clk0, nclk0 inputs. lvcmos / lvttl interface levels. 3 clk0 input pulldown non-inverting differential clock input. 4 nclk0 input pullup inverting differential clock input. 5 clk_en input pullup synchronizing clock enable. when high, clock outputs follow clock input. when low, q outputs are forced low, nq outputs are forced high. lvcmos / lvttl interface levels. 6 clk1 input pulldown non-inverting differential clock input. 7 nclk1 input pullup inverting differential clock input. 8v ee power negative supply pin. 9, 16, 25, 32 v cco power output supply pins. 10, 11 nq9, q9 output diff erential output pair. lvpecl interface levels. 12, 13 nq8, q8 output diff erential output pair. lvpecl interface levels. 14, 15 nq7, q7 output diff erential output pair. lvpecl interface levels. 17, 18 nq6, q6 output diff erential output pair. lvpecl interface levels. 19, 20 nq5, q5 output diff erential output pair. lvpecl interface levels. 21, 22 nq4, q4 output diff erential output pair. lvpecl interface levels. 23, 24 nq3, q3 output diff erential output pair. lvpecl interface levels. 26, 27 nq2, q2 output diff erential output pair. lvpecl interface levels. 28, 29 nq1, q1 output diff erential output pair. lvpecl interface levels. 30, 31 nq0, q0 output diff erential output pair. lvpecl interface levels. symbol parameter test conditions minimum typical maximum units c in input capacitance 4 pf r pullup input pullup resistor 51 k ? r pulldown input pulldown resistor 51 k ?
rev f 7/8/15 3 low skew, 1-to-10 differential-to-3.3v, 2.5v lvpecl/ecl fanout buffer 85310i-11 data sheet function tables table 3a. control input function table after clk_en switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as shown in fi gure 1. in the active mode, the state of the outpu ts are a function of the clk0, nclk0 and clk1, nclk1 input as described in table 3b. figure 1. clk_en timing diagram table 3b. clock input function table note 1: please refer to the applications information, wiring the differential input to accept single-ended levels. inputs outputs clk_en selected source q[0:9] nq[0:9] 0 clk0, nclk0 disabled; low disabled; high 1 clk1, nclk1 enabled enabled inputs outputs input to output mode polarity clk0 or clk1 nclk0 or nclk1 q[0:9] nq[0:9] 0 1 low high differential to differential non-inverting 1 0 high low differential to differential non-inverting 0 biased; note 1 low high single-ended to differential non-inverting 1 biased; note 1 high low single-ended to differential non-inverting biased; note 1 0 high low single-ended to differential inverting biased; note 1 1 low high single-ended to differential inverting enabled disabled clk[0:1] nclk[0:1] clk_en nq[0:9] q[0:9]
low skew, 1-to-10 differential-to-3.3v, 2.5v lvpecl/ecl fanout buffer 4 rev f 7/8/15 85310i-11 data sheet absolute maximum ratings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only . functional operation of product at t hese conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. dc electrical characteristics table 4a. power supply dc characteristics, v cc = v cco = 2.375v to 3.8v; v ee = 0v, t a = -40c to 85c table 4b. lvcmos/lvttl dc characteristics, v cc = v cco = 2.375v to 3.8v; v ee = 0v, t a = -40c to 85c table 4c. dc characteristics, v cc = v cco = 2.375v to 3.8v; v ee = 0v, t a = -40c to 85 c note 1: v il should not be less than -0.3v. note 2: common mode voltage is defined as v ih . item rating supply voltage, v cc 4.6v inputs, v i -0.5v to v cc + 0.5v outputs, i o continuous current surge current 50ma 100ma package thermal impedance, ? ja 47.9 ? c/w (0 lfpm) storage temperature, t stg -65 ? c to 150 ? c symbol parameter test conditio ns minimum typical maximum units v cc positive supply voltage 2.375 3.3 3.8 v v cco output supply voltage 2.375 3.3 3.8 v i ee power supply current 120 ma symbol parameter test conditi ons minimum typical maximum units v ih input high voltage 2 v cc + 0.3 v v il input low voltage -0.3 0.8 v i ih input high current clk_en v cc = v in = 3.8v 5 a clk_sel v cc = v in = 3.8v 150 a i il input low current clk_en v cc = 3.8v, v in = 0v -150 a clk_sel v cc = 3.8v, v in = 0v -5 a symbol parameter test conditions minimum typical maximum units i ih input high current clk[0:1], v cc = v in = 3.8v 150 a nclk[0:1] v cc = v in = 3.8v 5 a i il input low current clk[0:1] v cc = 3.8v, v in = 0v -5 a nclk[0:1] v cc = 3.8v, v in = 0v -150 a v pp peak-to-peak voltage; note 1 0.15 1.3 v v cmr common mode range; note 1, 2 v ee + 0.5 v cc ? 0.85 v
rev f 7/8/15 5 low skew, 1-to-10 differential-to-3.3v, 2.5v lvpecl/ecl fanout buffer 85310i-11 data sheet table 4d. lvpecl dc characteristics, v cc = v cco = 2.375v to 3.8v; v ee = 0v, t a = -40c to 85 c note 1: outputs terminated with 50 ? to v cco ? 2v. ac electrical characteristics table 5. ac characteristics, v cc = v cco = 2.375v to 3.8v; v ee = 0v, t a = -40c to 85c note: electrical parameters are guaranteed over the specified ambient operating temperature rang e, which is established when th e device is mounted in a test socket with maintained transverse airflow greate r than 500 lfpm. the device will meet specifications after th ermal equilibrium has been reached under these conditions. note: all parameters measured at 500mhz, unless otherwise noted. note 1: measured from the differential input crossi ng point to the differential output crossing point. note 2: defined as skew between outputs on different devices oper ating at the same supply voltage, same frequency, same tempera ture and with equal load conditions. using the same type of inputs on each device, the outputs are measured at the differential cross po ints. note 3: this parameter is defined according with jedec standard 65. note 4: defined as skew between outputs at the same supply voltage and with equal load conditions. measured at the output diffe rential cross points. symbol parameter test conditio ns minimum typical maximum units v oh output high voltage; note 1 v cco ? 1.4 v cco ? 0.9 v v ol output low voltage; note 1 v cco ? 2.0 v cco ? 1.7 v v swing peak-to-peak output voltage swing 0.6 1.0 v symbol parameter test conditions minimum typical maximum units f max output frequency 700 mhz t pd propagation delay; note 1 2 2.5 ns t sk(pp) part-to-part skew; note 2, 3 140 340 ps t sk(o) output skew; note 3, 4 30 55 ps t jit additive phase jitter, rms; refer to additive phase jitter section <0.13 ps t r / t f output rise/fall time 20% to 80% 200 700 ps odc output duty cycle 47 53 %
low skew, 1-to-10 differential-to-3.3v, 2.5v lvpecl/ecl fanout buffer 6 rev f 7/8/15 85310i-11 data sheet additive phase jitter the spectral purity in a band at a specific offset fr om the fundamental compared to the power of t he fundamental is called the dbc phase noise. this value is normally expressed using a phase noise plot and is most often the specified plot in many applications. phase noise is defined as the ratio of the noise power present in a 1hz band at a specified offset from the fundamen tal frequency to the power value of the fundamental. this ratio is expressed in decibels (dbm) or a ratio of the power in the 1hz band to the power in the fundamental. when the required offset is specif ied, the phase noise is called a dbc value, which simply means dbm at a specif ied offset from the fundamental. by investigating jitter in the frequency domain, we get a better understanding of its effect s on the desired application over the entire time record of the signal. it is mathematically possible to calculate an expected bit error rate given a phase noise plot. as with most timing specificat ions, phase noise measurements has issues relating to the limitations of the equipment. often the noise floor of the equipment is higher than the noise floor of the device. this is illustrated above. the device m eets the noise floor of what is shown, but can actually be lower. the phase noise is dependent on the input source and measurement equipment. additive phase jitter, rms @ 155.52mhz = <0.13ps (typical) ssb phase noise dbc/hz offset from carrier frequency (hz)
rev f 7/8/15 7 low skew, 1-to-10 differential-to-3.3v, 2.5v lvpecl/ecl fanout buffer 85310i-11 data sheet parameter measureme nt information lvpecl output load ac test circuit part-to-part skew propagation delay differential input level output skew output rise/fall time scope qx nqx v ee v cc, 2v -0.375v to -1.8v v cco t sk(pp) part 1 part 2 nqx qx nqy qy t pd nclk[0:1] clk[0:1] nq[0:9] q[0:9] v cmr cross points v pp v cc v ee nclk[0:1] clk[0:1] nqx qx nqy qy nq[0:9] q[0:9]
low skew, 1-to-10 differential-to-3.3v, 2.5v lvpecl/ecl fanout buffer 8 rev f 7/8/15 85310i-11 data sheet parameter measureme nt information output duty cycle/pulse width/period applications information wiring the differential input to accept single-ended levels figure 2 shows how a differential input can be wired to accept single ended levels. the reference voltage v ref = v cc /2 is generated by the bias resistors r1 and r2. the bypass capacitor (c1) is used to help filter noise on the dc bias. this bias circuit should be located as close to the input pin as possible. the ratio of r1 and r2 might need to be adjusted to position the v ref in the center of the input voltage swing. for example, if the input clock swing is 2.5v and v cc = 3.3v, r1 and r2 value should be adjusted to set v ref at 1.25v. the values below are for when both the single ended swing and v cc are at the same voltage. this configuration re quires that the sum of the output impedance of the driver (ro) and the series resistance (rs) equals the transmission line impedance. in addition, matched termination at the input will attenuate the signal in half. this can be done in one of two ways. first, r3 and r4 in parallel should equal the transmission line impedance. for most 50 ? applications, r3 and r4 can be 100 ? . the values of the resistors can be increased to reduce the loading for slower and weaker lvcmos driver. when using single-ended signaling, the noise rejection bene fits of differential signaling are reduced. even though the differential input can handle full rail lvcmos signaling, it is recommended that the amplitude be reduced. the datasheet specifies a lower differential amplitude, however this only applies to differential signals. for single-ended applications, the swing can be larger, however v il cannot be less than -0.3v and v ih cannot be more than v cc + 0.3v. though some of the recommended components might not be used, the pads should be placed in the layout. they can be utilized for debugging purposes. the datasheet specifications are characterized and guaranteed by using a differential signal. figure 2. recommended schematic for wiring a diff erential input to accept single-ended levels nq[0:9] q[0:9]
rev f 7/8/15 9 low skew, 1-to-10 differential-to-3.3v, 2.5v lvpecl/ecl fanout buffer 85310i-11 data sheet differential clock input interface the clk /nclk accepts lvds, lvpecl, lvhstl, sstl, hcsl and other differential signals. both v swing and v oh must meet the v pp and v cmr input requirements. figures 3a to 3f show interface examples for the clk/nclk input driven by the most common driver types. the input interfaces suggested here are examples only. please consult with the vendor of t he driver component to confirm the driver termination requirements. for example, in figure 3a, the input termination applies for idt open emitter lvhstl drivers. if you are using an lvhstl driver from another vendor, use their termination recommendation. figure 3a. clk/nclk input driven by an idt open emitter lvhstl driver figure 3c. clk/nclk input driven by a 3.3v lvpecl driver figure 3e. clk/nclk input driven by a 3.3v hcsl driver figure 3b. clk/nclk input driven by a 3.3v lvpecl driver figure 3d. clk/nclk input driven by a 3.3v lvds driver figure 3f. clk/nclk input driven by a 2.5v sstl driver r150 r250 1.8v zo = 50 zo = 50 clknclk 3.3v lvhstlidt lvhstl driver differentialinput h csl *r 3 * r4 c l k n c l k 3 . 3v 3 . 3v diff e r e nti a l in p u t clknclk differentialinput sstl 2.5v zo = 60 zo = 60 2.5v 3.3v r1120 r2120 r3120 r4120
low skew, 1-to-10 differential-to-3.3v, 2.5v lvpecl/ecl fanout buffer 10 rev f 7/8/15 85310i-11 data sheet recommendations for unused input pins inputs: clk/nclk inputs for applications not requiring the us e of the differential input, both clk and nclk can be left floating. though not required, but for additional protection, a 1k ? resistor can be tied from clk to ground. lvcmos control pins the control pins have an internal pullup and pulldown; additional resistance is not required but can be added for additional protection. a 1k ? resistor can be used. outputs: lvpecl outputs all unused lvpecl outputs can be le ft floating. we recommend that there is no trace attached. both sides of the differential output pair should either be left floating or terminated. termination for 3.3v lvpecl outputs the clock layout topology shown below is a typical termination for lvpecl outputs. the two different layouts mentioned are recommended only as guidelines. the differential outputs are low impedance follower outputs that generate ecl/lvpecl compatible out puts. therefore, terminating resistors (dc current path to ground) or current sources must be used for functionality. these outputs are designed to drive 50 ? transmission lines. matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. figures 4a and 4b show two different layouts which are recommended only as guidelines. other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. figure 4a. 3.3v lvpecl output termination figure 4b. 3.3v lvpecl output termination r184 ? r284 ? 3.3v r3125 ? r4125 ? z o = 50 ? z o = 50 ? input 3.3v 3.3v +_
rev f 7/8/15 11 low skew, 1-to-10 differential-to-3.3v, 2.5v lvpecl/ecl fanout buffer 85310i-11 data sheet termination for 2.5v lvpecl outputs figure 5a and figure 5b show examples of termination for 2.5v lvpecl driver. these terminations are equivalent to terminating 50 ? to v cc ? 2v. for v cc = 2.5v, the v cc ? 2v is very close to ground level. the r3 in figure 5b can be eliminated and the termination is shown in figure 5c. figure 5a. 2.5v lvpecl driver termination example figure 5c. 2.5v lvpecl driver termination example figure 5b. 2.5v lvpecl driver termination example 2.5v lvpecl driver v cc = 2.5v 2.5v 2.5v 50 50 r1250 r3250 r262.5 r462.5 + ? 2.5v lvpecl driver v cc = 2.5v 2.5v 50 50 r150 r250 + ? 2.5v lvpecl driver v cc = 2.5v 2.5v 50 50 r150 r250 r318 + ?
low skew, 1-to-10 differential-to-3.3v, 2.5v lvpecl/ecl fanout buffer 12 rev f 7/8/15 85310i-11 data sheet power considerations this section provides information on power dissipati on and junction temperatur e for the ics5311i-01. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ics5311i-01 is the sum of the core power plus the power dissipated in the load(s). the following is the power dissipation for v cc = 3.8v, which gives worst case results. note: please refer to section 3 for details on calculating power dissipated in the load. ? power (core) max = v cc_max * i ee_max = 3.8v * 120ma = 456mw ? power (outputs) max = 30mw/loaded output pair if all outputs are loaded, t he total power is 10 * 30mw = 300mw total power_ max (3.8v, with all outputs switching) = 456mw + 300mw = 756mw 2. junction temperature. junction temperature, tj, is the temperatur e at the junction of the bond wire and bo nd pad directly affects the reliability of the device. the maximum recommended junction temperature is 125c. limiting the internal transistor junction temperature, tj, to 125c ensures that the bond wire and bond pad temperature remains below 125c. the equation for tj is as follows: tj = ? ja * pd_total + t a tj = junction temperature ? ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ? ja must be used. assuming a moderate air flow of 200 linear feet per minute and a multi-layer boar d, the appropriate value is 42.1c/w per table 6 below. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 0.756w * 42.1c/w = 116.8c. th is is well below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (single layer or multi-layer). table 6. thermal resistance ? ja for 32 lead lqfp, forced convection ? ja by velocity linear feet per minute 02 0 05 0 0 single-layer pcb, jedec standard te st boards 67.8c/w 55.9c/w 50.1c/w multi-layer pcb, jedec standard test boards 47.9c/w 42.1c/w 39.4c/w note: most modern pcb designs use multi-layered boards. t he data in the second row pertains to most designs.
rev f 7/8/15 13 low skew, 1-to-10 differential-to-3.3v, 2.5v lvpecl/ecl fanout buffer 85310i-11 data sheet 3. calculations and equations. the purpose of this section is to calculate the power dissipation fo r the lvpecl output pair. lvpecl output driver circuit and termination are shown in figure 6. figure 6. lvpecl driver circuit and termination t o calculate worst case power dissipation into the load, use the following equations which assume a 50 ? load, and a termination voltage of v cco ? 2v. ? for logic high, v out = v oh_max = v cco_max ? 0.9v (v cco_max ? v oh_max ) = 0.9v ? for logic low, v out = v ol_max = v cco_max ? 1.7v (v cco_max ? v ol_max ) = 1.7v pd_h is power dissipation when the output drives high. pd_l is the power dissipation when the output drives low. pd_h = [(v oh_max ? (v cco_max ? 2v))/r l ] * (v cco_max ? v oh_max ) = [(2v ? (v cco_max ? v oh_max ))/r l ] * (v cco_max ? v oh_max ) = [(2v ? 0.9v)/50 ? ] * 0.9v = 19.8mw pd_l = [(v ol_max ? (v cco_max ? 2v))/r l ] * (v cco_max ? v ol_max ) = [(2v ? (v cco_max ? v ol_max ))/r l] * (v cco_max ? v ol_max ) = [(2v ? 1.7v)/50 ? ] * 1.7v = 10.2mw total power dissipation per output pair = pd_h + pd_l = 30mw v out v cco v cco - 2v q1 rl 50
low skew, 1-to-10 differential-to-3.3v, 2.5v lvpecl/ecl fanout buffer 14 rev f 7/8/15 85310i-11 data sheet reliability information table 7. ? ja vs. air flow table for a 32 lead lqfp transistor count the transistor count for 85310i-11 is: 1034 ? ja by velocity linear feet per minute 0 200 500 single-layer pcb, jedec standard test boards 67.8c/w 55.9c/w 50.1c/w multi-layer pcb, jedec standard te st boards 47.9c/w 42.1c/w 39.4c/w note: most modern pcb designs use multi-layered boards. t he data in the second row pertains to most designs.
rev f 7/8/15 15 low skew, 1-to-10 differential-to-3.3v, 2.5v lvpecl/ecl fanout buffer 85310i-11 data sheet package outline and package dimensions package outline - y suffix for 32 lead lqfp table 8. package dimensions for 32 lead lqfp reference document: jedec publication 95, ms-026 jedec variation: bba all dimensions in millimeters symbol minimum nominal maximum n 32 a 1.60 a1 0.05 0.15 a2 1.35 1.40 1.45 b 0.30 0.37 0.45 c 0.09 0.20 d & e 9.00 basic d1 & e1 7.00 basic d2 & e2 5.60 ref. e 0.80 basic l 0.45 0.60 0.75 ? 0 7 ccc 0.10
low skew, 1-to-10 differential-to-3.3v, 2.5v lvpecl/ecl fanout buffer 16 rev f 7/8/15 85310i-11 data sheet ordering information table 9. ordering information note: parts that are ordered with an "lf" suffix to the part number are the pb-free config uration and are rohs compliant. part/order number marking package shipping packaging temperature 85310ayi-11lf ics5310ai11l ?lead-free? 32 lead lqfp tray -40 ? c to 85 ? c 85310AYI-11LFT ics5310ai11l ?lead-free? 32 lead lqfp tape & reel -40 ? c to 85 ? c
rev f 7/8/15 17 low skew, 1-to-10 differential-to-3.3v, 2.5v lvpecl/ecl fanout buffer 85310i-11 data sheet revision history sheet rev table page description of change date b t5 5 ac characteristics table - t pd row, revised value from 2.25ns max. to 2.5ns max. 4/29/02 b 9 added termination for lvpecl outputs. 5/29/02 c t4d 5 added lvpecl dc characteristics table. changed part number from ics85310-11 to 85310i-11 in title and all subsequent areas throughout the datasheet. 7/25/02 d t4a 4 7 power supply table - increased max. value for i ee to 120ma from 30ma max. power considerations have re-adjusted to the increased i ee value. 10/23/02 e t2t5 t9 12 5 6 9 1015 features section - added additive phase jitter bullet and lead-free bullet. pin characteristics - changed c in 4pf max. to 4pf typical. ac characteristics table - added additive phase jitter spec. added additive phase jitter section. added termination for 2.5v lvpecl outputs. added differential clo ck input interface. ordering information table - added lead-free part number and note. 7/7/05 f t4d 5 11 - 12 lvpecl dc characteristics table -corrected v oh max. from v cco - 1.0v to v cco - 0.9v; and v swing max. from 0.85v to 1.0v. power considerations - corrected power dissipation to reflect v oh max in table 4d. 4/11/07 f t4c t5t9 45 8 1016 differential dc characterist ics table -updated notes. ac characteristics table - added thermal note. updated wiring the differential input to accept single-ended levels section. updated figure 4a & 4b. ordering information table - corrected lead-free marking. converted datasheet format. 6/9/10 f t9 16 ordering information - removed leaded devices. updated data sheet format. 7/8/15
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