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sn65lvds387 , sn75lvds387 , sn65lvds389 sn75lvds389 , sn65lvds391 , sn75lvds391 slls362g ? september 1999 ? revised january 2016 snx5lvds3xx high-speed differential line drivers 1 features 3 description this family of 4, 8, and 16 differential line drivers 1 ? four ('391), eight ('389), or sixteen ('387) line implements the electrical characteristics of low- drivers meet or exceed the requirements of ansi voltage differential signaling (lvds). this signaling eia/tia-644 standard technique lowers the output voltage levels of 5-v ? designed for signaling rates up to 630 mbps differential standard levels (such as eia/tia-422b) to with very low radiation (emi) reduce the power, increase the switching speeds, and allow operation with a 3.3-v supply rail. any of the 16 ? low-voltage differential signaling with typical current-mode drivers will deliver a minimum output voltage of 350 mv and a 100- ? load differential output voltage magnitude of 247 mv into a ? propagation delay times less than 2.9 ns 100- ? load when enabled. ? output skew is less than 150 ps device information (1) ? part-to-part skew is less than 1.5 ns part number package body size (nom) ? 35-mw total power dissipation in each driver sn65lvds387 tssop (64) 17.00 mm 6.10 mm operating at 200 mhz sn75lvds387 tssop (38) 9.70 mm 4.40 mm ? driver is high-impedance when disabled or with soic (16) 9.90 mm 3.91 mm v cc < 1.5 v sn65lvds389 tssop (16) 5.00 mm 4.40 mm ? sn65' version bus-pin esd protection exceeds sn75lvds389 tssop (64) 17.00 mm 6.10 mm 15 kv sn65lvds391 tssop (38) 9.70 mm 4.40 mm ? packaged in thin shrink small-outline package soic (16) 9.90 mm 3.91 mm with 20-mil pin pitch sn75lvds391 tssop (16) 5.00 mm 4.40 mm ? low-voltage ttl (lvttl) logic inputs are 5-v tolerant (1) for all available packages, see the orderable addendum at the end of the data sheet. 2 applications ? wireless infrastructure ? telecom infrastructure ? printer typical application schematic 1 an important notice at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. production data. host controller tx clock sn65l vds387 or 389 target controller target l vds receiver(s) indicates twisting of theconductors. t t t t t indicates the line terminationcircuit. host balanced interconnect power power db0 db1 db2 dbn3 t t t t dbn2 dbn1 dbn rx clock db0 db1 db2 dbn3 dbn2 dbn1 dbn productfolder sample &buy technical documents tools & software support &community
sn65lvds387 , sn75lvds387 , sn65lvds389 sn75lvds389 , sn65lvds391 , sn75lvds391 slls362g ? september 1999 ? revised january 2016 www.ti.com table of contents 10.2 functional block diagram ..................................... 13 1 features .................................................................. 1 10.3 feature description ............................................... 13 2 applications ........................................................... 1 10.4 device functional modes ...................................... 14 3 description ............................................................. 1 11 application and implementation ........................ 15 4 revision history ..................................................... 2 11.1 application information .......................................... 15 5 description (continued) ........................................ 3 11.2 typical application ................................................ 16 6 device options ....................................................... 3 12 power supply recommendations ..................... 22 7 pin configuration and functions ......................... 3 13 layout ................................................................... 22 8 specifications ......................................................... 6 13.1 layout guidelines ................................................. 22 8.1 absolute maximum ratings ...................................... 6 13.2 layout example .................................................... 24 8.2 esd ratings .............................................................. 6 14 device and documentation support ................. 25 8.3 recommended operating conditions ....................... 7 14.1 device support ...................................................... 25 8.4 thermal information .................................................. 7 14.2 documentation support ........................................ 25 8.5 electrical characteristics .......................................... 7 14.3 related links ........................................................ 25 8.6 switching characteristics .......................................... 8 14.4 trademarks ........................................................... 25 8.7 typical characteristics .............................................. 9 14.5 electrostatic discharge caution ............................ 25 9 parameter measurement information ................ 11 14.6 glossary ................................................................ 26 10 detailed description ........................................... 13 15 mechanical, packaging, and orderable 10.1 overview ............................................................... 13 information ........................................................... 26 4 revision history changes from revision f (december 2014) to revision g page ? changed c3a from: pin 20 to: pin 21 in the pin functions: snx5lvds387 table ............................................................. 5 changes from revision e (november 2004) to revision f page ? added pin configuration and functions section, esd ratings table, feature description section, device functional modes , application and implementation section, power supply recommendations section, layout section, device and documentation support section, and mechanical, packaging, and orderable information section .............................. 1 2 submit documentation feedback copyright ? 1999 ? 2016, texas instruments incorporated product folder links: sn65lvds387 sn75lvds387 sn65lvds389 sn75lvds389 sn65lvds391 sn75lvds391
sn65lvds387 , sn75lvds387 , sn65lvds389 sn75lvds389 , sn65lvds391 , sn75lvds391 www.ti.com slls362g ? september 1999 ? revised january 2016 5 description (continued) when disabled, the driver outputs are high-impedance. each driver input (a) and enable (en) have an internal pulldown that will drive the input to a low level when open-circuited. the sn65lvds387, sn65lvds389, and sn65lvds391 devices are characterized for operation from ? 40 c to 85 c. the sn75lvds387, sn75lvds389, and sn75lvds391 devices are characterized for operation from 0 c to 70 c. 6 device options part number (1) temperature range number of drivers bus-pin esd sn65lvds387dgg ? 40 c to 85 c 16 15 kv sn75lvds387dgg 0 c to 70 c 16 4 kv sn65lvds389dbt ? 40 c to 85 c 8 15 kv sn75lvds389dbt 0 c to 70 c 8 4 kv sn65lvds391d ? 40 c to 85 c 4 15 kv sn75lvds391d 0 c to 70 c 4 4 kv sn65lvds391pw ? 40 c to 85 c 4 15 kv sn75lvds391pw 0 c to 70 c 4 4 kv (1) this package is available taped and reeled. to order this packaging option, add an r suffix to the part number (for example, sn65lvds387dggr). 7 pin configuration and functions copyright ? 1999 ? 2016, texas instruments incorporated submit documentation feedback 3 product folder links: sn65lvds387 sn75lvds387 sn65lvds389 sn75lvds389 sn65lvds391 sn75lvds391 12 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 6463 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 gnd v cc v cc gnd ena a1aa2a a3a a4a enb b1ab2a b3a b4a gnd v cc v cc gnd c1ac2a c3a c4a enc d1ad2a d3a d4a end gnd v cc v cc gnd a1ya1z a2y a2z a3y a3z a4y a4z b1y b1z b2y b2z b3y b3z b4y b4z c1y c1z c2y c2z c3y c3z c4y c4z d1y d1z d2y d2z d3y d3z d4y d4z 12 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 3837 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 gnd v cc gnd ena a1aa2a a3a a4a gnd v cc gnd b1ab2a b3a b4a enb gnd v cc gnd a1ya1z a2y a2z a3y a3z a4y a4z nc nc nc b1y b1z b2y b2z b3y b3z b4y b4z 'lvds389 dbt p ackage (t op view) 'lvds387 dgg p ackage (t op view) 12 3 4 5 6 7 8 1615 14 13 12 11 10 9 en1,2 1a2a v cc gnd 3a4a en3,4 1y1z 2y 2z 3y 3z 4y 4z 'lvds391 d or pw p ackage (t op view)
sn65lvds387 , sn75lvds387 , sn65lvds389 sn75lvds389 , sn65lvds391 , sn75lvds391 slls362g ? september 1999 ? revised january 2016 www.ti.com pin functions: snx5lvds391 pin i/o description name number v cc 4 ? supply voltage gnd 5 ? ground 1a 2 i lvttl input signal 1y 16 o differential (lvds) non-inverting output 1z 15 o differential (lvds) inverting output 2a 3 i lvttl input signal 2y 14 o differential (lvds) non-inverting output 2z 13 o differential (lvds) inverting output 3a 6 i lvttl input signal 3y 12 o differential (lvds) non-inverting output 3z 11 o differential (lvds) inverting output 4a 7 i lvttl input signal 4y 10 o differential (lvds) non-inverting output 4z 9 o differential (lvds) inverting output en1,2 1 i enable for channels 1 and 2 en3,4 8 i enable for channels 3 and 4 pin functions: snx5lvds389 pin i/o description name number v cc 2, 10, 18 ? supply voltage 1, 3, 9, 11, gnd ? ground 17, 19 a1a 5 i lvttl input signal a1y 38 o differential (lvds) non-inverting output a1z 37 o differential (lvds) inverting output a2a 6 i lvttl input signal a2y 36 o differential (lvds) non-inverting output a2z 35 o differential (lvds) inverting output a3a 7 i lvttl input signal a3y 34 o differential (lvds) non-inverting output a3z 33 o differential (lvds) inverting output a4a 8 i lvttl input signal a4y 32 o differential (lvds) non-inverting output a4z 31 o differential (lvds) inverting output b1a 12 i lvttl input signal b1y 27 o differential (lvds) non-inverting output b1z 26 o differential (lvds) inverting output b2a 13 i lvttl input signal b2y 25 o differential (lvds) non-inverting output b2z 24 o differential (lvds) inverting output b3a 14 i lvttl input signal b3y 23 o differential (lvds) non-inverting output b3z 22 o differential (lvds) inverting output b4a 15 i lvttl input signal b4y 21 o differential (lvds) non-inverting output b4b 20 o differential (lvds) inverting output 4 submit documentation feedback copyright ? 1999 ? 2016, texas instruments incorporated product folder links: sn65lvds387 sn75lvds387 sn65lvds389 sn75lvds389 sn65lvds391 sn75lvds391
sn65lvds387 , sn75lvds387 , sn65lvds389 sn75lvds389 , sn65lvds391 , sn75lvds391 www.ti.com slls362g ? september 1999 ? revised january 2016 pin functions: snx5lvds389 (continued) pin i/o description name number ena 4 i enable for channel a enb 16 i enable for channel b nc 28, 29, 30 ? no connection pin functions: snx5lvds387 pin i/o description name number 2, 3, 16, 17, v cc ? supply voltage 30, 31 1, 4, 15, 18, gnd ? ground 29, 32 a1a 6 i lvttl input signal a1y 64 o differential (lvds) non-inverting output a1z 73 o differential (lvds) inverting output a2a 7 i lvttl input signal a2y 62 o differential (lvds) non-inverting output a2z 61 o differential (lvds) inverting output a3a 8 i lvttl input signal a3y 60 o differential (lvds) non-inverting output a3z 59 o differential (lvds) inverting output a4a 9 i lvttl input signal a4y 58 o differential (lvds) non-inverting output a4z 57 o differential (lvds) inverting output b1a 11 i lvttl input signal b1y 56 o differential (lvds) non-inverting output b1z 55 o differential (lvds) inverting output b2a 12 i lvttl input signal b2y 54 o differential (lvds) non-inverting output b2z 53 o differential (lvds) inverting output b3a 13 i lvttl input signal b3y 52 o differential (lvds) non-inverting output b3z 51 o differential (lvds) inverting output b4a 14 i lvttl input signal b4y 50 o differential (lvds) non-inverting output b4b 49 o differential (lvds) inverting output c1a 19 i lvttl input signal c1y 48 o differential (lvds) non-inverting output c1z 47 o differential (lvds) inverting output c2a 20 i lvttl input signal c2y 46 o differential (lvds) non-inverting output c2z 45 o differential (lvds) inverting output c3a 21 i lvttl input signal c3y 44 o differential (lvds) non-inverting output c3z 43 o differential (lvds) inverting output c4a 22 i lvttl input signal c4y 42 o differential (lvds) non-inverting output c4z 41 o differential (lvds) inverting output copyright ? 1999 ? 2016, texas instruments incorporated submit documentation feedback 5 product folder links: sn65lvds387 sn75lvds387 sn65lvds389 sn75lvds389 sn65lvds391 sn75lvds391
sn65lvds387 , sn75lvds387 , sn65lvds389 sn75lvds389 , sn65lvds391 , sn75lvds391 slls362g ? september 1999 ? revised january 2016 www.ti.com pin functions: snx5lvds387 (continued) pin i/o description name number d1a 24 i lvttl input signal d1y 40 o differential (lvds) non-inverting output d1z 39 o differential (lvds) inverting output d2a 25 i lvttl input signal d2y 38 o differential (lvds) non-inverting output d2z 37 o differential (lvds) inverting output d3a 26 i lvttl input signal d3y 36 o differential (lvds) non-inverting output d3z 35 o differential (lvds) inverting output d4a 27 i lvttl input signal d4y 34 o differential (lvds) non-inverting output b4b 33 o differential (lvds) inverting output ena 5 i enable for channel a enb 10 i enable for channel b enc 23 i enable for channel c end 26 i enable for channel d 8 specifications 8.1 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) (1) min max unit supply voltage range, v cc (2) ? 0.5 4 v inputs ? 0.5 6 v input voltage range y or z ? 0.5 4 v continuous power dissipation see thermal information lead temperature 1.6 mm (1/16 in) from case for 10 seconds 260 c storage temperature, t stg ? 65 150 c (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) all voltage values, except differential i/o bus voltages, are with respect to network ground pin. 8.2 esd ratings value unit class 3, a 15000 v sn65 ' (y, z, and gnd) class 3, b 400 v v (esd) electrostatic discharge class 3, a 4000 v sn75 ' (y, z, and gnd) class 3, b 400 v lead temperature 1.6 mm (1/16 in) from case for 10 seconds 260 c 6 submit documentation feedback copyright ? 1999 ? 2016, texas instruments incorporated product folder links: sn65lvds387 sn75lvds387 sn65lvds389 sn75lvds389 sn65lvds391 sn75lvds391
sn65lvds387 , sn75lvds387 , sn65lvds389 sn75lvds389 , sn65lvds391 , sn75lvds391 www.ti.com slls362g ? september 1999 ? revised january 2016 8.3 recommended operating conditions min nom max unit v cc supply voltage 3 3.3 3.6 v v ih high-level input voltage 2 v v il low-level input voltage 0.8 v sn75 ' 0 70 c operating free-air t a temperature sn65 ' ? 40 85 c 8.4 thermal information sn65lvds387 sn75lvds387 sn65lvds389 sn75lvds389 sn65lvds391 sn75lvds391 thermal metric (1) unit dgg dbt d pw 64 pins 38 pins 16 pins 16 pins derating factor above t a = 25 c (2) 16.7 8.5 7.6 6.2 mw/ c power rating: t a 25 c 2094 1071 950 774 power rating: t a = 70 c 1342 688 608 496 mw power rating: t a = 85 c 1089 556 494 402 (1) for more information about traditional and new thermal metrics, see the ic package thermal metrics application report, spra953 . (2) this is the inverse of the junction-to-ambient thermal resistance when board-mounted (low-k) and with no air flow. 8.5 electrical characteristics over recommended operating conditions (unless otherwise noted) parameter test conditions min typ (1) max unit |v od | differential output voltage magnitude 247 340 454 r l = 100 ? , mv change in differential output voltage see figure 9 and figure 10 |v od | ? 50 50 magnitude between logic states steady-state common-mode output v oc(ss) 1.125 1.375 v voltage change in steady-state common- v oc(ss) mode output voltage between logic see figure 11 ? 50 50 mv states peak-to-peak common-mode output v oc(pp) 50 150 mv voltage ' lvds387 85 95 enabled, r l = 100 ? , ' lvds389 50 70 v in = 0.8 v or 2 v ' lvds391 20 26 i cc supply current ma ' lvds387 0.5 1.5 disabled, ' lvds389 0.5 1.5 v in = 0 v or v cc ' lvds391 0.5 1.3 i ih high-level input current v ih = 2 v 3 20 a i il low-level input current v il = 0.8 v 2 10 a v oy or v oz = 0 v 24 ma i os short-circuit output current v od = 0 v 12 ma i oz high-impedance output current v o = 0 v or v cc 1 a i o(off) power-off output current v cc = 1.5 v, v o = 2.4 v 1 a c in input capacitance v i = 0.4sin(4e6 t) + 0.5 v 5 pf c o output capacitance v i = 0.4sin(4e6 t) + 0.5 v, disabled 9.4 pf (1) all typical values are at 25 c and with a 3.3-v supply. copyright ? 1999 ? 2016, texas instruments incorporated submit documentation feedback 7 product folder links: sn65lvds387 sn75lvds387 sn65lvds389 sn75lvds389 sn65lvds391 sn75lvds391
sn65lvds387 , sn75lvds387 , sn65lvds389 sn75lvds389 , sn65lvds391 , sn75lvds391 slls362g ? september 1999 ? revised january 2016 www.ti.com 8.6 switching characteristics over recommended operating conditions (unless otherwise noted) parameter test conditions min typ (1) max unit t plh propagation delay time, low-to-high-level output 0.9 1.7 2.9 ns t phl propagation delay time, high-to-low-level output 0.9 1.6 2.9 ns t r differential output signal rise time 0.4 0.8 1 ns r l = 100 ? , t f differential output signal fall time c l = 10 pf, 0.4 0.8 1 ns see figure 12 t sk(p) pulse skew (|t phl ? t plh |) 150 500 ps t sk(o) output skew (2) 80 150 ps t sk(pp) part-to-part skew (3) 1.5 ns propagation delay time, high-impedance-to-high- t pzh 6.4 15 ns level output propagation delay time, high-impedance-to-low- t pzl 5.9 15 ns level output see figure 13 propagation delay time, high-level-to-high- t phz 3.5 15 ns impedance output propagation delay time, low-level-to-high- t plz 4.5 15 ns impedance output (1) all typical values are at 25 c and with a 3.3-v supply. (2) t sk(o) is the magnitude of the time difference between the t plh or t phl of all drivers of a single device with all of their inputs connected together. (3) t sk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of any two devices characterized in this data sheet when both devices operate with the same supply voltage, at the same temperature, and have the same test circuits. 8 submit documentation feedback copyright ? 1999 ? 2016, texas instruments incorporated product folder links: sn65lvds387 sn75lvds387 sn65lvds389 sn75lvds389 sn65lvds391 sn75lvds391
sn65lvds387 , sn75lvds387 , sn65lvds389 sn75lvds389 , sn65lvds391 , sn75lvds391 www.ti.com slls362g ? september 1999 ? revised january 2016 8.7 typical characteristics figure 2. ' lvds387 supply current (rms) vs switching figure 1. ' lvds391 supply current vs (rms) switching frequency frequency figure 3. ' lvds389 supply current (rms) vs switching figure 4. low-to-high propagation delay time vs free-air frequency temperature figure 5. high-to-low propagation delay time vs free-air figure 6. low-level output voltage vs low-level output temperature current copyright ? 1999 ? 2016, texas instruments incorporated submit documentation feedback 9 product folder links: sn65lvds387 sn75lvds387 sn65lvds389 sn75lvds389 sn65lvds391 sn75lvds391 t a ? free-air t emperature ? c 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 ?40 ?20 0 20 40 60 80 100 v cc = 3.6 v v cc = 3 v v cc = 3.3 v t plh ? low-t o-high propagation delay t ime ? ns f ? frequency ? mhz ? supply current ? ma i cc 0 10 20 30 40 50 60 0 50 100 150 200 250 300 v cc = 3.6 v all outputs loaded and enabled. v cc = 3.3 v v cc = 3 v f ? frequency ? mhz ? supply current ? ma i cc 80 100 120 140 160 180 200 220 240 0 50 100 150 200 250 300 350 v cc = 3.6 v all outputs loaded and enabled. v cc = 3.3 v v cc = 3 v 0 i ol ? low-level output current ? ma 43 0 4 6 2 2 v cc = 3.3 v t a = 25 c 1 v ol ? low-level output v oltage ? v t a ? free-air t emperature ? c 1.0 1.2 1.4 1.6 1.8 2.0 2.2 ?40 ?20 0 20 40 60 80 100 t phl ? high-t o-low propagation delay t ime ? ns v cc = 3.6 v v cc = 3 v v cc = 3.3 v f ? frequency ? mhz ? supply current ? ma i cc 40 50 60 70 80 90 100 110 0 50 100 150 200 250 300 v cc = 3.6 v all outputs loaded and enabled. v cc = 3.3 v v cc = 3 v
sn65lvds387 , sn75lvds387 , sn65lvds389 sn75lvds389 , sn65lvds391 , sn75lvds391 slls362g ? september 1999 ? revised january 2016 www.ti.com typical characteristics (continued) figure 8. output voltage vs time figure 7. high-level output voltage vs high-level output current 10 submit documentation feedback copyright ? 1999 ? 2016, texas instruments incorporated product folder links: sn65lvds387 sn75lvds387 sn65lvds389 sn75lvds389 sn65lvds391 sn75lvds391 ?4 i oh ? high-level output current ? ma 3.52.5 0 ?2 0 1.5 ?3 0.5 v oh ? high-level output v oltage ? v ?1 32 1 v cc = 3.3 v t a = 25 c t ? t ime ? ns ? output v oltage ? v v o v oy v oz v od
sn65lvds387 , sn75lvds387 , sn65lvds389 sn75lvds389 , sn65lvds391 , sn75lvds391 www.ti.com slls362g ? september 1999 ? revised january 2016 9 parameter measurement information figure 9. voltage and current definitions figure 10. v od test circuit note: all input pulses are supplied by a generator having the following characteristics: t r or t f 1 ns, pulse repetition rate (prr) = 0.5 mpps, pulse width = 500 10 ns. c l includes instrumentation and fixture capacitance within 0.06 m of the device under test. the measurement of v oc(pp) is made on test equipment with a ? 3 db bandwidth of at least 300 mhz. figure 11. test circuit and definitions for the driver common-mode output voltage copyright ? 1999 ? 2016, texas instruments incorporated submit documentation feedback 11 product folder links: sn65lvds387 sn75lvds387 sn65lvds389 sn75lvds389 sn65lvds391 sn75lvds391 yz input 50 pf 49.9 w 1% (2 places) v oc v o v oc(pp) v oc(ss) 0 v 3 v v i 3.75 k w 0 v v test 2.4 v yz v od input 100 w 3.75 k w gnd v i a (v oy + v oz )/2 i oz i oy yz v od v oy v oc i i v oz
sn65lvds387 , sn75lvds387 , sn65lvds389 sn75lvds389 , sn65lvds391 , sn75lvds391 slls362g ? september 1999 ? revised january 2016 www.ti.com parameter measurement information (continued) note: all input pulses are supplied by a generator having the following characteristics: t r or t f 1 ns, pulse repetition rate (prr) = 50 mpps, pulse width = 10 0.2 ns. c l includes instrumentation and fixture capacitance within 0.06 m of the device under test. figure 12. test circuit, timing, and voltage definitions for the differential output signal note: all input pulses are supplied by a generator having the following characteristics: t r or t f 1 ns, pulse repetition rate (prr) = 0.5 mpps, pulse width = 500 10 ns. c l includes instrumentation and fixture capacitance within 0.06 m of the device under test. figure 13. enable and disable time circuit and definitions 12 submit documentation feedback copyright ? 1999 ? 2016, texas instruments incorporated product folder links: sn65lvds387 sn75lvds387 sn65lvds389 sn75lvds389 sn65lvds391 sn75lvds391 c l = 10 pf (2 places) yz input 49.9 w 1% (2 places) t pzh t phz t pzl t plz 2 v1.4 v 0.8 v @ 1.4 v 1.3 v1.2 v @ 1 v 1.2 v1.1 v input v oy or v oz v oz or v oy v oy v oz 0.8 v or 2 v 1.2 v + yz v od input c l = 10 pf (2 places) 100 w 1 % 2 v1.4 v 0.8 v t plh t phl 100%80% 20% 0% input output 0 v t f t r v od(h) v od(l)
sn65lvds387 , sn75lvds387 , sn65lvds389 sn75lvds389 , sn65lvds391 , sn75lvds391 www.ti.com slls362g ? september 1999 ? revised january 2016 10 detailed description 10.1 overview the snx5lvdsxx devices are quad-, eight-, and 16-channel lvds line drivers. they operate from a single supply that is nominally 3.3 v, but can be as low as 3 v and as high as 3.6 v. the input signals to the snx5lvdsxx device are lvttl signals. the outputs of the device are differential signals complying with the lvds standard (tia/eia-644a). the differential output signal operates with a signal level of 340 mv, nominally, at a common-mode voltage of 1.2 v. this low differential output voltage results in a low emitted radiated energy, which is dependent on the signal slew rate. the differential nature of the output provides immunity to common- mode coupled signals. the snx5lvdsxx device is intended to drive a 100- transmission line. this transmission line may be a printed- circuit board (pcb) or cabled interconnect. with transmission lines, the optimum signal quality and power delivery is reached when the transmission line is terminated with a load equal to the characteristic impedance of the interconnect. likewise, the driven 100- transmission line should be terminated with a matched resistance. 10.2 functional block diagram figure 14. logic diagram (positive logic) 10.3 feature description 10.3.1 driver output voltage and power-on reset the snx5lvdsxx driver operates and meets all the specified performance requirements for supply voltages in the range of 3.0 v to 3.6 v. when the supply voltage drops below 1.5 v (or is turning on and has not yet reached 1.5 v), power-on reset circuitry sets the driver output to a high-impedance state. 10.3.2 5-v input tolerance 5-v and 3.3-v ttl logic standards share the same input high-voltage and input low-voltage thresholds, namely 2.0 v and 0.8 v, respectively. although the maximum supply voltage for the snx5lvdsxx is 3.6 v, the driver can operate and meet all performance requirements when the input signals are as high as 5 v. this allows operation with 3.3-v ttl as well as 5-v ttl logic. 3.3-v cmos and 5-v cmos inputs are also allowable, although one should ensure that the duty-cycle distortion that will result from the ttl (ground-referenced) thresholds are acceptable. 10.3.3 nc pins nc (not connected) pins are pins where the die is not physically connected to the lead frame or package. for optimum thermal performance, a good rule of thumb is to ground the nc pins at the board level. 10.3.4 unused enable pins unused enable pins should be tied to v cc or gnd as appropriate. copyright ? 1999 ? 2016, texas instruments incorporated submit documentation feedback 13 product folder links: sn65lvds387 sn75lvds387 sn65lvds389 sn75lvds389 sn65lvds391 sn75lvds391 4z 4y 3z 3y 2z 2y 1z 1y 4a 3a 2a 1a (1/4 of 'l vds387 or 1/2 of 'l vds389 shown) en 4z 4y 3z 3y 2z 2y 1z 1y 4a 3a 2a 1a ('l vds391 shown) enen
sn65lvds387 , sn75lvds387 , sn65lvds389 sn75lvds389 , sn65lvds391 , sn75lvds391 slls362g ? september 1999 ? revised january 2016 www.ti.com feature description (continued) 10.3.5 driver equivalent schematics the snx5lvdsxx equivalent output schematic diagrams are shown in figure 15 . the driver input is represented by a cmos inverter stage with a 7-v zener diode. the input stage is high-impedance, and includes an internal pulldown to ground. if the driver input is left open, the driver input provides a low-level signal to the rest of the driver circuitry, resulting in a low-level signal at the driver output pins. the zener diode provides esd protection. the driver output stage is a differential pair, one half of which is shown in figure 15 . like the input stage, the driver output includes zener diodes for esd protection. the schematic shows an output stage that includes a set of current sources (nominally 3.5 ma) that are connected to the output load circuit based upon the input stage signal. to the first order, the snx5lvdsxx output stage acts a constant-current source. figure 15. equivalent input and output schematic diagrams 10.4 device functional modes table 1 provides the truth table for the snx5lvdsxx devices. table 1. driver function table (1) input enable outputs a en y z h h h l l h l h x l z z open h l h (1) h = high-level, l = low-level, x = irrelevant, z = high-impedance (off) 14 submit documentation feedback copyright ? 1999 ? 2016, texas instruments incorporated product folder links: sn65lvds387 sn75lvds387 sn65lvds389 sn75lvds389 sn65lvds391 sn75lvds391 7 v 300 k w 50 w v cc a or en input v cc 5 w 7 v y or zoutput equiv alent of each a or en input typical of all outputs 10 k w
sn65lvds387 , sn75lvds387 , sn65lvds389 sn75lvds389 , sn65lvds391 , sn75lvds391 www.ti.com slls362g ? september 1999 ? revised january 2016 11 application and implementation note information in the following applications sections is not part of the ti component specification, and ti does not warrant its accuracy or completeness. ti ? s customers are responsible for determining suitability of components for their purposes. customers should validate and test their design implementation to confirm system functionality. 11.1 application information the intended application of this device and signaling technique is for point-to-point and multidrop baseband data transmission over controlled impedance media of approximately 100 ? . the transmission media can be printed- circuit board traces, backplanes, or cables. the large number of drivers integrated into the same substrate, along with the low pulse skew of balanced signaling, allows extremely precise timing alignment of clock and data for synchronous parallel data transfers. when used with the companion 16- or 8-channel receivers, the sn65lvds386 or sn65lvds388, over 200 million data transfers per second in single-edge clocked systems are possible with very little power. note the ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media, the noise coupling to the environment, and other system characteristics. 11.1.1 signaling rate vs distance the ultimate data transfer rate over a given cable or trace length involves many variables. starting with the capabilities of this lvds driver to reproduce a data pulse as short as 1.6 ns (a 630-mbps signaling rate) with less than 500 ps of pulse distortion, any degradation of this pulse by the transmission media will necessarily reduce the timing margin at the receiving end of the data link. the timing uncertainty induced by the transmission media is commonly referred to as jitter and comes from numerous sources. the characteristics of a particular transmission media can be quantified by using an eye pattern measurement such as shown in figure 16 , which shows about 340 ps of jitter or 20% of the data pulse width. copyright ? 1999 ? 2016, texas instruments incorporated submit documentation feedback 15 product folder links: sn65lvds387 sn75lvds387 sn65lvds389 sn75lvds389 sn65lvds391 sn75lvds391
sn65lvds387 , sn75lvds387 , sn65lvds389 sn75lvds389 , sn65lvds391 , sn75lvds391 slls362g ? september 1999 ? revised january 2016 www.ti.com application information (continued) figure 16. typical lvds eye pattern a generally accepted range of jitter at the receiver inputs that allows data recovery is 5% to 20% of the unit interval (data pulse width). table 2 shows the signaling rate achieved on various cables and lengths at a 5% eye pattern jitter with a typical lvds driver. table 2. signaling rates for various cables for 5% eye pattern jitter cable length a (1) b (2) c (3) d (4) e (5) f (6) (m) (mbps) (mbps) (mbps) (mbps) (mbps) (mbps) 1 240 200 240 270 180 230 5 205 210 230 250 215 230 10 180 150 195 200 145 180 (1) cable a: cat 3, specified up to 16 mhz, no shield, outside conductor diameter ( ? ) 0.52 mm (2) cable b: cat 5, specified up to 100 mhz, no shield, ? 0.52 mm (3) cable c: cat 5, specified up to 100 mhz, taped over all shield, ? 0.52 mm (4) cable d: cat 5 (exceeding cat 5), specified up to 300 mhz, braided over all shield plus taped individual shield for any pair, ? 0.64 mm (awg22) (5) cable e: cat 5 (exceeding cat 5), specified up to 350 mhz, ? 0.64 mm (awg22), no shield (6) cable f: cat 5 (exceeding cat 5), specified up to 350 mhz, self-shielded , ? 0.64 mm (awg22) during synchronous parallel transfers, skew between the data and clock lines will also reduce the timing margin. this should be accounted for in the system timing budget. fortunately, the low output skew of this lvds driver will generally be a small portion of this budget. 11.2 typical application 11.2.1 point-to-point communications the most basic application for lvds buffers, as found in this data sheet, is for point-to-point communications of digital data, as shown in figure 17 . 16 submit documentation feedback copyright ? 1999 ? 2016, texas instruments incorporated product folder links: sn65lvds387 sn75lvds387 sn65lvds389 sn75lvds389 sn65lvds391 sn75lvds391 width abs . jitter height unit interval
sn65lvds387 , sn75lvds387 , sn65lvds389 sn75lvds389 , sn65lvds391 , sn75lvds391 www.ti.com slls362g ? september 1999 ? revised january 2016 typical application (continued) figure 17. point-to-point topology a point-to-point communications channel has a single transmitter (driver) and a single receiver. this communications topology is often referred to as simplex. in figure 17 the driver receives a single-ended input signal and the receiver outputs a single-ended recovered signal. the lvds driver converts the single-ended input to a differential signal for transmission over a balanced interconnecting media of 100- characteristic impedance. the conversion from a single-ended signal to an lvds signal retains the digital data payload while translating to a signal whose features are more appropriate for communication over extended distances or in a noisy environment. 11.2.1.1 design requirements design parameters example value driver supply voltage (v ccd ) 3.0 to 3.6 v driver input voltage 0.8 to 3.3 v driver signaling rate dc to 200 mbps interconnect characteristic impedance 100 termination resistance 100 number of receiver nodes 1 receiver supply voltage (v ccr ) 3.0 to 3.6 v receiver input voltage 0 to 2.4 v receiver signaling rate dc to 200 mbps ground shift between driver and receiver 1 v 11.2.1.2 detailed design procedure 11.2.1.2.1 driver supply voltage the snx5lvdsxx driver is operated from a single supply. the device can support operation with a supply as low as 3 v and as high as 3.6 v. the differential output voltage is nominally 340 mv over the complete output range. the minimum output voltage stays within the specified lvds limits (247 mv to 454 mv) for the complete 3-v to 3.6-v supply range. 11.2.1.2.2 driver bypass capacitance bypass capacitors play a key role in power distribution circuitry. specifically, they create low-impedance paths between power and ground. at low frequencies, a good digital power supply offers very-low-impedance paths between its terminals. however, as higher frequency currents propagate through power traces, the source is quite often incapable of maintaining a low-impedance path to ground. bypass capacitors are used to address this shortcoming. usually, large bypass capacitors (10 f to 1000 f) at the board-level do a good job up into the khz range. due to their size and length of their leads, they tend to have large inductance values at the switching frequencies of modern digital circuitry. to solve this problem, one should resort to the use of smaller capacitors (nf to f range) installed locally next to the integrated circuit. multilayer ceramic chip or surface-mount capacitors (size 0603 or 0805) minimize lead inductances of bypass capacitors in high-speed environments, because their lead inductance is about 1 nh. for comparison purposes, a typical capacitor with leads has a lead inductance around 5 nh. copyright ? 1999 ? 2016, texas instruments incorporated submit documentation feedback 17 product folder links: sn65lvds387 sn75lvds387 sn65lvds389 sn75lvds389 sn65lvds391 sn75lvds391 driver 100 receiver in+ in- out+ out-
sn65lvds387 , sn75lvds387 , sn65lvds389 sn75lvds389 , sn65lvds391 , sn75lvds391 slls362g ? september 1999 ? revised january 2016 www.ti.com the value of the bypass capacitors used locally with lvds chips can be determined by the following formula according to johnson (1) , equations 8.18 to 8.21. a conservative rise time of 200 ps and a worst-case change in supply current of 1 a covers the whole range of lvds devices offered by texas instruments. in this example, the maximum power supply noise tolerated is 200 mv; however, this figure varies depending on the noise budget available in your design. (1) (1) (2) the following example lowers lead inductance and covers intermediate frequencies between the board-level capacitor ( > 10 f) and the value of capacitance found above (0.001 f). you should place the smallest value of capacitance as close as possible to the chip. figure 18. recommended lvds bypass capacitor layout 11.2.1.2.3 driver output voltage the snx5lvdsxx driver output is a 1.2-v common-mode voltage, with a nominal differential output signal of 340 mv. this 340 mv is the absolute value of the differential swing (v od = |v + ? v ? |). the peak-to-peak differential voltage is twice this value, or 680 mv. 11.2.1.2.4 interconnecting media the physical communication channel between the driver and the receiver may be any balanced paired metal conductors meeting the requirements of the lvds standard, the key points which will be included here. this media may be a twisted pair, twinax, flat ribbon cable, or pcb traces. the nominal characteristic impedance of the interconnect should be between 100 and 120 with variation no more than 10% (90 to 132 ). 11.2.1.2.5 pcb transmission lines as per snla187 , figure 19 depicts several transmission line structures commonly used in printed-circuit boards (pcbs). each structure consists of a signal line and a return path with uniform cross-section along its length. a microstrip is a signal trace on the top (or bottom) layer, separated by a dielectric layer from its return path in a ground or power plane. a stripline is a signal trace in the inner layer, with a dielectric layer in between a ground plane above and below the signal trace. the dimensions of the structure along with the dielectric material properties determine the characteristic impedance of the transmission line (also called controlled-impedance transmission line). when two signal lines are placed close by, they form a pair of coupled transmission lines. figure 19 shows examples of edge-coupled microstrips, and edge-coupled or broad-side-coupled striplines. when excited by differential signals, the coupled transmission line is referred to as a differential pair. the characteristic impedance of each line is called odd-mode impedance. the sum of the odd-mode impedances of each line is the differential impedance of the differential pair. in addition to the trace dimensions and dielectric material properties, the spacing between the two traces determines the mutual coupling and impacts the differential impedance. when the two lines are immediately adjacent; for example, s is less than 2 w, the differential pair is called a tightly- coupled differential pair. to maintain constant differential impedance along the length, it is important to keep the trace width and spacing uniform along the length, as well as maintain good symmetry between the two lines. (1) howard johnson & martin graham.1993. high speed digital design ? a handbook of black magic. prentice hall prt. isbn number 013395724. 18 submit documentation feedback copyright ? 1999 ? 2016, texas instruments incorporated product folder links: sn65lvds387 sn75lvds387 sn65lvds389 sn75lvds389 sn65lvds391 sn75lvds391 0.1 f 0.001 f 3.3 v lvds 1a c 200 ps 0.001 f 0.2v ? ? = = m ? ? maximum step change supply current chip rise time maximum power supply noise i c t v d ? ? = ? d ?
sn65lvds387 , sn75lvds387 , sn65lvds389 sn75lvds389 , sn65lvds391 , sn75lvds391 www.ti.com slls362g ? september 1999 ? revised january 2016 figure 19. controlled-impedance transmission lines 11.2.1.2.6 termination resistor as shown earlier, an lvds communication channel employs a current source driving a transmission line which is terminated with a resistive load. this load serves to convert the transmitted current into a voltage at the receiver input. to ensure incident wave switching (which is necessary to operate the channel at the highest signaling rate), the termination resistance should be matched to the characteristic impedance of the transmission line. the designer should ensure that the termination resistance is within 10% of the nominal media characteristic impedance. if the transmission line is targeted for 100- impedance, the termination resistance should be between 90 and 110 . the line termination resistance should be located as close as possible to the receiver, thereby minimizing the stub length from the resistor to the receiver. the limiting case would be to incorporate the termination resistor into the receiver, which is exactly what is offered with the ti ? lvdt receivers. while we talk in this section about point-to-point communications, a word of caution is useful when a multidrop topology is used. in such topologies, line termination resistors are to be located only at the end(s) of the transmission line. in such an environment, lvds receivers could be used for loads branching off the main bus with an lvdt receiver used only at the bus end. 11.2.1.2.7 driver nc pins nc (not connected) pins are pins where the die is not physically connected to the lead frame or package. for optimum thermal performance, a good rule of thumb is to ground the nc pins at the board level. copyright ? 1999 ? 2016, texas instruments incorporated submit documentation feedback 19 product folder links: sn65lvds387 sn75lvds387 sn65lvds389 sn75lvds389 sn65lvds391 sn75lvds391 0 r 87 5.98 h z ln 0.8 w t 1.41 ? h ? 1 > @ > @ 0 r 1.9 2 h t 60 z ln 0.8 w t ? ? h ? 1 s 0.96 h diff 0 z 2 z 1 0.48 e u ? u u u ? ? 1 s 2.9 h diff 0 z 2 z 1 0.347e u ? u u ? ? 1 co-planar coupled microstrips broad-side coupled striplines edge-coupled edge-coupled single-ended microstrip single-ended stripline w h t w t h h s h differential microstrip differential stripline s h s h h g g w w w s
sn65lvds387 , sn75lvds387 , sn65lvds389 sn75lvds389 , sn65lvds391 , sn75lvds391 slls362g ? september 1999 ? revised january 2016 www.ti.com 11.2.1.3 application curve figure 20. typical driver output eye pattern in point-to-point system 11.2.2 multidrop communications a second common application of lvds buffers is a multidrop topology. in a multidrop configuration, a single driver and a shared bus are present along with two or more receivers (with a maximum permissible number of 32 receivers). figure 21 shows an example of a multidrop system. figure 21. multidrop topology 11.2.2.1 design requirements design parameters example value driver supply voltage (v ccd ) 3.0 to 3.6 v driver input voltage 0.8 to 3.3 v driver signaling rate dc to 200 mbps interconnect characteristic impedance 100 termination resistance 100 number of receiver nodes 2 to 32 receiver supply voltage (v ccr ) 3.0 to 3.6 v receiver input voltage 0 to 2.4 v receiver signaling rate dc to 200 mbps ground shift between driver and receiver 1 v 11.2.2.2 detailed design procedure 11.2.2.2.1 interconnecting media the interconnect in a multidrop system differs considerably from a point-to-point system. while point-to-point interconnects are straightforward and well understood, the bus type architecture encountered with multidrop systems requires more careful attention. we will use figure 21 above to explore these details. 20 submit documentation feedback copyright ? 1999 ? 2016, texas instruments incorporated product folder links: sn65lvds387 sn75lvds387 sn65lvds389 sn75lvds389 sn65lvds391 sn75lvds391 driver + | 100 receiver minimize stub lengths minimize stub lengths + receiver + receiver
sn65lvds387 , sn75lvds387 , sn65lvds389 sn75lvds389 , sn65lvds391 , sn75lvds391 www.ti.com slls362g ? september 1999 ? revised january 2016 the most basic multidrop system would include a single driver, located at a bus origin, with multiple receiver nodes branching off the main line, and a final receiver at the end of the transmission line, co-located with a bus termination resistor. while this would be the most basic multidrop system, it has several considerations not yet explored. the location of the transmitter at one bus end allows the design concerns to be simplified, but this comes at the cost of flexibility. with a transmitter located at the origin, a single bus termination at the far-end is required. the far-end termination absorbs the incident traveling wave. the flexibility lost with this arrangement is thus: if the single transmitter needed to be relocated on the bus, at any location other than the origin, we would be faced with a bus with one open-circuited end, and one properly terminated end. locating the transmitter say in the middle of the bus may be desired to reduce (by ? ) the maximum flight time from the transmitter to receiver. another new feature in figure 21 is clear in that every node branching off the main line results in stubs. the stubs should be minimized in any case, but have the unintended effect of locally changing the loaded impedance of the bus. to a good approximation, the characteristic transmission line impedance seen into any cut point in the unloaded multipoint or multidrop bus is defined by l/c, where l is the inductance per unit length and c is the capacitance per unit length. as capacitance is added to the bus in the form of devices and interconnections, the bus characteristic impedance is lowered. this may result in signal reflections from the impedance mismatch between the unloaded and loaded segments of the bus. if the number of loads is constant and can be distributed evenly along the line, reflections can be reduced by changing the bus termination resistors to match the loaded characteristic impedance. normally, the number of loads are not constant or distributed evenly and the reflections resulting from any mismatching should be accounted for in the noise budget. 11.2.2.3 application curve figure 22. typical driver output eye pattern in multidrop system copyright ? 1999 ? 2016, texas instruments incorporated submit documentation feedback 21 product folder links: sn65lvds387 sn75lvds387 sn65lvds389 sn75lvds389 sn65lvds391 sn75lvds391
sn65lvds387 , sn75lvds387 , sn65lvds389 sn75lvds389 , sn65lvds391 , sn75lvds391 slls362g ? september 1999 ? revised january 2016 www.ti.com 12 power supply recommendations the lvds driver and receivers in this data sheet are designed to operate from a single power supply. both drivers and receivers operate with supply voltages in the range of 2.4 v to 3.6 v. in a typical application, a driver and a receiver may be on separate boards, or even separate equipment. in these cases, separate supplies would be used at each location. the expected ground potential difference between the driver power supply and the receiver power supply would be less than | 1 v|. board-level and local device-level bypass capacitance should be used and are covered in driver bypass capacitance . 13 layout 13.1 layout guidelines 13.1.1 microstrip vs stripline topologies as per slld009 , printed-circuit boards usually offer designers two transmission line options: microstrip and stripline. microstrips are traces on the outer layer of a pcb, as shown in figure 23 . figure 23. microstrip topology on the other hand, striplines are traces between two ground planes. striplines are less prone to emissions and susceptibility problems because the reference planes effectively shield the embedded traces. however, from the standpoint of high-speed transmission, juxtaposing two planes creates additional capacitance. ti recommends routing lvds signals on microstrip transmission lines, if possible. the pcb traces allow designers to specify the necessary tolerances for z o based on the overall noise budget and reflection allowances. footnotes 1 (1) , 2 (2) , and 3 (3) provide formulas for z o and t pd for differential and single-ended traces. (1) (2) (3) figure 24. stripline topology 13.1.2 dielectric type and board construction the speeds at which signals travel across the board dictates the choice of dielectric. fr-4, or equivalent, usually provides adequate performance for use with lvds signals. if rise or fall times of ttl/cmos signals are less than 500 ps, empirical results indicate that a material with a dielectric constant near 3.4, such as rogers ? 4350 or nelco n4000-13 is better suited. once the designer chooses the dielectric, there are several parameters pertaining to the board construction that can affect performance. the following set of guidelines were developed experimentally through several designs involving lvds devices: ? copper weight: 15 g or 1/2 oz start, plated to 30 g or 1 oz ? all exposed circuitry should be solder-plated (60/40) to 7.62 m or 0.0003 in (minimum). ? copper plating should be 25.4 m or 0.001 in (minimum) in plated-through-holes. ? solder mask over bare copper with solder hot-air leveling (1) howard johnson & martin graham.1993. high speed digital design ? a handbook of black magic. prentice hall prt. isbn number 013395724. (2) mark i. montrose. 1996. printed circuit board design techniques for emc compliance. ieee press. isbn number 0780311310. (3) clyde f. coombs, jr. ed, printed circuits handbook, mcgraw hill, isbn number 0070127549. 22 submit documentation feedback copyright ? 1999 ? 2016, texas instruments incorporated product folder links: sn65lvds387 sn75lvds387 sn65lvds389 sn75lvds389 sn65lvds391 sn75lvds391
sn65lvds387 , sn75lvds387 , sn65lvds389 sn75lvds389 , sn65lvds391 , sn75lvds391 www.ti.com slls362g ? september 1999 ? revised january 2016 layout guidelines (continued) 13.1.3 recommended stack layout following the choice of dielectrics and design specifications, you should decide how many levels to use in the stack. to reduce the ttl/cmos to lvds crosstalk, it is a good practice to have at least two separate signal planes as shown in figure 25 . figure 25. four-layer pcb board note the separation between layers 2 and 3 should be 127 m (0.005 in). by keeping the power and ground planes tightly coupled, the increased capacitance acts as a bypass for transients. one of the most common stack configurations is the six-layer board, as shown in figure 26 . figure 26. six-layer pcb board in this particular configuration, it is possible to isolate each signal layer from the power plane by at least one ground plane. the result is improved signal integrity; however, fabrication is more expensive. using the 6-layer board is preferable, because it offers the layout designer more flexibility in varying the distance between signal layers and referenced planes, in addition to ensuring reference to a ground plane for signal layers 1 and 6. 13.1.4 separation between traces the separation between traces depends on several factors; however, the amount of coupling that can be tolerated usually dictates the actual separation. low-noise coupling requires close coupling between the differential pair of an lvds link to benefit from the electromagnetic field cancellation. the traces should be 100- ? differential and thus coupled in the manner that best fits this requirement. in addition, differential pairs should have the same electrical length to ensure that they are balanced, thus minimizing problems with skew and signal reflection. in the case of two adjacent single-ended traces, one should use the 3-w rule, which stipulates that the distance between two traces should be greater than two times the width of a single trace, or three times its width measured from trace center to trace center. this increased separation effectively reduces the potential for crosstalk. the same rule should be applied to the separation between adjacent lvds differential pairs, whether the traces are edge-coupled or broad-side-coupled. figure 27. 3-w rule for single-ended and differential traces (top view) copyright ? 1999 ? 2016, texas instruments incorporated submit documentation feedback 23 product folder links: sn65lvds387 sn75lvds387 sn65lvds389 sn75lvds389 sn65lvds391 sn75lvds391 t 2 w w ww minimum spacing as defined by pcb vendor lvds pair ttl/cmos trace differential traces single-ended traces s = layer 4: routed plane (ttl signals) layer 3: power plane layer 2: ground plane layer 1: routed plane (lvds signals) layer 4: ground plane layer 5: ground plane layer 4: routed plane (ttl/cmos signals) layer 3: power plane layer 2: ground plane layer 1: routed plane (lvds signals)
sn65lvds387 , sn75lvds387 , sn65lvds389 sn75lvds389 , sn65lvds391 , sn75lvds391 slls362g ? september 1999 ? revised january 2016 www.ti.com layout guidelines (continued) you should exercise caution when using autorouters, because they do not always account for all factors affecting crosstalk and signal reflection. for instance, it is best to avoid sharp 90 turns to prevent discontinuities in the signal path. using successive 45 turns tends to minimize reflections. 13.1.5 crosstalk and ground bounce minimization to reduce crosstalk, it is important to provide a return path to high-frequency currents that is as close as possible to its originating trace. a ground plane usually achieves this. because the returning currents always choose the path of lowest inductance, they are most likely to return directly under the original trace, thus minimizing crosstalk. lowering the area of the current loop lowers the potential for crosstalk. traces kept as short as possible with an uninterrupted ground plane running beneath them emit the minimum amount of electromagnetic field strength. discontinuities in the ground plane increase the return path inductance and should be avoided. 13.2 layout example at least two or three times the width of an individual trace should separate single-ended traces and differential pairs to minimize the potential for crosstalk. single-ended traces that run in parallel for less than the wavelength of the rise or fall times usually have negligible crosstalk. increase the spacing between signal paths for long parallel runs to reduce crosstalk. boards with limited real estate can benefit from the staggered trace layout, as shown in figure 28 . figure 28. staggered trace layout this configuration lays out alternating signal traces on different layers; thus, the horizontal separation between traces can be less than 2 or 3 times the width of individual traces. to ensure continuity in the ground signal path, ti recommends having an adjacent ground via for every signal via, as shown in figure 29 . note that vias create additional capacitance. for example, a typical via has a lumped capacitance effect of 1/2 pf to 1 pf in fr4. figure 29. ground via location (side view) short and low-impedance connection of the device ground pins to the pcb ground plane reduces ground bounce. holes and cutouts in the ground planes can adversely affect current return paths if they create discontinuities that increase returning current loop areas. to minimize emi problems, ti recommends avoiding discontinuities below a trace (for example, holes, slits, and so on) and keeping traces as short as possible. zoning the board wisely by placing all similar functions in the same area, as opposed to mixing them together, helps reduce susceptibility issues. 24 submit documentation feedback copyright ? 1999 ? 2016, texas instruments incorporated product folder links: sn65lvds387 sn75lvds387 sn65lvds389 sn75lvds389 sn65lvds391 sn75lvds391 signal trace uninterrupted ground plane signal trace uninterrupted ground plane signal via ground via layer 6 layer 1
sn65lvds387 , sn75lvds387 , sn65lvds389 sn75lvds389 , sn65lvds391 , sn75lvds391 www.ti.com slls362g ? september 1999 ? revised january 2016 14 device and documentation support 14.1 device support 14.1.1 third-party products disclaimer ti's publication of information regarding third-party products or services does not constitute an endorsement regarding the suitability of such products or services or a warranty, representation or endorsement of such products or services, either alone or in combination with any ti product or service. 14.1.2 other lvds products for other products and application notes in the lvds and lvdm product families visit our web site at http://www.ti.com/sc/datatran . 14.2 documentation support 14.2.1 related information ibis modeling is available for this device. contact the local ti sales office or the ti web site at www.ti.com for more information. for more application guidelines, see the following documents: ? low-voltage differential signaling design notes ( slla014 ) ? interface circuits for tia/eia-644 (lvds) ( slla038 ) ? reducing emi with lvds ( slla030 ) ? slew rate control of lvds circuits ( slla034 ) ? using an lvds receiver with rs-422 data ( slla031 ) ? evaluating the lvds evm ( slla033 ) 14.3 related links table 3 lists quick access links. categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. table 3. related links technical tools & support & parts product folder sample & buy documents software community sn65lvds387 click here click here click here click here click here sn75lvds387 click here click here click here click here click here sn65lvds389 click here click here click here click here click here sn75lvds389 click here click here click here click here click here sn65lvds391 click here click here click here click here click here sn75lvds391 click here click here click here click here click here 14.4 trademarks rogers is a trademark of rogers corporation. all other trademarks are the property of their respective owners. 14.5 electrostatic discharge caution these devices have limited built-in esd protection. the leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the mos gates. copyright ? 1999 ? 2016, texas instruments incorporated submit documentation feedback 25 product folder links: sn65lvds387 sn75lvds387 sn65lvds389 sn75lvds389 sn65lvds391 sn75lvds391
sn65lvds387 , sn75lvds387 , sn65lvds389 sn75lvds389 , sn65lvds391 , sn75lvds391 slls362g ? september 1999 ? revised january 2016 www.ti.com 14.6 glossary slyz022 ? ti glossary . this glossary lists and explains terms, acronyms, and definitions. 15 mechanical, packaging, and orderable information the following pages include mechanical, packaging, and orderable information. this information is the most current data available for the designated devices. this data is subject to change without notice and revision of this document. for browser-based versions of this data sheet, refer to the left-hand navigation. 26 submit documentation feedback copyright ? 1999 ? 2016, texas instruments incorporated product folder links: sn65lvds387 sn75lvds387 sn65lvds389 sn75lvds389 sn65lvds391 sn75lvds391
package option addendum www.ti.com 14-jan-2016 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples sn65lvds387dgg active tssop dgg 64 25 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 85 lvds387 sn65lvds387dggg4 active tssop dgg 64 25 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 85 lvds387 sn65lvds387dggr active tssop dgg 64 2000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 85 lvds387 sn65lvds387dggrg4 active tssop dgg 64 2000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 85 lvds387 sn65lvds389dbt active tssop dbt 38 50 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 85 lvds389 sn65lvds389dbtg4 active tssop dbt 38 50 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 85 lvds389 sn65lvds389dbtr active tssop dbt 38 2000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 85 lvds389 sn65lvds391d active soic d 16 40 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 85 lvds391 sn65lvds391dg4 active soic d 16 40 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 85 lvds391 sn65lvds391dr active soic d 16 2500 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 85 lvds391 sn65lvds391drg4 active soic d 16 2500 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 85 lvds391 sn65lvds391pw active tssop pw 16 90 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 85 lvds391 sn65lvds391pwg4 active tssop pw 16 90 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 85 lvds391 sn65lvds391pwr active tssop pw 16 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 85 lvds391 sn65lvds391pwrg4 active tssop pw 16 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 85 lvds391 sn75lvds387dgg active tssop dgg 64 25 green (rohs & no sb/br) cu nipdau level-2-260c-1 year 0 to 70 75lvds387 sn75lvds387dggg4 active tssop dgg 64 25 green (rohs & no sb/br) cu nipdau level-2-260c-1 year 0 to 70 75lvds387
package option addendum www.ti.com 14-jan-2016 addendum-page 2 orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples sn75lvds387dggr active tssop dgg 64 2000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year 0 to 70 75lvds387 sn75lvds387dggrg4 active tssop dgg 64 2000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year 0 to 70 75lvds387 sn75lvds389dbt active tssop dbt 38 50 green (rohs & no sb/br) cu nipdau level-2-260c-1 year 0 to 70 75lvds389 sn75lvds389dbtg4 active tssop dbt 38 50 green (rohs & no sb/br) cu nipdau level-2-260c-1 year 0 to 70 75lvds389 sn75lvds389dbtr active tssop dbt 38 2000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year 0 to 70 75lvds389 sn75lvds389dbtrg4 active tssop dbt 38 2000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year 0 to 70 75lvds389 sn75lvds391d active soic d 16 40 green (rohs & no sb/br) cu nipdau level-1-260c-unlim 0 to 70 75lvds391 SN75LVDS391DG4 active soic d 16 40 green (rohs & no sb/br) cu nipdau level-1-260c-unlim 0 to 70 75lvds391 sn75lvds391dr active soic d 16 2500 green (rohs & no sb/br) cu nipdau level-1-260c-unlim 0 to 70 75lvds391 sn75lvds391pw active tssop pw 16 90 green (rohs & no sb/br) cu nipdau level-1-260c-unlim 0 to 70 ds391 sn75lvds391pwg4 active tssop pw 16 90 green (rohs & no sb/br) cu nipdau level-1-260c-unlim 0 to 70 ds391 sn75lvds391pwr active tssop pw 16 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim 0 to 70 ds391 sn75lvds391pwrg4 active tssop pw 16 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim 0 to 70 ds391 (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined.
package option addendum www.ti.com 14-jan-2016 addendum-page 3 pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant sn65lvds387dggr tssop dgg 64 2000 330.0 24.4 8.4 17.3 1.7 12.0 24.0 q1 sn65lvds389dbtr tssop dbt 38 2000 330.0 16.4 6.9 10.2 1.8 12.0 16.0 q1 sn65lvds391dr soic d 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 q1 sn65lvds391pwr tssop pw 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 q1 sn75lvds387dggr tssop dgg 64 2000 330.0 24.4 8.4 17.3 1.7 12.0 24.0 q1 sn75lvds389dbtr tssop dbt 38 2000 330.0 16.4 6.9 10.2 1.8 12.0 16.0 q1 sn75lvds391dr soic d 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 q1 sn75lvds391pwr tssop pw 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 q1 package materials information www.ti.com 14-jan-2016 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) sn65lvds387dggr tssop dgg 64 2000 367.0 367.0 45.0 sn65lvds389dbtr tssop dbt 38 2000 367.0 367.0 38.0 sn65lvds391dr soic d 16 2500 367.0 367.0 38.0 sn65lvds391pwr tssop pw 16 2000 367.0 367.0 35.0 sn75lvds387dggr tssop dgg 64 2000 367.0 367.0 45.0 sn75lvds389dbtr tssop dbt 38 2000 367.0 367.0 38.0 sn75lvds391dr soic d 16 2500 367.0 367.0 38.0 sn75lvds391pwr tssop pw 16 2000 367.0 367.0 35.0 package materials information www.ti.com 14-jan-2016 pack materials-page 2

mechanical data mtss003d january 1995 revised january 1998 post office box 655303 ? dallas, texas 75265 dgg (r-pdso-g**) plastic small-outline package 4040078 / f 12/97 48 pins shown 0,25 0,15 nom gage plane 6,00 6,20 8,30 7,90 0,75 0,50 seating plane 25 0,27 0,17 24 a 48 1 1,20 max m 0,08 0,10 0,50 0 8 56 14,10 13,90 48 dim a max a min pins ** 12,40 12,60 64 17,10 16,90 0,15 0,05 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. body dimensions do not include mold protrusion not to exceed 0,15. d. falls within jedec mo-153
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