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general description the max3880 deserializer with clock recovery is idealfor converting 2.488gbps serial data to 16-bit-wide, 155mbps parallel data for sdh/sonet applications. operating from a single +3.3v supply, this device accepts high-speed serial-data inputs and delivers low- voltage differential-signal (lvds) parallel clock and data outputs for interfacing with digital circuitry. the max3880 includes a low-power clock recovery and data retiming function for 2.488gbps applications. the fully integrated phase-locked loop (pll) recovers a synchronous clock signal from the serial nrz data input; the signal is then retimed by the recovered clock. the max3880? jitter performance exceeds all sdh/sonet specifications. an additional 2.488gbps serial input is available for system loopback diagnostic testing. the device also includes a ttl-compatible loss-of-lock ( lol ) monitor and lvds synchronization inputs that enable data realignment and reframing.the max3880 is available in the extended temperature range (-40? to +85?) in a 64-pin tqfp-ep (exposed pad) package. applications 2.488gbps sdh/sonet transmission systemsadd/drop multiplexers digital cross-connects features ? single +3.3v supply ? 910mw operating power ? fully integrated clock recovery and dataretiming ? exceeds ansi, itu, and bellcore specifications ? additional high-speed input facilitates systemloopback diagnostic testing ? 2.488gbps serial to 155mbps parallel conversion ? lvds data outputs and synchronization inputs ? tolerates >2000 consecutive identical digits ? loss-of-lock indicator max3880 +3.3v, 2.488gbps, sdh/sonet 1:16 deserializer with clock recovery ________________________________________________________________ maxim integrated products 1 max3866 max3880 pre/postamplifier overhead termination 100 ? * *required only if overhead circuit does not include internal input termination. this symbol represents a transmission line of characteristic impedance z 0 = 50 ?. v cc +3.3v phadj- v cc lol gnd fil- fil+ sis ttl ttl sdi+ out+ v cc in+ fil out- lop ttl sdi-slbi- slbi+ systemloopback sync+ sync- pd15+ pd15- 100 ? * pd0+ pd0- 100 ? * pclk+ pclk- phadj+ 0.01 f +3.3v c f 1 f t ypical application circuit 19-1467; rev 2; 12/05 part MAX3880ECB -40? to +85? temp. range pin-package 64 tqfp-ep* ordering information * exposed pad + denotes lead-free package. pin configuration appears at end of data sheet. for free samples and the latest literature, visit www.maxim-ic.com or phone 1-800-998-8800.for small orders, phone 1-800-835-8769. MAX3880ECB+ -40? to +85? 64 tqfp-ep* downloaded from: http:///
max3880 +3.3v, 2.488gbps, sdh/sonet 1:16 deserializer with clock recovery 2 _______________________________________________________________________________________ absolute maximum ratings dc electrical characteristics(v cc = +3.0v to +3.6v, differential loads = 100 ? ?%, t a = -40? to +85?, unless otherwise noted. typical values are at v cc = +3.3v, t a = +25?.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. positive supply voltage (v cc ) ...............................-0.5v to +7.0v input voltage level (sdi+, sdi-, slbi+, slbi-, sync+, sync-)........................... (v cc - 0.5v) to (v cc + 0.5v) input current level (sdi+, sdi-, slbi+, slbi-)................?0ma voltage at lol , sis, phadj+, phadj-, fil+, fil- .................................................-0.5v to (v cc + 0.5v) output current lvds outputs ............................................10ma continuous power dissipation (t a = +85?) tqfp (derate 33.3mw/? above +85?) .......................1.44w operating temperature range ...........................-40? to +85? storage temperature range .............................-55? to +150? lead temperature (soldering, 10s) .................................+300? figure 1 common-mode voltage = 50mv figure 2 differential input voltage = 100mv conditions % ?.5 ?0 ? r o change in magnitude of single-ended output resistance for complementary outputs ? 40 95 140 r o single-ended outputresistance mv ?5 ? v os change in magnitude of outputoffset voltage for complementary states v 1.125 1.275 v os output offset voltage mv ?5 ? | v od | change in magnitude ofdifferential output voltage for complementary states mv 250 400 | v od | differential output voltage v 0.925 v ol output low voltage mvp-p 50 800 v id differential input voltage ma 275 380 i cc supply current v 1.475 v oh output high voltage ? 85 100 115 r in differential input resistance mv 78 v hyst threshold hysteresis mv -100 100 v idth differential input threshold v v cc - 0.4 v cc + 0.2 v is single-ended input voltage ? 50 r in input termination to vcc v 0 2.4 v i input voltage range units min typ max symbol parameter v 0.8 v il input low voltage v 2.0 v ih input high voltage v 2.4 v cc v oh output high voltage ? -10 +10 input current v 0.4 v ol output low voltage serial data inputs (sdi, slbi) lvds inputs and outputs (sync, pclk, pd _ ) ttl inputs and outputs (sis, lol ) downloaded from: http:///
max3880 +3.3v, 2.488gbps, sdh/sonet 1:16 deserializer with clock recovery _______________________________________________________________________________________ 3 ac electrical characteristics(v cc = +3.0v to +3.6v, differential loads = 100 ? ?%, t a = -40? to +85?, unless otherwise noted. typical values are at v cc = +3.3v, t a = +25?.) (note 1) note 1: ac characteristics are guaranteed by design and characterization. note 2: at jitter frequencies <70khz, the jitter tolerance characteristics exceed the itu/bellcore specifications. the low-frequencyjitter tolerance outperforms the instrument? measurement capability. figure 5 100khz to 2.5ghz f = 10mhz f = 70khz (note 2) f = 100khz f = 1mhz 2.5ghz to 4.0ghz conditions db -11 input return loss (sdi? slbi? ps 200 450 900 t clk-q parallel clock-to-data outputdelay mbps 155.52 gbps 2.488 sdi serial data rate parallel output data rate -18 bits >2,000 tolerated consecutive identicaldigits uip-p 0.28 0.46 jitter tolerance 2.31 3.3 1.74 2.41 0.38 0.57 units min typ max symbol parameter sdi+ sdi- v id (sdi+) - (sdi-) 50mvp-p min800mvp-p max 25mv min400mv max single-ended output | v od | v pd- v oh v os v od , p-p = v pd+ - v pd- -v od +v od 0v 0v (diff) v ol v pd+ differential output v pd+ - v pd- d pd+ r l = 100 ? v od pd- v figure 1. input amplitude figure 2. driver output levels downloaded from: http:///
max3880 +3.3v, 2.488gbps, sdh/sonet 1:16 deserializer with clock recovery 4 _______________________________________________________________________________________ 0 10 1,000 100 jitter tolerance vs. input voltage 0.30.1 0.60.4 0.8 0.2 0.70.5 max3880-04 input voltage (mvp-p) jitter tolerance (uip-p) jitter frequency = 1mhz jitter frequency = 5mhz sonet spec 10 -10 10 -8 10 -9 10 -6 10 -7 10 -4 10 -5 10 -3 6.0 7.0 6.5 7.5 8.0 8.5 9.0 9.5 10.0 bit error rate vs. input voltage max3880-05 input voltage (mvp-p) bit error rate 200 300 400 600500 700 -50 0 -25 25 50 75 100 parallel clock to data output propagation delay vs. temperature max3880-06 temperature (?) pclk to data output propagation delay (ps) t ypical operating characteristics (v cc = +3.3v, t a = +25?, unless otherwise noted.) 1.64ns/div data clock recovered data and clock (differential output) max3880-01 2 23 - 1 pattern 240 250 260 270 280 290 300 -50 -25 0 25 50 75 100 supply current vs. temperature max3880-02 temperature (?) supply current (ma) v cc = 3.6v v cc = 3.0v 10 0.1 10 1,000 10,000 jitter tolerance 1 max3880-03 jitter frequency (khz) input jitter (uipp-p) 100 downloaded from: http:///
max3880 +3.3v, 2.488gbps, sdh/sonet 1:16 deserializer with clock recovery _______________________________________________________________________________________ 5 name function 1, 17, 25, 33, 41, 49, 56, 62, 64 gnd ground pin pin description 2 fil+ positive filter input. pll loop filter connection. connect a 1.0? capacitor between fil+ and fil-. 3 fil- negative filter input. pll loop filter connection. connect a 1.0? capacitor between fil+ and fil-. 4, 7, 10, 13, 24, 32, 40, 48, 57 v cc +3.3v supply voltage 5 phadj+ positive phase-adjust input. used to optimally align internal pll phase. connect to v cc if not used. 6 phadj- negative phase-adjust input. used to optimally align internal pll phase. connect to v cc if not used. 8 sdi+ positive serial data input. 2.488gbps data stream. 9 sdi- negative serial data input. 2.488gbps data stream. 11 slbi+ positive system loopback input. 2.488gbps data stream. 12 slbi- negative system loopback input. 2.488gbps data stream. 14 sis signal input selection. ttl low for normal data input (sdi). ttl high for system loopback input(slbi). 15 sync- negative synchronizing pulse lvds input. pulse the sync signal high for at least four serial-databit periods (1.6ns) to shift the data alignment by dropping 1 bit. 16 sync+ positive synchronizing pulse lvds input. pulse the sync signal high for at least four serial-databit periods (1.6ns) to shift the data alignment by dropping 1 bit. 18 pclk- negative parallel clock lvds output 19 pclk+ positive parallel clock lvds output 20, 22, 26,28, 30, 34, 36, 38, 42, 44, 46, 50, 52, 54, 58, 60 pd0- to pd15- negative parallel data lvds outputs. data is updated on the negative transition of the pclksignal (figure 5). 21, 23, 27,29, 31, 35, 37, 39, 43, 45, 47, 51, 53, 55, 59, 61 pd0+ to pd15+ positive parallel data lvds outputs. data is updated on the negative transition of the pclksignal (figure 5). 63 lol loss-of-lock output. pll loss-of-lock monitor, ttl active low (internal 10k ? pull-up resistor). the lol monitor is valid only when a data stream is present on the inputs to the max3880. ep exposed pad ground. this must be soldered to a circuit board for proper thermal performance (see package information ). downloaded from: http:///
max3880 +3.3v, 2.488gbps, sdh/sonet 1:16 deserializer with clock recovery 6 _______________________________________________________________________________________ max3880 sdi+ amp lvds pd15+pd15- lvds lvds lvds lvds lol ttl 100 ? 50 ? 50 ? mux phase & frequency detector sdi- slbi+ amp slbi- sis v cc v cc sync- sync+ loop filter vco 16-bit demultiplexer d q ck phadj+ phadj- fil+ fil- clock divider pd1+pd1- pd0+pd0- pclk+pclk- figure 3. max3880 functional diagram detailed description the max3880 deserializer with clock recovery converts2.488gbps serial data to 16-bit-wide, 155mbps parallel data. the device combines a fully integrated phase- locked loop (pll), input amplifier, data retiming block, 16-bit demultiplexer, clock divider, and lvds output buffer (figure 3). the pll consists of a phase/frequen- cy detector (pfd), a loop filter, and a voltage-controlled oscillator (vco). the max3880 is designed to deliver the best combination of jitter performance and power dissipation by using a fully differential signal architec- ture and low-noise design techniques. the pll recov- ers the serial clock from the serial input data stream. the demultiplexer generates a 16-bit-wide 155mbps parallel data output. the synchronization inputs (sync+, sync-) realign the output data word. realignment is guaranteed to occur within two complete pclk cycles of the sync signal? positive transition. during synchronization, the first incoming bit of data during that pclk cycle is downloaded from: http:///
max3880 +3.3v, 2.488gbps, sdh/sonet 1:16 deserializer with clock recovery _______________________________________________________________________________________ 7 dropped, shifting the alignment between pclk anddata by 1 bit. the sync signal must be at least four serial bit periods wide (4 x 402ps). see figure 4 for the timing diagram and figure 5 for the timing parameters diagram. input amplifier the input amplifiers on both the main data and systemloopback accept a differential input amplitude from 50mvp-p to 800mvp-p. the bit error rate (ber) is bet- ter than 1 x 10 -10 for input signals as small as 9.5mvp- p, although the jitter tolerance performance will bedegraded. for interfacing with pecl signal levels, see applications information . phase detector the phase detector in the max3880 produces a volt- age proportional to the phase difference between the incoming data and the internal clock. because of its feedback nature, the pll drives the error voltage to zero, aligning the recovered clock to the center of the incoming data eye for retiming. the external phase adjust pins (phadj+, phadj-) allow the user to vary the internal phase alignment. frequency detector the digital frequency detector (fd) aids frequencyacquisition during start-up conditions. the frequency difference between the received data and the vco clock is derived by sampling the in-phase and quadra-ture vco outputs on both edges of the data input sig- nal. depending on the polarity of the frequency difference, the fd drives the vco until the frequency difference is reduced to zero. once frequency acquisi- tion is complete, the fd returns to a neutral state. false locking is completely eliminated by this digital frequen- cy detector. loop filter and vco the phase detector and frequency detector outputs are summed into the loop filter. a 1.0? capacitor, c f , is required to set the pll damping ratio. the loop filter output controls the on-chip lc vco run- ning at 2.488ghz. the vco provides low phase noise and is trimmed to the correct frequency. loss-of-lock monitor a loss-of-lock ( lol ) monitor is included in the max3880 frequency detector. a loss-of-lock conditionis signaled immediately with a ttl low. when the pll is frequency-locked, lol switches to ttl high in approxi- mately 800ns.note that the lol monitor is only valid when a data stream is present on the inputs to the max3880. as aresult, lol does not detect a loss-of-power condition resulting from a loss of the incoming signal. sdi sync pclk d0 d15 d14 d13 d16 d32 d48 1 bit has slippedin this time slice d65 (lsb) pd0 d1 d17 d33 d49 d66 pd1 d15 (msb) transmitted first d31 d47 d64 d80 pd15 figure 4. timing diagram downloaded from: http:///
max3880 +3.3v, 2.488gbps, sdh/sonet 1:16 deserializer with clock recovery 8 _______________________________________________________________________________________ low-voltage differential-signal (lvds) inputs and outputs the max3880 features lvds inputs and outputs forinterfacing with high-speed digital circuitry. the lvds standard is based on the ieee 1596.3 lvds specifica- tion. this technology uses 500mvp-p to 800mvp-p dif- ferential low-voltage swings to achieve fast transition times, minimize power dissipation, and improve noise immunity. for proper operation, the parallel clock and data lvds outputs (pclk+, pclk-, pd_+, pd_-) require 100 ? differential dc termination between the positive and negative outputs. do not terminate theseoutputs to ground. the synchronization lvds inputs (sync+, sync-) are internally terminated with 100 ? differential input resistance and therefore do not requireexternal termination. design procedure jitter tolerance and input sensitivity trade-offs when the received data amplitude is higher than 50mvp-p, the max3880 provides a typical jitter toler- ance of 0.46 ui at jitter frequencies greater than 10mhz. the sdh/sonet jitter tolerance specification is 0.15ui, leaving a jitter allowance of 0.31ui for receiver preamplifier and postamplifier design. the ber is better than 1 x 10 -10 for input signals greater than 9.5mvp-p. at 25mvp-p, jitter tolerance willbe degraded, but will still be above the sdh/sonet requirement. trade-offs can be made between jitter tol- erance and input sensitivity according to the specific application. see the typical operating characteristics for jitter tolerance and ber vs. input voltage graphs. applications information consecutive identical digits (cids) the max3880 has a low phase and frequency drift inthe absence of data transitions. as a result, long runs of consecutive zeros and ones can be tolerated while maintaining a ber of 1 x 10 -10 . the cid tolerance is tested using a 2 13 - 1 pseudorandom bit stream (prbs), substituting a long run of zeros to simulate theworst case. a cid tolerance of greater than 2,000 bits is typical. phase adjust the internal clock is aligned to the center of the dataeye. for specific applications, this sampling position can be shifted using the phadj inputs to optimize ber performance. the phadj inputs operate with differen- tial input voltages up to ?.5v. a simple resistor-divider with a bypass capacitor is sufficient to set these levels (figure 6). when the phadj inputs are not used, they should be tied directly to v cc . system loopback the max3880 is designed to allow system loopbacktesting. the user can connect a serializer output (max3890) in a transceiver directly to the slbi+ and slbi- inputs of the max3880 for system diagnostics. to select the slbi inputs, apply a ttl logic high to the sis pin. pclk pd0?d15 note: signals shown are differential. for example, pclk = (pclk+) - (pclk-). t clk-q figure 5. timing parameters max3880 phadj+ (pin 5) phadj- (pin 6) 3.3v figure 6. phase-adjust resistor-divider downloaded from: http:///
max3880 +3.3v, 2.488gbps, sdh/sonet 1:16 deserializer with clock recovery _______________________________________________________________________________________ 9 interfacing with pecl input levels when interfacing with differential pecl input levels, it isimportant to attenuate the signal while still maintaining 50 ? termination (figure 7). ac-coupling is also required to maintain the input common-mode level. layout techniques for best performance, use good high-frequency layout techniques. filter voltage supplies, keep ground con- nections short, and use multiple vias where possible. use controlled impedance transmission lines to inter- face with the max3880 high-speed inputs and outputs. power-supply decoupling should be placed as close to v cc as possible. to reduce feedthrough, take care to isolate the input signals from the output signals. max3880 50 ? 50 ? v cc 100 ? pecl levels sdi+ 25 ? 25 ? 0.1 f 0.1 f sdi- figure 7. interfacing with pecl input levels chip information transistor count: 4102 downloaded from: http:///
max3880 +3.3v, 2.488gbps, sdh/sonet 1:16 deserializer with clock recovery 10 ______________________________________________________________________________________ pin configuration pd13- pd13+ gnd v cc pd14- pd14+gnd pd11- pd11+ pd12- pd12+ pd15- pd15+ gnd lol gnd slbi+ v cc sdi- sdi+ v cc phadj- sync+ sync- sis v cc slbi- phadj+ v cc fil- fil+ gnd pclk- pclk+ pd0- pd0+ pd1- pd1+ v cc gnd pd2- pd2+ pd3- pd3+ pd4- pd4+ v cc gnd pd10+ top view pd10-pd9+ pd9- pd8+ pd8- gnd v cc pd7+pd7- pd6+ pd6- pd5+pd5- gnd v cc tqfp-ep 58 59 60 61 62 54 55 56 57 63 38 39 40 41 42 43 44 45 46 47 52 53 49 50 51 33 34 35 36 37 48 64 23 22 21 20 19 27 26 25 24 18 29 28 32 31 30 17 11 10 9 8 7 6 5 4 3 2 16 15 14 13 12 1 max3880 downloaded from: http:///
max3880 +3.3v, 2.488gbps, sdh/sonet 1:16 deserializer with clock recovery ______________________________________________________________________________________ 11 64l, tqfp.eps c 1 2 21-0084 package outline,64l tqfp, 10x10x1.0mm ep option package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages .) downloaded from: http:///
max3880 +3.3v, 2.488gbps, sdh/sonet 1:16 deserializer with clock recovery maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 12 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2005 maxim integrated products printed usa is a registered trademark of maxim integrated products, inc. c 2 2 21-0084 package outline,64l tqfp, 10x10x1.0mm ep option package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages .) downloaded from: http:///

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