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evaluates: max11259 MAX11259PMB peripheral module general description the MAX11259PMB peripheral module (pmod?) provides the necessary hardware to interface to the max11259, a 24-bit, 6-channel, 64ksps, integrated pga delta-sigma adc to any system that utilizes pmod-compatible expan - sion ports configurable for i 2 c communication. the peripheral module includes a graphical user interface (gui) that provides communication from the target device to the pc through the usb2pmb2#. the peripheral mod - ule can operate in multiple modes: 1) using usb2pmb2# adapter: in standalone mode, the peripheral module is connected to the pc via a usb2pmb2# adapter board and performs a subset of the complete peripheral module functions with limita - tions for sample rate, sample size, and no support for coherent sampling. 2) user-supplied i 2 c mode: the peripheral module pro - vides a 12-pin pmod-style header for user-supplied i 2 c interface to connect the signals for scl, sda, rstb, and rdyb. the peripheral module includes windows xp ? , windows ? 7, and windows 8.1-compatible software for exercising the features of the ic. the peripheral module gui allows different sample sizes, adjustable sampling rates, internal or external reference options, and graphing software that includes the fft and histogram of the sampled signals. the peripheral module can be powered by a local +3.3v supply and comes installed with a max11259awx+ in a 36-bump wlp package. features various sample sizes and sample rates time domain, frequency domain, and histogram plotting on-board voltage reference (max6072) proven pcb layout fully assembled and tested windows xp-, windows 7-, and windows 8.1-compatible software pmod is a trademark of digilent inc. windows and windows xp are registered trademarks and reg - istered service marks of microsoft corporation. ordering information appears at end of data sheet. 19-7738; rev 0; 9/15 downloaded from: http:///
maxim integrated 2 www.maximintegrated.com evaluates: max11259 MAX11259PMB peripheral module MAX11259PMB photo downloaded from: http:///
maxim integrated 3 www.maximintegrated.com evaluates: max11259 MAX11259PMB peripheral module quick start required equipment MAX11259PMB +3.3v (50ma) for the MAX11259PMB micro-usb cable usb2pmb2# adapter function generator (optional) windows xp, windows 7, or windows 8.1 pc with a spare usb port note: in the following section(s), software-related items are identified by bolding. text in bold refers to items direct - ly from the ev system software. text in bold and under - line refers to items from the windows operating system. procedure the peripheral module is fully assembled and tested. follow the steps below to verify board operation: 1) visit www.maximintegrated.com/evkitsoftware to download the latest version of the peripheral mod - ule software, max11253_54_59evkitsetup v1.12. zip. save the peripheral module software to a temporary folder and uncompress the zip ile. 2) install the peripheral module software and usb driver on your computer by running the max11253_54_59evkitsetupv1.12.exe program in - side the temporary folder. the program iles are cop - ied to your pc and icons are created in the windows start | programs menu. at the end of the installation process the installer will launch the installer for the ftdichip cdm drivers. 3) verify that all jumpers are in their default positions for the peripheral module board ( table 1 ). file decription max11253_54_59evkitsetupv1.12.exe application program (gui) system block diagram MAX11259PMB peripheral module files downloaded from: http:///
maxim integrated 4 www.maximintegrated.com evaluates: max11259 MAX11259PMB peripheral module 4) connect the pc to the peripheral module via the usb2pmb2 adapter board using a micro-usb cable. 5) start the peripheral module software by opening its icon in the start | programs menu. the peripheral module software appears as shown in figure 1 . from the device menu select standalone . verify that the lower left status bar indicates the ev kit hardware is connected . 6) connect the positive terminal of the function genera - tor to the ch0+ (j11-1) test point on the peripheral module. connect the negative terminal of the function generator to the ch0- (j11-2) test point on the periph - eral module. 7) conigure the signal source to generate a 100hz, 1v p-p sinusoidal wave with +1v offset. 8) turn on the function generator. 9) in the coniguration group of the device menu, select channel 0 and click convert in the serial interface menu. 10) click on the scope tab. 11) check the remove dc offset checkbox to remove the dc component of the sampled data. 12) click the capture button to start the data analysis. 13) the peripheral module software appears as shown in figure 1 . 14) verify that the frequency, which is displayed on the right, is approximately 100hz. the scope image has buttons in the upper right corner that allow zooming in to detail. downloaded from: http:///
maxim integrated 5 www.maximintegrated.com evaluates: max11259 MAX11259PMB peripheral module table 1. MAX11259PMB board jumper settings *default configuration header jumper position description jmp1/jmp2 1-2*/1-2* select address 0x30 1-2/1-3 select address 0x31 1-2/1-4 select address 0x33 1-3/1-2 select address 0x34 1-3/1-3 select address 0x35 1-3/1-4 select address 0x37 1-4/1-2 select address 0x3c 1-4/1-3 select address 0x3d 1-4/1-4 select address 0x3f j2 1-2 use max6072 v ref /2 as vcom 2-3* use gnd as vcom j4 1-2* select +3.3v for dvdd open select user-provided supply for dvdd at j4-1 j5 1-2* select +3.0v for avdd open select user-provided supply for dvdd at j5-1 j6 1-2* select gnd for avss open select user-provided supply for avss at j6-1 j7 open* use internal 1.8v subregulator if dvdd 2.0v 1-2 use dvdd for internal logic if dvdd 2.0v j8 1-2* select v ref from the on-board max6072 as the voltage reference 2-3 select avdd as the voltage reference downloaded from: http:///
maxim integrated 6 www.maximintegrated.com evaluates: max11259 MAX11259PMB peripheral module general description of software the main window of the peripheral module software con - tains seven tabs: configuration, scope, dmm, histogram, fft, scan mode, and registers. the configuration tab provides control for the adc configuration including cali - bration and data capture. the other six tabs are used for evaluating the data captured by the adc. coniguration tab the configuration tab provides an interface for selecting and configuring the adc from a functional perspective. select the desired device in the drop-down menu and the corresponding properties of the device are displayed includ - ing channel number, sample rate , number of samples , reference voltage , sequencing mode , calibration , gpo/gpio selection , input path (direct or internal pga) , delta-sigma modulator type selection for different data format and conversion mode , serial interface function ( convert , and read all ), power setting ( nop , power down , and standby ), reset registers , and rstb reset , clock/sync ( internal or external clock , and disable or enable sync mode ), and other for disable or enable current sink/source and capreg ldo . the sample settings are available on the left of the config - uration menu, which allow the user to select the channel , sample rate , and number of samples . the read data and status information is displayed on the right, which shows the data in both voltage and hex, the sample rate, and power state for the selected chan - nel. in addition, if there are any errors, the indicator lights will turn red. channel selection to select the desired channel among the six available channels, click channel # drop-down menu at the top left and select the desired channel from 0 to 5. the default selection is channel 0 . figure 1. peripheral module software (configuration tab) downloaded from: http:///
maxim integrated 7 www.maximintegrated.com evaluates: max11259 MAX11259PMB peripheral module sample rate (sps) to select the desired data rate for single-cycle mode from 50sps to 12800sps and for continuous mode data rate from 1.9sps to 64000sps, choose the sample rate (sps) from the drop-down menu below the channel # selection. reference voltage there are two different reference voltages available on board: max6072aut18+ (2.5v), and avdd (+3.0v). to select 2.5v, connnect j8-1 to j8-2. to select 3.0v, con - nect j8-2 to j8-3.sequencer mode to change the sequencer mode, click the sequence mode selection below the sequencing menu and select mode 1, 2, or 3 as desired. check the gpo sequencer mode box to enable gpo/gpio function in mode 3. in addition, check the enable box to enable the mux and gpo delay . choose the desired delay in microseconds by clicking on the + or C buttons. adc calibration two types of software calibration for offset and gain are available: self calibration and system calibration. the primary mode for calibration is using the drop-down list to select a calibration mode, followed by clicking the calibrate button. the checkboxes for self offset , self gain , system offset , and system gain allow for the user to enable or disable the calibration values. the cali - bration values can also be changed manually by entering a hex value in the numeric box. gpo/gpio to select gpo or gpio ports, choose the option under the gpo/gpio drop-down menu and check the enable box. input pathselect direct under the input path drop-down menu to bypass the internal amplifiers and apply the analog input signals directly to the MAX11259PMB inputs at j11. select pga under the input path drop-down menu to use the internal programmable gain amplifiers.delta-sigma modulator to select the desired data format, click the data format drop-down menu under the delta-sigma modulator section and choose either bipolar or unipolar with twos complement or offset binary options. three conversion modes are provided: continuous , single cycle , and single continuous . click the conversion modes drop-down menu under the delta- sigma modulator section to select the desired conver - sion mode. serial interface to starting converting, click the convert button under the serial interface section. to read all registers, click the read all button. power the MAX11259PMB peripheral module features three power-down states: normal operating power (nop) , power down , and standby . select the desired power state by clicking the drop-down menu under the power section. to reset the configuration settings back to default values, press the reset registers button. to exercise the power-on reset feature, click the rstb button.clock/sync the internal clock mode is set at default condition. to use user-supplied external clock, select external under the clock/sync section and connect the external clock signal to j9-1, gpio0/clk pin. in addition, the sync mode can be enabled or disabled by clicking the drop- down menu under this clock/sync section and connect the external sync signal to j9-2, gpio1/sync. the sync signal should be provided externally. other to enable (j7 open) or disable (j7 installed and v ddvd 2.0v) the internal capreg ldo for digital and i/o sup - ply, select this option from the drop-down menu under the other section. additionally, current sink/source can also be disabled or enabled under this section. read data and statusthe read data and status on the far right hand side of this configuration menu depicts the received data and status of the device such as the selected channel, data rate, sample rate, and power state. click the read data and status button to view the updated status. to save a configuration, select save adc config as in the file menu. this saves all the adc register values to a xml file. to load a configuration, select load adc config in the file menu. when the xml file is loaded, all the reg - ister values in the file are written to the adc. downloaded from: http:///
maxim integrated 8 www.maximintegrated.com evaluates: max11259 MAX11259PMB peripheral module scope tab the scope tab sheet is used to capture data and display it in the time domain. the desired channel # , sample rate , number of samples , display unit , average samples , and resolution selection can also be set in this tab if they were not appropriately adjusted in other tabs. the display unit drop-down list allows counts in lsb and voltages in v, mv, or v. once the desired configuration is set, click on the capture button. the right side of the tab sheet displays details of the waveform, such as average, standard deviation, maximum, minimum, and fundamen - tal frequency as shown in figure 2 . to save the captured data to a file, select options > save graph > scope . this saves the setting on the left and the data captured to a csv file. figure 2. peripheral module software (scope tab) downloaded from: http:///
maxim integrated 9 www.maximintegrated.com evaluates: max11259 MAX11259PMB peripheral module dmm tab the dmm tab sheet provides the typical information as a digital multimeter. once the desired configuration is set, click on the capture button. figure 3 displays the results shown by the dmm tab when a 1.5v signal is applied to ain0+ and 1.0v to ain0-. figure 3. peripheral module software (dmm tab) downloaded from: http:///
maxim integrated 10 www.maximintegrated.com evaluates: max11259 MAX11259PMB peripheral module histogram tab the histogram tab sheet is used to show the histogram of the data. sample rate and number of samples can also be set in this tab if they were not appropriately adjusted in other tabs. once the desired configuration is set, click on the capture button. the right side of the tab sheet displays details of the histogram such as average, stan - dard deviation, maximum, minimum, peak-to-peak noise, effective resolution, and noise-free resolution as shown in figure 4 . the histogram tab is enabled at default. using the histogram will slow down the gui response. to disable it, check the disable histogram box. to save the histogram data to a file, go to options > save graph > histogram . this saves the setting on the left and the histogram data captured to a csv file. figure 4. peripheral module software (histogram tab) downloaded from: http:///
maxim integrated 11 www.maximintegrated.com evaluates: max11259 MAX11259PMB peripheral module fft tab the fft tab sheet is used to display the fft of the data. the sample rate , number of samples , resolution and window function type can be set as desired. to calcu - late the adjusted input signal frequency for coherent sampling , enter the input signal frequency in hertz and push the calculate button. once the preferred configura - tion is set, click on the capture button. the right side of the tab displays the performance based on the fft, such as fundamental frequency, snr, sinad, thd, sfdr, enob, and noise floor as shown in figure 5 . to save the fft data to a file, go to options > save graph > fft . this saves the setting on the left and the fft data captured to a csv file. when coherent sampling is needed, this tab allows the user to calculate the external clock frequen - cy applied to the board. adjust the input frequency of the low-jitter clock to the value as shown in the adjusted master clock (hz) and apply it to the ev kit ext_clk connector. see the sync input and sync output section before using this feature. figure 5. peripheral module software (fft tab) downloaded from: http:///
maxim integrated 12 www.maximintegrated.com evaluates: max11259 MAX11259PMB peripheral module figure 6 shows the setup maxim integrated uses to capture data for coherent sampling. for coherent fft evaluation, use the jumper settings from table 1 for proper configurations. the low-jitter clock is synchronized with the signal generator at 10mhz from the external clock generator. to achieve coherent sampling, click on the calculate button and enter the adjusted master clock (hz) frequency of approximately 8.192mhz into our low-jitter clock. timing for all i 2 c timing and sampling rate are based off the system clock. figure 6. peripheral module coherent sampling setup downloaded from: http:///
maxim integrated 13 www.maximintegrated.com evaluates: max11259 MAX11259PMB peripheral module scan mode tab the scan mode tab is used to perform selected data conversions and read the converted data.in the sequence setting section at the bottom, set the desired sequencer mode (2 or 3) from the sequence mode drop-down menu and select whether to assert the rdyb pin after one channel or after scan com - pletes options under the rdyb menu. check the gpo sequencer mode and enable boxes as desired. then set the conversion time delay in s for mux and gpo by clicking on the + or - buttons under the mux delay and gpo delay menu, allowing for high impedance source networks to stabilize after the channels are selected. finally press the read all button to view the selected settings.in the read data section on top, select the desired unit in either lsb or voltage (v, mv, or v) under the display unit drop-down menu. then choose the desired sample rate by clicking on the sample rate drop-down menu under. finally, click the scan button to start convert - ing and press the read data button to view the con - verted data displayed on the right hand side as shown in figure 7 . figure 7. peripheral module software (scan mode tab) downloaded from: http:///
maxim integrated 14 www.maximintegrated.com evaluates: max11259 MAX11259PMB peripheral module adc registers tab the registers tab sheet shows the device registers on the left. the middle section shows the descriptions of the selected register. click read all to read all registers and refresh the window with the register settings. to write a register first select the hex value in the value column, type the desired hex value and press enter . the command byte is on the right side of the tab sheet. this byte precedes all i 2 c transactions and is described in the ic data sheet. to send a command byte enter a hex value in the numeric box and click the send button. the command byte has two different formats includ - ing conversion command and register read/write . select the radio button for the desired mode to see the bit description in the table. see figure 8 . detailed description of hardware the MAX11259PMB peripheral module provides a proven signal path and board layout to demonstrate the perfor - mance of the max11259awx 24-bit, delta-sigma adc. included in the peripheral module are digital isolators, ultra-low-noise ldos to all supply pins of the ic, on-board reference (max6072), and sync-in and sync-out signals for coherent sampling. the usb2pmb2 ftdi controller is provided to allow for evaluation in standalone mode, which has limitations on maximum sample speed and on sample depth. the peripheral module can be used with fpga to achieve full speed and a larger sample depth. the peripheral module supports a number of different devices as listed in table 2 . figure 8. peripheral module software (adc registers tab) downloaded from: http:///
maxim integrated 15 www.maximintegrated.com evaluates: max11259 MAX11259PMB peripheral module user-supplied i 2 c to evaluate the peripheral module with a user-supplied i 2 c bus, apply the user-supplied i 2 c signals to j1. make sure the return ground is connected to MAX11259PMB ground. voltage references there are two different reference voltages available on board: max6072 (2.5v), avdd (3.0v). to select 2.5v, connect j8-1 to j8-2. to select 3.0v, connect j8-2 to j8-3. for user-supplied external references, remove jumper j8 and connect a reference voltage to j8-2. measure and enter the value of the external reference voltage into the reference voltage edit box on the configuration tab of the gui. table 2 depicts the reference source options. external dvdd power supply the internal 1.8v regulator can be replaced by an exter - nal supply in the range of 1.7v to 2.0v. to use external dvdd, disable the internal regulator by selecting the disable in the capreg ldo drop-down menu in the other section and install j7.user-supplied power supply the peripheral module receives power from a single dc source of +3.3v (50ma) through the standard pmod connector, j1, to provide supply to dvdd. the power is then regulated to +3.0v supply for avdd and max6072 voltage reference. see the peripheral module schematic pdf for details. specific voltages can be connected to the board, see table 2 for corresponding jumper positions. table 2. reference source options table 3. power supply to the board ref source jumper connection function max6072 (2.5v) j8 1-2 select u3 max6072 avdd j8 2-3 select avdd user-supplied j8 open. connect user-supplied reference to j8-2 select user-supplied reference power jumpers an external +3.3v j1-6 downloaded from: http:///
maxim integrated 16 www.maximintegrated.com evaluates: max11259 MAX11259PMB peripheral module external clock for coherent sampling set the external low jitter clock generator with the value calculated by the gui in the fft tab. connect the output of the clock generator to gpio0/clk pin (j9-1). the relationship between f in , f s , n cycles , and m samples is given as follows: cycles in s samples n f fm = where:f in = input frequency f s = sampling frequency n cycles = prime number of cycles in the sampled set m samples = total number of samples #denotes rohs compliant. the MAX11259PMB# comes with a max11259awx+ in a 36-bump wlp package. part type MAX11259PMB# peripheral module usb2pmb2# munich adapter board max11259sys1# peripheral module and munich adapter board component list, schematics, and pcb layout diagrams see the following links for component information, sche - matic diagrams, and pcb layout diagrams: MAX11259PMB bom MAX11259PMB schematics MAX11259PMB pcb layout ordering information downloaded from: http:///
maxim integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim integrated product. no circuit patent licenses are implied. maxim integrated reserves the right to change the circuitry and speciications without n otice at any time. maxim integrated and the maxim integrated logo are trademarks of maxim integrated products, inc. ? 2015 maxim integrated products, inc. 17 evaluates: max11259 MAX11259PMB peripheral module revision number revision date description pages changed 0 9/15 initial release revision history for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim integrateds website at www.maximintegrated.com. downloaded from: http:///
title: bill of materials date: 06/15/2015 design: MAX11259PMB rev a item qty ref des mfg part # manufacturer value description 1 7 c1, c8, c12, c19-c21, c27 c1608x7r1v105k080ac tdk 1uf capacitor; smt (0603); ceramic chip; 1uf; 35v; tol=10%; tg=-55 degc to +125 degc; tc=x7r 2 7 c2-c7, c25 grm1555c1h102ja01; c1005c0g1h102j050 murata; tdk 1000pf capacitor; smt (0402); ceramic chip; 1000pf; 50v; tol=5%; tg=-55 degc to +125 degc 3 6 c9, c11, c15-c17, c26 c0603c104k5rac; c1608x7r1h104k kemet; tdk 0.1uf capacitor; smt (0603); ceramic chip; 0.1uf; 50v; tol=10%; tg=-55 degc to +125 degc; tc=x7r;note: not recommended for new design use 20-000u1-01 4 2 c10, c18 c1608c0g1e103j tdk 0.01uf capacitor; smt (0603); ceramic chip; 0.01uf; 25v; tol=5%; model=; tg=-55 degc to +125 degc; tc=c0g 5 5 c13, c14, c22-c24 c2012x7r1e475k125ab tdk 4.7uf capacitor; smt (0805); ceramic chip; 4.7uf; 25v; tol=10%; model=; tg=-55 degc to +125 degc; tc=x7r 6 1 j1 tsw-106-08-s-d-ra samtec tsw-106-08-s-d-ra connector; through hole; double row; right angle; 12pins; this part is dedicated for pmod peripheral board 7 2 j2, j8 pcc03saan sullins pcc03saan connector; male; through hole; breakaway; straight through; 3pins; -65 degc to +125 degc 8 1 j3 pbc12saan sullins electronics co pbc12saan connector; male; through hole; breakaway; straight; 12pins; -65 degc to +125 degc 9 4 j4-j7 pcc02saan sullins pcc02saan connector; male; through hole; breakaway; straight through; 2pins; -65 degc to +125 degc 10 1 j9 pbc07saan sullins electronics co pbc07saan connector; male; through hole; breakaway; straight; 7pins; -65 degc to +125 degc 11 1 j10 pbc06saan sullins electronics co pbc06saan connector; male; through hole; breakaway; straight; 6pins; -65 degc to +125 degc 12 1 j11 ostvn12a150 on-shore technology ostvn12a150 connector; female; through hole; screw type; green terminal block; right angle; 12pins 13 2 jmp1, jmp2 22-28-4043 molex 22-28-4043 connector; male; through hole; flat vertical breakaway; straight; 4pins 14 6 r1-r6 erj-3ekf28r0v panasonic 28 resistor; 0603; 28 ohm; 1%; 100ppm; 0.10w; thick film 15 12 r7-r18 crcw04021m00fk vishay dale 1m resistor; 0402; 1m; 1%; 100ppm; 0.0625w; thick film 16 12 r19-r30 crcw040210r0fk; 9c04021a10r0fl vishay dale 10 resistor; 0402; 10 ohm; 1%; 100ppm; 0.0625w; thick film 17 3 r31, r34, r35 crcw060310k0fk; 9c06031a1002fk; erj-3ekf1002 vishay dale/yageo phi 10k resistor; 0603; 10k; 1%; 100ppm; 0.10w; thick film 18 7 su1-su7 sx1100-b kycon sx1100-b test point; jumper; str; total length=0.24in; black; insulation=pbt;phosphor bronze contact=gold plated 19 3 tp1, tp3, tp7 5000 keystone n/a test point; pin dia=0.1in; total length=0.3in; board hole=0.04in; red; phosphor bronze wire silver plate finish; recommended for board thickness=0.062in; not for cold test 20 3 tp2, tp5, tp6 5001 keystone n/a test point; pin dia=0.1in; total length=0.3in; board hole=0.04in; black; phosphor bronze wire silver plate finish; recommended for board thickness=0.062in; not for cold test 21 1 tp4 5004 keystone n/a test point; pin dia=0.1in; total length=0.3in; board hole=0.04in; yellow; phosphor bronze wire silver plate finish; recommended for board thickness=0.062in; not for cold test 22 1 u1 max11259ewx+ maxim max11259ewx+ evkit part - ic; max11259; wlp36; outline dwg 21-0898; pkg code w362c2+1 23 1 u2 max8510exk29+ maxim max8510exk29+ ic; vreg; ultra-low-noise; high psrr; low- dropout; 0.12a linear regulator; sc70-5 24 1 u3 max6072aaub25+ maxim max6072aaub25+ ic; vref; hig-precision; dual-output series voltage reference; umax10 total 90
j11 r9 r10 r7 r8 r11 r12 r15 r16 r13 r14 r17 r18 silk_top ch0- ch0+ r22 r23 j3 ch1- ch1+ r25 c5 r24 ch2- ch3+ ch2+ r28 r26 ch4- ch4+ ch3- ch5- ch5+ j9 r19 c2 r20 r21 u1 c7 c6 c4 c3 r29 r27 r30 06/15 amd rev-a and shall not be reproduced wholly or in part, this document contains information considered proprietary, nor disclosed to others without specific written permission. c13 c15 c27 c18 c1 gnd c25 j2 vcom designer: odb++/gerber: c21 r35 r34 j8 j7 c20 avdd tp6 c24 gnd 1/6 tp4 avdd tp3 c26 c22 j5 1 2 4 vref tp7 u3 vref tp5 gnd gnd avss c16 c14 jmp2 j6 3 sda c19 c23 gnd c17 tp1 tp2 dvdd jmp1 1 2 3 4 sda c10 gnd 1-888-629-4642 www.maximintegrated.com do not modify top soldermask on u1 r31 r4 r3 j10 j4 c11 gnd rstb r5 r1 r6 scl sda rdyb r2 u2 c12 1" 06/02/2015 c9 c8 hardware name:MAX11259PMB_evkit_a hardware number: engineer: date: j1 MAX11259PMB downloaded from: http:///
top and shall not be reproduced wholly or in part, this document contains information considered proprietary, nor disclosed to others without specific written permission. designer: odb++/gerber: 2/6 do not modify top soldermask on u1 1" 06/02/2015 hardware name:MAX11259PMB_evkit_a hardware number: engineer: date: downloaded from: http:///
layer2 and shall not be reproduced wholly or in part, this document contains information considered proprietary, nor disclosed to others without specific written permission. designer: odb++/gerber: 3/6 do not modify top soldermask on u1 1" 06/02/2015 hardware name:MAX11259PMB_evkit_a hardware number: engineer: date: downloaded from: http:///
layer3 and shall not be reproduced wholly or in part, this document contains information considered proprietary, nor disclosed to others without specific written permission. designer: odb++/gerber: 4/6 do not modify top soldermask on u1 1" 06/02/2015 hardware name:MAX11259PMB_evkit_a hardware number: engineer: date: downloaded from: http:///
bottom and shall not be reproduced wholly or in part, this document contains information considered proprietary, nor disclosed to others without specific written permission. designer: odb++/gerber: 5/6 do not modify top soldermask on u1 1" 06/02/2015 hardware name:MAX11259PMB_evkit_a hardware number: engineer: date: downloaded from: http:///
silk_bot and shall not be reproduced wholly or in part, this document contains information considered proprietary, nor disclosed to others without specific written permission. r32 r33 designer: odb++/gerber: 6/6 do not modify top soldermask on u1 1" 06/02/2015 hardware name:MAX11259PMB_evkit_a hardware number: engineer: date: downloaded from: http:///
ch0- gpo0 gpognd gpo2 gpio2gpo1 ch5- ch2-ch5+ ch4- ch4+ ch3+ ch2+ch3- ch1- ch1+ ch0+ gpio1/sync gpio0/clk sheet 1 of 1 10 1000pf 2.2k dni 2.2k dni agnd agnd 0.1uf 4.7uf 0.1uf 10k 0.01uf 1m1m 28 28 1m max6072aaub25+ 1uf 1000pf 4.7uf 0.1uf agnd max11259ewx+ 4.7uf max8510exk30+ 0.1uf 0.1uf 0.1uf 1uf pbc12saan 1m1m 1m 0.01uf 1m 1uf 1uf 1uf 1m 1m 1uf 1uf 28 28 1m 1000pf 1m1m 28 28 1000pf 1000pf1000pf 10 10 10 10 10 10 10 10 1010 1000pf 10k 10k 4.7uf 10 MAX11259PMB a 5/08/2015 4.7uf r32 r33 c2 j9 tp7 j8 c16 j2 r31 tp2 c14 c19 c17 r4 r5 r10 c11 r6 r3 u3 c25 c13 c15 j7 c22 c26 c9 c8 c3 c24 c23 j6 j5 j11 tp4 j3 r13r17 tp3 tp5 c18 u2 c10 j4 r12 c12 c20 c21 c27 r18 r15 r14 r11 r8 j10 jmp1jmp2 u1 j1 r16 r7 r9 r2 r1 tp6 c1 c4c5 c7 c6 r29r30 r28 r27 r26 r25 r24 r23 r22 r21 r20 r19 tp1 r35 r34 ain3n dvdd sda dvdd gpio0/clk gpo0gpo2 gpio1/sync avdd vref refp gpio1/sync gpio0/clk gpio2 dvdd avss gpo1 avss +3.3v +3.3v sda rdyb avss vcom sda scl scl vref adr0 ain0p ain0n ain1p ain2p ain3p ain4p adr0 adr1 refp rstb sda gpo2 rdyb gpo0 avss gpo1 +3.0v ain2n ain3n ain4n scl adr1 avdd +3.0v +3.3v +3.3v rstb sclsda rdybrstb ain4n ain5pain5n rstb ain1n avdd ain3p ain2n ain2p ain1n ain1p ain0p ain0n gpio2 sda avss dvdd dvdd ain5nain5p dvdd +3.0v ain4p vcom 23 3 7 1 1 2 3 f6 d2 6 5 4 3 2 1 2 8 3 9 10 4 7 6 1 6 3 1 1011 12 9 8 56 7 4 3 2 1 8 12 79 2 5 1 d5d4 e5 c5 e3 d1 e1 5 3 c4 f3 f4 e4 c1c6 b4 78 9 10 12 3 4 5 6 1112 a6b3 a2 e2b2 f2 d3c2 d6 e6b6 b5 a5a4 a3 f1 2 4 2 4 1 c3 4 f5 15 4 3 1 2 1011 6 3 25 4 b1a1 2 1 2 1 2 1 2 1 sdascl rstbrefp refn rdyb gpognd gpo2gpo1 gpo0 gpio2gpio1/sync gpio0/clk dvdd dvdd dgnd capreg capp capn avss avss avdd ain5p ain5nain4p ain4nain3p ain3nain2p ain2nain1p ain1nain0p ain0n adr1adr0 out out in in out in en1 out1s out1f gnd gnd out2f out2s in2 in1en2 in out out in in out in in in in in in in in in in in in in out out out in in in out out out out out out out out out out out out in in in in in in in in in in in in in in in in in in in in in in in in in out out j1-12 j1-11 j1-10 j1-9 j1-8 j1-7 j1-6 j1-5 j1-4 j1-3 j1-2 j1-1 out out out out in bp shdn out gnd in in in out in out out in in in engineer: ed c b a 7 6 5 4 3 2 1 7 6 5 4 3 2 1 ed c b a 8 f f c c 8 rev.: date: c c size: drawing title: template rev.: drawn by: hardware number: project title:

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