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RT1710 ? ds1710-00 may 2016 www.richtek.com 1 copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. ? simplified application circuit cable id for usb type-c cables general description RT1710 is a type-c cable id for active and passive cables. all usb full-featured type-c cables shall be electronically marked. electronically marked cables shall support usb power delivery structured vdm discover identity command directed to sop'. this provides a method to determine the characteristics of the cable, e.g. its current carrying capability, its performance, vendor identification, etc. this may be referred to as the usb type-c cable id function. RT1710 is available in a wdfn-8l 2x3 package . features ? ? ? ? ? support sop' communication ? ? ? ? ? integrated transceiver (bmc phy) ? ? ? ? ? embedded both side ra resistor ? ? ? ? ? embedded both side iso diode ? ? ? ? ? embedded mtp ? ? ? ? ? support multi-tme writable memory to store vdm data ? ? ? ? ? support 4v to 5.5v operation on vcon1 / vcon2 pin ? ? ? ? ? built-in slew rate control for bmc signal to reduce the effect of emi ? ? ? ? ? support custom structured vdm writing through ccin pin ? ? ? ? ? support i 2 c bus for programming vdm data applications ? usb full-featured type-c cables pin configurations (top view) wdfn-8l 2x3 ordering information note : richtek products are : ? rohs compliant and compatible with the current require- ments of ipc/jedec j-std-020. ? suitable for use in snpb or pb-free soldering processes. RT1710 package type qw : wdfn-8l 2x3 (w-type) lead plating system g : green (halogen free and pb free) vcon1 gnd ccin nc(dg0) nc(dg1) scl sda vcon2 gnd 9 7 6 5 1 2 3 4 8 marking information 13w 13 : product code w : date code cc pin vconn 0.1f RT1710 sda scl nc nc gnd vcon2 vcon1 ccin vconn (another side) 0.1f test pad test pad
RT1710 2 ds1710-00 may 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. function block diagram functional pin description pin no. pin name pin function 1 vcon1 the input pin supplied from vconn. 2 ccin configuration channel pin used in the discovery, configuration and management of connections. 3 vcon2 the input pin supplied from another side vconn. 4 gnd ground. 5 sda this pin is only used for debug. please connect it to ground. 6 scl this pin is only used for debug. please connect it to ground. 7 nc(dg1) no internal connection. 8 nc(dg0) no internal connection. 9 (exposed pad) gnd power ground. the exposed pad must be soldered to a large pcb and connected to gnd for maximum power dissipation. operation RT1710 is a type-c cable id for active and passive cables. all usb full-featured type-c cables shall be electronically marked. electronically marked cables shall support usb power d elivery structured vdm discover identity command directed to sop'. this provides a method to determine the characteristics of the cable, e.g. its current carrying capability, its performance, vendor identification, etc. this may be referred to as the u sb type-c cable id function. an electronically marked cable incorporates electronics that require v conn , although v bus or another source may be used. electronically marked cables that do not incorporate data bus signal conditioning circuits shall consume no more than 70mw from v conn . during usb suspend, electronically marked cables shall not draw more than 7.5ma from v conn . vcon1 vcon2 ccin gnd scl sda i2c controller voltage regulator mtp internal bus cable policy engine register block detection mux control protocol layer usb pd physical layer dg0 dg1 ra ra
RT1710 3 ds1710-00 may 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. electrical characteristics (v dd = 5v, t a = 25 c, unless otherwise specified.) parameter symbol test conditions min typ max unit common normative signaling requirements bit rate fbitrate 270 300 330 kbps common normative signaling requirements for transmitter maximum difference between the bit-rate during the part of the packet following the preamble and the reference bit-rate. pbitrate -- -- 0.25 % time from the end of last bit of a frame until the start of the first bit of the next preamble. t interframegap 25 -- -- ? s time before the start of the first bit of the preamble when the transmitter shall start driving the line. t startdrive ? 1 -- 1 ? s bmc common normative requirements time to cease driving the line after the end of the last bit of the frame. t enddrivebmc -- -- 23 ? s fall time t fall 300 -- -- ns time to cease driving the line after the final high-to-low transition t holdlowbmc 1 -- -- ? s rise time t rise 300 -- -- ns voltage swing v swing 1.05 1.125 1.2 v transmitter output impedance zdriver 33 -- 75 ? absolute maximum ratings (note 1) ? vcon1/vcon2 ------------------------------------------------------------------------------------------------------------ ? 0.3v to 6v ? power dissipation, p d @ t a = 25 c wdfn-8l 2x3 -------------------------------------------------------------------------------------------------------------- 3.17w ? package thermal resistance (note 2) wdfn-8l 2x3, ja --------------------------------------------------------------------------------------------------------- 31.5 c/w wdfn-8l 2x3, jc -------------------------------------------------------------------------------------------------------- 7.5 c/w ? lead temperature (soldering, 10 sec.) ------------------------------------------------------------------------------- 260 c ? junction temperature ----------------------------------------------------------------------------------------------------- 150 c ? storage temperature range -------------------------------------------------------------------------------------------- ? 65 c to 150 c ? esd susceptibility (note 3) hbm (human body model) ---------------------------------------------------------------------------------------------- 8kv mm (ma chine model) ----------------------------------------------------------------------------------------------------- 600v recommended operating conditions (note 4) ? suply input voltage ------------------------------------------------------------------------------------------------------- 4v to 5.5v ? junction temperature range -------------------------------------------------------------------------------------------- ? 40 c to 125 c ? ambient temperature range -------------------------------------------------------------------------------------------- ? 40 c to 85 c
RT1710 4 ds1710-00 may 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. note 1. stresses beyond those listed ? absolute maximum ratings ? may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions may affect device reliability. note 2. ja is measured at t a = 25 c on a high effective thermal conductivity four-layer test board per jedec 51-7. jc is measured at the exposed pad of the package. note 3. devices are esd sensitive. handling precaution is recommended. note 4. the device is not guaranteed to function outside its operating conditions. parameter symbol test conditions min typ max unit bmc receiver normative requirements cable termination ra 800 -- 1200 ? time window for detecting non-idle t transitionw indow 12 -- 20 ? s receiver input impedance zbmcrx 10 -- -- m ?
RT1710 5 ds1710-00 may 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. inter-frame gap timings bmc encoded start of preamble transmitting or receiving bmc encoded frame terminated data in bmc 0 1 0 1 0 1 0 1 0 0 0 1 1 0 0 0 1 1 preamble sync-1 sync-1 bmc example end of frame bus driven after end of frame bus driven before preamble preamble t interframegap t enddrivebfsk or t enddrivebmc t startdrive 000 111 t startdrive 1ui 1ui 1ui 1ui 1ui 1ui high impedance (level set by rp/rd) etc 1ui min t holdlowbmc max t enddrivebmc t interframegap 0 0 high impedance (level set by rp/rd) final bit of frame trailing edge of final bit preamble for next frame
RT1710 6 ds1710-00 may 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. bmc tc mask definition, x values parameter symbol test conditions min typ max units left edge of mask x1tx 0.015 ui x2tx point x2tx 0.07 ui x3tx point x3tx 0.15 ui x4tx point x4tx 0.25 ui x5tx point x5tx 0.35 ui x6tx point x6tx 0.43 ui x7tx point x7tx 0.485 ui x8tx point x8tx 0.515 ui x9tx point x9tx 0.57 ui x10tx point x10tx 0.65 ui x11tx point x11tx 0.75 ui x12tx point x12tx 0.85 ui x13tx point x13tx 0.93 ui right edge of mask x14tx 0.985 ui ? bmc tc mask definition, y values parameter symbol test conditions min typ max units lower bound of outer mask y1tx -0.075 v lower bound of inner mask y2tx 0.075 v y3tx point y3tx 0.15 v y4tx point y4tx 0.325 v inner mask vertical midpoint y5tx 0.5625 v y6tx point y6tx 0.8 v y7tx point y7tx 0.975 v y8tx point y8tx 1.04 v upper bound of outer mask y9tx 1.2 v ?
RT1710 7 ds1710-00 may 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. bmc t x ? zero ? mask bmc t x ? one ? mask 1ui y9 y8 y7 y6 y5 y4 y3 y2 y1 x1 x2 x3 x4 x5 x6x7 x8 x9 x10 0.5ui x11 x12 x13 x14 1ui y9 y8 y7 y6 y5 y4 y3 y2 y1 x1 x2 x3 x4 0.5ui x12 x13 x14
RT1710 8 ds1710-00 may 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. typical application circuit electronically marked cable with vconn connected through the cable electronically marked cable with sop' at b oth ends RT1710 sda scl nc nc gnd vcon2 vcon1 ccin gnd cc pin vbus vconn cc pin vbus vconn gnd 0.1f 9 (exposed pad) 6 5 1 2 3 4, 0.1f test pad test pad gnd cc pin vbus vconn cc pin vbus vconn gnd RT1710 sda scl nc nc gnd vcon2 vcon1 ccin 6 5 1 2 3 0.1f RT1710 sda scl nc nc gnd vcon2 vcon1 ccin 6 5 1 2 3 4, 0.1f 9 (exposed pad) 4, test pad test pad test pad test pad 0.1f 0.1f 9 (exposed pad)
RT1710 9 ds1710-00 may 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. application information start of packet sequence prime (sop') the sop' ordered set is defined as : two sync-1 k-codes followed by two sync-3 k-codes k-code number k-code in code table 1 sync-1 2 sync-1 3 sync-3 4 sync-3 a cable plug capable of sop' communications shall only detect and communicate with packets starting with sop'. a dfp or source needing to communicate with a cable plug capable of sop' communications, attached between a port pair will be able to communicate using both packets starting with sop' to communicate with the cable plug and starting with sop to communicate with its port partner. the dfp or source shall co-ordinate sop and sop' communication so as to avoid collisions. structured vdm setting the vdm type field to 1 (structured vdm) defines the use of bits b14..0 in the structured vdm header. the fields in the structured vdm header are defined in table. the following rules apply to the use of structured vdm messages : ? structured vdms shall only be used when an explicit contract is in place with the following exception : prior to est ablishing an explicit contract a source may issue discover identity messages, to a cable plug using sop' packet s, as an initiator. ? only the dfp shall be an initiator of structured vdms except for the attention command that shall only be initiated by the ufp. ? only the ufp or a cable plug shall be a responder to structured vdms. ? structured vdms shall not be initiated or responded to under any other circumstances. ? a dfp or ufp which does not support structured vdms shall ignore any structure d vdms received. ? a command sequence shall be interruptible e.g. due to the need for a message sequence using sop packets.
RT1710 10 ds1710-00 may 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. bit (s) field description bit[31:16] standard or vendor id (svid) unique 16 bit unsigned integer, assigned by the usb-if bit[15] vdm type 1 = structured vdm bit[14:13] structured vdm version version number of the structured vdm (not this specification version) : version 1.0 = 0 values 1-3 are reserved bit[12:11] reserved shall be set to 0 and shall be ignored bit[10:8] object position for the enter mode and exit mode commands : 000b = reserved 001b..110b = index into the list of vdos to identify the desired mode vdo 111b = exit all modes (equivalent of a power on reset). shall not be used with the enter mode command. bit[7:6] command type 00b = initiator 01b = responder ack 10b = responder nak 11b = responder busy bit[5] reserved shall be set to 0 and shall be ignored bit[4:0] command (note 1) 0 = reserved, shall not be used 1 = discover identity 2 = discover svids 3 = discover modes 4 = enter mode 5 = exit mode 6 = attention 7-15 = reserved, shall not be used 16..31 = svid specific commands note 1 : in the case where a sid is used the modes are defined by a standard. when a vid is used the modes are defined by the vendor. discover identity the discover identity command is provided to enable an initiator (dfp) to identify its port partner and for an initiator (source or dfp) to identify the attached cable plug (responder). the svid in the discover svids command shall be set to the pd sid by both the initiator and the responder for this command. the discover identity command sent back by the responder contains an id header, a cert stat vdo and some type specific vdos which depend on the product type. this specification defines the following type specific vdos : header no. of data objects = 4..7 vdm header id header cert stat vdo product vdo 0..3 product type vdo(s) ?
RT1710 11 ds1710-00 may 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. id header the id header contains the vendor id corresponding to the power delivery product. bit (s) description bit[31] data capable as usb host : ? shall be set to one if the product is capable of enumerating usb devices. ? shall be set to zero otherwise bit[30] data capable as a usb device : ? shall be set to one if the product is capable of enumerating as a usb device. ? shall be set to zero otherwise bit[29:27] product type: ? 000b ? undefined ? 001b ? hub ? 010b ? peripheral ? 011b ? passive cable ? 100b ? active cable ? 101b ? alternate mode adapter (ama) ? 111b..110b ? reserved, shall not be used. bit[26] modal operation supported : ? shall be set to one if the product supports modal operation. ? shall be set to zero otherwise bit[25:16] reserved. shall be set to zero. bit[15:0] 16-bit unsigned integer. usb vendor id ? cert stat vdo the cert stat vdo contains the test id (tid) allocated by usb-if during certification. bit (s) description bit[31:20] reserved, shall be set to zero. bit[19:0] 20-bit unsigned integer ? product vdo the product vdo contains identity information relating to the product. bit (s) description bit[31:16] 16-bit unsigned integer. usb product id bit[15:0] 16-bit unsigned integer. bcddevice
RT1710 12 ds1710-00 may 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. cable vdo the cable vdo defined in this section shall be sent when the product type is given as passive or active cable. bit (s) field description bit[31:28] cable hw version 0000b..1111b assigned by the vid owner bit[27:24] cable firmware version 0000b..1111b assigned by the vid owner bit[23:20] reserved shall be set to zero. bit[19:18] type-c to type-a/b/c 00b = type-a 01b = type-b 10b = type-c 11b = captive bit[17] type-c to plug/receptacle 0 = plug 1 = receptacle (not valid when b19..18 set to type-c or captive) bit[16:13] cable latency 0000b ? reserved 0001b ? <10ns (~1m) 0010b ? 10ns to 20ns (~2m) 0011b ? 20ns to 30ns (~3m) 0100b ? 30ns to 40ns (~4m) 0101b ? 40ns to 50ns (~5m) 0110b ? 50ns to 60ns (~6m) 0111b ? 60ns to 70ns (~7m) 1000b ?1000ns (~100m) 1001b ?2000ns (~200m) 1010b ? 3000ns (~300m) 1011b ?.1111b reserved includes latency of electronics in active cable bit[12:11] cable termination type 00b = both ends passive, vconn not required 01b = both ends passive, vconn required 10b = one end active, one end passive, vconn required 11b = both ends active, vconn required bit[10] sstx1 directionality support 0 = fixed 1 = configurable bit[9] sstx2 directionality support 0 = fixed 1 = configurable bit[8] ssrx1 directionality support 0 = fixed 1 = configurable bit[7] ssrx2 directionality support 0 = fixed 1 = configurable bit[6:5] vbus current handling capability 00b = vbus not through cable 01b = 3a 10b = 5a 11b = reserved. bit[4] vbus through cable 0 = no 1 = yes bit[3] sop? controller present 1 = sop? controller present 0 = no sop? controller present bit[2:0] usb super speed signaling support 000b = usb 2.0 only 001b = [usb3.1] gen1 010b = [usb3.1] gen1 and gen2 011b.. 111b = reserved. ?
RT1710 13 ds1710-00 may 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. figure 3. derating curve of maximum power dissipation thermal considerations for continuous operation, do not exceed absolute maximum junction temperature. the maximum power dissipation depends on the thermal resistance of the ic package, pcb layout, rate of surrounding airflow, and difference between junction and ambient temperature. the maximum power dissipation can be calculated by the following formula : p d(max) = (t j(max) ? t a ) / ja where t j(max) is the maximum junction temperature, t a is the ambient temperature, and ja is the junction to ambient thermal resistance. for recommended operating condition specifications, the maximum junction temperature is 125 c. the junction to ambient thermal resistance, ja , is layout dependent. for wdfn-8l 2x3 package, the thermal resistance, ja , is 31.5 c/w on a standard jedec 51-7 four-layer thermal test board. the maximum power dissipation at t a = 25 c can be calculated by the following formula : p d(max) = (125 c ? 25 c) / (31.5 c/w) = 3.17w for wdfn-8l 2x3 package the maximum power dissipation depends on the operating ambient temperature for fixed t j(max) and thermal resistance, ja . the derating curve in figure 3 allows the designer to see the effect of rising ambient temperature on the maximum power dissipation. 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0 25 50 75 100 125 ambient temperature (c) maximum power dissipation (w) 1 four-layer pcb layout consideration ? pcb layout is very important for designing e-marked ic (RT1710) circuits. ? the vcon1 and vcon2 traces should be wide (10mil) and short especially for the current loop. ? connect vcon1/vcon2 pins with bypass capacitor, and as near the pins as possible. ? the exposed pad of the chip should be connected to a large ground plane for thermal consideration. ? keep the cc1 traces away from those sensing pins (d+, d-, sstx+, sstx-, ssrx+, ssrx-, sbu). figure 4. pcb layout guide the exposed pad of the chip should be connected to a large ground plane for thermal consideration. cc pin vconn 0.1f RT1710 sda scl nc nc gnd vcon2 vcon1 ccin ep test pad test pad vconn (another side) 0.1f keep the cc1 traces away from those sensing pins (d+,d-,sstx+,sstx-,ssrx+,ssrx-,sbu) the vcon1 and vcon2 traces should be wide (10mil) and short especially for the current loop. connect vcon1/vcon2 pins with bypass capacitor,and as near the pins as possible.
RT1710 14 ds1710-00 may 2016 www.richtek.com richtek technology corporation 14f, no. 8, tai yuen 1 st street, chupei city hsinchu, taiwan, r.o.c. tel: (8863)5526789 richtek products are sold by description only. richtek reserves the right to change the circuitry and/or specifications without notice at any time. customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a richtek product. information furnish ed by richtek is believed to be accurate and reliable. however, no responsibility is assumed by richtek or its subsidiaries for its use; nor for any infringeme nts of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of r ichtek or its subsidiaries. outline dimension dimensions in millimeters dim ensions in inches sy mbol min max min max a 0.700 0.800 0.028 0.031 a1 0.000 0.050 0.000 0.002 a3 0.175 0.250 0.007 0.010 b 0.200 0.300 0.008 0.012 d 1.900 2.100 0.075 0.083 d2 1.550 1.650 0.061 0.065 e 2.900 3.100 0.114 0.122 e2 1.650 1.750 0.065 0.069 e 0.500 0.020 l 0.350 0.450 0.014 0.018 w-type 8l dfn 2x3 package 1 1 2 2 note : the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. det ail a pin #1 id and tie bar mark options d 1 e a3 a a1 d2 e2 l b e see detail a

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