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lm5117 , lm5117-q1 snvs698f ? april 2011 ? revised august 2015 lm5117/q1 wide input range synchronous buck controller with analog current monitor 1 features 3 description the lm5117 is a synchronous buck controller 1 ? lm5117-q1 is qualified for automotive intended for step-down regulator applications from a applications high voltage or widely varying input supply. the ? aec-q100 qualified with the following results: control method is based upon current mode control ? device temperature grade 1: -40 c to 125 c utilizing an emulated current ramp. current mode control provides inherent line feed-forward, cycle-by- ambient operating temperature range cycle current limiting and ease of loop compensation. ? emulated peak current mode control the use of an emulated control ramp reduces noise ? wide operating range from 5.5 v to 65 v sensitivity of the pulse-width modulation circuit, ? robust 3.3-a peak gate drives allowing reliable control of very small duty cycles necessary in high input voltage applications. ? adaptive dead-time output driver control ? free-run or synchronizable clock up to 750 khz the operating frequency is programmable from 50 khz to 750 khz. the lm5117 drives external high- ? optional diode emulation mode side and low-side nmos power switches with ? programmable output from 0.8 v adaptive dead-time control. a user-selectable diode ? precision 1.5% voltage reference emulation mode enables discontinuous mode operation for improved efficiency at light load ? analog current monitor conditions. a high voltage bias regulator that allows ? programmable current limit external bias supply further improves efficiency. the ? hiccup mode overcurrent protection lm5117 ? s unique analog telemetry feature provides average output current information. additional ? programmable soft-start and tracking features include thermal shutdown, frequency ? programmable line undervoltage lockout synchronization, hiccup mode current limit, and ? programmable switchover to external bias supply adjustable line undervoltage lockout. ? thermal shutdown device information (1) 2 applications part number package body size (nom) lm5117 htssop (20) pwp 6.50 mm 4.40 mm ? automotive infotainment lm5117-q1 wqfn (24) rtw 4.00 mm 4.00 mm ? industrial dc-dc motor drivers (1) for all available packages, see the orderable addendum at ? automotive usb power the end of the datasheet. ? telecom server typical application 1 an important notice at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. production data. v out ss res rt comp fb ramp pgnd csg cs lo sw ho hb vcc vin agnd uvlo vccdis demb cm v in v out sw lm5117 productfolder sample &buy technical documents tools & software support &community
lm5117 , lm5117-q1 snvs698f ? april 2011 ? revised august 2015 www.ti.com table of contents 7.3 feature description ................................................. 13 1 features .................................................................. 1 7.4 device functional modes ........................................ 21 2 applications ........................................................... 1 8 application and implementation ........................ 22 3 description ............................................................. 1 8.1 application information ............................................ 22 4 revision history ..................................................... 2 8.2 typical applications ............................................... 22 5 pin configuration and functions ......................... 3 8.3 detailed design procedure ..................................... 22 6 specifications ......................................................... 5 8.4 application curves .................................................. 32 6.1 absolute maximum ratings ..................................... 5 9 power supply recommendations ...................... 35 6.2 esd ratings (lm5117) ............................................. 5 10 layout ................................................................... 35 6.3 esd ratings (lm5117-q1) ....................................... 5 10.1 layout guideline ................................................... 35 6.4 recommended operating conditions ....................... 6 11 device and documentation support ................. 36 6.5 thermal information .................................................. 6 11.1 related links ........................................................ 36 6.6 electrical characteristics ........................................... 7 11.2 community resources .......................................... 36 6.7 switching characteristics .......................................... 8 11.3 trademarks ........................................................... 36 6.8 typical characteristics .............................................. 9 11.4 electrostatic discharge caution ............................ 36 7 detailed description ............................................ 11 11.5 glossary ................................................................ 36 7.1 overview ................................................................. 11 12 mechanical, packaging, and orderable 7.2 functional block diagram ....................................... 12 information ........................................................... 36 4 revision history note: page numbers for previous revisions may differ from page numbers in the current version. changes from revision e (march 2013) to revision f page ? added device information and pin configuration and functions sections, esd rating table, feature description , device functional modes , application and implementation , power supply recommendations , layout , device and documentation support , and mechanical, packaging, and orderable information sections ................................................ 1 ? changed h into f ............................................................................................................................................................ 29 changes from revision d (march 2013) to revision e page ? changed layout of national data sheet to ti format ........................................................................................................... 34 2 submit documentation feedback copyright ? 2011 ? 2015, texas instruments incorporated product folder links: lm5117 lm5117-q1
lm5117 , lm5117-q1 www.ti.com snvs698f ? april 2011 ? revised august 2015 5 pin configuration and functions pwp package 20-pin htssop top view rtw package 24-pin wqfn top view copyright ? 2011 ? 2015, texas instruments incorporated submit documentation feedback 3 product folder links: lm5117 lm5117-q1 pgnd uvlo agnd demb res ss rt fb comp cm 1 6 23 4 5 8 9 20 14 15 19 18 17 16 13 12 11 vin lo hb ho sw vcc csg cs ramp 21 22 23 24 vccdis 7 10 nc nc nc nc ep uvlo agnd demb res ss rt fb comp cm vin pgnd lo hb ho sw vcc csg cs ramp 1 6 23 4 5 8 9 20 14 15 19 18 17 16 13 12 11 ep vccdis 10 7
lm5117 , lm5117-q1 snvs698f ? april 2011 ? revised august 2015 www.ti.com pin functions pin type (1) description htssop wqfn name 1 24 uvlo undervoltage lockout programming pin. if the uvlo pin voltage is below 0.4 v, the regulator is in the shutdown mode with all functions disabled. if the uvlo pin voltage is greater than 0.4 v and less than 1.25 v, the regulator is in standby mode with the vcc regulator operational, the ss pin grounded, and no switching at the ho and lo outputs. i if the uvlo pin voltage is above 1.25 v, the ss pin is allowed to ramp and pulse width modulated gate drive signals are delivered to the ho and lo pins. a 20 a current source is enabled when uvlo exceeds 1.25 v and flows through the external uvlo resistors to provide hysteresis. 2 1 demb optional logic input that enables diode emulation when in the low state. in diode emulation mode, the low-side nmos is latched off for the remainder of the pwm cycle after detecting reverse current flow (current flow from output to ground through the low- i side nmos). when demb is high, diode emulation is disabled allowing current to flow in either direction through the low-side nmos. a 50-k ? pull-down resistor internal to the lm5117 holds demb pin low and enables diode emulation if the pin is left floating. 3 2 res the restart timer pin that configures the hiccup mode current limiting. a capacitor on the res pin determines the time the controller remains off before automatically restarting. o the hiccup mode commences when the controller experiences 256 consecutive pwm cycles of cycle-by-cycle current limiting. after this occurs, a 10- a current source charges the res pin capacitor to the 1.25 v threshold and restarts lm5117. 4 3 ss an external capacitor and an internal 10- a current source set the ramp rate of the error i amplifier reference during soft-start. the ss pin is held low when vcc < 5 v, uvlo < 1.25 v or during thermal shutdown. 5 4 rt the internal oscillator is programmed with a single resistor between rt and the agnd. the recommended maximum oscillator frequency is 750khz. the internal oscillator can i be synchronized to an external clock by coupling a positive pulse into the rt pin through a small coupling capacitor. 6 5 agnd g analog ground. return for the internal 0.8 v voltage reference and analog circuits. 7 7 vccdis optional input that disables the internal vcc regulator. if vccdis > 1.25 v, the internal vcc regulator is disabled. vccdis has an internal 500-k ? pulldown resistor to enable i the vcc regulator when the pin is left floating. the internal 500-k ? pull-down resistor can be overridden by pulling vccdis above 1.25 v with a resistor divider connected to an external bias supply. 8 8 fb feedback. inverting input of the internal error amplifier. a resistor divider from the output i to this pin sets the output voltage level. the regulation threshold at the fb pin is 0.8 v. 9 9 comp output of the internal error amplifier. the loop compensation network should be o connected between this pin and the fb pin. 10 10 cm current monitor output. average of the sensed inductor current is provided. monitor o directly between cm and agnd. cm should be left floating when the pin is not used. 11 11 ramp pwm ramp signal. an external resistor and capacitor connected between the sw pin, the ramp pin and the agnd pin sets the pwm ramp slope. proper selection of component i values produces a ramp signal that emulates the ac component of the inductor with a slope proportional to input supply voltage. 12 12 cs i current sense amplifier input. connect to the high-side of the current sense resistor. 13 13 csg kelvin ground connection to the current sense resistor. connect directly to the low-side of g the current sense resistor. 14 14 pgnd power ground return pin for low-side nmos gate driver. connect directly to the low-side o of the current sense resistor. 15 15 lo low-side nmos gate drive output. connect to the gate of the low-side synchronous p/o/i nmos transistor through a short, low inductance path. 16 16 vcc bias supply pin. locally decouple to pgnd using a low esr/esl capacitor located as i/o close to controller as possible. 17 18 sw switching node of the buck regulator. connect to the bootstrap capacitor, the source o terminal of the high-side nmos transistor and the drain terminal of the low-side nmos through a short, low inductance path. 18 19 ho high-side nmos gate drive output. connect to the gate of the high-side nmos transistor p through a short, low inductance path. (1) i = input, o = output, g = ground, p = power 4 submit documentation feedback copyright ? 2011 ? 2015, texas instruments incorporated product folder links: lm5117 lm5117-q1
lm5117 , lm5117-q1 www.ti.com snvs698f ? april 2011 ? revised august 2015 pin functions (continued) pin type (1) description htssop wqfn name 19 20 hb high-side driver supply for the bootstrap gate drive. connect to the cathode of the external bootstrap diode and to the bootstrap capacitor. the bootstrap capacitor supplies p/i current to charge the high-side nmos gate and should be placed as close to controller as possible. 20 22 vin p/i supply voltage input source for the vcc regulator. ep ep ep exposed pad of the package. electrically isolated. should be soldered to the ground - plane to reduce thermal resistance. 6 nc - no electrical contact. 17 nc - no electrical contact. 21 nc - no electrical contact. 23 nc - no electrical contact. 6 specifications 6.1 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) (1) min max unit vin to agnd ? 0.3 75 v sw to agnd ? 3.0 75 v hb to sw ? 0.3 15 v vcc to agnd (2) ? 0.3 15 v ho to sw ? 0.3 hb + 0.3 v lo to agnd ? 0.3 vcc + 0.3 v fb, demb, res, vccdis, uvlo to agnd ? 0.3 15 v cm, comp to agnd (3) ? 0.3 7 v ss, ramp, rt to agnd ? 0.3 7 v cs, csg, pgnd, to agnd ? 0.3 0.3 v storage temperature, t stg ? 55 150 c junction temperature ? 40 150 c (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions . exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) see application and implementation when input supply voltage is less than the vcc voltage. (3) these pins are output pins. as such they are not specified to have an external voltage applied. 6.2 esd ratings (lm5117) value unit human-body model (hbm), per ansi/esda/jedec js-001 (1) 2000 v v (esd) electrostatic discharge charged-device model (cdm), per jedec specification jesd22- v 750 v c101 (2) (1) jedec document jep155 states that 500-v hbm allows safe manufacturing with a standard esd control process. (2) jedec document jep157 states that 250-v cdm allows safe manufacturing with a standard esd control process. 6.3 esd ratings (lm5117-q1) value unit human-body model (hbm), per aec q100-002 (1) 2000 v v (esd) electrostatic discharge charged-device model (cdm), per aec q100-011 750 v (1) aec q100-002 indicates that hbm stressing shall be in accordance with the ansi/esda/jedec js-001 specification. copyright ? 2011 ? 2015, texas instruments incorporated submit documentation feedback 5 product folder links: lm5117 lm5117-q1
lm5117 , lm5117-q1 snvs698f ? april 2011 ? revised august 2015 www.ti.com 6.4 recommended operating conditions over operating free-air temperature range (unless otherwise noted) (1) min max unit vin (2) 5.5 65 v vcc 5.5 14 v hb to sw 5.5 14 v junction temperature -40 125 c (1) recommended operating conditions are conditions under which operation of the device is intended to be functional, but does not ensure specific performance limits. for specifications and test conditions see electrical characteristics . (2) minimum vin operating voltage is defined with vcc supplied by the internal hv startup regulator and no external load on vcc. when vcc is supplied by an external source, minimum vin operating voltage is 4.5 v. 6.5 thermal information lm5117, lm5117-q1 thermal metric (1) pwp (htssop) rtw (wqfn) unit 20 pins 24 pins r ja junction-to-ambient thermal resistance 40 40 c/w r jc(top) junction-to-case (top) thermal resistance 4 6 c/w (1) for more information about traditional and new thermal metrics, see the semiconductor and ic package thermal metrics application report, spra953 . 6 submit documentation feedback copyright ? 2011 ? 2015, texas instruments incorporated product folder links: lm5117 lm5117-q1
lm5117 , lm5117-q1 www.ti.com snvs698f ? april 2011 ? revised august 2015 6.6 electrical characteristics typical limits are for t j = 25 c only, represent the most likely parametric norm at t j = 25 c, and are provided for reference purposes only; minimum and maximum limits apply over the junction temperature range of ? 40 c to +125 c. unless otherwise specified, the following conditions apply: v vin = 48 v, v vccdis = 0 v, r t = 25 k ? , no load on lo and ho. parameter test conditions min typ max unit vin supply v ss = 0 v 4.8 6.2 ma i bias v in operating current (1) v ss = 0 v, v vccdis = 2 v 0.4 0.55 ma i shutdown v in shutdown current v ss = 0 v, v uvlo = 0 v 16 40 a vcc regulator v cc(reg) vcc regulation no load 6.85 7.6 8.2 v v vin = 5.5 v, no external load 0.05 0.14 v vcc dropout (vin to vcc) v vin = 6 v, i cc = 20 ma 0.4 0.5 v vcc sourcing current limit v vcc = 0 v 30 42 ma v ss = 0 v, v vccdis = 2 v 4 5 ma i vcc vcc operating current (1) v ss = 0 v, v vccdis = 2 v, v vcc = 14 5.8 7.3 ma v vcc undervoltage threshold vcc rising 4.7 4.9 5.15 v vcc undervoltage hysteresis 0.2 v vcc disable vccdis threshold vccdis rising 1.22 1.25 1.29 v vccdis hysteresis 0.06 v vccdis input current v vccdis = 0 v -20 na vccdis pulldown resistance 500 k ? uvlo uvlo threshold uvlo rising 1.22 1.25 1.29 v uvlo hysteresis current v uvlo = 1.4 v 15 20 25 a uvlo shutdown threshold uvlo falling 0.23 0.3 v uvlo shutdown hysteresis 0.1 v soft start i ss ss current source v ss = 0 v 7 10 12 a ss pulldown resistance 13 24 ? error amplifier v ref fb reference voltage measured at fb, fb = comp 788 800 812 mv fb input bias current v fb = 0.8 v 1 na v oh comp output high voltage i source = 3 ma 2.8 v v ol comp output low voltage i sink = 3 ma 0.26 v a ol dc gain 80 db ? bw unity gain bandwidth 3 mhz pwm comparator t ho(off) forced ho off-time 260 320 440 ns t on(min) minimum ho on-time v vin = 65 v 100 ns comp to pwm comparator offset 1.2 v oscillator ? sw1 frequency 1 r t = 25 k ? 180 200 220 khz ? sw2 frequency 2 r t = 10 k ? 430 480 530 khz rt output voltage 1.25 v rt sync positive threshold 2.6 3.2 3.95 v sync pulse width 100 ns (1) operating current does not include the current into the r t resistor. copyright ? 2011 ? 2015, texas instruments incorporated submit documentation feedback 7 product folder links: lm5117 lm5117-q1
lm5117 , lm5117-q1 snvs698f ? april 2011 ? revised august 2015 www.ti.com electrical characteristics (continued) typical limits are for t j = 25 c only, represent the most likely parametric norm at t j = 25 c, and are provided for reference purposes only; minimum and maximum limits apply over the junction temperature range of ? 40 c to +125 c. unless otherwise specified, the following conditions apply: v vin = 48 v, v vccdis = 0 v, r t = 25 k ? , no load on lo and ho. parameter test conditions min typ max unit current limit cycle-by-cycle sense voltage v cs(th) v ramp = 0 v, csg to cs 106 120 135 mv threshold cs input bias current v cs = 0 v ? 100 -66 a csg input bias current v csg = 0 v ? 100 -66 a current sense amplifier gain 10 v/v hiccup mode fault timer 256 cycles res i res res current source 10 a v res res threshold res rising 1.22 1.25 1.285 v diode emulation v il demb input low threshold 2 1.65 v v ih demb input high threshold 2.95 2.5 v sw zero cross threshold ? 5 mv demb input pulldown resistance 50 k ? current monitor current monitor amplifier gain cs to cm 17.5 20.5 23.5 v/v current monitor amplifier gain drift over temperature ? 2 0 2 % zero input offset 25 120 mv ho gate driver v ohh ho high-state voltage drop i ho = ? 100 ma, v ohh = v hb ? v ho 0.17 0.3 v v olh ho low-state voltage drop i ho = 100 ma, v olh = v ho ? v sw 0.1 0.2 v ho rise time c-load = 1000 pf (2) 6 ns ho fall time c-load = 1000pf (2) 5 ns i ohh peak ho source current v ho = 0 v, sw = 0 v, hb = 7.6 v 2.2 a i olh peak ho sink current v ho = v hb = 7.6 v 3.3 a hb to sw undervoltage 2.56 2.9 3.32 v hb dc bias current hb ? sw = 7.6 v 65 100 a lo gate driver v ohl lo high-state voltage drop i lo = ? 100 ma, v ohl = v cc -v lo 0.17 0.27 v v oll lo low-state voltage drop i lo = 100 ma, v oll = v lo 0.1 0.2 v lo rise time c-load = 1000 pf (2) 6 ns lo fall time c-load = 1000 pf (2) 5 ns i ohl peak lo source current v lo = 0 v 2.5 a i oll peak lo sink current v lo = 7.6 v 3.3 a thermal t sd thermal shutdown temperature rising 165 c thermal shutdown hysteresis 25 c (2) high and low reference are 80% and 20% of the pulse amplitude, respectively. 6.7 switching characteristics over operating free-air temperature range (unless otherwise noted) parameter test conditions min typ max unit t dlh lo fall to ho rise delay 72 ns no load t dhl ho fall to lo rise delay 71 ns 8 submit documentation feedback copyright ? 2011 ? 2015, texas instruments incorporated product folder links: lm5117 lm5117-q1
lm5117 , lm5117-q1 www.ti.com snvs698f ? april 2011 ? revised august 2015 6.8 typical characteristics figure 1. ho peak driver current vs output voltage figure 2. lo peak driver current vs output voltage figure 3. driver dead time vs v vcc figure 4. driver dead time vs temperature figure 5. forced ho off-time vs temperature figure 6. switching frequency vs r t copyright ? 2011 ? 2015, texas instruments incorporated submit documentation feedback 9 product folder links: lm5117 lm5117-q1
lm5117 , lm5117-q1 snvs698f ? april 2011 ? revised august 2015 www.ti.com typical characteristics (continued) figure 7. v vcc vs i vcc figure 8. v vcc vs v vin figure 9. v cs(th) vs temperature figure 10. v ref vs temperature figure 12. error amp gain and phase vs frequency figure 11. v vcc vs temperature 10 submit documentation feedback copyright ? 2011 ? 2015, texas instruments incorporated product folder links: lm5117 lm5117-q1
lm5117 , lm5117-q1 www.ti.com snvs698f ? april 2011 ? revised august 2015 typical characteristics (continued) figure 13. v cm vs i out figure 14. v cm vs v csg-cs 7 detailed description 7.1 overview the lm5117 high voltage switching controller features all of the functions necessary to implement an efficient high voltage buck regulator that operates over a very wide input voltage range. this easy to use controller integrates high-side and low-side nmos drivers. the regulator control method is based upon peak current mode control utilizing an emulated current ramp. peak current mode control provides inherent line feed-forward, cycle- by-cycle current limiting and ease of loop compensation. the use of an emulated control ramp reduces noise sensitivity of the pwm circuit, allowing reliable processing of the very small duty cycles necessary in high input voltage applications. the switching frequency is user programmable up to 750 khz. the rt pin allows the switching frequency to be programmed by a single resistor or synchronized to an external clock. fault protection features include cycle-by- cycle and hiccup mode current limiting, thermal shutdown and remote shutdown capability by pulling down uvlo pin. the uvlo input enables the regulator when the input voltage reaches a user selected threshold and provides a very low quiescent shutdown current when pulled low. a unique analog telemetry feature provides averaged output current information, allowing various applications that need either a current monitor or current control. the functional block diagram and typical application circuit of the lm5117 are shown in functional block diagram . the device is available in a htssop-20 (6.5 mm x 4.4 mm) package, as well as a wqfn-24 (4 mm 4 mm) package which features an exposed pad to aid in thermal dissipation. copyright ? 2011 ? 2015, texas instruments incorporated submit documentation feedback 11 product folder links: lm5117 lm5117-q1
lm5117 , lm5117-q1 snvs698f ? april 2011 ? revised august 2015 www.ti.com 7.2 functional block diagram 12 submit documentation feedback copyright ? 2011 ? 2015, texas instruments incorporated product folder links: lm5117 lm5117-q1 rt res agnd ref disable vcc ho driver lo driver level shift/ adaptive timer + - s r q q clk + - + - -+ ++ - 1.2v demb ss current vin vcc uvlo vcc off fb ss hb ho sw lo cs pgnd comp csg cm vcc regulator thermal shutdown uvlo shutdown threshold standby standby vcc off res reset uvlo threshold uvlo hysteresis current restart timer hiccup mode fault timer 256 cycles res current uvlo vcc standby de_enable + - standby res reset hiccup 10 u v cs(th) pwm comparator c/l comparator 50 k : + - + - de_enable 2.0 / 2.5v oscillator / sync detector clk a=2 40 k : conditioner current sense amplifier ramp ho_enable + - + - zcd comparator -5 mv diode emulation control lo_enable err amp vccdis 500 k : vccdis threshold vcc off + - de_enable lm5117 ref v out v in c in c out1 c out2 l o q h q l r snb c snb r s r gh r gl d hb c vcc c cs r cs2 r cs1 c hb r vin c vin sync c ft c ramp r ramp r fb2 r fb1 r comp c comp c hf c sync r t c res c ss r uv2 r uv1 r cm c cm standby standby vcc off ho_enable hb uvlo current monitor amplifier a=10
lm5117 , lm5117-q1 www.ti.com snvs698f ? april 2011 ? revised august 2015 7.3 feature description 7.3.1 high voltage start-up regulator and vcc disable the lm5117 contains an internal high voltage bias regulator that provides the vcc bias supply for the pwm controller and nmos gate drivers. the vin pin can be connected to an input voltage source as high as 65 v. the output of the vcc regulator is set to 7.6v. when the input voltage is below the vcc set-point level, the vcc output tracks the vin with a small dropout voltage. the output of the vcc regulator is current limited at 30ma minimum. upon power-up, the regulator sources current into the capacitor connected to the vcc pin. the recommended capacitance range for the pin vcc is 0.47 f to 10 f. when the vcc pin voltage exceeds the vcc uv threshold and the uvlo pin is greater than uvlo threshold, the ho and lo drivers are enabled and a soft-start sequence begins. the ho and lo drivers remain enabled until either the vcc pin voltage falls below vcc uv threshold, the uvlo pin voltage falls below uvlo threshold, hiccup mode is activated or the die temperature exceeds the thermal shutdown threshold. enabling/disabling the ic by controlling uvlo is recommended in most of cases. an output voltage derived bias supply can be applied to the vcc pin to reduce the controller power dissipation at higher input voltage. the vccdis input can be used to disable the internal vcc regulator when external biasing is supplied. the externally supplied bias should be coupled to the vcc pin through a diode, preferably a schottky diode. if the vccdis pin voltage exceeds the vccdis threshold, the internal vcc regulator is disabled. vccdis has a 500-k ? internal pull-down resistor to ground for normal operation with no external bias. the vcc regulator series pass transistor includes a diode between vcc (anode) and vin (cathode) that should not be forward biased in normal operation. if the voltage of the external bias supply is greater than the vin pin voltage, an external blocking diode is required from the input power supply to the vin pin to prevent the external bias supply from passing current to the input supply through vcc. figure 15. vin configuration for v vin < v vcc for v out between 6 v and 14.5 v, the output can be connected directly to vcc through a diode. figure 16. external vcc supply for 6 v < v out < 14.5 v for v out < 6 v, a bias winding on the output inductor can be added to generate the external vcc supply voltage. figure 17. external vcc supply for v out < 6 v copyright ? 2011 ? 2015, texas instruments incorporated submit documentation feedback 13 product folder links: lm5117 lm5117-q1 vcc vccdis lm5117 v out vccdis resistor divider is required when external vcc supplying voltage is smaller than 8.5v sw vcc vccdis lm5117 v out vccdis resistor divider is required when external vcc supplying voltage is smaller than 8.5v vin lm5117 v in vcc external vcc supply
lm5117 , lm5117-q1 snvs698f ? april 2011 ? revised august 2015 www.ti.com feature description (continued) for 14.5 v < v out , the external supply voltage can be regulated by using a series zener diode from the output to vcc. figure 18. external vcc supply for 14.5 v < v out in high input voltage applications, extra care should be taken to ensure the vin pin does not exceed the absolute maximum voltage rating of 75v. during line or load transients, voltage ringing on the vin that exceeds the absolute maximum rating can damage the ic. both careful pc board layout and the use of quality bypass capacitors located close to the vin and agnd pin are essential. adding an r-c filter (r vin , c vin ) on vin is optional and helps to prevent faulty operation caused by poor pc board layout and high frequency switching noise injection. the recommended capacitance and resistance range are 0.1 f to 10 f and 1 ? to 10 ? . 7.3.2 uvlo the lm5117 contains a dual level uvlo (under-voltage lockout) circuit. when the uvlo is less than 0.4 v, the lm5117 is in shutdown mode. the shutdown comparator provides 100 mv of hysteresis to avoid chatter during transitions. when the uvlo pin voltage is greater than 0.4 v but less than 1.25 v, the controller is in standby mode. in the standby mode, the vcc bias regulator is active but the ho and lo drivers are disabled and the ss pin is held low. this feature allows the uvlo pin to be used as a remote shutdown function by pulling the uvlo pin down below 0.4 v with an external open collector or open drain device. when the vcc pin exceeds its under- voltage lockout threshold and the uvlo pin voltage is greater than 1.25 v, the ho and lo drivers are enabled and normal operation begins. figure 19. uvlo configuration the uvlo pin should not be left floating. an external uvlo set-point voltage divider from the vin to agnd is used to set the minimum input operating voltage of the regulator. the divider must be designed such that the voltage at the uvlo pin is greater than 1.25 v and never exceeds 15 v when the input voltage is in the desired operating range. if necessary, the uvlo pin can be clamped with a zener diode. uvlo hysteresis is accomplished with an internal 20 a current source that is switched on or off into the impedance of the uvlo set-point divider. when the uvlo pin voltage exceeds the 1.25 v threshold, the current source is enabled to quickly raise the voltage at the uvlo pin. when the uvlo pin voltage falls below the 1.25 v threshold, the current source is disabled causing the voltage at the uvlo pin to quickly fall. the use of a c ft capacitor in parallel with r uv1 helps to minimize switching noise injection into uvlo pin, but it may slow down the falling speed of the uvlo pin when the 20 a current source is disabled. the recommended range for c ft is 10 pf to 220 pf. 14 submit documentation feedback copyright ? 2011 ? 2015, texas instruments incorporated product folder links: lm5117 lm5117-q1 lm5117 v in uvlo shutdown threshold shutdown uvlo threshold uvlo hysteresis current uvlo + - + - c ft r uv2 r uv1 standby vcc lm5117 v out zener r 1 r1 is required to limit maximum reverse zener current 30 k : minimum resistive loss at vcc guarantees minimum reverse zener current 30 k :
lm5117 , lm5117-q1 www.ti.com snvs698f ? april 2011 ? revised august 2015 feature description (continued) the values of r uv1 and r uv2 can be determined from the following equations: (1) where ? v hys is the desired uvlo hysteresis and v in(startup) is the desired start-up voltage of the regulator during turn- on (2) 7.3.3 oscillator and sync capability the lm5117 switching frequency is programmed by a single external resistor connected between the rt pin and the agnd pin. the resistor should be located very close to the device and connected directly to the rt and agnd pins. to set a desired switching frequency ( ? sw ), the resistor value can be calculated from the following equation: (3) the rt pin can be used to synchronize the internal oscillator to an external clock. the internal oscillator can be synchronized by ac coupling a positive edge into the rt pin. the voltage at the rt pin is nominally 1.25 v and the voltage at the rt pin must exceed the rt sync positive threshold to trip the internal synchronization pulse detector. a 5 v amplitude pulse signal coupled through a 100-pf capacitor is a good starting point. the frequency of the external synchronization pulse is recommended to be within 10% of the frequency programmed by the rt resistor but will operate to +100/-40% of the programmed frequency. care should be taken to guarantee that the rt pin voltage does not go below ? 0.3 v at the falling edge of the external pulse. this may limit the duty cycle of external synchronization pulse. the r t resistor is always required, whether the oscillator is free running or externally synchronized. 7.3.4 ramp generator and emulated current sense the ramp signal used in the pulse width modulator for traditional current mode control is typically derived directly from the high-side switch current. this switch current corresponds to the positive slope portion of the inductor current. using this signal for the pwm ramp simplifies the control loop transfer function to a single pole response and provides inherent input voltage feed-forward compensation. the disadvantage of using the high-side switch current signal for pwm control is the large leading edge spike due to circuit parasitics that must be filtered or blanked. minimum achievable pulse width is limited by the filtering, blanking time and propagation delay with a high-side current sensing scheme. in the applications where the input voltage may be relatively large in comparison to the output voltage, controlling small pulse widths and duty cycles are necessary for regulation. the lm5117 utilizes a unique ramp generator which does not actually measure the high-side switch current but rather reconstructs the signal. representing or emulating the inductor current provides a ramp signal to the pwm comparator that is free of leading edge spikes and measurement or filtering delays, while maintaining the advantages of traditional peak current mode control. the current reconstruction is comprised of two elements: a sample-and-hold dc level and the emulated inductor current ramp as shown in figure 20 . the sample-and-hold dc level is derived from a measurement of the recirculating current flowing through the current sense resistor. the voltage across the sense resistor is sampled and held just prior to the onset of the next conduction interval of the high-side switch. the current sense amplifier with a gain of 10 and sample-and-hold circuit provide the dc level of the reconstructed current signal as shown in figure 21 . copyright ? 2011 ? 2015, texas instruments incorporated submit documentation feedback 15 product folder links: lm5117 lm5117-q1 5.2 x 10 9 r t = - 948 [ 5 ] f sw 1.25v x r uv2 r uv1 = v in(startup) - 1.25v [ 5 ] v hys r uv2 = 20 a [ 5 ]
lm5117 , lm5117-q1 snvs698f ? april 2011 ? revised august 2015 www.ti.com feature description (continued) figure 20. composition of emulated current sense signal figure 21. ramp generator and current limit circuit the positive slope inductor current ramp is emulated by c ramp connected between ramp and agnd and r ramp connected between sw and ramp. r ramp should not be connected to vin directly because the ramp pin absolute maximum voltage rating could be exceeded under high input voltage conditions. c ramp is discharged by an internal switch during the off-time and must be fully discharged during the minimum off-time. this limits the ramp capacitor to be less than 2 nf. a good quality, thermally stable ceramic capacitor is recommended for c ramp . the selection of r ramp and c ramp can be simplified by adopting a k factor, which is defined as: where ? a s is the current sense amplifier gain which is normally 10 (4) by choosing 1 as the k factor, the regulator removes any error after one switching cycle and the design procedure is simplified. see application and implementation for detailed information. 7.3.5 error amplifier and pwm comparator the internal high-gain error amplifier generates an error signal proportional to the difference between the fb pin voltage and the internal precision 0.8-v reference. the output of error amplifier is connected to the comp pin allowing the user to provide type 2 loop compensation components, r comp , c comp and optional c hf . 16 submit documentation feedback copyright ? 2011 ? 2015, texas instruments incorporated product folder links: lm5117 lm5117-q1 l o r ramp x c ramp x r s x a s k = ho_enable sw cs ramp csg + - + - a s =10 r ramp c ramp r s i l 10 x v cs(th) current limit comparator current sense amplifier lm5117 sample and hold dc level t on i lo x r s x 10 additional slope v in x t on r ramp x c ramp ramp pk =
lm5117 , lm5117-q1 www.ti.com snvs698f ? april 2011 ? revised august 2015 feature description (continued) figure 22. feedback configuration and pwm comparator r comp , c comp and c hf configure the error amplifier gain and phase characteristics to achieve a stable voltage loop gain. this network creates a pole at dc (f p1 ), a mid-band zero (f z ) for phase boost, and a high frequency pole (f p2 ). the recommended range of r comp is 2 k ? to 40 k ? . see application and implementation for detailed information. (5) (6) (7) the pwm comparator compares the emulated current sense signal from ramp generator to the voltage at the comp pin through a 1.2-v internal voltage drop and terminates the present cycle when the emulated current sense signal is greater than v comp ? 1.2 v. 7.3.6 soft-start the soft-start feature allows the regulator to gradually reach the steady state operating point, thus reducing startup stresses and surges. the lm5117 regulates the fb pin to the ss pin voltage or the internal 0.8-v reference, whichever is lower. the internal 10- a soft-start current source gradually increases the voltage on an external soft-start capacitor connected to the ss pin. this results in a gradual rise of the output voltage. soft-start time (t ss ) can be calculated from the following equation: (8) the lm5117 can track the output of a master power supply during soft-start by connecting a voltage divider from the output of master power supply to the ss pin. at the beginning of the soft-start sequence, v ss should be allowed to go below 25 mv by the internal ss pull-down switch. during soft-start period, when ss pin voltage is less than 0.8v, the lm5117 forces diode emulation for startup into a pre-biased load. if the tracking feature is desired, connect the demb pin to gnd or leave the pin floating. 7.3.7 cycle-by-cycle current limit the lm5117 contains a current limit monitoring scheme to protect the regulator from possible over-current conditions as shown in figure 21 . if the emulated ramp signal exceeds 1.2 v, the present cycle is terminated. for the case where the switch current overshoots when the inductor is saturated or the output is shorted to ground, the sample-and-hold circuit detects the excess recirculating current before the high-side nmos driver is turned on again. the high-side nmos driver is disabled and will skip pulses until the current has decayed below the current limit threshold. this approach prevents current runaway conditions since the inductor current is forced to decay to a controlled level following any current overshoot. copyright ? 2011 ? 2015, texas instruments incorporated submit documentation feedback 17 product folder links: lm5117 lm5117-q1 10 a c ss x 0.8v t ss = [sec] f p2 = 1 c comp x c hf c comp + c hf 2 s x r comp x 1 ? [hz] 2 s x r comp x c comp 1 f z = [hz] f p1 = 0 [hz] v out comp fb lm5117 + - r fb2 r fb1 r comp c comp c hf ref error amplifier type 2 compensation components -+ pwm comparator + - ramp generator output (optional)
lm5117 , lm5117-q1 snvs698f ? april 2011 ? revised august 2015 www.ti.com feature description (continued) maximum peak inductor current can be calculated as: (9) where ? i pp represents inductor peak to peak ripple current in figure 23 , and is defined as: (10) (11) figure 23. inductor current during an output short condition, the worst case peak inductor current is limited to: where ? t on(min) is the minimum ho on-time (12) in most cases, especially if the output voltage is relatively high, it is recommended that a soft-saturating inductor such as a powder core device is used. if a sharp-saturating inductor is used, the inductor saturation level must be above i lim_pk . the temperatures of the nmos devices, r s and inductor should be checked under this output short condition. 7.3.8 hiccup mode current limiting to further protect the regulator during prolonged current limit conditions, lm5117 provides a hiccup mode current limit. an internal hiccup mode fault timer counts the pwm clock cycles during which cycle-by-cycle current limiting occurs. when the hiccup mode fault timer detects 256 consecutive cycles of current limiting, an internal restart timer forces the controller to enter a low power dissipation standby mode and starts sourcing 10 a of current into the res pin capacitor c res . in this standby mode, ho and lo outputs are disabled and the soft-start capacitor c ss is discharged. 18 submit documentation feedback copyright ? 2011 ? 2015, texas instruments incorporated product folder links: lm5117 lm5117-q1 r s l o v in(max) x t on(min) + i lim_pk = v cs(th) [a] 0 i out i pp f sw 1 t= ? 1 ? v in i pp = 1 - v out v out x l o x f sw [a] 2 i pp i l(max)_ave = i l(max)_pk - [a] v out f sw x a s x r s x r ramp x c ramp + i pp - v cs(th) r s i l(max)_pk = [a]
lm5117 , lm5117-q1 www.ti.com snvs698f ? april 2011 ? revised august 2015 feature description (continued) c res is connected from res pin to agnd and determines the time (t res ) in which the lm5117 remains in the standby before automatically restarting. when the res pin voltage exceeds the 1.25-v res threshold, res capacitor is discharged and a soft-start sequence begins. t res can be calculated from the following equation: (13) figure 24. hiccup mode current limit timing diagram figure 25. hiccup mode current limit circuit the res pin can also be configured for latch-off mode current limiting or non-hiccup mode cycle-by-cycle current limiting. if the res pin is tied to vcc or a voltage greater than the res threshold at initial power-on, the restart timer is disabled and the regulator operates with non-hiccup mode cycle-by-cycle current limit. if the res pin is tied to gnd, the regulator enters into the standby mode after 256 consecutive cycles of current limiting and then never restarts until uvlo shutdown is cycled. the restart timer is configured during initial power-on when uvlo is above the uvlo threshold and vcc is above the vcc uv threshold. figure 26. res configurations copyright ? 2011 ? 2015, texas instruments incorporated submit documentation feedback 19 product folder links: lm5117 lm5117-q1 res lm5117 vcc c res res lm5117 res lm5117 vcc (a) hiccup mode current limit (b) latch-off mode current limit (c) cycle-by-cycle current limit res restart timer hiccup mode fault timer 256 cycles res current standby hiccup current limit comparator c res + - lm5117 ho lo ss res 0v 1.25v res threshold 0.8v ref current limit detected current limit persists during 256 consecutive cycles t ss t res i res = 10 a i ss = 10 a 10 p a c res x 1.25v t res = [sec]
lm5117 , lm5117-q1 snvs698f ? april 2011 ? revised august 2015 www.ti.com feature description (continued) 7.3.9 ho and lo drivers the lm5117 contains high current nmos drivers and an associated high-side level shifter to drive the external high-side nmos device. this high-side gate driver works in conjunction with an external diode d hb , and bootstrap capacitor c hb . a 0.1- f or larger ceramic capacitor, connected with short traces between the hb and sw pin, is recommended. during the off-time of the high-side nmos driver, the sw pin voltage is approximately 0v and the c hb is charged from vcc through the d hb . when operating with a high pwm duty cycle, the high- side nmos device is forced off each cycle for 320 ns to ensure that c hb is recharged. the lo and ho outputs are controlled with an adaptive dead-time methodology which insures that both outputs are never enabled at the same time. when the controller commands ho to be enabled, the adaptive dead-time logic first disables lo and waits for the lo voltage to drop. ho is then enabled after a small delay (lo fall to ho rise delay). similarly, the lo turn-on is delayed until the ho voltage has discharged. lo is then enabled after a small delay (ho fall to lo rise delay). this technique insures adequate dead-time for any size nmos device, especially when vcc is supplied by a higher external voltage source. the adaptive dead-time circuitry monitors the voltages of ho and lo outputs and insures the dead-time between the ho and lo outputs. adding a gate resister, r gh or r gl , may decrease the effective dead-time. care should be exercised in selecting an output nmos device with the appropriate threshold voltage, especially if vcc is supplied by an external bias supply voltage below the vcc regulation level. during startup at low input voltages, the low-side nmos device gate plateau voltage should be lower than the vcc under-voltage lockout threshold. otherwise, there may be insufficient vcc voltage to completely enhance the nmos device as the vcc under-voltage lockout is released during startup. if the high-side nmos drive voltage is lower than the high- side nmos device gate plateau voltage during startup, the regulator may not start or it may hang up momentarily in a high power dissipation state. this condition can be addressed by selecting an nmos device with a lower threshold voltage. this situation can be avoided if the minimum input voltage programmed by the uvlo resistor is above the vcc regulation level. 7.3.10 current monitor the lm5117 provides average output current information, enabling various applications requiring monitoring or control of the output current. figure 27. current monitor the average of cm output can be calculated by: (14) the current monitor output is only valid in continuous conduction operation. the current monitor has a limited bandwidth of approximately one tenth of f sw . adding an r-c filter, r cm and c cm , on the output of current monitor with the cut off frequency below one tenth of f sw is recommended to attenuate sampling noise. 20 submit documentation feedback copyright ? 2011 ? 2015, texas instruments incorporated product folder links: lm5117 lm5117-q1 ( ) [ ] cm _ ave peak valley s s v i i r a v = + cm a m = 2 40 k : r cm c cm current monitor amplifier current sense amplifier output lm5117 conditioner
lm5117 , lm5117-q1 www.ti.com snvs698f ? april 2011 ? revised august 2015 feature description (continued) 7.3.11 maximum duty cycle when operating with a high pwm duty cycle, the high-side nmos device is forced off each cycle for 320ns to ensure that c hb is recharged and to allow time to sample and hold the current in the low-side nmos fet. this forced off-time limits the maximum duty cycle of the controller. when designing a regulator with high switching frequency and high duty cycle requirements, a check should be made of the required maximum duty cycle against the graph shown in figure 28 . the actual maximum duty cycle varies with the switching frequency as follows: figure 28. maximum duty cycle vs switching frequency 7.3.12 thermal protection internal thermal shutdown circuitry is provided to protect the controller in the event the maximum junction temperature is exceeded. when activated, typically at 165 c, the controller is forced into a low power shutdown mode, disabling the output drivers and the vcc regulator. this feature is designed to prevent overheating and destroying the device. 7.4 device functional modes 7.4.1 diode emulation a fully synchronous buck regulator implemented with a freewheeling nmos rather than a diode has the capability to sink current from the output in certain conditions such as light load, over-voltage or pre-bias startup. the lm5117 provides a diode emulation feature that can be enabled to prevent reverse current flow in the low- side nmos device. when configured for diode emulation, the low-side nmos driver is disabled when sw pin voltage is greater than -5mv during the off-time of the high-side nmos driver, preventing reverse current flow. a benefit of the diode emulation is lower power loss at no load or light load conditions. the negative effect of diode emulation is degraded light load transient response. the diode emulation feature is configured with the demb pin. to enable diode emulation, connect the demb pin to gnd or leave the pin floating. if continuous conduction operation is desired, the demb pin should be tied to a voltage greater than 3 v and may be connected to vcc. the lm5117 forces the regulator to operate in diode emulation mode when ss pin voltage is less than the internal 0.8-v reference, allowing for startup into a pre- biased load with the continuous conduction configuration. copyright ? 2011 ? 2015, texas instruments incorporated submit documentation feedback 21 product folder links: lm5117 lm5117-q1
lm5117 , lm5117-q1 snvs698f ? april 2011 ? revised august 2015 www.ti.com 8 application and implementation note information in the following applications sections is not part of the ti component specification, and ti does not warrant its accuracy or completeness. ti ? s customers are responsible for determining suitability of components for their purposes. customers should validate and test their design implementation to confirm system functionality. 8.1 application information the lm5117 is a step-down dc-dc controller. the device is typically used to convert a higher dc-dc voltage to a lower dc voltage. use the following design procedure to select component values. alternately, use the webench ? software to generate a complete design. the webench software uses an iterative design procedure and assesses a comprehensive database of components when generating a design. 8.2 typical applications figure 29. 12 v, 9 a typical application schematic 8.3 detailed design procedure 8.3.1 feedback compensation open loop response of the regulator is defined as the product of modulator transfer function and feedback transfer function. when plotted on a db scale, the open loop gain is shown as the sum of modulator gain and feedback gain. 22 submit documentation feedback copyright ? 2011 ? 2015, texas instruments incorporated product folder links: lm5117 lm5117-q1
lm5117 , lm5117-q1 www.ti.com snvs698f ? april 2011 ? revised august 2015 detailed design procedure (continued) the modulator transfer function includes a power stage transfer function with an embedded current loop and can be simplified as one pole and one zero system as shown in equation 15 . (15) if the esr of c out (r esr ) is very small, the modulator transfer function can be further simplified to a one pole system and the voltage loop can be closed with only two loop compensation components, r comp and c comp , leaving a single pole response at the crossover frequency. a single pole response at the crossover frequency yields a very stable loop with 90 degrees of phase margin. the feedback transfer function includes the feedback resistor divider and loop compensation of the error amplifier. r comp , c comp and optional c hf configure the error amplifier gain and phase characteristics and create a pole at origin, a low frequency zero and a high frequency pole. this is shown mathematically in equation 16 . (16) the pole at the origin minimizes output steady state error. the low frequency zero should be placed to cancel the load pole of the modulator. the high frequency pole can be used to cancel the zero created by the output capacitor esr or to decrease noise susceptibility of the error amplifier. by placing the low frequency zero an order of magnitude less than the crossover frequency, the maximum amount of phase boost can be achieved at the crossover frequency. the high frequency pole should be placed well beyond the crossover frequency since the addition of c hf adds a pole in the feedback transfer function. the crossover frequency (loop bandwidth) is usually selected between one twentieth and one fifth of the f sw . in a simplified formula, the crossover frequency can be defined as: (17) for higher crossover frequency, r comp can be increased, while proportionally decreasing c comp . conversely, decreasing r comp while proportionally increasing c comp , results in lower bandwidth while keeping the same zero frequency in the feedback transfer function. the sampled gain inductor pole is inversely proportional to the k factor, which is defined as: (18) copyright ? 2011 ? 2015, texas instruments incorporated submit documentation feedback 23 product folder links: lm5117 lm5117-q1 k - 0.5 f sw z p_hf = 2 x ' x r s x r fb2 x a s x c out r comp f cross = [hz] r fb2 x (c comp + c hf ) 1 where a fb (feedback dc gain) = , r comp x c comp 1 w z_ea (low frequency zero) = , r comp x c hf 1 w p_ea (high frequency pole) = = s a fb x z p_ea v out ^ v comp ^ - z z_ea 1 + s s x ( 1+ ) 1 r load x c out z p_lf (load pole) = z z_esr (esr zero) = 1 r esr x c out , r load r s x a s where a m (modulator dc gain) = , z z_esr 1 + v out v comp = a m x s 1+ s z p_lf ? 1 ^ ^
lm5117 , lm5117-q1 snvs698f ? april 2011 ? revised august 2015 www.ti.com detailed design procedure (continued) the maximum achievable loop bandwidth, in fact, is limited by this sampled gain inductor pole. in traditional current mode control, the maximum achievable loop bandwidth varies with input voltage. with the lm5117 ? s unique slope compensation scheme, the sampled gain inductor pole is independent of changes to the input voltage. this frees the user from additional concerns in wide varying input range applications and is an advantage of the lm5117. if the sampled gain inductor pole or the esr zero is close to the crossover frequency, it is recommended that the comprehensive formulas in table 1 be used and the stability should be checked by a network analyzer. the modulator transfer function can be measured and the feedback transfer function can be configured for the desired open loop transfer function. if a network analyzer is not available, step load transient tests can be performed to verify acceptable performance. the step load goal is minimum overshoot/undershoot with a damped response. 8.3.2 sub-harmonic oscillation peak current mode regulators can exhibit unstable behavior when operating above 50% duty cycle. this behavior is known as sub-harmonic oscillation and is characterized by alternating wide and narrow pulses at the sw pin. sub-harmonic oscillation can be prevented by adding an additional voltage ramp (slope compensation) on top of the sensed inductor current shown in figure 20 . by choosing k 1, the regulator will not be subject to sub-harmonic oscillation caused by a varying input voltage. in time-domain analysis, the steady-state inductor current starts and ends at the same value during one clock cycle. if the magnitude of the end-of-cycle current error, di 1 , caused by an initial perturbation, di 0 , is less than the magnitude of di 0 or di 1 /di 0 > -1, the perturbation naturally disappears after a few cycles. when di 1 /di 0 < -1, the initial perturbation does not disappear, resulting in sub-harmonic oscillation in steady-state operation. figure 30. effect of initial perturbation when dl 1 /dl 0 < -1 di 1 /di 0 can be calculated by: (19) the relationship between di 1 /di 0 and k factor is illustrated graphically in figure 31 . figure 31. dl 1 /dl 0 vs k factor 24 submit documentation feedback copyright ? 2011 ? 2015, texas instruments incorporated product folder links: lm5117 lm5117-q1 = 1 - k 1 dl 0 dl 1 steady-state inductor current di 0 di 1 t on inductor current with initial perturbation
lm5117 , lm5117-q1 www.ti.com snvs698f ? april 2011 ? revised august 2015 detailed design procedure (continued) the minimum value of k is 0.5. when k < 0.5, the amplitude of di 1 is greater than the amplitude of di 0 and any initial perturbation results in sub-harmonic oscillation. if k=1, any initial perturbation will be removed in one switching cycle. this is known as one-cycle damping. when -1 < dl 1 /dl 0 < 0, any initial perturbation will be under- damped. any perturbation will be over-damped when 0 < dl 1 /dl 0 < 1. in the frequency-domain, q, the quality factor of the sampling gain term in the modulator transfer function, is used to predict the tendency for sub-harmonic oscillation, which is defined as: (20) the relationship between q and k factor is illustrated graphically in figure 32 . figure 32. sampling gain q vs k factor the minimum value of k is 0.5 again. this is the same as time domain analysis result. when k < 0.5, the regulator is unstable. high gain peaking at 0.5 results in sub-harmonic oscillation at f sw /2. when k=1, one-cycle damping is realized. q is equal to 0.673 at this point. a higher k factor may introduce additional phase shift by moving the sampled gain inductor pole closer to the crossover frequency, but will help reduce noise sensitivity in the current loop. the maximum allowable value of k factor can be calculated by the maximum crossover frequency equation in table 1 . 8.3.3 design requirements design parameter example value output voltage 12 v full load current, i out 9 a minimum input voltage, v in(min) 15 v maximum input voltage, v in(max) 55 v switching frequency, ? sw 230 khz diode emulation yes external vcc supply yes 8.3.4 timing resistor r t generally, higher frequency applications are smaller but have higher losses. operation at 230 khz was selected for this example as a reasonable compromise between small size and high efficiency. the value of r t for 230 khz switching frequency can be calculated from equation 3 as follows: (21) a standard value of 22.1 k ? was chosen for r t . copyright ? 2011 ? 2015, texas instruments incorporated submit documentation feedback 25 product folder links: lm5117 lm5117-q1 5.2 x 10 9 r t = 230 x 10 3 - 948 = 21.7 k : 1 s (k-0.5) q =
lm5117 , lm5117-q1 snvs698f ? april 2011 ? revised august 2015 www.ti.com 8.3.5 output inductor l o the maximum inductor ripple current occurs at the maximum input voltage. typically, 20% to 40% of the full load current is a good compromise between core loss and copper loss of the inductor. higher ripple current allows for a smaller inductor size, but places more of a burden on the output capacitor to smooth the ripple voltage on the output. for this example, a ripple current of 40% of 9 a was chosen. knowing the switching frequency, maximum ripple current, maximum input voltage and the nominal output voltage, the inductor value can be calculated as follows: (22) the closest standard value of 10 h was chosen for l o . using the value of 10 h for l o , calculate i pp again. this step is necessary if the chosen value of l o differs significantly from the calculated value. from equation 11 , (23) at the minimum input voltage, this value is 1.04 a. 8.3.6 diode emulation function the demb pin is left floating since this example uses diode emulation to reduce the power loss under no load or light load conditions. 8.3.7 current sense resistor r s the performance of the converter will vary depending on the k value. for this example, k = 1 was chosen to control sub-harmonic oscillation and achieve one-cycle damping. the maximum output current capability (i out(max) ) should be 20~50% higher than the required output current, to account for tolerances and ripple current. for this example, 130% of 9 a was chosen. the current sense resistor value can be calculated from equation 9 and equation 10 as follows: (24) (25) a value of 7.41 m ? was realized for r s by placing an additional 0.1- ? sense resistor in parallel with 8 m ? . the sense resistor must be rated to handle the power dissipation at maximum input voltage when current flows through the low-side nmos for the majority of the pwm cycle. the maximum power dissipation of r s can be calculated as: (26) (27) the worst case peak inductor current under the output short condition can be calculated from equation 12 as follows: where ? t on(min) is normally 100ns (28) 26 submit documentation feedback copyright ? 2011 ? 2015, texas instruments incorporated product folder links: lm5117 lm5117-q1 7.41 m : 10 p h 55v x 100 ns + i lim_pk = 0.12v = 16.7a 1 ? 55v p rs = 1 - x 9a 2 x 7.41 m : = 0.47w 12v ? 1 ? v in(max) p rs = 1 - i out 2 x r s v out x [w] 9a x 1.3 + 230 khz x 10 h 12 x 1 r s = 0.12v = 7.3 m : 1.04a _ 2 r s = v cs(th) >:@ i out(max) + f sw x l o v out x k i pp 2 _ ? 1 ? 55v i pp(max) = x 1 - 12v 12v 10 p h x 230 khz = 4.1a ( ) out out o pp(max) sw in max v v 12 v 12 v l 1 1 11.3 h i f v 9 a 0.4 230khz 55 v ? ? ? ? ? = - = - = m ? ? ? ?
lm5117 , lm5117-q1 www.ti.com snvs698f ? april 2011 ? revised august 2015 8.3.8 current sense filter r cs and c cs the lm5117 itself is not affected by the large leading edge spike because it samples valley current just prior to the onset of the high-side switch. a current sense filter is used to minimize a noise injection from any external noise sources. in general, a current sense filter is not necessary. in this example, a current sense filter is not used adding r cs resistor changes the current sense amplifier gain which is defined as a s =10 k / (1 k+r cs ). a small value of r cs resistor below 100 ? is recommended to minimize the gain change which is caused by the temperature coefficient difference between internal and external resistors. 8.3.9 ramp resistor r ramp and ramp capacitor c ramp the positive slope of the inductor current ramp signal is emulated by r ramp and c ramp . for this example, the value of c ramp was set at the standard capacitor value of 820 pf. with the inductor, sense resistor and the k factor selected, the value of r ramp can be calculated from equation 4 as follows: (29) (30) the standard value of 165 k ? was selected for r ramp . 8.3.10 uvlo divider r uv2 , r uv1 and c ft the desired startup voltage and the hysteresis are set by the voltage divider r uv1 and r uv2 . capacitor c ft provides filtering for the divider. for this design, the startup voltage was set to 14 v, 1 v below v in(min) . v hys was set to 2 v. the value of r uv1 , r uv2 can be calculated from equation 1 and equation 2 as follows: (31) (32) the standard value of 100 k ? was selected for r uv2 . r uv1 was selected to be 9.76 k ? . a value of 47 pf was chosen for c ft . 8.3.11 vcc disable and external vcc supply the 12-v output voltage allows the external vcc supply configuration as shown in figure 16 . in this example, vccdis can be left floating since v out is higher than vcc regulator set-point level. 8.3.12 power switches q h and q l selection of the power nmos devices is governed by the same trade-offs as switching frequency. breaking down the losses in the high-side and low-side nmos devices is one way to compare the relative efficiencies of different devices. losses in the power nmos devices can be broken down into conduction loss, gate charging loss, and switching loss. conduction loss p dc is approximately: (33) where ? d is the duty cycle ? the factor of 1.3 accounts for the increase in the nmos device on-resistance due to heating (34) alternatively, the factor of 1.3 can be eliminated and the high temperature on-resistance of the nmos device can be estimated using the r ds(on) vs temperature curves in the mosfet datasheet. copyright ? 2011 ? 2015, texas instruments incorporated submit documentation feedback 27 product folder links: lm5117 lm5117-q1 p dc (low-side) = (1 d) x (i out 2 x r ds(on) x 1.3) [w] p dc (high-side) = d x (i out 2 x r ds(on) x 1.3) [w] 1.25v x 100 k : 14v -1.25v r uv1 = = 9.8 k : 2v 20 a r uv2 = = 100 k : 10 p h 1 x 820 pf x 7.41 m : x 10 r ramp = = 165 k : l o k x c ramp x r s x a s r ramp = [ :@
lm5117 , lm5117-q1 snvs698f ? april 2011 ? revised august 2015 www.ti.com gate charging loss (p gc ) results from the current driving the gate capacitance of the power nmos devices and is approximated as: (35) qg refers to the total gate charge of an individual nmos device, and ? n ? is the number of nmos devices. gate charge loss differs from conduction and switching losses in that the actual dissipation occurs in the controller ic. switching loss (p sw ) occurs during the brief transition period as the high-side nmos device turns on and off. during the transition period both current and voltage are present in the channel of the nmos device. the switching loss can be approximated as: (36) t r and t f are the rise and fall times of the high-side nmos device. the rise and fall times are usually mentioned in the mosfet datasheet or can be empirically observed with an oscilloscope. switching loss is calculated for the high-side nmos device only. switching loss in the low-side nmos device is negligible because the body diode of the low-side nmos device turns on before and after the low-side nmos device switches. for this example, the maximum drain-to-source voltage applied to either nmos device is 55 v. the selected nmos devices must be able to withstand 55 v plus any ringing from drain to source and must be able to handle at least the vcc voltage plus any ringing from gate to source. 8.3.13 snubber components r snb and c snb a resistor-capacitor snubber network across the low-side nmos device reduces ringing and spikes at the switching node. excessive ringing and spikes can cause erratic operation and can couple noise to the output voltage. selecting the values for the snubber is best accomplished through empirical methods. first, make sure the lead lengths for the snubber connections are very short. start with a resistor value between 5 and 50 ? . increasing the value of the snubber capacitor results in more damping, but higher snubber losses. select a minimum value for the snubber capacitor that provides adequate damping of the spikes on the switch waveform at heavy load. a snubber may not be necessary with an optimized layout. 8.3.14 bootstrap capacitor c hb and bootstrap diode d hb the bootstrap capacitor between the hb and sw pin supplies the gate current to charge the high-side nmos device gate during each cycle ? s turn-on and also supplies recovery charge for the bootstrap diode. these current peaks can be several amperes. the recommended value of the bootstrap capacitor is at least 0.1 f. c hb should be a good quality, low esr, ceramic capacitor located at the pins of the ic to minimize potentially damaging voltage transients caused by trace inductance. the absolute minimum value for the bootstrap capacitor is calculated as: where ? qg is the high-side nmos gate charge ? v hb is the tolerable voltage droop on c hb , which is typically less than 5% of vcc or 0.15 v conservatively (37) a value of 0.47 f was selected for this design. 8.3.15 vcc capacitor c vcc the primary purpose of the vcc capacitor (c vcc ) is to supply the peak transient currents of the lo driver and bootstrap diode as well as provide stability for the vcc regulator. these peak currents can be several amperes. the recommended value of c vcc should be no smaller than 0.47 f, and should be a good quality, low esr, ceramic capacitor. c vcc should be placed at the pins of the ic to minimize potentially damaging voltage transients caused by trace inductance. a value of 1 f was selected for this design. 28 submit documentation feedback copyright ? 2011 ? 2015, texas instruments incorporated product folder links: lm5117 lm5117-q1 c hb q g ' v hb t [f] p sw = 0.5 x v in x i out x (t r + t f ) x f sw [w] p gc = n x v vcc x q g x f sw [w]
lm5117 , lm5117-q1 www.ti.com snvs698f ? april 2011 ? revised august 2015 8.3.16 output capacitor c o the output capacitors smooth the output voltage ripple caused by inductor ripple current and provide a source of charge during transient loading conditions. for this design example, a 470- f electrolytic capacitor with maximum 20m ? esr was selected as the main output capacitor. the fundamental component of the output ripple voltage with maximum esr is approximated as: (38) (39) additional low ers / esl ceramic capacitors can be placed in parallel with the main output capacitor to further reduce the output voltage ripple and spikes. in this example, two 22 f capacitors were added. 8.3.17 input capacitor c in the regulator input supply voltage typically has high source impedance at the switching frequency. good quality input capacitors are necessary to limit the ripple voltage at the vin pin while supplying most of the switch current during the on-time. when the high-side nmos device turns on, the current into the device steps to the valley of the inductor current waveform, ramps up to the peak value, and then drops to the zero at turnoff. the input capacitor should be selected for rms current rating and minimum ripple voltage. a good approximation for the required ripple current rating necessary is i rms > i out / 2. in this example, seven 3.3 f ceramic capacitors were used. with ceramic capacitors, the input ripple voltage will be triangular. the input ripple voltage can be approximated as: (40) (41) capacitors connected in parallel should be evaluated for rms current rating. the current will split between the input capacitors based on the relative impedance of the capacitors at the switching frequency. 8.3.18 vin filter r vin , c vin an r-c filter (r vin , c vin ) on vin is optional. the filter helps to prevent faults caused by high frequency switching noise injection into the vin pin. a 0.47- f ceramic capacitor is used for c vin in the example. r vin is selected to be 3.9 ? . 8.3.19 soft-start capacitor c ss the capacitor at the ss pin (c ss ) determines the soft-start time (t ss ), which is the time for the output voltage to reach the final regulated value. the t ss for a given c ss can be calculated from equation 8 as follows: (42) for this example, a value of 0.1 f was chosen for a soft-start time of 8 ms. 8.3.20 restart capacitor c res the capacitor at the res pin (c res ) determines t res , which is the time the lm5117 remains off before a restart attempt is made in hiccup mode current limiting. t res for a given c res can be calculated from equation 13 as follows: (43) for this example, a value of 0.47 f was chosen for a restart time of 59 ms. copyright ? 2011 ? 2015, texas instruments incorporated submit documentation feedback 29 product folder links: lm5117 lm5117-q1 t res 0.47 f x 1.25v 10 a = = 59 ms 0.1 f x 0.8v t ss = 10 a = 8 ms ' v in = 4 x 230 khz x 3.3 p f x 7 9 a = 0.42 v ' v in = 4 x x c in f sw i out [v] 1 2 ? 1 ? 8 x 230 khz x 470 p f ' v out = 4.1 x 0.02 : 2 + = 82 mv 1 2 ? 1 ? 8 x x c out f sw ' v out = i pp x r esr 2 + [v]
lm5117 , lm5117-q1 snvs698f ? april 2011 ? revised august 2015 www.ti.com 8.3.21 output voltage divider r fb2 and r fb1 r fb1 and r fb2 set the output voltage level. the ratio of these resistors is calculated as: (44) the ratio between r comp and r fb2 determines the mid-band gain, a fb_mid . a larger value for r fb2 may require a corresponding larger value for r comp . r fb2 should be large enough to keep the total divider power dissipation small. 4.99 k ? was chosen for r fb2 in this example, which results in a r fb1 value of 357 ? for 12-v output. 8.3.22 loop compensation components c comp , r comp and c hf r comp , c comp and c hf configure the error amplifier gain and phase characteristics to produce a stable voltage loop. for a quick start, follow the 4 steps listed below. step1: select f cross by selecting one tenth of the switching frequency, f cross is calculated as follows: (45) step2: determine required r comp knowing f cross , r comp is calculated as follows: (46) (47) the standard value of 27.4k ? was selected for r comp step3: determine c comp to cancel load pole knowing r comp , c comp is calculated as follows: (48) the standard value of 22nf was selected for c comp step4: determine c hf to cancel esr zero knowing r comp and c comp , c hf is calculated as follows: (49) (50) half of the maximum esr is assumed as a typical esr. the standard value of 180pf was selected for c hf . 30 submit documentation feedback copyright ? 2011 ? 2015, texas instruments incorporated product folder links: lm5117 lm5117-q1 c hf 10 m : x 514 f x 22 nf 27.4k : x 22 nf - 10 m : x 514 f = = 189 pf c hf r esr x c out x c comp r comp x c comp - r esr x c out = [f] load out comp comp 12 v 514 f 9 a r c c 25nf r 27.4k ? ? m ? ? = = = w r comp = 2 s x 7.41 m : x 10 x 514 f x 4.99 k : x 23 khz = 27.5 k : r comp = 2 s x r s x a s x c out x r fb2 x f cross [ :@ 10 f cross = = 23 khz f sw r fb2 - 1 r fb1 v out 0.8v =
lm5117 , lm5117-q1 www.ti.com snvs698f ? april 2011 ? revised august 2015 table 1. lm5117 frequency analysis formulas simple formula comprehensive formula (1) modulator transfer function modulator dc gain esr zero esr pole not considered dominant load pole sampled gain not considered inductor pole quality factor not considered sub-harmonic not considered double pole k factor feedback transfer function feedback dc gain mid-band gain low frequency zero high frequency pole (1) comprehensive equation includes an inductor pole and a gain peaking at f sw /2, which caused by sampling effect of the current mode control. also it assumes that a ceramic capacitor c out2 (no esr) is connected in parallel with c out1 . r esr1 represents esr of c out1 . copyright ? 2011 ? 2015, texas instruments incorporated submit documentation feedback 31 product folder links: lm5117 lm5117-q1 ( 1 + ) z z_esr = s v out ^ v comp ^ a m x z p_lf 1 + s 1 z p_ea = r comp x c hf 1 z p_ea = r comp x (c hf // c comp ) z z_ea = r comp x c comp 1 a fb_mid = r comp r fb2 a fb = 1 r fb2 x (c comp + c hf ) = s a fb x z p_ea v out ^ v comp ^ - z z_ea 1 + s s x ( 1+ ) k = 1 k = l o r ramp x c ramp x r s x a s 2 f sw z n = z sw 2 = s x f sw or f n = q = 1 s (k - 0.5) z p_hf q x z n = z p_hf f sw k 0.5 = or z p_lf = r load x c out 1 z p_lf = (r load + r esr1 ) x (c out1 + c out2 ) l o x (c out1 + c out2 ) x z p_hf 1 1 + r esr1 1 z p_esr = x (c out1 // c out2 ) z z_esr = r esr 1 x c out z z_esr = r esr1 1 x c out1 a m = r load r s x a s x l o z p_hf x 1 1 + r load a m = r load r s x a s = v out ^ v comp ^ a m x z z_esr 1 + s s ( 1 + ) z p_lf x ( 1 + ) z p_esr x ( 1 + + ) s s z p_hf s 2 z n 2
lm5117 , lm5117-q1 snvs698f ? april 2011 ? revised august 2015 www.ti.com table 1. lm5117 frequency analysis formulas (continued) simple formula comprehensive formula (1) open-loop response cross over frequency (open loop bandwidth) maximum cross over frequency the frequency at which 45 phase shift occurs in modulator phase characteristics. 8.4 application curves figure 34. typical efficiency vs load current figure 33. start-up with resistive load 32 submit documentation feedback copyright ? 2011 ? 2015, texas instruments incorporated product folder links: lm5117 lm5117-q1 f cross_max = f sw 4 x q 1 + 4 x q 2 -1 x ( ) f cross_max = f sw 5 z p_ea = z z_esr z z_ea = z p_lf when & f cross < z p_hf 2 x s x 10 & & f cross < z p_esr 2 x s x 10 z p_ea = z z_esr z z_ea = z p_lf & when 2 x ' x r s x r fb2 x a s x c out r comp f cross = 2 x ' x r s x r fb2 x a s x (c out1 + c out2 ) r comp f cross = z z_ea = z p_lf when t(s) = s a m x a fb x z z_esr 1 + s s ( 1 + ) z p_ea x ( 1 + ) z p_esr x ( 1 + + ) s s z p_hf s 2 z n 2 t(s) a m x a fb s = t(s) = a m x a fb x x z z_esr 1 + s s ( 1 + ) z p_lf x ( 1 + ) z p_esr x ( 1 + + ) s s z p_hf s 2 z n 2 s ( 1 + ) z p_ea s x z z_ea 1 + s t(s) = a m x a fb x z z_ea s ( 1 + ) z p_ea 1 + s s x s ( 1 + ) z p_lf x z z_esr 1 + s
lm5117 , lm5117-q1 www.ti.com snvs698f ? april 2011 ? revised august 2015 application curves (continued) 8.4.1 constant current regulator the lm5117 can be configured as a constant current regulator by using the current monitor feature (cm) as the feedback input. a voltage divider at the vccdis pin from vout to agnd can be used to protect against output over-voltage. when the vccdis pin voltage is greater than the vccdis threshold, the controller disables the vcc regulator and the vcc pin voltage decays. when the vcc pin voltage is less than the vcc uv threshold, both ho and lo outputs stop switching. due to the time delay required for vcc to decay below the vcc uv threshold, the over-voltage protection operates in hiccup mode. see figure 35 . figure 35. constant current regulator with hiccup mode output ovp 8.4.2 constant voltage and constant current regulator the lm5117 also can be configured as a constant voltage and constant current regulator, known as cv+cc regulator. in this configuration, there is much less variation in the current limiting as compared to peak cycle-by- cycle current limiting of the inductor current. the lmv431 and the pnp transistor create a voltage-to-current amplifier in the current loop. this amplifier circuitry does not affect the normal operation when the output current is less than the current limit set-point. when the output current is greater than the set-point, the pnp transistor sources a current into c ramp and increases the positive slope of emulated inductor current ramp until the output current is less than or equal to the current limit set-point. see figure 36 and figure 37 . copyright ? 2011 ? 2015, texas instruments incorporated submit documentation feedback 33 product folder links: lm5117 lm5117-q1 v out ss res rt comp fb ramp pgnd csg cs lo sw ho hb vcc vin agnd uvlo vccdis demb cm v in v out sw lm5117 c in q h q l c hb d hb c vcc hiccup mode ovp triggered at 13.4v cc mode: 2a 100k : 15 k : 80 f 68 h 1500 pf 100 k : 22.1 k : 0.47 f 3.24 k : 2.37 k : 0.022 f 47 m : current control (cc) 3.24 k : 332 :
lm5117 , lm5117-q1 snvs698f ? april 2011 ? revised august 2015 www.ti.com application curves (continued) figure 36. constant voltage regulator with accurate current limit figure 37. current limit comparison 34 submit documentation feedback copyright ? 2011 ? 2015, texas instruments incorporated product folder links: lm5117 lm5117-q1 v out ss res rt comp fb ramp pgnd csg cs lo sw ho hb vcc vin agnd uvlo vccdis demb cm v in v out sw lm5117 c in q h q l current control (cc) c hb d hb c vcc v cc voltage control (cv) lmv431 cv mode : 5v cc mode: 2a 100 k : 15 k : 80 p f 68 p h 1500 pf 100 k : 22.1 k : 0.33 p f x2 3.24 k : 619 : 34.8 k : 0.1 p f 47 m : 1 nf 100 k : 10 k : 100 : pnp 200 k :
lm5117 , lm5117-q1 www.ti.com snvs698f ? april 2011 ? revised august 2015 9 power supply recommendations the lm5117 is a power management device. the power supply for the device is any dc voltage source within the specified input range. 10 layout 10.1 layout guideline figure 38. layout example 10.1.1 pc board layout recommendation in a buck regulator the primary switching loop consists of the input capacitor, nmos power switches and current sense resistor. minimizing the area of this loop reduces the stray inductance and minimizes noise and possible erratic operation. high quality input capacitors should be placed as close as possible to the nmos power switches, with the v in side of the capacitor connected directly to the high-side nmos drain and the ground side of the capacitor connected as close as possible to the current sense resistor ground connection. connect all of the low power ground connections (r uv1 , r t , r fb1 , c ss , c res , c cm , c vin , c ramp ) directly to the regulator agnd pin. connect c vcc directly to the regulator pgnd pin. note that c vin and c vcc must be as physically close as possible to the ic. agnd and pgnd must be directly connected together through a top-side copper pattern connected to the exposed pad. ensure no high current flows beneath the underside exposed pad. the lm5117 has an exposed thermal pad to aid power dissipation. adding several vias under the exposed pad helps conduct heat away from the ic. the junction to ambient thermal resistance varies with application. the most significant variables are the area of copper in the pc board, the number of vias under the exposed pad and the amount of forced air cooling. the integrity of the solder connection from the ic exposed pad to the pc board is critical. excessive voids greatly decrease the thermal dissipation capacity. the highest power dissipating components are the two power switches. selecting nmos switches with exposed pads aids the power dissipation of these devices. copyright ? 2011 ? 2015, texas instruments incorporated submit documentation feedback 35 product folder links: lm5117 lm5117-q1 controller vout gnd gnd vin inductor c in c in c out c out r sense q h q l place controller as close to the switches
lm5117 , lm5117-q1 snvs698f ? april 2011 ? revised august 2015 www.ti.com 11 device and documentation support 11.1 related links the table below lists quick access links. categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. table 2. related links technical tools & support & parts product folder sample & buy documents software community lm5117 click here click here click here click here click here lm5117-q1 click here click here click here click here click here 11.2 community resources the following links connect to ti community resources. linked contents are provided "as is" by the respective contributors. they do not constitute ti specifications and do not necessarily reflect ti's views; see ti's terms of use . ti e2e ? online community ti's engineer-to-engineer (e2e) community. created to foster collaboration among engineers. at e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. design support ti's design support quickly find helpful e2e forums along with design support tools and contact information for technical support. 11.3 trademarks e2e is a trademark of texas instruments. webench is a registered trademark of texas instruments. all other trademarks are the property of their respective owners. 11.4 electrostatic discharge caution these devices have limited built-in esd protection. the leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the mos gates. 11.5 glossary slyz022 ? ti glossary . this glossary lists and explains terms, acronyms, and definitions. 12 mechanical, packaging, and orderable information the following pages include mechanical, packaging, and orderable information. this information is the most current data available for the designated devices. this data is subject to change without notice and revision of this document. for browser-based versions of this data sheet, refer to the left-hand navigation. 36 submit documentation feedback copyright ? 2011 ? 2015, texas instruments incorporated product folder links: lm5117 lm5117-q1
package option addendum www.ti.com 5-jun-2015 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples lm5117pmh/nopb active htssop pwp 20 73 green (rohs & no sb/br) cu sn level-3-260c-168 hr -40 to 125 lm5117 pmh lm5117pmhe/nopb active htssop pwp 20 250 green (rohs & no sb/br) cu sn level-3-260c-168 hr -40 to 125 lm5117 pmh lm5117pmhx/nopb active htssop pwp 20 2500 green (rohs & no sb/br) cu sn level-3-260c-168 hr -40 to 125 lm5117 pmh lm5117psq/nopb active wqfn rtw 24 1000 green (rohs & no sb/br) cu sn level-1-260c-unlim -40 to 125 l5117p lm5117psqe/nopb active wqfn rtw 24 250 green (rohs & no sb/br) cu sn level-1-260c-unlim -40 to 125 l5117p lm5117psqx/nopb active wqfn rtw 24 4500 green (rohs & no sb/br) cu sn level-1-260c-unlim -40 to 125 l5117p lm5117qpmh/nopb active htssop pwp 20 73 green (rohs & no sb/br) cu sn level-3-260c-168 hr -40 to 125 lm5117 qmh lm5117qpmhe/nopb active htssop pwp 20 250 green (rohs & no sb/br) cu sn level-3-260c-168 hr -40 to 125 lm5117 qmh lm5117qpmhx/nopb active htssop pwp 20 2500 green (rohs & no sb/br) cu sn level-3-260c-168 hr -40 to 125 lm5117 qmh lm5117qpsq/nopb active wqfn rtw 24 1000 green (rohs & no sb/br) cu sn level-1-260c-unlim -40 to 125 l5117q lm5117qpsqe/nopb active wqfn rtw 24 250 green (rohs & no sb/br) cu sn level-1-260c-unlim -40 to 125 l5117q lm5117qpsqx/nopb active wqfn rtw 24 4500 green (rohs & no sb/br) cu sn level-1-260c-unlim -40 to 125 l5117q (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined.
package option addendum www.ti.com 5-jun-2015 addendum-page 2 pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. other qualified versions of lm5117, lm5117-q1 : ? catalog: lm5117 ? automotive: lm5117-q1 note: qualified version definitions: ? catalog - ti's standard catalog product ? automotive - q100 devices qualified for high-reliability automotive applications targeting zero defects
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant lm5117pmhe/nopb htssop pwp 20 250 178.0 16.4 6.95 7.1 1.6 8.0 16.0 q1 lm5117pmhx/nopb htssop pwp 20 2500 330.0 16.4 6.95 7.1 1.6 8.0 16.0 q1 lm5117psq/nopb wqfn rtw 24 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 q1 lm5117psqe/nopb wqfn rtw 24 250 178.0 12.4 4.3 4.3 1.3 8.0 12.0 q1 lm5117psqx/nopb wqfn rtw 24 4500 330.0 12.4 4.3 4.3 1.3 8.0 12.0 q1 lm5117qpmhe/nopb htssop pwp 20 250 178.0 16.4 6.95 7.1 1.6 8.0 16.0 q1 lm5117qpmhx/nopb htssop pwp 20 2500 330.0 16.4 6.95 7.1 1.6 8.0 16.0 q1 lm5117qpsq/nopb wqfn rtw 24 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 q1 lm5117qpsqe/nopb wqfn rtw 24 250 178.0 12.4 4.3 4.3 1.3 8.0 12.0 q1 lm5117qpsqx/nopb wqfn rtw 24 4500 330.0 12.4 4.3 4.3 1.3 8.0 12.0 q1 package materials information www.ti.com 5-jun-2015 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) lm5117pmhe/nopb htssop pwp 20 250 213.0 191.0 55.0 lm5117pmhx/nopb htssop pwp 20 2500 367.0 367.0 38.0 lm5117psq/nopb wqfn rtw 24 1000 210.0 185.0 35.0 lm5117psqe/nopb wqfn rtw 24 250 210.0 185.0 35.0 lm5117psqx/nopb wqfn rtw 24 4500 367.0 367.0 35.0 lm5117qpmhe/nopb htssop pwp 20 250 213.0 191.0 55.0 lm5117qpmhx/nopb htssop pwp 20 2500 367.0 367.0 38.0 lm5117qpsq/nopb wqfn rtw 24 1000 210.0 185.0 35.0 lm5117qpsqe/nopb wqfn rtw 24 250 210.0 185.0 35.0 lm5117qpsqx/nopb wqfn rtw 24 4500 367.0 367.0 35.0 package materials information www.ti.com 5-jun-2015 pack materials-page 2
mechanical da t a pwp0020a www .ti.com m x a 2 0 a ( r e v c )
mechanical da t a r tw0024a www .ti.com s q a 2 4 a ( r e v b )
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