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6-bit, 75? digital step attenuator 5mhz to 3ghz f1978 datasheet ? 2017 integrated device technology, inc. 1 rev o august 28 , 2017 description t he f1978 digital step attenuator (dsa) is a product in idts glitch- free tm dsa family, which is optimized for the demanding requirements of catv and satellite systems . it operates in the frequency range of 5mhz to 3000mhz. this device is offered in a compact 4 mm ? 4 mm , 20 -pin thin qfn package with a 75 impedance for ease of integration. the f1978 dsa has rf performance identical to the f1975 digital step attenuator. the difference between the f1978 and f1975 is that the f1978 has an additional programming mode called direct serial programming. consult the programming section of this datasheet or the application note an- 945 comparison of f1975 and f1978 digital step attenuator serial programming methods . advantages digital step attenuators are used in receivers and transmitters to provide gain control . th e f1978 is a 6-bit step attenuator optimized for these demanding applications . the silicon design has very low insertion loss and low distortion (+64 dbm iip3) . the device has pinpoint attenuation accuracy . most importantly, the f1978 i ncludes idts glitch- free tm technology, which results in low over- shoot and ringing during most significant bit (msb) transitions. ? glitch- free tm technology protects the power amplifier or analog - to -digital converter (adc) from damage during transit ions between attenuation states ? extremely accurate attenuation levels ? ultra-low distortion ? low insertion loss for best signal- to -noise ratio (snr) ? allows direct serial programming of attenuation typical applications ? catv infrastructure ? catv set -top boxes ? catv satellite modems ? data network equipment ? fiber networks features ? frequency: 5mhz to 3000mhz ? serial and 6-b it parallel interface ? 31.5db control range ? 0.5db step ? glitch- free tm technology, low transient overshoot ? 3.0 v to 5.25v supply ? 1.8 v or 3.3v control logic ? attenuator step error: 0.1 db at 1 ghz ? low insertion loss: 1.2 db at 1ghz ? ultra- li near iip3: +64 dbm ? iip2: +125dbm typical ? stable integral non-linearity over temperature ? low current consumption: 550 a typical ? bi-directional ? operating temperature: - 40 c to +105c ? 4 mm ? 4 mm , 20 -tqfn package block diagram figure 1. block diagram decoder rf 1 rf 2 spi bias v mode clk data le d[5:0] glitch-free tm v dd
f1978 datasheet ? 2017 integrated device technology, inc. 2 rev o august 28 , 2017 pin assignments figure 2. pin assignments for 4mm ? 4mm ? 0.75mm, 20 -tqfn package C top view (through package) clk data d0 d1 d3 nc v mode gnd d4 le nc rf 2 rf 1 d2 d5 v dd nc gnd 2 1 3 5 4 12 11 13 15 14 6 7 9 8 10 16 17 19 18 20 ncnc exposed pad
f1978 datasheet ? 2017 integrated device technology, inc. 3 rev o august 28 , 2017 pin descriptions table 1. pin descriptions number name description 1 d5 16db attenuation control bit. this pin is activated by logi c high (see table 12 ). [a] 2 rf1 device rf input or output (bi-directional). 3 data serial interface data input. 4 clk serial interface clock input. 5 le serial interface latch enable input. internal pull- up (100 k?). see programming section for proper usage of this line. 6 v dd power supply pin. 7 C 9, 12, 18 nc no internal connection . the nc pins can be left unconnected , have a voltage applied, or be connected to ground (recommended). 10 , 11 gnd internally grounded. connect pin directly to paddle ground or as close as possible to the pin with thru vias . 13 v mode pull this pin high for serial control mode . ground this pin for parallel control mode. 14 rf2 device rf input or output (bi-directional). 15 d4 8 db attenuation control bit. this pin is activated by logic high (see table 12 ). [a] 16 d3 4 db attenuation control bit. this pin is activated by logic high (see table 12 ). [a] 17 d2 2 db attenuation control bit. this pin is activated by logic high (see table 12 ). [a] 19 d1 1 db attenuation control bit . this pin is activated by logic high (see table 12 ). [a] 20 d0 0.5db attenuation control bit . this pin is activated by logic high (see table 12 ). [a] e pad exposed p ad dle . internally connected to ground (gnd) . solder this exposed paddle to a printed circuit board ( pcb ) pad that uses multiple ground vias to provide heat transfer out of the device into the pcb ground planes . these multiple ground vias are also required to achieve the specified rf performance. [a] there is a 100k? pull -up resistor to the internally regulated 2.5v power supply.
f1978 datasheet ? 2017 integrated device technology, inc. 4 rev o august 28 , 2017 absolute maximum ratings the absolute maximum ratings are stress ratings only . stresses greater than those listed below can cause permanent damage to the device . functional operation of the f1978 at absolute maximum ratings is not implied . exposure to absolute maximum rating conditions could affect device reliability. table 2. absolute maximum ratings parameter symbol minimum maximum units v dd to gnd v dd - 0.3 +5.5 v data, le, clk, d[5:0], v mode v logic - 0.3 minimum (v dd +0.3, 3.6) v rf1, rf2 v rf - 0.3 +0.3 v maximum input power applied to rf1 or rf2 (>100mhz) p rf +34 dbm continuous power dissipation p diss 1.75 dbm junction temperature t j +140 c storage temperature range t stor - 65 +150 c lead temperature (soldering, 10s) +260 c electrostatic discharge C hbm (jedec/esda js- 001 -2012) v esdhbm 2000 (class 2) v electrostatic discharge C cdm (jedec 22-c101f) v esdcdm 500 (class c2) v
f1978 datasheet ? 2017 integrated device technology, inc. 5 rev o august 28 , 2017 recommended operating conditions table 3. recommended operating conditions parameter symbol condition minimum typical maximum units supply voltage(s) v dd 3.00 5.25 v frequency range f rf 5 3000 mhz operating temperature range t ep exposed paddle - 40 105 c rf cw input power p cw rf1 or rf2 see figure 3 dbm rf1 impedance z rf1 single -e nded 75 rf2 impedance z rf2 single - ended 75 figure 3. maximum continuous operating rf input power versus input frequency (+25 ? c) 8 10 12 14 16 18 20 22 24 26 28 30 0.01 0.1 1 10 100 1000 10000 maximum operating power (dbm) frequency (mhz) +25 c - cw
f1978 datasheet ? 2017 integrated device technology, inc. 6 rev o august 28 , 2017 electrical characteristics the specifications in table 4 apply at v dd = +3.3v, t ep = +25c, f rf = 1000mhz, p in = 0dbm, serial mode, z s = z l = 75 ?, evaluation board (evkit) trace and connector losses are de-embedded , unless otherwise noted. table 4. electrical characteristics parameter symbol condition minimum typical maximum units logic input high threshold v ih all control pins v dd > 3.6v 1.17 [a] 3.6 v 3.0v v dd 3.6v 1.17 v dd logic input low threshold v il all control pins 0.63 v logic current i ih, i il all control pins - 35 +35 a supply current [b] i dd v dd = 3.3v 550 830 a v dd = 5.0v 620 900 rf1 return loss s 11 18 db rf2 return loss s 22 18 db attenuation step lsb least significant bit 0.5 db insertion loss (minimum attenuation) a min d[5:0]=[000000 bin ] (il state) 1.2 2.0 db attenuation range a range d[5:0]=[111111 bin ]=31.5db 30.5 31.1 31.7 db step error dnl 0.1 db absolute error inl d[5:0]=[100111 bin ]= 19.5db - 0.7 +0.5 db insertion phase delta f rf = 0.5ghz (a max to a min ) 10 d eg f rf = 1.0ghz (a max to a min ) 20 input ip3 iip3 p in = +10dbm/tone, f 1 = 900mhz, f 2 = 950mhz attn = 0.0db, rf in = rf1 60 64 dbm attn =15.5db, rf in = rf1 59 62 [a] specifications in the minimum/maximum columns that are shown in bold italics are guaranteed by test. specifications in these columns that are not shown in bold italics are guaranteed by design characterization. [b] current is tested using the serial mode with parallel pins floating. if parallel pins are grounded, add 25a per pin.
f1978 datasheet ? 2017 integrated device technology, inc. 7 rev o august 28 , 2017 electrical characteristics (continued) the specifications in table 5 apply at v dd = +3.3v, t ep = +25c, f rf = 1000mhz, p in = 0dbm, serial mode, z s = z l = 75 ?, evaluation board (evkit) trace and connector losses are de-embedded , unless otherwise noted. table 5. electrical characteristics parameter symbol condition minimum typical maximum units input ip2 iip2 p in = +12dbm/tone f 1 = 945mhz, f 2 = 949mhz f 1 + f 2 = 1894mhz rf in = rf1 125 dbm second harmonic h2 p in = +15dbm rf in = 945mhz rf out = 1890mhz rf in = rf1 108 dbc input 0.1db compression [c] ip 0.1 d[5:0] = [000000] = a min , rf in = rf1 30.5 dbm msb step time t lsb start at le rising edge end 0.10db p out settling for 15.5db to 16.0db transition 500 ns maximum spurious level on any rf port [d] s pur max - 130 dbm maximum switching rate sw rate 25 khz dsa settling time [e] ? set maximum to minimum attenuation to settle to within 0.5db of final value 0.9 s maximum to minimum attenuation to settle to within 0.5db of final value 1.8 control interface spi bit 6 bit serial clock speed spi clk 25 mhz [c] the input 0.1db compression point is a linearity figure of merit. refer to absolute maximum ratings section for the maximum rf input power. this specification is measured in a 50? system. [d] spurious due to on-chip negative voltage generator. typical generator fundamental frequency is 2.2mhz. [e] speeds are measured after spi programming is completed (data latched with le = high).
f1978 datasheet ? 2017 integrated device technology, inc. 8 rev o august 28 , 2017 thermal characteristics table 6. package thermal characteristics parameter symbol value units junctio n to ambient thermal resistance ja 50 c/w junct ion to case thermal resistance (case is defined as the exposed paddle) jc -bot 3 c/w moisture sensitivity rating (per j-std-020) msl 1 typical operating conditions (toc) unless otherwise noted for the toc graphs on the following pages, the following conditions apply. ? v dd = +3.3 v ? z l = z s = 75 single -ended ? t ep = +25c ? f rf = 1 ghz ? p in = 0 dbm for single tone measurements ? p in = +10dbm/tone for multi-tone measurements ? tone spacing = 50mhz ? evaluation board connector and board losses are de -embedded ? measured in a 75 system unless otherwise specified
f1978 datasheet ? 2017 integrated device technology, inc. 9 rev o august 28 , 2017 typical performance characteristics figure 4. insertion loss vs. frequency figure 5. insertion loss vs. attenuation state figure 6. rf1 return loss vs. frequency (all states) figure 7. rf1 return loss vs. attenuation state figure 8. rf2 return loss vs. frequency (all states) figure 9. rf2 return loss vs. attenuation state -4.0 -3.5 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 insertion loss (db) frequency (ghz) -40 c +25 c +105 c - 35 - 30 - 25 - 20 - 15 - 10 -5 0 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 insertion loss (db) attenuation (db) 1 ghz, -40 c 1 ghz, +25 c 1 ghz, +105 c - 40 - 35 - 30 - 25 - 20 - 15 - 10 -5 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 match (db) frequency (ghz) - 40 - 35 - 30 - 25 - 20 - 15 - 10 -5 0 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 match(db) attenuation (db) 0.01 ghz 0.50 ghz 0.75 ghz 1.00 ghz 1.25 ghz 1.50 ghz 1.75 ghz 2.00 ghz - 40 - 35 - 30 - 25 - 20 - 15 - 10 -5 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 match (db) frequency (ghz) - 40 - 35 - 30 - 25 - 20 - 15 - 10 -5 0 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 match (db) attenuation (db) 0.01 ghz 0.50 ghz 0.75 ghz 1.00 ghz 1.25 ghz 1.50 ghz 1.75 ghz 2.00 ghz
f1978 datasheet ? 2017 integrated device technology, inc. 10 rev o august 28 , 2017 typical performance characteristics figure 10 . relative insertion phase vs. frequency (all states) figure 11 . relative insertion phase vs. attenuation figure 12 . worst-case absolute accuracy error figure 13 . accuracy error vs. attenuation figure 14 . worst-case step accuracy figure 15 . step error vs. attenuation -5 0 5 10 15 20 25 30 35 40 45 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 phase (degrees) frequency (ghz) -5 0 5 10 15 20 25 30 35 40 45 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 phase (degrees) attenuation (db) 0.01 ghz 0.50 ghz 0.75 ghz 1.00 ghz 1.25 ghz 1.50 ghz 1.75 ghz 2.00 ghz -2.0 -1.5 -1.0 -0.5 0.0 0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 error (db) frequency (ghz) -40 c min -40 c max +25 c min +25 c max +105 c min +105 c max -2.0 -1.5 -1.0 -0.5 0.0 0.5 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 error (db) attenuation (db) 0.01 ghz 0.50 ghz 0.75 ghz 1.00 ghz 1.25 ghz 1.50 ghz 1.75 ghz 2.00 ghz -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 error (db) frequency (ghz) -40 c min -40 c max +25 c min +25 c max +105 c min +105 c max -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 error (db) attenuation (db) 0.01 ghz 0.50 ghz 0.75 ghz 1.00 ghz 1.25 ghz 1.50 ghz 1.75 ghz 2.00 ghz
f1978 datasheet ? 2017 integrated device technology, inc. 11 rev o august 28 , 2017 typical performance characteristics figure 16 . compression versus input power [attenuation = 0.0 db ] figure 17 . input ip3 versus attenuation setting -2.0 -1.5 -1.0 -0.5 0.0 0.5 16 18 20 22 24 26 28 30 32 34 compression (db) input power (dbm) 0.005 ghz 0.050 ghz 0.100 ghz 0.500 ghz 1.000 ghz 1.500 ghz 2.000 ghz measured in a 50 ohm system 25 30 35 40 45 50 55 60 65 70 75 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 input ip3 (dbm) attenuation setting (db) 0.035 ghz 0.065 ghz 0.130 ghz 0.500 ghz 0.920 ghz 1.400 ghz 2.000 ghz
f1978 datasheet ? 2017 integrated device technology, inc. 12 rev o august 28 , 2017 programming the f1978 can be programmed using either the parallel or the serial interface, which is selectable via v mode (pin 13) . serial mode is selected by floating v mode or pulling it to a logic high, and parallel mode is selected by setting v mode to a logic low . for a comparison of the f1975 and f1978 products, see the application note an945 C comparison of f1975 and f1978 digital step attenuator serial programming methods. serial control mode the f1978 serial mode is selected by floating v mode (pin 13) or pulling it to a logic high . the serial interface is a 6-bit shift register and shifts in the most significant bit (msb) (d5 bit ) first. the f1978 can be programmed through the serial interface using one of two methods, conventional serial mode or direct serial mode, as described in the following sections. table 7. 6 bit spi data word sequence bit definition d5 attenuation 16 db control bit d4 attenuator 8 db control bit d3 attenuator 4 db control bit d2 attenuator 2 db control bit d1 attenuator 1 db control bit d0 attenuator 0.5 db control bit table 8. truth table for serial control word bits d5 (msb) d4 d3 d2 d1 d0 (lsb) attenuation (db) 0 0 0 0 0 0 0 0 0 0 0 0 1 0.5 0 0 0 0 1 0 1 0 0 0 1 0 0 2 0 0 1 0 0 0 4 0 1 0 0 0 0 8 1 0 0 0 0 0 16 1 1 1 1 1 1 31.5
f1978 datasheet ? 2017 integrated device technology, inc. 13 rev o august 28 , 2017 conventional serial mode programming in the conventional serial mode, the f1978 is programmed via the serial port on the rising edge of the latch enable (le) signal . it is required that le be kept at logic low until all data bits are clocked into the shift register . the f1978 will change its attenuation state after the data word is latched into the active register as illustrated in figure 18 . after the data word in the shift register has been latched into the active register, the le signal must be dropped low. this allows shifting new data into the shift register without uploading it to the active re gister until the next time le goes high. the timing specification intervals are shown in blue font in figure 18 . figure 18 . conventional serial register timing diagram note: if the conventional serial register programming method is used, the attenuator will change to the new attenuation state only after the data word is latched into the active register, a single programming event . the conventional serial register method is recommended for best system performance. table 9. conventional serial mode timing table interval symbol description min spec max spec units t mc parallel mode to serial mode setup time: fr om the rising edge of v mode to the rising edge of clk for the d5 bit 100 ns t ds clock high pulse width 10 ns t cls le setup time: from the rising edge of the clk pulse for d0 to le rising edge minus half the clock peri od 10 ns t clh le hold time: from the falling edge of the le pulse to the rising edge of cl k 10 ns t lew le pulse width 10 ns t dcs data setup time: from the starting edge of the da ta bit to the rising edge of clk 10 ns t dht data hold time: fro m rising edge of clk to falling edge of the data bit 10 ns
f1978 datasheet ? 2017 integrated device technology, inc. 14 rev o august 28 , 2017 direct serial mode programming direct serial mode programming is available for the f1978, b ut it is not a recommended mode of operation . in the direct serial mode, the f1978 is programmed via the serial port with le kept at a constant logic high . data is shifted into the register with each clock cycle . in this mode, the device attenuation state will be set immediately based on the contents of the shift register as illustrated in figure 19 . note: the timing specification intervals for direct serial mode programming are shown in blue font in figure 19 . figure 19 . direct serial register timing diagram important note: if the direct serial register programming method is used, the attenuator state will be programmed each time a data bit is clocked into the shift register , therefore as the serial word is moving through the device, the attenuator can swing over a 16db range. table 10 . direct serial programming mode timing table interval symbol description min spec max spec units t mc parallel mode to serial mode setup time: from the rising edge of v mode to the rising edge of clk for the d5 bit 100 ns t ds clock high pulse width 10 ns t dcs data setup time: from the starting edge of the d ata bit to the rising edge of clk 10 ns t dht data hold time: from the rising edge of clk to the falling edge of t he data bi t 10 ns serial mode default startup condition when the device is first powered up, it will default to the maximum attenuation of 31.5 db independent of the parallel pin [d5:d0] conditions. table 11 . default control word for the serial mode d5 (msb) d4 d3 d2 d1 d0 (lsb) attenuation (db) 1 1 1 1 1 1 31.5
f1978 datasheet ? 2017 integrated device technology, inc. 15 rev o august 28 , 2017 parallel control mode for the f1978, the user has the option of programming in one of two parallel modes: direct parallel mode or latched parallel mode. direct parallel mode direct parallel mode is selected when v mode (pin 13) is set to a logic low and le (pin 5) is set to a logic high . in this mode, the device will immediately react to any voltage changes in the parallel control pins (1, 15, 16, 17, 19, and 20) . use direct parallel mode for the fastest settling time. direct parallel default startup condition in the direct parallel mode, the attenuation value is determined by the logic condition of the parallel pins (1, 15, 16, 1 7, 19, and 20 ) at the time of start - up. latched parallel mode the latched parallel mode is selected when v mode is set to a logic low and le (pin 5) is toggled from a logic low to a logic high . to utilize the latched parallel mode, complete these steps: ? set the le pin to a logic low . ? set pins 1, 15, 16, 17, 19, and 20 for the desired attenuation setting . (while le is set to a logic low , the attenuation state will not change .) ? toggle le to a logic high . the device will then transition to the attenuation settings reflected by pins d5 through d0. latched parallel default startup condition the latched parallel mode establishes a default attenuation state when the device is first powered up which is the maximum attenuation. table 12 . truth table for the parallel pins d5 d4 d3 d2 d1 d0 attenuation (db) 0 0 0 0 0 0 0 0 0 0 0 0 1 0.5 0 0 0 0 1 0 1 0 0 0 1 0 0 2 0 0 1 0 0 0 4 0 1 0 0 0 0 8 1 0 0 0 0 0 16 1 1 1 1 1 1 31.5
f1978 datasheet ? 2017 integrated device technology, inc. 16 rev o august 28 , 2017 figure 20 . latched parallel mode timing diagram table 13 . latched parallel mode timing interval symbol description min spec max spec units t sps serial mode to parallel mode setup time 100 ns t pdh parallel data hold time 10 ns t pds le minimum pulse width 10 ns t le parallel data setup time 10 ns applications information f1978 digital pin voltage and resistance values (pins not connected) table 14 lists the resistance between various pins and ground when no dc power is applied . when the device is powered up with +5v dc, these pins will exhibit a voltage to ground as indicat ed. table 14 . voltage and resistance to ground for the logic pins pin name dc voltage (volts) resistance (o hms) 13 v mode 2.5 v 100 k ? pull -up resistor to internally regulated 2.5v. 3, 4, 5 data, clk, le 2.5 v 100 k ? pull -up resis tor to internally regulated 2.5v. 1, 15 C 17, 19, 20 d5, d4, d3, d2, d1, d0 2.5v 100k? pull -up resistor to internally regulated 2.5v. v mode t sps t le t pdh t pds le d[5:0] time data word latched into the register
f1978 datasheet ? 2017 integrated device technology, inc. 17 rev o august 28 , 2017 f1978 evaluation kit figure 21 . f1978evbi evaluation board C top view vdd rf2 rf1 j4 parallel control pins set u2 switches d0 to d5 for parallel data v mode j11 serial control pins logic high switch position (+) open circuit switch position (o) logic low switch position ( C )
f1978 datasheet ? 2017 integrated device technology, inc. 18 rev o august 28 , 2017 figure 22 . f1978evbi evaluation board C back view
f1978 datasheet ? 2017 integrated device technology, inc. 19 rev o august 28 , 2017 evaluation kit / applications circuit figure 23 . electrical schematic r3 c3 r4 c4 r5 c5 r6 c6 r7 c7 r8 r25 r26 c8 r27 8 pin dip switch 8 7 6 5 4 3 2 1 9 16 j2 header 1x2 1 2 j4 header 1x9 1 2 3 4 5 6 7 8 9 j7 vdd j12 j5 header 1x2 1 2 j13 thru cal 75 ohm r21 r22 r23 c12 c15 u2 gnd rf2 f-type d0 d1 d2 d3 d4 d5 vmode vdd gnd vlogic vdd z0 = 75 ohm rf1 f-type f-type f-type vdd r24 length = rf1 + rf2 lines r9 c9 z0 = 75 ohm clk data le j11 header 4x2 2 4 6 8 1 3 5 7 r10 r11 r12 r13 r18 r16 u1 d5 1 rf1 2 data 3 clk 4 le 5 vdd 6 nc 7 nc 8 nc 9 gnd 10 d4 15 rf2 14 vmode 13 nc 12 gnd 11 d0 20 d1 19 nc 18 d2 17 d3 16 epad 21 c13 c14 logic low switch to '-' position logic high switch to '+' position open circuit switch to 'o' position r2 r1 vdd j8 c10 c11 j3 header 1x2 1 2 vdd j1 c2 c1 j6
f1978 datasheet ? 2017 integrated device technology, inc. 20 rev o august 28 , 2017 bill of materials (bom) table 15 . evaluation kit bill of material part reference qty description manufacturer part # manufacturer c1, c11, c15 3 100nf 10%, 16v, x7r ceramic capacitor (0402) grm155r71c104k murata c2, c10 2 10nf 5%, 50v, x7r ceramic capacitor (0603) grm188r71h103j murata c3, c4, c5, c6, c7, c8, c9, c12, c13, c14 10 100pf 5%, 50v, c0g ceramic capacitor (0402) grm1555c1h101j murata r3, r4, r5, r6, r7, r8, r9 7 100 1%, 1/10 w, resistor (0402) erj -2rkf1000x panasonic r10-r13, r15-r18, r24-r27 12 0 resistor (0402) erj -2ge0r00x panasonic r21, r22, r23 3 3k 1%, 1/10 w, resistor (0402) erj -2rkf3001x panasonic r1 1 8.25 k 1%, 1/10 w, resistor (0402) erj -2rkf8251x panasonic r2 1 10 k 5%, 1/10w, resistor (0402) erj -2rkf1002x panasonic j2, j3, j5 3 conn header vert sgl 2 x 1 pos gold 961102 - 6404 - ar 3m j11 1 conn header v ert dbl 4 x 2 pos gold 67997 -108hlf fci j4 1 conn header v ert sgl 9 x 1 pos gold 961109 - 6404 - ar 3m j1, j8 2 edge launch sma (0.250 inch pitch ground, round) 142 -0711- 821 emerson johnson j6, j7 , j12, j13 4 edge launch f- type 75 o hm 222181 amphenol u2 1 switch 8-position dip switch kat1108e e-switch u1 1 dsa f1978ncgk idt 1 printed circuit board f1975 e vk it rev 02 idt
f1978 datasheet ? 2017 integrated device technology, inc. 21 rev o august 28 , 2017 evaluation kit operation power supply setup set up a power supply in the voltage range of 3.0v to 5.25v with the power supply output disabled. the voltage can be applied via one of the following connections (see figure 24 ): ? j8 connector ? j5 h eader connection (note the polarity of the gnd pin on this connector) ? pi n 8 (v dd ) and pin 9 (gnd) on the j4 header connection figure 24 . power supply and logic voltage connections j8 connector gnd C j4, pin 9 vdd C j4, pin 8 j5 j1 connector j2 j3 parallel logic control setup the evaluation board has the ability to control the f1978 in the parallel mode. for external control, apply logic voltages to the j4 header pi ns 1 through 6 (see figure 21 ). for manual control, switches 1 through 6 on u2 can be set. the switch is a three-position switch. the bottom pos ition, C will ground the pin. the center position o will leave the pin open circuited. setting the switch to t he top position + will apply a voltage that is sup plied to the switch. the logic voltage can be applied in one of two ways (see figure 24 ) : ? connect directly to connector j1. ? l eav e j1 open circuit, and add jumpers to headers j2 and j3. this will apply a logic voltage that is 0.24 ? v dd . the f1978 has internal pull-up resistors for the d0 C d5 parallel pins and v mode . the switches can be used to apply a logic low (ground) for proper operation. to use the parallel mode, either apply a ground to the vmod pin 7 on j4 or set u2 switch 7 (vmod) to the C position (see figure 21 ). the attenuation setting can be set via the u2 switches 1 through 6 (d0 through d5) according to table 12 .
f1978 datasheet ? 2017 integrated device technology, inc. 22 rev o august 28 , 2017 serial logic control setup the evaluation board has the ability to control the f1978 in the serial mode. connect the serial controller to the j11 header connection as show n in figure 25 . to use the serial mode, set u2 switch 7 to the + or o position. the attenuation setting can be programmed according to table 8. figure 25 . serial logic connections power-on procedure set up the voltage supplies and evaluation board as described in the power supply setup section and either the parallel logic control setup or serial logic control setup sections above. enable the v dd supply. enable the proper attenuation setting according to figure 21 and table 8 for serial mode or table 12 for the parallel mode. power-off procedure set the logic control pins to a logic low. disable the v dd supply.
f1978 datasheet ? 2017 integrated device technology, inc. 23 rev o august 28 , 2017 package drawings figure 26 . package outline drawing ncg20 psc-4445
f1978 datasheet ? 2017 integrated device technology, inc. 24 rev o august 28 , 2017 recommended land pattern figure 27 . recommended land pattern for ncg20 psc-4445
f1978 datasheet ? 2017 integrated device technology, inc. 25 rev o august 28 , 2017 marking diagram idtf 19 78 ncgk z715beg 1. line 1 and 2 are the part number. 2. line 3 : z is for die version. 3. line 3 : yww = 715 = one digit year and two digit week that the part was assembled. 4. line 3 : beg denotes assembly site. ordering information orderable part number description and package msl rating shipping packaging temperature f1978ncgk 4 mm x 4 mm x 0.75mm tqfn 1 tray - 40 c to +105c F1978NCGK8 4mm x 4mm x 0.75mm tqfn 1 reel - 40 c to +105c f1978evbi evaluation board f1978evsi evaluation solution including the evaluation board, controller board, and cable. the evaluation software is available for download on the product page on the idt website: www.idt.com/f1978
f1978 datasheet ? 2017 integrated device technology, inc. 26 rev o august 28 , 2017 revision history revision revision date description of change o august 28, 2017 initial r elease of the datash eet . corporate headquarters 6024 silver creek valley road san jose, ca 95138 www.idt.com sales 1- 800 -345-7015 or 408- 284 -8200 fax: 408 - 284 -2775 www.idt.com/go/sales tech support www.idt.com/go/support disclaimer integrated device technology, inc. (idt) a nd its affiliated companies (herein referred to as idt) reserve the right to modify t he products and/or specifications described herein at any time, without notice, at idt's sole discretion. performance spe cifications and operating parameters of the described p roducts are d etermined in an independent state and a re not guaranteed to perform the same way when installed in customer products. the informati on contained herein is provided without representation or warranty of a ny kind, whether express or implied , including, but not limited to, the suitability of idt's products for any particular purpose, an implie d warranty of merchantability, or non -infringement of t he intellectual property rights of others. this docume nt is presented only as a guide and does not convey any license under intellectual property rights of idt or any third parties. idt's products are not intended for use in applicati ons involving extreme environmental conditions or in life support systems or similar devices where the failu re or malfunction of an idt product can be re asonably expected to significantly affect the health or safety of users. anyone using an idt product in such a manner does so at their own risk, absent an express, written agreement by idt. integrated device technology, idt and the idt logo are trademarks or registered trademarks of idt and its subsidiaries in the united states and other count ries. other trademarks used herein are the property of idt or their respective third party owners. for d atasheet type definitions and a glossary of common terms, vi sit www.idt.com/go/glossary . all contents of this document are copyright of integrated device technology, inc. all rights reserved.

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