? semiconductor components industries, llc, 2012 june, 2012 ? rev. 6 1 publication order number: nthd4502n/d nthd4502n power mosfet 30 v, 3.9 a, dual n ? channel chipfet features ? planar technology device offers low r ds(on) and fast switching speed ? leadless chipfet pack age has 40% smaller footprint than tsop ? 6. ideal device for applications wh ere board space is at a premium. ? chipfet package exhibits excellent thermal capabilities. ideal for applications where heat transfer is required. ? these devices are pb ? free and are rohs compliant applications ? dc ? dc buck or boost converters ? low side switching ? optimized for battery and low side switching applications in computing and portable equipment maximum ratings (t j = 25 c unless otherwise noted) parameter symbol value unit drain ? to ? source voltage v dss 30 v gate ? to ? source voltage v gs 20 v continuous drain current (note 1) steady state t a = 25 c i d 2.9 a t a = 85 c 2.1 t 5 s t a = 25 c 3.9 power dissipation (note 1) steady state t a = 25 c p d 1.13 w t 5 s 2.1 continuous drain current (note 2) steady state t a = 25 c i d 2.2 a t a = 85 c 1.6 power dissipation (note 2) t a = 25 c p d 0.64 w pulsed drain current t p = 10 s i dm 12 a esd capability (note 3) c = 100 pf, r s = 1500 esd ? hbm 125 v operating junction and storage temperature t j , t stg ? 55 to 150 c source current (body diode) i s 2.5 a lead temperature for soldering purposes (1/8? from case for 10 s) t l 260 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above the recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may affect device reliability. 1. surface mounted on fr4 board using 1 in sq pad size (cu area = 1.127 in sq [1 oz] including traces). 2. surface mounted on fr4 board using the minimum recommended pad size (cu area = 0.214 in sq). 3. esd rating information: hbm class 0. device package shipping ? ordering information chipfet case 1206a style 2 http://onsemi.com 30 v 110 m @ 4.5 v 80 m @ 10 v r ds(on) typ 3.9 a i d max v (br)dss marking diagram 1 2 3 4 s 1 g 1 s 2 g 2 d 1 d 1 d 2 d 2 pin connections nthd4502nt1g chipfet (pb ? free) 3000/tape & reel 8 7 6 5 5 6 7 81 2 3 4 d 1 (7, 8) g 1 (2) s 1 (1) ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd8011/d. c5 m c5 = specific device code m = month code = pb ? free package n ? channel mosfet 1 8 d 2 (5, 6) g 2 (4) s 2 (3)
nthd4502n http://onsemi.com 2 thermal resistance ratings parameter symbol max unit junction ? to ? ambient ? steady state (note 4) r ja 110 c/w junction ? to ? ambient ? t 5 s (note 4) r ja 60 junction ? to ? ambient ? steady state (note 5) r ja 195 junction ? to ? foot ? steady state (note 5) r jf 40 4. surface mounted on fr4 board using 1 in sq pad size (cu area = 1.127 in sq [1 oz] including traces). 5. surface mounted on fr4 board using the minimum recommended pad size (cu area = 0.214 in sq). electrical characteristics (t j = 25 c unless otherwise noted) parameter symbol test conditions min typ max units off characteristics drain ? to ? source breakdown voltage v (br)dss v gs = 0 v, i d = 250 a 30 36 v zero gate voltage drain current i dss v gs = 0 v, v ds = 24 v 1.0 a v gs = 0 v, v ds = 24 v, t j = 125 c 10 gate ? to ? source leakage current i gss v ds = 0 v, v gs = 20 v 100 na on characteristics (note 6) gate threshold voltage v gs(th) v gs = v ds , i d = 250 a 1.0 1.65 3.0 v drain ? to ? source on ? resistance r ds(on) v gs = 10 v, i d = 2.9 a 78 85 m v gs = 4.5 v, i d = 2.2 a 105 140 forward transconductance g fs v ds = 15 v, i d = 2.9 a 3.8 s charges and capacitances input capacitance c iss v gs = 0 v, f = 1.0 mhz, v ds = 15 v 140 pf output capacitance c oss 53 reverse transfer capacitance c rss 16 input capacitance c iss v gs = 0 v, f = 1.0 mhz, v ds = 24 v 135 250 pf output capacitance c oss 42 75 reverse transfer capacitance c rss 13 25 total gate charge q g(tot) v gs = 10 v, v ds = 15 v, i d = 2.9 a 3.6 7.0 nc threshold gate charge q g(th) 0.3 gate ? to ? source charge q gs 0.6 gate ? to ? drain charge q gd 0.7 total gate charge q g(tot) v gs = 4.5 v, v ds = 24 v, i d = 2.9 a 1.9 nc threshold gate charge q g(th) 0.3 gate ? to ? source charge q gs 0.6 gate ? to ? drain charge q gd 0.9 6. pulse test: pulse width 300 s, duty cycle 2%.
nthd4502n http://onsemi.com 3 electrical characteristics (continued) (t j = 25 c unless otherwise noted) parameter symbol test conditions min typ max units drain ? source diode characteristics forward diode voltage v sd v gs = 0 v, i s = 2.5 a 0.85 1.2 v reverse recovery time t rr v gs = 0 v, i s = 2.9 a, di s /dt = 100 a/ s 8.6 ns reverse recovery charge q rr 4.0 nc reverse recovery time t rr v gs = 0 v, i s = 1.0 a, di s /dt = 100 a/ s 8.4 ns reverse recovery charge q rr 4.0 nc switching characteristics (note 7) turn ? on delay time t d(on) v gs = 10 v, v dd = 24 v, i d = 1 a, r g = 6 6.5 12 ns rise time t r 5.4 10 turn ? off delay time t d(off) 14.9 25 fall time t f 1.8 5.0 turn ? on delay time t d(on) v gs = 4.5 v, v dd = 24 v, i d = 2.9 a, r g = 2.5 7.8 ns rise time t r 12.6 turn ? off delay time t d(off) 9.6 fall time t f 2.8 7. switching characteristics are independent of operating junction temperatures.
nthd4502n http://onsemi.com 4 typical performance curves 4 v 100 c 0 10 5 6 6 3 2 v ds , drain ? to ? source voltage (volts) i d, drain current (amps) 4 2 0 1 figure 1. on ? region characteristics 1 6 45 5 4 2 3 0 6 figure 2. transfer characteristics v gs , gate ? to ? source voltage (volts) 57 0.2 0.1 0 figure 3. on ? resistance vs. gate ? to ? source voltage v gs , gate ? to ? source voltage (volts) r ds(on), drain ? to ? source resistance ( ) i d, drain current (amps) 26 figure 4. on ? resistance vs. drain current and gate voltage i d, drain current (amps) ? 50 0 ? 25 25 1.4 1.2 1.0 0.8 0.6 50 125 100 figure 5. on ? resistance variation with temperature t j , junction temperature ( c) t j = 25 c 0.3 46 t j = ? 55 c i d = 2.9 a t j = 25 c 0.12 0.07 75 150 t j = 25 c i d = 2.9 a v gs = 10 v r ds(on), drain ? to ? source resistance (normalized) 4 25 c r ds(on), drain ? to ? source resistance ( ) 1.8 v gs = 4.5 v 310 5 0.1 30 25 figure 6. drain ? to ? source leakage current vs. voltage v ds , drain ? to ? source voltage (volts) 15 v gs = 0 v i dss , leakage (na) t j = 100 c 3.4 v 2.6 v 2.8 v v gs = 10 v 10 1000 v ds 10 v 35 0.09 10 v gs = 10, 6, 5, 4.5 & 4.2 v resp. 2 2 0.25 89 0.10 0.08 0.11 4 1.6 100 1 20 t j = 150 c 8 3 v 3.2 v 3.6 v 3.8 v 3 1 0.15 0.05
nthd4502n http://onsemi.com 5 typical performance curves v ds = 0 v v gs = 0 v 5 10 10 300 200 100 0 30 gate ? to ? source or drain ? to ? source voltage (volts) figure 7. capacitance variation c, capacitance (pf) 02 1 8 2 0 figure 8. gate ? to ? source and drain ? to ? source voltage vs. total charge q g , total gate charge (nc) v gs, gate ? to ? source voltage (volts) t j = 25 c c oss c iss c rss i d = 2.9 a t j = 25 c q g 4 6 v ds, drain ? to ? source voltage (volts) 24 8 0 q gd 10 1 10 0.1 100 r g , gate resistance (ohms) figure 9. resistive switching time variation vs. gate resistance t, time (ns) v dd = 24 v i d = 1.0 a v gs = 10 v 100 50 12 4 t d(off) t d(on) t f t r v gs v ds 15 4 0.9 3 0 v sd , source ? to ? drain voltage (volts) figure 10. diode forward voltage vs. current i s , source current (amps) v gs = 0 v t j = 25 c 0.7 0.4 0.3 1 2 20 1 0.5 0.8 q gs 16 12 10 3 1 0.6 20 25 v ds v gs
nthd4502n http://onsemi.com 6 package dimensions chipfet case 1206a ? 03 issue k style 2: pin 1. source 1 2. gate 1 3. source 2 4. gate 2 5. drain 2 6. drain 2 7. drain 1 8. drain 1 e a b e e1 d 1234 8765 c l 1 2 3 4 8 7 6 5 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. mold gate burrs shall not exceed 0.13 mm per side. 4. leadframe to molded body offset in horizontal and vertical shall not exceed 0.08 mm. 5. dimensions a and b exclusive of mold gate burrs. 6. no mold flash allowed on the top and bottom lead surface. 0.05 (0.002) dim a min nom max min millimeters 1.00 1.05 1.10 0.039 inches b 0.25 0.30 0.35 0.010 c 0.10 0.15 0.20 0.004 d 2.95 3.05 3.10 0.116 e 1.55 1.65 1.70 0.061 e 0.65 bsc e1 0.55 bsc l 0.28 0.35 0.42 0.011 0.041 0.043 0.012 0.014 0.006 0.008 0.120 0.122 0.065 0.067 0.025 bsc 0.022 bsc 0.014 0.017 nom max 1.80 1.90 2.00 0.071 0.075 0.079 h e 5 nom 5 nom h e soldering footprint 0.457 0.018 2.032 0.08 0.65 0.025 pitch 0.66 0.026 mm inches 2.362 0.093 1 8x 8x on semiconductor and are registered trademar ks of semiconductor components industries, llc (s cillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other intellectual property. a list ing of scillc?s product/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent ? marking.pdf. scillc reserves the right to make changes without further notice to an y products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of th e application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typical s? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products ar e not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associ ated with such unintended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action em ployer. this literature is subject to all applicable copyrig ht laws and is not fo r resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 nthd4502n/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loca l sales representative
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