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TLC5949 www.ti.com sbvs219a ? december 2012 ? revised december 2012 16-channel, 12-bit, es-pwm, full self-diagnosis led driver for 7-bit global bc led lamp check for samples: TLC5949 1 features 2 ? 16 constant-current sink output channels ? pre-thermal warning (ptw) ? sink current capability with ? four-channel grouped delay switching to maximum bc data: 2 ma to 45 ma prevent inrush current ? global brightness control (bc): ? operating temperature: ? 40 c to +85 c ? 7-bit (128 steps) with 25% to 100% range applications ? grayscale control (gs) with enhanced ? led video displays spectrum or conventional pwm: ? led signboards ? 12-bit (4096 steps) ? led power-supply voltage: up to 10 v description ? vcc: 3.0 v to 3.6 v the TLC5949 is a 16-channel, constant-current sink ? constant-current accuracy: led driver. each channel has an individually- ? channel-to-channel: 0.6% (typ), 2% (max) adjustable, pulse width modulation (pwm) grayscale (gs) brightness control with 4096 steps. all channels ? device-to-device: 1% (typ), 4% (max) have a 128-step global brightness control (bc). bc ? data transfer rate: 33 mhz adjusts brightness deviation with other led drivers. ? grayscale control clock: 33 mhz gs and bc data are accessible with a serial interface port. ? auto display repeat and auto data refresh ? display timing reset the TLC5949 has six error flags: led open detection (lod), led short detection (lsd), output leakage ? power-save mode to minimize vcc current detection (old), reference current terminal short flag ? lod and lsd with invisible detection detection (isf), pre-thermal warning (ptw), and mode (idm) thermal error flag (tef). the error detection results ? output leakage detection (old) can be read with a serial interface port. ? current reference terminal short flag (isf) ? thermal shutdown (tsd) and error flag (tef) typical application circuit (multiple daisy-chained TLC5949s) 1 please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2 all trademarks are the property of their respective owners. production data information is current as of publication date. copyright ? 2012, texas instruments incorporated products conform to specifications per the terms of the texas instruments standard warranty. production processing does not necessarily include testing of all parameters. ? sinsclk lat gsclk sout gnd vcc device 1 vcc ? ? ? sinsclk lat gsclk r iref iref sout device n out0 out15 data sclk gsclk ? r iref iref controller gnd vcc vcc 3 lat ? ? out0 out15 ? data read vled
TLC5949 sbvs219a ? december 2012 ? revised december 2012 www.ti.com this integrated circuit can be damaged by esd. texas instruments recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures can cause damage. esd damage can range from subtle performance degradation to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. package and ordering information (1) product package designator ordering number transport media TLC5949dbqr tape and reel dbq TLC5949dbq tube TLC5949 TLC5949pwpr tape and reel pwp TLC5949pwp tube (1) for the most current package and ordering information, see the package option addendum at the end of this document, or visit the device product folder at www.ti.com . absolute maximum ratings (1) over operating free-air temperature range, unless otherwise noted. value min max unit vcc ? 0.3 +6.0 v sin, sclk, lat, gsclk, iref ? 0.3 v cc + 0.3 v voltage (2) sout ? 0.3 v cc + 0.3 v out0 to out15 ? 0.3 +11 v current out0 to out15 +60 ma operating junction, t j (max) +150 c temperature storage, t stg ? 55 +150 c human body model (hbm) 3000 v electrostatic discharge (esd) ratings charged device model (cdm) 2000 v (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and do not imply functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions . exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) all voltages are with respect to device ground terminal. thermal information TLC5949 dbq pwp thermal metric (1) units (ssop, qsop) (htssop) 24 pins 24 pins ja junction-to-ambient thermal resistance 80.4 39.9 jctop junction-to-case (top) thermal resistance 44.2 23.2 jb junction-to-board thermal resistance 33.5 21.5 c/w jt junction-to-top characterization parameter 8.8 0.6 jb junction-to-board characterization parameter 33.2 21.3 jcbot junction-to-case (bottom) thermal resistance n/a 3.8 (1) for more information about traditional and new thermal metrics, see the ic package thermal metrics application report, spra953 . 2 submit documentation feedback copyright ? 2012, texas instruments incorporated product folder links: TLC5949
TLC5949 www.ti.com sbvs219a ? december 2012 ? revised december 2012 recommended operating conditions at t a = ? 40 c to +85 c and v cc = 3 v to 3.6 v, unless otherwise noted. parameter test conditions min nom max unit dc characteristics v cc supply voltage 3.0 3.6 v v o voltage applied to output out0 to out15 10 v v ih high-level input voltage sin, sclk, lat, gsclk 0.7 v cc v cc v v il low-level input voltage sin, sclk, lat, gsclk gnd 0.3 v cc v i oh high-level output current sout ? 2 ma i ol low-level output current sout 2 ma out0 to out15, i olc constant output sink current 45 ma 3 v v cc 3.6 v t a operating free-air temperature range ? 40 +85 c t j operating junction temperature range ? 40 +125 c ac characteristics f clk (sclk) data shift clock frequency sclk 33 mhz f clk (gsclk) grayscale control clock frequency gsclk 33 mhz t wh0 sclk 10 ns t wl0 sclk 10 ns t wh1 pulse duration gsclk 10 ns t wl1 gsclk 10 ns t wh2 lat 30 ns t su0 sin to sclk 5 ns t su1 lat to sclk 120 ns lat for blank bit ' 0 ' set to t su2 50 ns setup time gsclk lat for gs data written to t su3 gsclk when display time 100 ns reset mode is enabled t h0 sclk to sin 5 ns hold time t h1 sclk to lat 5 ns copyright ? 2012, texas instruments incorporated submit documentation feedback 3 product folder links: TLC5949
TLC5949 sbvs219a ? december 2012 ? revised december 2012 www.ti.com electrical characteristics at t a = ? 40 c to +85 c and v cc = 3 v to 3.6 v, unless otherwise noted. typical values are at t a = +25 c and v cc = 3.3 v. parameter test conditions min typ max unit high-level output voltage v oh i oh = ? 2 ma v cc ? 0.4 v cc v (sout) low-level output voltage v ol i ol = 2 ma 0.4 v (sout) v lod0 all out n = on, lodvlt = 00 0.25 0.30 0.35 v v lod1 all out n = on, lodvlt = 01 0.55 0.6 0.65 v led open-detection threshold v lod2 all out n = on, lodvlt = 10 0.85 0.9 0.95 v v lod3 all out n = on, lodvlt = 11 1.15 1.2 1.25 v v lsd0 all out n = on, lsdvlt = 00 0.30 v cc 0.35 v cc 0.40 v cc v v lsd1 all out n = on, lsdvlt = 01 0.40 v cc 0.45 v cc 0.50 v cc v led short-detection threshold v lsd2 all out n = on, lsdvlt = 10 0.50 v cc 0.55 v cc 0.60 v cc v v lsd3 all out n = on, lsdvlt = 11 0.60 v cc 0.65 v cc 0.70 v cc v v iref reference voltage output r iref = 1.1 k ? 1.17 1.20 1.23 v input current i in v in = v cc or gnd ? 1 1 a (sin, sclk, lat, gsclk) sin, sclk, lat, and gsclk = gnd, blank = 1, i cc0 gs n = fffh, bc = 7fh, v outn = 0.8 v, 1.5 3 ma r iref = open (all outputs off) sin, sclk, lat, and gsclk = gnd, blank = 1, gs n = fffh, bc = 7fh, i cc1 5 7 ma v outn = 0.8 v, r iref = 2.2 k ? (all outputs off, i outn = 23.1-ma target) sin, sclk, and lat = gnd, blank = 0, auto display repeat enabled, gsclk = 33 mhz, gs n = fffh, i cc2 7 9 ma bc = 7fh, v outn = 0.8 v, r iref = 2.2 k ? supply current (v cc ) (i out = 23.1-ma target) sin, sclk, and lat = gnd, blank = 0, auto display repeat enabled, gsclk = 33 mhz, gs n = fffh, i cc3 11 14 ma bc = 7fh, v outn = 0.8 v, r iref = 1.1 k ? (i out = 46.1-ma target) v cc = 3.3 v, sin, sclk, lat, and gsclk = gnd, blank = 0, auto display repeat enabled, gs n = 000h, i cc4 bc = 7fh, in power-save mode, 10 40 a v outn = 0.8 v, r iref = 1.1 k ? (i out = 46.1-ma target) all out n = on, bc = 7fh, v outn = v outfix = 0.8 v, constant output sink current i olc0 r iref = 1.1 k , t a = +25 c 43.4 46.1 48.8 ma (out0 to out15) (i olcn = 46.1-ma target) i olkg0 t j = +25 c 0.1 a all out n = off, blank = 1, output leakage current i olkg1 v outn = v outfix = 10 v, t j = +85 c (1) 0.2 a (out0 to out15) r iref = 1.1 k ? i olkg2 t j = +125 c (1) 0.3 0.8 a (1) not tested; specified by design. 4 submit documentation feedback copyright ? 2012, texas instruments incorporated product folder links: TLC5949
TLC5949 www.ti.com sbvs219a ? december 2012 ? revised december 2012 electrical characteristics (continued) at t a = ? 40 c to +85 c and v cc = 3 v to 3.6 v, unless otherwise noted. typical values are at t a = +25 c and v cc = 3.3 v. parameter test conditions min typ max unit constant-current error all out n = on, bc = 7fh, v outn = v outfix = 0.8 v, i olc0 (channel-to-channel, r iref = 1.1 k ? , t a = +25 c 0.6 2 % out0 to out15) (2) (i outn = 46.1-ma target) constant-current error all out n = on, bc = 7fh, v outn = v outfix = 0.8 v, i olc1 (device-to-device, r iref = 1.1 k ? , t a = +25 c 1 4 % out0 to out15) (3) (i outn = 46.1-ma target) v cc = 3.0 v to 3.6 v, all out n = on, bc = 7fh, line regulation i olc2 v outn = v outfix = 0.8 v, r iref = 1.1 k ? 0.1 1 %/v (out0 to out15) (4) (i outn = 46.1-ma target) all out n = on, bc = 7fh, v outn = 0.8 v to 3.0 v, load regulation i olc3 v outfix = 0.8 v, r iref = 1.1 k ? 0.1 1 %/v (out0 to out15) (5) (i outn = 46.1-ma target) t tef thermal error flag threshold junction temperature (6) 150 165 180 c t hys thermal error flag hysteresis junction temperature (6) 5 10 20 c t ptw pre-thermal warning threshold junction temperature (6) 125 138 150 c (2) the deviation of each output from the out0 to out15 constant-current average. deviation is calculated by the formula: where n = 0 to 15. (3) deviation of the out0 to out15 constant-current average from the ideal constant-current value. deviation is calculated by the formula: ideal current is calculated by the formula: (4) line regulation is calculated by the formula: where n = 0 to 15. (5) load regulation is calculated by the equation: where n = 0 to 15. (6) not tested; specified by design. copyright ? 2012, texas instruments incorporated submit documentation feedback 5 product folder links: TLC5949 i at v = 0.8 v olc out n n (i at v = 3 v) (i at v = 0.8 v) olc out n - n n n olc out d (%/v) = 3 v 0.8 v - 100 i at v = 3 v olc cc n (i at v = 3.6 v) (i at v = 3 v) olc olc cc n n cc - d (%/v) = 3.6 v 3 v - 100 127 3/4 bc i = out n i olcmax 4 1 + d (%) = 100 - 1 i olc n i + i + ... + i + i olc0 olc1 olc15 olc14 16 d (%) = 100 ideal output current - ideal output current (i + i + ... i + i ) olc0 olc1 olc14 olc15 16
TLC5949 sbvs219a ? december 2012 ? revised december 2012 www.ti.com switching characteristics (see figure 4 , figure 5 , and figure 8 through figure 11 ) at t a = ? 40 c to +85 c, v cc = 3 v to 3.6 v, c l = 15 pf, r l = 82 ? , r iref = 1.1 k ? , and v led = 5.0 v, unless otherwise noted. typical values are at v cc = 3.3 v and t a = +25 c. parameter test conditions min typ max unit t r0 sout 5 ns rise time t r1 out n and bc = 7fh 13 ns t f0 sout 5 ns fall time t f1 out n and bc = 7fh 23 ns t d0 sclk to sout 15 25 ns t d1 lat for blank = 1 and out0, out7, out8, and out15 off 40 75 ns t d2 gsclk to out0, out7, out8, and out15 on/off with bc = 7fh 5 36 65 ns t d3 gsclk to out1, out6, out9, and out14 on/off with bc = 7fh 20 62 97 ns t d4 gsclk to out2, out5, out10, and out13 on/off with bc = 7fh 35 88 129 ns propagation delay t d5 gsclk to out3, out4, out11, and out12 on/off with bc = 7fh 50 114 161 ns lat to power-save mode by writing data for out n off with blank = 1 t d6 200 ns and psmode = 110 sclk to normal mode with psmode = 101 or lat to normal mode t d7 50 s by writing gs data for out n on with blank = 1 and psmode = 110 t outon ? t gsclk , gs n = 001h, gsclk = 33 mhz, t on_err output on-time error (1) ? 20 10 ns bc = 7fh, t a = +25 c (1) output on-time error (t on_err ) is calculated by the formula: t on_err = t out_on ? t gsclk . t outon is the actual on-time of the constant- current driver. t gsclk is the gsclk period. 6 submit documentation feedback copyright ? 2012, texas instruments incorporated product folder links: TLC5949
TLC5949 www.ti.com sbvs219a ? december 2012 ? revised december 2012 parameter measurement information pin-equivalent input and output schematic diagrams figure 1. sin, sclk, lat, gsclk figure 2. sout (1) n = 0 to 15. figure 3. out0 through out15 copyright ? 2012, texas instruments incorporated submit documentation feedback 7 product folder links: TLC5949 vccoutn (1) gnd vccsout gnd vcc input gnd
TLC5949 sbvs219a ? december 2012 ? revised december 2012 www.ti.com test circuits (1) n = 0 to 15. (2) c l includes measurement probe and jig capacitance. figure 4. rise time and fall time test circuit for out n (1) c l includes measurement probe and jig capacitance. figure 5. rise time and fall time test circuit for sout (1) n = 0 to 15. figure 6. constant-current test circuit for out n 8 submit documentation feedback copyright ? 2012, texas instruments incorporated product folder links: TLC5949 ? ? v cc r iref v outfix v outn out0 vcc out n (1) out15 gnd iref v cc vccgnd sout c l (1) v cc vcc gnd iref out n (1) r iref r l c l (2) v led
TLC5949 www.ti.com sbvs219a ? december 2012 ? revised december 2012 timing diagrams (1) input pulse rise and fall time is 1 ns to 3 ns. figure 7. input timing (1) input pulse rise and fall time is 1 ns to 3 ns. figure 8. output timing copyright ? 2012, texas instruments incorporated submit documentation feedback 9 product folder links: TLC5949 t , t , t , t , t , t , t , t , t , t : r0 r1 f0 f1 d0 d1 d2 d3 d4 d5 , t , t d6 d7 input (1) 50%50% 90%10% output t d t or t r f v or v ol outnl v or v oh outnh gnd v cc t , t , t , t , t : wh0 wl0 wh1 wl1 wh2 input (1) clock input (1) data and control clock (1) t , t , t , t , t , t su0 su1 h0 h1 : su2 su3 v cc v cc gnd v cc gndgnd 50%50% 50% t wh t wl t su t h
TLC5949 sbvs219a ? december 2012 ? revised december 2012 www.ti.com (1) rsv = reserved. (2) t outon refers to t on_err = t outon ? t gsclk . figure 9. grayscale data write timing 10 submit documentation feedback copyright ? 2012, texas instruments incorporated product folder links: TLC5949 rsv t d5 t d4 t d3 t d2 t d0 t wh1 gs0 1b 4095 t wl1 rsv gs0 0a gs15 15b t gsclk t wh2 gsclk sin out0, 7 8 15 out , out , out on off lat grayscale data in first gs data latch (internal) sout on off on off on off t su0 t su1 t h0 t , t r0 f0 t f1 low gs15 14b gs15 13b gs15 12b gs0 0b gs0 2b gs0 3b rsv rsv rsv rsv (1) rsv rsv rsv rsv rsv rsv lod 15 lod 14 lod 13 1 2 3 4 5 6 old data new data sclk 1 190 191 192 2 3 4 5 t wl0 1 2 3 4 5 6 7 t h1 t wh0 on off on off on off on off t d2 t d3 t d4 t d5 t , t su2 su3 t outon (2) t outon t outon t outon display timing reset enabled, auto display repeat disabled, all gs data are fffh (v ) outnh (v ) outnl gs data write low blank bit in first control data latch (internal) t r1 out1 6 9 14 , out , out , out out2 5 10 13 , out , out , out out3 4 11 12 , out , out , out display timing reset enabled, auto display repeat disabled, all gs data are 001h data = 0 low gs15 15c gs15 14c gs15 13c gs15 12c gs15 11c gs15 10c low gs data write out0 7 8 15 , out , out , out out1 6 9 14 , out , out , out out2 5 10 13 , out , out , out out3 4 11 12 , out , out , out 4094 193 t d0 4096 t d5 t d4 t d3 t d2 grayscale data in second gs data latch (internal) old data new data the data in the 193-bit common shift register are copiedto the first and second gs data latches when the display timing reset is enabled.
TLC5949 www.ti.com sbvs219a ? december 2012 ? revised december 2012 figure 10. power-save mode timing copyright ? 2012, texas instruments incorporated submit documentation feedback 11 product folder links: TLC5949 power-save mode sin lat second grayscale data latch (internal) previous on/off data sclk 1 2 3 191 192 193 1 2 3 4 5 6 ? all data are '0' low power-save mode normal mode normal mode normal mode '1' psmode bit in control data latch (internal) 001b off out0 7 8 15 , out , out , out off out1 6 9 14 , out , out , out off icc (vcc current) more than 100 a m less than 100 a m t d6 t d7 blank bit in control data latch (internal) on or offon or off on or off on on on off out2 5 10 13 , out , out , out on or off on out3 4 11 12 , out , out , out first grayscale data latch (internal) previous on/off data all data are 0' on or offon or off on or off on or off first and second gs data latches are changed simultaneously because the blank bit is '1'.
TLC5949 sbvs219a ? december 2012 ? revised december 2012 www.ti.com (1) rsv = reserved. (2) nv = not valid; these data are not used for any function. figure 11. control data write timing 12 submit documentation feedback copyright ? 2012, texas instruments incorporated product folder links: TLC5949 nv (2) t su1 t d0 191 192 193 t h1 t wh1 sclk sin 185 186 187 188 189 190 lat bc data in first control data latch (internal) sout t wh0 t wl0 t su0 t h0 rsv 7a rsv 6a rsv 8a rsv 5a rsv 4a rsv 3a rsv 0a (1) rsv 1a high high 1 2 3 4 191 193 192 t /t r0 f0 rsv 2a old data new data high nv rsv 0b rsv 1b rsv 2b rsv 0a rsv 1a rsv 2a data = 0 blank bit in first control data latch (internal) data = 1 off (v ) outnh (v ) outnl out0 7 8 15 , out , out , out on t d1 next new data nv rsv 7 nv nv nv nv rsv 6 rsv 5 rsv 4 rsv 3 rsv 2 rsv 1 rsv 0 out is turned off when the blank bit is 1. n on off on off on off out1 6 9 14 , out , out , out out2, out5, out10, out13 out3, out4, out11, out12 t d2 t d3 t d4
TLC5949 www.ti.com sbvs219a ? december 2012 ? revised december 2012 pin configuration dbq and pwp packages ssop-24, qsop-24, and htssop-24 (top view) note: the powerpad only applies to the pwp package. copyright ? 2012, texas instruments incorporated submit documentation feedback 13 product folder links: TLC5949 gnd sin sclk lat out0out1 out2 out3 out4 out5 out6 out7 vcciref sout gsclk out15 out14 out13 out12 out11 out10 out9 out8 12 3 4 5 6 7 8 9 1011 12 2423 22 21 20 19 18 17 16 15 14 13 powerpad (bottom side) (1)
TLC5949 sbvs219a ? december 2012 ? revised december 2012 www.ti.com pin descriptions pin name no. i/o description gnd 1 ? power ground grayscale (gs) pulse width modulation (pwm) reference clock control for out n . when blank = 0, each gsclk rising edge increments the gs counter for pwm control. gsclk 21 i when blank = 1, all constant-current outputs (out0 to out15) are forced off, the gs counter is reset to '0', and the gs pwm timing controller is initialized. reference current terminal. a resistor connected between iref to gnd sets the maximum current for all constant-current outputs. iref 23 i/o when iref is shorted to gnd with low resistance, all constant-current outputs are forced off and the iref short flag (isf) bit in the status information data (sid) is set to '1'. the lat rising edge either latches the data from the 193-bit common shift register into the first gs data latch when the common shift register msb is '0' or latches the data into the first control data latch when the common shift register msb is '1'. lat 4 i when the display timing reset bit (tmgrst) in the first control data latch is '1', the gs counter is initialized at the lat signal for gs data writes. at the same time, the data in the 193-bit common shift register are copied to the first and second gs data latches simultaneously and the bc data in the first control data latch are copied to the second data latch. out0 5 o out1 6 o out2 7 o out3 8 o out4 9 o out5 10 o out6 11 o constant-current outputs. out7 12 o multiple outputs can be configured in parallel to increase the constant-current capability. out8 13 o different voltages can be applied to each output. out9 14 o out10 15 o out11 16 o out12 17 o out13 18 o out14 19 o out15 20 o serial data shift clock. data present on sin are shifted to the 193-bit common shift register lsb with the sclk rising edge. data sclk 3 i in the shift register are shifted towards the msb at each sclk rising edge. the common shift register msb appears on sout. sin 2 i 193-bit common shift register serial data input. 193-bit common shift register serial data output. led open detection (lod), led short detection (lsd), output leak detection (old), thermal error flag sout 22 o (tef), and the iref pin short flag (isf) bits can be read out with sout as sid after the lat rising edge. sout is connected to the 193-bit common shift register msb. data are clocked out at the sclk rising edge. vcc 24 ? power-supply voltage 14 submit documentation feedback copyright ? 2012, texas instruments incorporated product folder links: TLC5949
TLC5949 www.ti.com sbvs219a ? december 2012 ? revised december 2012 functional block diagram copyright ? 2012, texas instruments incorporated submit documentation feedback 15 product folder links: TLC5949 192 msb 193-bit common shift register first grayscale (gs) data latch vcc 48 lsb msb 0 192 191 msb 191 sout bit 192 lsb 0 lsb 0 vcc sin sclk lat lod, lsd, and old data latch lodlsdlat oldlat 48 isf 192 second gs data latch lat first control data latch msb 136 msb 118 lsb 0 lsb 0 119 second control data latch for bc only 188 192 13 uvlo tef and ptw lat 2 tef ptw thermal detection 12-bit es pwm timing control 16 four-channel grouped switched delay 16 constant sink current driver with 7-bit bc gs counter, auto repeat, refresh lat lodlsdlat oldlat lat2nd gsclk 7 function control bit 17 reference current control with 7-bit bc isf iref 7 lod, lsd, old ?? 4 gnd out0 out1 out14 out15
TLC5949 sbvs219a ? december 2012 ? revised december 2012 www.ti.com typical characteristics at t a = +25 c, unless otherwise noted. figure 12. reference resistor figure 13. output current vs vs output current output voltage (+3.3 v) figure 14. output current vs figure 15. constant-current error output voltage (+3.3 v) vs output current figure 16. constant-current error vs figure 17. global brightness control linearity ambient temperature 16 submit documentation feedback copyright ? 2012, texas instruments incorporated product folder links: TLC5949 g006 bc data (decimal) 0 128 7060 50 40 30 20 10 0 output current (ma) 16 48 64 80 96 32 112 i = 60 ma o i = 45 ma o i = 10 ma o i = 2 ma o i = 30 ma o output voltage (v) 0 3 4948 47 46 45 44 43 42 41 output current (ma) 0.5 1 1.5 2 2.5 g013 v = 3.3 v bc = 7fh v = 0.8 v r = 1.13 k cc outn iref w t = 40 c a - t = +25 c a t = c a +85 output current (ma) 0 60 32 1 0 1 2 3 -- - d i (%) olc 10 20 30 40 50 t = +25 c bc = 7fh v = 0.8 v a led g003 i , output current (v) olc 0 60 100k 10k 1k 100 r (k ) w iref , reference resistor 10 20 30 40 50 923 25380 3384 2538 2030 1450 1128 10152 5076 1692 1015 1269 846 g001 output voltage (v) 0 3 7060 50 40 30 20 10 0 output current (ma) 0.5 1 1.5 2 2.5 g011 v = 3.3 v bc = 7fh v = 0.8 v t = +25 c cc outn a i = 45 ma olcmax i = 30 ma olcmax i = 20 ma olcmax i = 10 ma olcmax i = 5 ma olcmax i = 2 ma olcmax g004 ambient temperature ( c) - 40 100 32 1 0 1 2 3 -- - d i (%) olc - 20 20 40 60 80 r = 1.13 k bc = 7fh v = 0.8 v w iref led 0
TLC5949 www.ti.com sbvs219a ? december 2012 ? revised december 2012 typical characteristics (continued) at t a = +25 c, unless otherwise noted. figure 18. supply current vs output current figure 19. supply current vs ambient temperature figure 20. supply current in power-save mode figure 21. constant-current output vs ambient temperature voltage waveform copyright ? 2012, texas instruments incorporated submit documentation feedback 17 product folder links: TLC5949 g009 ambient temperature ( c) - 40 100 1614 12 10 86 4 2 0 i ( a) m cc - 20 40 60 80 20 r = 1.13 k bc = 7fh sin = sclk = low gsclk = low power-save mode iref w 0 g010 time (20 ns/div) ch 3 (2 v/div) r = 0.85 k v v = 5 v bc = 7fh, gs = 001h r = 68 c = 15 pf gsclk = 33 mhz iref cc led l w = 3.3 v l w, ch 4 (2 v/div) ch 2 (2 v/div) ch 1 (5 v/div) channel 1 gsclk channel 2 out0 channel 3 out1 channel 4 out4 output current (ma) 0 60 2520 15 10 50 i (ma) cc 10 30 40 50 g007 20 t = +25 c bc = 7fh 2 sin = sclk = 33 mhz gsclk = 33 mhz all outputs on a g008 ambient temperature ( c) - 40 100 2520 15 10 50 i (ma) cc - 20 40 60 80 20 r = 1.13 k bc = 7fh 2 sin = sclk = 33 mhz gsclk = 33 mhz all outputs on iref w 0
TLC5949 sbvs219a ? december 2012 ? revised december 2012 www.ti.com detailed description maximum constant sink current value the maximum output current value of each channel (i olcmax ) is programmed by a single resistor (r iref ) that is placed between the iref and gnd pins. the current value can be calculated by equation 1 : where: v iref = the internal reference voltage on iref, typically 1.20 v when the global brightness control (bc) data are at maximum i olcmax = 2 ma to 45 ma with bc = 7fh (1) i olcmax is the highest current for each output. each output sinks i olcmax current when it is turned on, and the global brightness control (bc) data are set to the maximum value of 7fh (127). each output sink current can be reduced by lowering the bc value. r iref must be between 1.13 k and 25.4 k in order to hold i olcmax between 45 ma (typ) and 2 ma (typ). otherwise, the output may be unstable. output currents lower than 2 ma can be achieved by setting i olcmax to 2 ma or higher and then using global bc to lower the output current. table 1 shows the characteristics of the constant-current sink versus the external resistor, r iref . table 1. maximum constant-current output versus external resistor value i olcmax (ma) r iref (k , typ) 45 1.13 40 1.27 35 1.45 30 1.70 25 2.03 20 2.53 15 3.38 10 5.08 5 10.2 2 25.4 global brightness control (bc) function the TLC5949 is capable of adjusting the output current of all constant-current outputs simultaneously. this function is called global brightness control (bc). the global bc for all outputs (out0 to out15) is programmed with a 7-bit word. the global bc adjusts all output currents in 128 steps from 25% to 100%, where 100% corresponds to the maximum output current set by r iref . equation 2 calculates the actual output current as a function of r iref and global bc value. bc data can be set via the serial interface. when the device is powered on, the bc data in the first and second control data latches contain random data. therefore, bc data must be written to the bc data latch before turning the constant-current output on. the output current value controlled by bc can be calculated by equation 2 . where: i olcmax = the maximum constant-current value for each output determined by r iref bc = the global brightness control value in the second control data latch (0h to 7fh) (2) 18 submit documentation feedback copyright ? 2012, texas instruments incorporated product folder links: TLC5949 127 3/4 bc i = out n i olcmax 4 1 + r = iref i olcmax v iref 42.3
TLC5949 www.ti.com sbvs219a ? december 2012 ? revised december 2012 table 2 summarizes the bc data versus the set current value. table 2. bc data versus constant-current ratio and set current value bc data ratio of output i out (ma) i out (ma) binary decimal hex current to i olcmax (%) (i olcmax = 45 ma, typ) (i olcmax = 2 ma, typ) 000 0000 0 00h 25.0 11.25 0.50 000 0001 1 01h 25.6 11.52 0.51 000 0010 2 02h 26.2 11.78 0.52 ? ? ? ? ? ? 111 1101 125 7dh 98.8 44.47 1.98 111 1110 126 7eh 99.4 44.73 1.99 111 1111 127 7fh 100.0 45.00 2.00 grayscale (gs) function (pwm control) the TLC5949 can adjust the brightness of each output channel using a pulse width modulation (pwm) control scheme. the architecture of 12 bits per channel results in 4096 brightness steps, from 0% up to 100% brightness. the pwm operation for out n is controlled by a 12-bit grayscale (gs) counter. the gs counter increments on each gs reference clock (gsclk) rising edge. the gs counter resets to 000h when the blank bit in the first control data latch is set to '1'; the counter value is held at 000h while the blank bit is '1', even if the gs clock input is toggled high and low. the TLC5949 has two types of pwm control: conventional pwm control and enhanced spectrum (es) pwm control. the conventional pwm control can be selected when the espwm bit in the first control data latch is '0'. the es pwm control is selected when the espwm bit is '1'. the on-time (t out_on ) of each output (out n ) can be calculated by equation 3 . t out_on = t gsclk gs n (3) copyright ? 2012, texas instruments incorporated submit documentation feedback 19 product folder links: TLC5949
TLC5949 sbvs219a ? december 2012 ? revised december 2012 www.ti.com table 3 summarizes the gs data values versus the output on-time duty cycle. when the device powers up, the blank bit in the first control data latch is set to '1'. the 193-bit common shift register and the first and second gs data latches contain random data. therefore, gs data must be written to the gs latches before the blank bit is set to '0'. all constant-current outputs are off when the blank bit is '1'. table 3. output duty cycle and on-time versus gs data gs data gs data decimal hex on-time duty (%) decimal hex on-time duty (%) 0 000h 0 2048 800h 50.001 1 001h 0.002 2049 801h 50.002 2 002h 0.003 2050 802h 50.004 3 003h 0.005 2051 803h 50.005 ? ? ? ? ? ? 511 1ffh 12.499 2559 9ffh 62.499 512 200h 12.500 2560 a00h 62.501 513 201h 12.502 2561 a01h 62.502 ? ? ? ? ? ? 1023 3ffh 24.999 3071 bffh 74.997 1024 400h 25.000 3072 c00h 74.998 1025 401h 25.002 3073 c01h 75.000 ? ? ? ? ? ? 1535 5ffh 37.499 3583 dffh 87.500 1536 600h 37.501 3584 e00h 87.501 1537 601h 37.502 3585 e01h 87.503 ? ? ? ? ? ? 2045 7fdh 49.996 4093 ffdh 99.997 2046 7feh 49.998 4094 ffeh 99.998 2047 7ffh 49.999 4095 fffh 100.000 conventional pwm control in this pwm control, the gs clock is enabled when the blank bit is set to '0'. the first gs clock rising edge after the blank bit is set to '0' increments the gs counter by one and switches on all outputs with a non-zero gs value programmed into the second gs data latch. each additional gs clock rising edge increases the corresponding gs counter by one. the gs counter keeps track of the number of clock pulses from the gs clock inputs. each output stays on while the counter is less than or equal to the programmed gs value. each output turns off at the gs counter value rising edge when the counter becomes greater than the output gs latch value. figure 22 illustrates the conventional pwm operation. 20 submit documentation feedback copyright ? 2012, texas instruments incorporated product folder links: TLC5949
TLC5949 www.ti.com sbvs219a ? december 2012 ? revised december 2012 (1) the internal signal is generated when lat inputs gs data with the display timing reset bit (tmgrst) set to ' 1 ' . this signal has the same function as a blank = 1 pulse. furthermore, the signal is generated at the 4096th gsclk when the auto display repeat bit (dsprpt) is set to ' 1 ' . (2) the gs counter begins to count gsclk pulses after the blank bit is set to ' 0 ' or when the lat signal for a gs data write is input with the display time reset mode enabled. (3) out n turns on at the first gsclk rising edge except when gs data are ' 0 ' after the blank bit is set to ' 0 ' or when the lat signal for a gs data write is input with the display time reset mode enabled. (4) out n does not turn on again until blank is set to ' 1 ' at least one time, except when the tmgrst or dsprpt bits are ' 1 ' . figure 22. conventional pwm operation copyright ? 2012, texas instruments incorporated submit documentation feedback 21 product folder links: TLC5949 1 2 3 4 no drivers turn on when gs data are '0'. gsclk out n (gsdata = 000h) on off on off t = gsclk 1 out n (gsdata = 001h) on off t = gsclk 2 on off t = gsclk 3 on off on off out n (gsdata = 002h) out n (gsdata = 003h) out n (gsdata = 7ffh) out n (gsdata = 800h) on off on off on off out n (gsdata = ffeh) out n (gsdata = fffh) out n (gsdata = 801h) on off out n (gsdata = ffdh) see (2) (v ) outnh (v ) outnl (v ) outnh 2048 2049 2050 blank bit (internal) (1) 1 2 3 4 4095 4096 4097 (v ) outnl (v ) outnh (v ) outnl (v ) outnh (v ) outnl (v ) outnh (v ) outnl (v ) outnh (v ) outnl (v ) outnh (v ) outnl (v ) outnh (v ) outnl (v ) outnh (v ) outnl (v ) outnh (v ) outnl see (3) see (4) t = gsclk 2048 t = gsclk 4095 t = gsclk 2049 t = gsclk 4093 t = gsclk 4094 t = gsclk 2047
TLC5949 sbvs219a ? december 2012 ? revised december 2012 www.ti.com enhanced spectrum (es) pwm control in this pwm control, the total display period is divided into 32 display segments. the total display period is the time from the first gs clock (gsclk) to the 4096th gsclk input after the blank bit is set to '0'. each display segment has a maximum of 128 gsclks. the out n on-time changes, depending on the 12-bit gs data. refer to table 4 for the sequence of information and to figure 23 for the timing information. table 4. es pwm drive turn-on time length gs data decimal hex out n driver operation 0 000h does not turn on 1 001h turns on for one gsclk period in the first display segment 2 002h turns on for one gsclk period in the first and 17th display segments 3 003h turns on for one gsclk period in the first, 17th, and 9th display segments 4 004h turns on for one gsclk period in the first, 17th, 9th, and 25th display segments 5 005h turns on for one gsclk period in the first, 17th, 9th, 25th, and 5th display segments 6 006h turns on for one gsclk period in the first, 17th, 9th, 25th, 5th, and 21th display segments the number of display segments where out n is turned on for one gsclk is incremented by increasing gs data in the following order: ? ? 1 > 17 > 9 > 25 5 > 21 > 13 > 29 > 3 > 19 > 11 > 27 > 7 > 23 > 15 > 31 > 2 > 18 > 10 > 26 > 6 > 22 > 14 > 30 > 4 > 20 > 12 > 28 > 8 > 24 > 16 > 32. turns on for one gsclk period in the first to 31st display segments, but does not turn on in the 31 01fh 32nd display segment 32 020h turns on for one gsclk period in all display segments (first to 32nd) turns on for two gsclk periods in the first display period and for one gsclk period in all other 33 021h display periods the number of display segments where out n is turned on for one gsclk is incremented by increasing gs data in the following order: ? ? 1 > 17 > 9 > 25 5 > 21 > 13 > 29 > 3 > 19 > 11 > 27 > 7 > 23 > 15 > 31 > 2 > 18 > 10 > 26 > 6 > 22 > 14 > 30 > 4 > 20 > 12 > 28 > 8 > 24 > 16 > 32. turns on for two gsclk periods in the first to 31st display segments and turns on one gsclk 63 03fh period in the 32nd display segment 64 040h turns on for two gsclk periods in all display segments (first to 32nd) turns on for three gsclk periods in the first display segment and for two gsclk periods in all 65 041h other display segments the number of display segments where out n is turned on for one gsclk is incremented by increasing gs data in the following order: ? ? 1 > 17 > 9 > 25 5 > 21 > 13 > 29 > 3 > 19 > 11 > 27 > 7 > 23 > 15 > 31 > 2 > 18 > 10 > 26 > 6 > 22 > 14 > 30 > 4 > 20 > 12 > 28 > 8 > 24 > 16 > 32. turns on for 127 gsclk periods in the first to 31st display segments, but only turns on for 126 4063 edfh gsclk periods in the 32nd display segment 4064 fe0h turns on for 127 gsclk periods in all display segments (first to 32nd) turns on for 128 gsclk periods in the first display period and for 127 gsclk periods in the 4065 fe1h second to 32nd display segments ? ? ? turns on for 128 gsclk periods in the first to 15th and 17th to 31st display segments; also turns 4094 ffeh on for 127 gsclk periods in the 16th and 32nd display segments. turns on for 128 gsclk periods in the first to 31st display segments but only turns on for 127 4095 fffh gsclk periods in the 32nd display segment 22 submit documentation feedback copyright ? 2012, texas instruments incorporated product folder links: TLC5949
TLC5949 www.ti.com sbvs219a ? december 2012 ? revised december 2012 (1) the internal signal is generated when lat inputs gs data when the display timing reset bit (tmgrst) is set to ' 1 ' . this signal has the same function as blank = 1. furthermore, the signal is generated at the 4096th gsclk when the auto display repeat bit (dsprpt) is set to ' 1 ' . (2) when auto display repeat is on. figure 23. es pwm operation copyright ? 2012, texas instruments incorporated submit documentation feedback 23 product folder links: TLC5949 4096 4094 4095 1 2 3 32nd period 17th period 24th period 3967 3970 3968 3969 127 129 128 130 gsclk blank bit in the first control data latch (internal) (1) on off off on off on off on off on off on 1022 1025 1023 1026 1024 1027 3070 3073 3071 3074 3072 3075 1st period 25th period 31st period (voltage level = high) note (2) 2nd period 8th period 16th period 9th period 2046 2049 2047 2050 2048 2051 1st period off on off on off on off on off on off on t = gsclk 128 off out n (gs data = 000h) out n (gs data = 001h) out n (gs data = 002h) out n (gs data = 003h) out n (gs data = 004h) out n (gs data = 010h) out n (gs data = 020h) out n (gs data = 021h) out n (gs data = 022h) out n (gs data = f80h) out n (gs data = f81h) out n (gs data = ffeh) out n (gs data = fffh) t = gsclk 127 t = gsclk 127 t = gsclk 128 t = gsclk 128 on ? ? ? ? ? ? ? ? ? ? t = gsclk 1d t = gsclk 1d t = gsclk 1d t = gsclk 1d t = gsclk 1d t = gsclk 1d (voltage level = low) t = gsclk 1d t = gsclk 127 t = gsclk 127 in 2nd to 32nd period t = gsclk 127 in 2nd to period 32nd t = gsclk 128 in 2nd to 31st period t = gsclk 128 in 2nd to 15th and 17th to periods, t = gsclk 127 in 16th period 31st t = gsclk t = gsclk 1d t = gsclk 1d t = gsclk 2d t = gsclk 2d t = gsclk 1d t = gsclk 1d t = gsclk 1d t = gsclk 2d t = gsclk 1d t = gsclk 1d t = gsclk 1d t = gsclk 1d t = gsclk 1d t = gsclk 1d t = gsclk 1d t = gsclk 1d t = gsclk 1d t = gsclk 1d t = gsclk 1d t = gsclk 1d t = gsclk 1d t = gsclk 1d t = gsclk 1d t = gsclk 1d
TLC5949 sbvs219a ? december 2012 ? revised december 2012 www.ti.com auto display repeat function this function can repeat the total display period as long as gsclk is present, as shown in figure 24 . this function is switched on or off by the content of the dsprpt bit in the first control data latch. when the dsprpt bit is '1', auto display repeat is enabled and the entire display period automatically repeats. when the dsprst bit is '0', the auto display repeat is disabled and the entire display period executes only one time after either the blank bit is changed from '1' to '0', or after a lat signal rising edge for a gs data write is input when the display timing reset is enabled. (1) out n is not turned on until blank changes from ' 1 ' to ' 0 ' or until lat changes from low to high for a gs data write with tmgrst = 1. figure 24. auto display repeat function auto data refresh function this function allows grayscale (gs) data and global brightness control (bc) data to be input at any time without synchronizing the input to the display timing. if gs and bc data are sent during a display period, the input data are held in the first latch for each data register. the data are then transferred to the second latch when the 4096th gsclk occurs. the second latch data are used for the next display period. refer to figure 25 and figure 26 for the auto data refresh function timing. however, when the blank bit in the first control data latch is set to '1' before the 4096th gsclk occurs, the first latch data immediately upload to the second latch. also, when a lat rising edge occurs while the blank bit is '1', the selected shift register data are transferred to the first and second latch at the same time. the data of bits 119-136 (blank, dsprpt, tmgrst, espwm, lodvlt, lsdvlt, lattmg, idmena, idmrpt, idmcur, olden, and psmode) in the control data latch immediately update whenever the data are written into the first latch. 24 submit documentation feedback copyright ? 2012, texas instruments incorporated product folder links: TLC5949 1 4094 1 2 2 4095 4096 gsclk outn (gs data = fffh) 1 4 2 5 3 2nd entire display period 4094 1 4 7 10 4095 4095 2 5 8 4093 4096 3 6 9 outn is forced off when blank is set to '1'. display period is repeated with auto display repeat function. off on 1st entire display period 4094 1 4 4095 2 5 4093 4096 3 note (1) '1' (auto display repeat enabled) dsprpt = 0 (auto display repeat disabled) 1st entire display period blank bit in first control data latch (internal) dsprpt bit in first control data latch (internal) 3rd entire display period blank = 1 (blank) blank = 0 (not blank)
TLC5949 www.ti.com sbvs219a ? december 2012 ? revised december 2012 (1) rsv = reserved. (2) blank data do not change with auto display repeat enabled. figure 25. auto data refresh function 1 copyright ? 2012, texas instruments incorporated submit documentation feedback 25 product folder links: TLC5949 gs0 1a sclk first gs data latch (internal) gsclk second gs data latch (internal) out n common shift register (internal) lat off on gs0 4a gs0 3a gs0 2a gs0 0a high not valid not valid rsv 0a (1) low gs15 15b new gs data old gs data old gs data new gs data 4095 4096 1 3 5 7 2 4 6 8 new control data old control dataold control data new control data gs and bc controlled by old data controlled by new data blank bit in first control data latch (internal) (2) data = 0 first control data latch (internal) second control data latch (internal) sin sout gs data write control data write rsv 1a rsv 2a rsv 3a gs15 14b gs15 13b high gs data write 188 189 190 191 192 193 1 2 3 190 191 192 193 1 2 3 4 low (bit 193 data) gs15 15a gs15 14a gs15 13a gs0 0a gs0 1a gs0 2a
TLC5949 sbvs219a ? december 2012 ? revised december 2012 www.ti.com (1) rsv = reserved. (2) the blank bit value is changed after the lat rising edge. (3) gs and bc are controlled by new data. figure 26. auto data refresh function 2 display timing reset function the display timing reset function allows initializing the display timing with a lat rising edge for a gs data write. this function can be switched on or off with the tmgrst bit in the first control data latch. when the tmgrst bit is '1', the gs counter is reset to '0' and all outputs are forced off at the lat rising edge for a gs data write. furthermore, the data in the 193-bit common shift register are copied to the first and second gs data latches at the same time. in addition, the bc data in the first control data latch are transferred to the second data latch simultaneously. this configuration is identical to the blank bit when it changes data from '0' to '1' and '1' to '0'. therefore, the blank bit is not required to control the display reset. pwm control resumes from the next gsclk rising edge. when the tmgrst bit is '0', the gs counter is not reset and the outputs are not forced off even with a lat rising edge. 26 submit documentation feedback copyright ? 2012, texas instruments incorporated product folder links: TLC5949 '0' control data write rsv 0a not valid gs0 1a sclk first gs data latch (internal) gsclk second gs data latch (internal) out n common shift register (internal) lat off on gs0 4a gs0 3a gs0 2a gs0 0a high rsv 0a (1) not valid new gs data old gs data old gs data new gs data new data old control dataold control data gs and bc controlled by old data note (3) blank bit in first control data latch (internal) (2) data = 0 first control data latch (internal) second control data latch (internal) sin sout low (bit 193 data) gs15 15a gs data write control data write not valid rsv 1a rsv 2a rsv 3a gs15 14a gs15 13a gs0 0a gs0 1a gs0 2a high (bit 193 data) 188 189 190 191 192 193 1 2 3 190 191 192 193 1 2 3 193 not valid high not valid 1 2 3 new data high data = 1 new data
TLC5949 www.ti.com sbvs219a ? december 2012 ? revised december 2012 register and data latch configuration the TLC5949 has one common shift register and two pairs of data latches: the first and second grayscale (gs) data latches and the first and second control data latches. the common shift register is 193 bits long and the gs data latches are 192 bits long in total. the first control data latch is 137 bits long and the second latch is 119 bits long. when the common shift register msb is '0', the least significant 256 bits from the common shift register are latched into the first gs data latch. when the msb is '1', the data are latched into the first control data latch. figure 27 shows the common shift register and latch configurations. (1) rsv = reserved. figure 27. common shift register and control data latches configuration copyright ? 2012, texas instruments incorporated submit documentation feedback 27 product folder links: TLC5949 lower 137 bits of 192 bits sout sclk sin common shift register (193bits) msb lower 192 bits 1 2 3 4 5 187 188 189 190 191 192 latch select bit common data bit 191 common data bit 190 common data bit 189 common data bit 188 common data bit 187 common data bit 5 common data bit 4 common data bit 3 common data bit 2 common data bit 1 this latch pulsecomes from the lat pin when the msb of the common shift register is 1. lsb 0 common data bit 0 192 bits first grayscale (gs) data latch (192 bits) msb 191 48 180 gs data for out15 out15 bit 15 out15 bit 0 out3 bit 0 32 47 out2 bit 15 out2 bit 0 gs data for out2 16 31 out1 bit 15 out1 bit 0 gs data for out1 lsb 0 15 out0 bit 15 out0 bit 0 gs data for out0 this latch pulse comes from the lat pin when the msb of the common shift register is '0'. 192 bits second grayscale (gs) data latch (192 bits) msb 191 48 180 gs data for out15 out15 bit 15 out15 bit 0 out3 bit 0 32 47 out2 bit 15 out2 bit 0 gs data for out2 16 31 out1 bit 15 out1 bit 0 gs data for out1 lsb 0 15 out0 bit 15 out0 bit 0 gs data for out0 the 4096th gsclk is usedto latch the data when the auto display repeat is enabled or when the blank bit is set to '1'. 192 bits to gs timing control circuit second control data latch (119 bits) 7 bits 112 bits 13-7 20-14 27-21 97-91 104-98 111-105 msb 118-112 90-84 bc bits[6:0] for out n to global brightness control circuit no applied bits lsb 6-0 the 4096th gsclk is usedto latch the data when the auto display repeat is enabled or when the blank bit is set to '1'. rsv bits rsv bits rsv bits rsv bits rsv bits rsv bits rsv bits rsv bits bc, 7 bits 112 reserved bits (write '1' to all bits) first control data latch (137 bits) 18 bits msb 136-119 13-7 20-14 27-21 97-91 104-98 111-105 118-112 fc, 18 bits 90-84 func bits 17-0 bc bits[6:0] for out n to function control circuit lsb 6-0 rsv bits (1) rsv bits rsv bits rsv bits rsv bits rsv bits rsv bits rsv bits bc, 7 bits 112 bits (write 1 to all bits) reserved 119 bits
TLC5949 sbvs219a ? december 2012 ? revised december 2012 www.ti.com 193-bit common shift register the 193-bit common shift register is used to shift data from the sin pin into the TLC5949. the data shifted into the register are used for gs and global bc functions. the common shift register lsb is connected to sin and the msb is connected to sout. on each sclk rising edge, the data on sin are shifted into the lsb and all 193 bits are shifted towards the msb. the register msb is always connected to sout. when the device is powered up, the data in the 193-bit common shift register are random. first and second grayscale (gs) data latch the first and second gs data latches are each 192 bits long, and set the pwm timing for each constant-current output. the on-time of all constant-current outputs is controlled by the data in the second gs data latch. a lat rising edge when the common shift register msb is '0' shifts the least significant 192 bits of the common shift register into the first gs latch. the gs data from the first latch are copied into the second latch either when the 4096th gsclk occurs with the auto display repeat mode enabled, a lat rising edge for a gs data write occurs with the display timing reset mode enabled, or the blank bit in the first control data latch is set to '1'. when the device is powered up, the data in the first and second latches are random. therefore, gs data must be written to the gs data latches before turning on the constant-current output. the first and second gs data latch configurations are shown in figure 28 . the data bit assignment is shown in table 5 . figure 28. first and second grayscale data latch configuration table 5. grayscale data latch bit description gs data latch bit controlled gs data latch bit controlled number bit name channel number bit name channel 11-0 gsout0 bits 11 to 0 for out0 107-96 gsout8 bits 11 to 0 for out8 23-12 gsout1 bits 11 to 0 for out1 119-108 gsout9 bits 11 to 0 for out9 35-24 gsout2 bits 11 to 0 for out2 131-120 gsout10 bits 11 to 0 for out10 47-36 gsout3 bits 11 to 0 for out3 143-132 gsout11 bits 11 to 0 for out11 59-48 gsout4 bits 11 to 0 for out4 155-144 gsout12 bits 11 to 0 for out12 71-60 gsout5 bits 11 to 0 for out5 167-156 gsout13 bits 11 to 0 for out13 83-72 gsout6 bits 11 to 0 for out6 179-168 gsout14 bits 11 to 0 for out14 95-84 gsout7 bits 11 to 0 for out7 191-180 gsout15 bits 11 to 0 for out15 28 submit documentation feedback copyright ? 2012, texas instruments incorporated product folder links: TLC5949 192 bits first grayscale (gs) data latch ( bits) 192 msb 191 48 180 gs data for out15 out15 bit 15 out15 bit 0 out3 bit 0 32 47 out2 bit 15 out2 bit 0 gs data for out2 16 31 out1 bit 15 out1 bit 0 gs data for out1 lsb 0 15 out0 bit 15 out0 bit 0 gs data for out0 192 bits second grayscale (gs) data latch ( bits) 192 msb 191 48 180 gs data for out15 out15 bit 15 out15 bit 0 out3 bit 0 32 47 out2 bit 15 out2 bit 0 gs data for out2 16 31 out1 bit 15 out1 bit 0 gs data for out1 lsb 0 15 out0 bit 15 out0 bit 0 gs data for out0 192 bits to gs timing control circuit from common shift register this latch pulse comes from the lat pin when the msb of the common shift register is 0. the 4096th gsclk is usedto latch the data when the auto display repeat is enabled or when the blank bit is set to 1.
TLC5949 www.ti.com sbvs219a ? december 2012 ? revised december 2012 first and second control data latch the first and second control data latches are 137 bits and 119 bits long, respectively. the first latch contains global brightness control (bc) data and function control (fc) data; the second latch contains global bc data. the dc for each constant-current output and the bc for all constant-current outputs are controlled by the second control data latch. the control data in the first latch are set by the least significant 137 bits from the common shift register at the lat rising edge when the common shift register msb is '1'. the 119 bits of bc data from the first control data latch are copied to the second latch when the 4096th gsclk occurs or when the blank bit in the first control data latch is set to '1'. when the device is powered up, the data in the first latch (except the blank and psmode bits of the fc bits) and second latch are random. therefore, bc and fc data must be written to the first and second control data latches before turning on the constant-current outputs. the default value of the blank bit is '1'. the first and second control data latch configurations are shown in figure 29 . (1) rsv = reserved. figure 29. first and second control data (bc and fc) latch configuration global brightness control (bc) data global bc data are seven bits long. the global brightness for all outputs is controlled by the second control data latch. the data are used to adjust the constant-current values for the 16 constant-current outputs. as explained in the global brightness control (bc) function section, the bc values are used to adjust the output current from 25% to 100% of the maximum value. the global bc data bit assignment in the first and second latches is shown in table 6 . table 2 summarizes the bc data value versus set current value. table 6. global brightness control data bit assignment in the control data latch bit number bit name controlled channel 118-112 bc bc[6:0] bits for all channels (out0-out15) copyright ? 2012, texas instruments incorporated submit documentation feedback 29 product folder links: TLC5949 lower 137 bits second control data latch (119 bits) 7 bits 112 bits 13-7 20-14 27-21 97-91 104-98 111-105 msb 118-112 90-84 bc bits[6:0] for out n to global brightness control circuit no applied bits lsb 6-0 rsv bits rsv bits rsv bits rsv bits rsv bits rsv bits rsv bits rsv bits bc, 7 bits 112 reserved bits (write '1' to all bits) first control data latch (137 bits) 18 bits msb 136-119 13-7 20-14 27-21 97-91 104-98 111-105 118-112 fc, 18 bits 90-84 fc bits 17-0 bc bits[6:0] for out n to function control circuit lsb 6-0 rsv bits (1) rsv bits rsv bits rsv bits rsv bits rsv bits rsv bits rsv bits bc, 7 bits 112 reserved bits (write 1 to all bits) 119 bits from common shift register this latch pulse comes from the lat pin when the msb of the common shift register is 1. the 4096th gsclk is usedto latch the data when the auto display repeat is enabled or when the blank bit is set to 1.
TLC5949 sbvs219a ? december 2012 ? revised december 2012 www.ti.com function control (fc) data latch the fc data latch is 13 bits long. this latch enables the constant-current outputs, enables the auto display repeat and display timing reset functions, and sets the pwm control mode and the lod, lsd, and old data latch timing. each function is selected by the first control data latch. when the device is powered on, the fc data in the first control data latch are random (except the blank and psmode bits) in order to disable all constant- current outputs. the fc data bit assignment in the first control data latch is shown in table 7 . table 7. function control data latch bit description default bit bit value number name (binary) description constant-current output blank bit 0 = on, 1 = off when this bit is '0', all constant-current outputs (out0-out15) are controlled 119 blank 1 by the gs pwm timing controller. when this bit is '1', all constant-current outputs are forced off, the gs counter is reset to '0', and the gs pwm timing controller is initialized. when the device is powered on, this bit is set to '1'. auto display repeat mode enable bit 0 = disabled, 1 = enabled when this bit is '0', the auto display repeat function is disabled. each constant- 120 dsprpt ? current output is turned on and off for one display period after the blank bit is set to '0'. when this bit is '1', each output is repeated every 4096 gs clocks. when the device is powered on, this bit is random. display timing reset mode enable bit 0 = disabled, 1 = enabled when this bit is '0', the gs counter is not reset and the outputs are not forced off even with a lat rising edge. 121 tmgrst ? when this bit is '1', the gs counter is reset to '0' and all outputs are forced off at the lat rising edge for a gs data write. this function is identical to the blank bit. therefore, a blank bit data change is not required to control the outputs from a controller. pwm control resumes from the next gsclk rising edge. when the device is powered on, this bit is random. es-pwm mode enable bit 0 = disabled, 1 = enabled when this bit is '0', the conventional pwm control mode is selected. 122 espwm ? when this bit is '1', es-pwm control mode is selected. if the TLC5949 is used for multiplexing a drive, the conventional pwm mode should be selected to prevent excess on/off switching. when the device is powered on, this bit is random. lod detection voltage selection bits led open detection (lod) detects a fault caused by an open led by 123, 124 lodvlt ? comparing the out n voltage to the lod detection threshold voltage. the threshold voltage is selected with these bits. refer to table 8 for the detect voltage truth table. when the device is powered on, this bit is random. lsd detection voltage selection bits led short detection (lsd) detects a fault caused by a shorted led by 125, 126 lsdvlt ? comparing the out n voltage to the lsd detection threshold voltage. the threshold voltage is selected by these bits. refer to table 9 for the detect voltage truth table. when the device is powered on, this bit is random. lod and lsd data reading timing selection bits the lod and lsd data reading time is selected by these bits. when dsprpt is '1' and idmrpt is '0', lod and lsd data are loaded to the 127, 128 lattmg ? lod and lsd data latch one time only after new gs data are written into the second gs data latch. refer to table 10 for the data load timing truth table. when the device is powered on, this bit is random. 30 submit documentation feedback copyright ? 2012, texas instruments incorporated product folder links: TLC5949
TLC5949 www.ti.com sbvs219a ? december 2012 ? revised december 2012 table 7. function control data latch bit description (continued) default bit bit value number name (binary) description invisible detection mode (idm) enable bit 0 = disabled, 1 = enabled when this bit is '0', idm is disabled. therefore, lod and lsd check led status only at power-up. when this bit is '1', lod and lsd check led status with very small current 129 idmena ? sinking at out n in a specific display segment. lod and lsd can be checked even if out n is off. the current value is set by the idmcur bits (bits 132, 131) and the time is set by the lattmg bits (bits 128, 127) in the function control data latch. furthermore, the idm operation is repeated every display period with auto display mode enabled when the idmrpt bit (bit 130) is set to '1'. when the device is powered on, this bit is random. invisible detection mode (idm) repeat bit 0 = not repeated, 1 = repeated when this bit is '0', idm is not repeated. therefore, lod and lsd check led status only one time after the blank bit is changed from '1' to '0'. otherwise, lat is input for a gs write when tmgrst is '1' or the gs counter is reset at 130 idmrpt ? power-up only one time at the time programmed by lattmg. idm is disabled when idmena is set to '0' even if this bit is '1'. when this bit is '1', idm operation is repeated every display period with the auto display mode enabled. lod and lsd check led status at out n every display period even if out n is off. when the device is powered on, this bit is random. invisible detection mode (idm) current select bits the out n sink current for idm can be selected with these bits. refer to 131, 132 idmcur ? table 11 for the idm sink current truth table. when the device is powered on, these bits are random. output leak detection mode (old) enable bit 0 = disabled, 1 = enabled when this bit is '0', old is not checked and all old bits in the status information data (sid) are set to '0'. old data are loaded into the old data latch at the 4095th gs clock. old data in sid may show the result of the previous display period, depending on the lat input timing. 133 oldena ? when this bit is '1', old checks the led status with a small current sourced through out n in a display segment. old only checks out n with gs data set to '0'. when out n current leakage is detected, the old bit that corresponds to the leaking output is set to '1' in the sid. when idmena is '1', old operation is disabled even if the oldena bit is set to '1' because old cannot obtain a correct result when idm is enabled. when the device is powered on, this bit is random. power-save mode (psm) selection bits the power-save mode is selected with these bits. refer to table 12 and 134-136 psmode 111 table 13 for the psm truth tables. when the device is powered on, these bits are all set to '1'. copyright ? 2012, texas instruments incorporated submit documentation feedback 31 product folder links: TLC5949
TLC5949 sbvs219a ? december 2012 ? revised december 2012 www.ti.com table 8. lod threshold voltage truth table lodvlt bit 124 bit 123 led open detection (lod) threshold voltage 0 0 vlod0 (0.3 v, typ) 0 1 vlod1 (0.6 v, typ) 1 0 vlod2 (0.9 v, typ) 1 1 vlod3 (1.2 v, typ) table 9. lsd threshold voltage truth table lsdvlt bit 126 bit 125 led short detection (lsd) threshold voltage 0 0 vlsd0 (0.35 vcc, typ) 0 1 vlsd1 (0.45 vcc, typ) 1 0 vlsd2 (0.55 vcc, typ) 1 1 vlsd3 (0.65 vcc, typ) table 10. lod and lsd data latch time truth table lattmg bit 128 bit 127 lod and lsd data latch timing 0 0 17th gsclk after blank bit is changed to '0' or gs counter is reset. (1) 0 1 33rd gsclk after blank bit is changed to '0' or gs counter is reset. (1) 1 0 65th gsclk after blank bit is changed to '0' or gs counter is reset. (1) 1 1 129th gsclk after blank bit is changed to '0' or gs counter is reset. (1) (1) when dsprpt is ' 1 ' and idmrpt is ' 0 ' , the resulting lod and lsd data are loaded to the lod and lsd data latch only one time after new gs data are written into the second gs data latch. table 11. idm sink current truth table idmcur bit 132 bit 131 invisible detection mode (idm) sink current 0 0 2 a (typ) 0 1 10 a (typ) 1 0 20 a (typ) 1 1 1 ma (typ) 32 submit documentation feedback copyright ? 2012, texas instruments incorporated product folder links: TLC5949
TLC5949 www.ti.com sbvs219a ? december 2012 ? revised december 2012 table 12. psm select truth table: bits 135, 134 psmode bit 135 bit 134 power-save mode (psm) function 0 0 power-save mode is disabled in every condition when all '0's are written into the second gs data latch, the device goes into power-save mode. when an sclk rising edge occurs, the device goes to normal 0 1 operation and starts to control the output current. however, some recovery time (t d7 ) is required to resume normal operation after an sclk rising edge. when all '0's are written into the second gs data latch, the device goes into power-save mode. when the data (except all '0's) are written into the second gs 1 0 data latch, the device goes to normal operation and starts to control the output current. however, some recovery time (t d7 ) is required to resume normal operation after the data changes. power-save mode is enabled in every condition. when the device is powered up, 1 (default) 1 (default) this mode is selected. table 13. psm select truth table: bit 136 psmode bit 136 power-save mode (psm) function the gsclk signal is used for gs timing control in the same manner as in normal mode even if the 0 device is in power-save mode. when the device is in power-save mode, the gsclk signal is forced low internally and gs timing control logic is not operational in order to reduce power consumption. however, if the lower two bits of 1 (default) psmode (bits 135, 134) are set to '0', the gsclk signal is not forced low because the psm is disabled. when the device is powered up, this mode is selected. copyright ? 2012, texas instruments incorporated submit documentation feedback 33 product folder links: TLC5949
TLC5949 sbvs219a ? december 2012 ? revised december 2012 www.ti.com status information data (sid) the status information data (sid) contain the status of the led open detection (lod), led short detection (lsd), output leakage detection (old), pre-thermal warning (ptw), thermal error flag (tef), and iref short flag (isf). when the lat rising edge for a gs data write is input, the sid overwrite the common shift register data after the data in the common shift register are copied to the gs latch. if the common shift register msb is '1', the sid data are not copied to the common shift register. after being copied into the common shift register, new sid data cannot be copied until at least one new bit of data is written into the common shift register. otherwise, the lat signal is ignored. to recheck sid without changing the gs data, reprogram the common shift register with the same data currently programmed into the gs latch. when lat goes high, the gs data do not change, but the sid data are loaded into the common shift register. lod, lsd, old, ptw, tef, and isf are shifted out of sout with each sclk rising edge. the sid load configuration and sid read timing are shown in figure 30 and table 14 , respectively. figure 30. sid load configuration table 14. sid load description common shift register bit number loaded sid description bits[112:0] reserved data. these 113 bits of data are not set and can be '0' or '1'. iref short flag (isf) data; 1-bit data. bit 113 0 = normal operation (default) 1 = iref terminal connected to gnd with low resistance pre-thermal warning (ptw) data; 1-bit data. bit 114 0 = normal operation (default) 1 = higher temperature condition than the detected ptw temperature range thermal error flag (tef) data; 1-bit data. bit 115 0 = normal operation (default) 1 = higher temperature condition than the detected tef temperature range bits[119:116] reserved data. these four bits of data are not set and can be either '0' or '1'. output leakage detection (old) data bit for out0 to out7. the 8-bit data bit assignment of the output channel is: bit 120 = out0 old bit 121 = out1 old bits[127:120] ? bit 126 = out6 old bit 127 = out7 old 0 = normal operation (default) 1 = led current leaks to gnd when the output is off bits[131:128] reserved data. these four bits of data are not set and can be either '0' or '1'. 34 submit documentation feedback copyright ? 2012, texas instruments incorporated product folder links: TLC5949 sclk sin lsb msb common shift register (193 bits) sout sid are loaded to thecommon shift register at the lat rising edge when the common shift register msb is 0. reserved h[3:0] lod data out[15:8] old data out[15:8] reserved d[3:0] lsd data out[7:0] reserved e[3:0] lsd data out[15:8] reserved f[3:0] lod data out[7:0] reserved g[3:0] reserved b[3:0] old data out[7:0] reserved c[3:0] reserved a[112:0] tef ptw isf common data bits [191:188] common data bits [187:180] common data bits [139:132] common data bits [143:140] common data bits [151:144] common data bits [155:152] common data bits [163:156] common data bits [167:164] common data bits [175:168] common data bits [179:176] common data bits [119:116] common data bits [127:120] common data bits [131:128] common data bits [112:0] common data bits [115:113] common data bit 192
TLC5949 www.ti.com sbvs219a ? december 2012 ? revised december 2012 table 14. sid load description (continued) common shift register bit number loaded sid description output leakage detection (old) data bit for out8 to out15. the 8-bit data bit assignment of the output channel is: bit 132 = out8 old bit 133 = out9 old bits[139:132] ? bit 138 = out14 old bit 139 = out15 old 0 = normal operation (default) 1 = output current leaks to gnd when the output is off bits[143:140] reserved data. these four bits of data are not set and can be either '0' or '1'. led short detection (lsd) data bit for out0 to out7. the 8-bit data bit assignment of the output channel is: bit 144 = out0 lsd bit 145 = out1 lsd ? bits[151:144] bit 150 = out6 lsd bit 151 = out7 lsd 0 = normal operation (default) 1 = led is shorted bits[155:152] reserved data. these four bits of data are not set and can be either '0' or '1'. led short detection (lsd) data bit for out8 to out15. the 8-bit data bit assignment of the output channel is: bit 156 = out8 lsd bit 157 = out9 lsd ? bits[163:156] bit 162 = out14 lsd bit 163 = out15 lsd 0 = normal operation (default) 1 = led is shorted bits[167:164] reserved data. these four bits of data are not set and can be either '0' or '1'. led open detection (lod) data bit for out0 to out7. the 8-bit data bit assignment of the output channel is: bit 168 = out0 lod bit 169 = out1 lod ? bits[175:168] bit 174 = out6 lod bit 175 = out7 lod 0 = normal operation (default) 1 = led is open or connected to gnd with low resistance bits[179:176] reserved data. these four bits of data are not set and can be either '0' or '1'. led open detection (lod) data bit for out8 to out15. the 8-bit data bit assignment of the output channel is: bit 180 = out8 lod bit 181 = out9 lod ? bits[187:180] bit 186 = out14 lod bit 187 = out15 lod 0 = normal operation (default) 1 = led is open or connected to gnd with low resistance bits[191:188] reserved data. these four bits of data are not set and can be either '0' or '1'. bit 192 no data loaded copyright ? 2012, texas instruments incorporated submit documentation feedback 35 product folder links: TLC5949
TLC5949 sbvs219a ? december 2012 ? revised december 2012 www.ti.com led open detection (lod) lod detects a fault caused by an led open circuit or a short from out n to ground with low resistance by comparing the out n voltage to the lod detection threshold voltage. if the out n voltage is lower than the threshold voltage (set by the lodvlt bits in the first control data latch) when out n is on, that output lod bit is set to '1' to indicate an open led. otherwise, the lod bit is set to '0'. lod data are only valid for outputs that are programmed to be on during the lod data read selected by the lattmg bits in the first control data latch. lod data are latched into the lod data latch when lod data are read, as selected by lattmg. lod data for outputs programmed to be off at the lod latch timing are always '0' when idm is not enabled. led short detection (lsd) lsd data detect a fault caused by a shorted led by comparing the out n voltage to the lsd detection threshold voltage level set by lsdvlt in the first control data latch. if the out n voltage is higher than the programmed voltage when out n is on, the corresponding output lsd bit is set to '1' to indicate a shorted led. otherwise, the lsd bit is set to '0'. lsd data are only valid for outputs that are programmed to be on when the lsd data are read, as selected by the lattmg bits in the first control data latch. lsd data are latched into the lsd data latch when the lsd data are read, as selected by lattmg. lsd data for outputs programmed to be off at the lsd latch timing are always '0' when idm is not enabled. output leakage detection (old) old detects a fault caused by a short with high resistance from out n to gnd by comparing the out n voltage to the lsd detection threshold voltage when the output is off. a small current is sourced from out n to detect led leakage. old operation can be disabled by the oldena bit. also, old is disabled when the invisible detection mode (idm) is enabled (see the invisible detection mode section). if the out n voltage is lower than the programmed lsd threshold voltage, the corresponding output old bit is set to '1' to indicate a leaking led. otherwise, the old bit is set to '0'. the old result is valid for disabled outputs only. the old data are latched into the old data latch at the end of the display period or when blank is changed to '1'. also, the old data are latched when the gs data are written if the display timing reset is enabled. old data always read '0' when the output gs is not '0', or when old is disabled. invisible detection mode (idm) idm can detect lod and lsd without dependency upon gs data. when the idm bit in the function control data latch is set, out n starts sinking the current set by the idmcur bits in the function control latch at the first gsclk; the idm sink current is turned off at the gsclk programmed by lattmg. when the idm current is turned off, lod and lsd data are latched into the lod and lsd data latch. during the idm timing, the original pwm control continues. when the idm bit in the control data latch is set to '0', the out n on/off timing is only controlled by gs data. lod and lsd data are not valid for approximately 1 s after the constant-current output turns on. therefore, gs data must be set to turn on the output for at least 1 s. furthermore, the lod and lsd latch timing bits (lattmg) should be set as shown in equation 4 : the number of gsclks required to obtain a valid lod and lsd = 1 s / t gsclk where: t gsclk = one gsclk period (4) if the gsclk frequency is 33 mhz, the outputs must be on for 33 gsclk periods or more. therefore, the lattmg bits can only be set to '01', '10', or '11'. if the gsclk frequency is 2 mhz, the outputs must be on for two or more gsclk periods. in this case, the lattmg bits can be set to any pattern. 36 submit documentation feedback copyright ? 2012, texas instruments incorporated product folder links: TLC5949
TLC5949 www.ti.com sbvs219a ? december 2012 ? revised december 2012 when lod and lsd data must be read with invisible brightness, the lattmg bits should be set to the minimum data larger than the calculated number of gsclk periods defined by equation 4 . idm does not work in power- save mode. figure 31 shows the lod, lsd, old, and idm circuit and table 15 shows a truth table for lod, lsd, old, and idm. refer to figure 32 for the pwm operation timing. figure 31. lod, lsd, and old circuit table 15. lod, lsd, old, isf, ptw, and tef truth table condition sid data lod lsd old isf ptw tef out n does not leak to device temperature is gnd device temperature is lower than thermal led is not opened led is not shorted (v outn > v lsd when iref terminal is not lower than pre-thermal 0 shutdown threshold (v outn > v lod ) (v outn v lsd ) constant-current shorted warning temperature temperature output off and out n (temperature t ptw ) (temperature t tef ) source current on) current leaks from out n to internal gnd, or out n is device temperature is led is shorted device temperature is shorted to external iref terminal is higher than thermal led is open or between anode and higher than pre- gnd with high shorted to gnd with shutdown threshold 1 shorted to gnd cathode, or shorted to thermal warning impedance low impedance and temperature and driver (v outn v lod ) higher voltage side temperature (v outn v lsd when out n are forced off is forced off (v outn > v lsd ) (temperature > t ptw ) constant-current (temperature > t tef ) output off and out n source current on) copyright ? 2012, texas instruments incorporated submit documentation feedback 37 product folder links: TLC5949 v lsd v lod old control 2 a (typ) m vcc vled pwm control idm control out n gnd lsd and old datalod data current flow for old current flow for pwm current flow for idm
TLC5949 sbvs219a ? december 2012 ? revised december 2012 www.ti.com (1) set the current with the external resistor and bc data. (2) select the output current with the idmcur bit in the control data latch. (3) select clock time with the lattmg bit in the control data latch. figure 32. pwm operation timing 38 submit documentation feedback copyright ? 2012, texas instruments incorporated product folder links: TLC5949 2 a, 10 a, 20 m m m a, or 1 ma out current for idm n '0' 193-bit common shift register data (internal) sid loaded into common shift register gs data lat '1' lod xxxh lod xxxh lod 000h lod xxxh lod data are not stable immediately after out turn on. n lod and lsd data latch (internal) 16-bit lod and lsd circuit output data (internal) lod and lsd old data lod xxxh 0 a m lod, lsd 000h lod xxxh 0 a m 2 a, 10 a, 20 m m m a lod and lsd data latch updated with latest data at the clock time selected by lattmg bit. out current for pwm control n (gsdata = fffh) 0 ma 0 ma (2) programmed output current blank bit in control data latch (internal) 1 2 3 5 4 16 17 18 19 20 4093 4095 4094 4096 1 2 3 5 4 lod xxxh control data unknown '1' tmgrst bit in control data latch (internal) (1) internal blank is generated when the lat signal is input because display timing reset is enabled. control data write latch signal. gs data write latch signal. (3)
TLC5949 www.ti.com sbvs219a ? december 2012 ? revised december 2012 power-save mode (psm) the power-save mode control bits are assigned in the function control data latch. the device dissipation current becomes 10 a (typ) in this mode. when the two lower bits in psmode are '01', '10', or '11', the power-save mode is enabled. when the lower two bits are '01' or '10', and if all '0' data are written in the second gs data latch, the TLC5949 goes into power-save mode. when an sclk rising edge is generated with the lower two psmode bits (bits 135, 134) set to '01', the device leaves psm for normal operation. out n are turned on at the first gsclk of the next display period after the device has left psm. figure 33 shows the power-save mode timing diagram. figure 33. power-save mode timing (bits 135 and 134 = 01) copyright ? 2012, texas instruments incorporated submit documentation feedback 39 product folder links: TLC5949 power-save mode 1 2 3 4 5 6 ? 191 192 193 sin lat second gs data latch (internal) previous on/off data sclk 1 2 3 all data are '0' low power-save mode normal mode normal mode normal mode '1' psmode bit in control data latch (internal) x01b or x10b off out0, 7, 8, 15 out out out off out1, 6, 9, 14 out out out off icc (vcc current) greater than 1 ma approximately 10 a m blank bit in control data latch (internal) on or offon or off on or off on on on off out2, 5, 10, 13 out out out on or off on out3, 4, 11, 12 out out out first gs data latch (internal) previous on/off data all data are '0' first and second gs data latches are changed simultaneously because the blank bit is '1'.
TLC5949 sbvs219a ? december 2012 ? revised december 2012 www.ti.com current reference (iref pin) short flag (isf) the isf function indicates that the iref terminal is shorted with low impedance to gnd. the isf bit in the sid is set to '1' during this condition. then all outputs, out n , are forced off. see table 15 for the isf truth table. pre-thermal warning (ptw) the ptw function indicates that the device junction temperature is high. the ptw in the sid is set to '1' while the device junction temperature exceeds the temperature threshold (t ptw = +138 c, typ); however, the outputs are not forced off. when the ptw is set, the device temperature should be reduced by lowering the power dissipated in it to avoid a forced shutdown by the thermal shutdown circuit. this reduction can be accomplished by lowering the gs or bc data values. when the device junction temperature drops below the t ptw temperature, the ptw bit in the sid is set to '0'. figure 34 shows a timing diagram; see table 15 for the ptw truth table. (1) this internal signal is reset when lat is input for a gs write with the display timing reset enabled. (2) the ptw bit in sid is reset to ' 0 ' at the lat rising edge for a gs data write if the device junction temperature is below t ptw . (3) the ptw bit is set to ' 1 ' when the device junction temperature is greater than t ptw . (4) the tef bit in sid is reset to ' 0 ' at the lat rising edge for a gs data write if the device junction temperature is below t tef . (5) out0 to out15 are forced off when t j exceeds t tef . furthermore, the tef bit is set to ' 1 ' at the same time. (6) out0 to out15 are turned on at the first gsclk rising edge if the device junction temperature is below t tef with blank set to ' 0 ' . figure 34. ptw, tef, and tsd timing 40 submit documentation feedback copyright ? 2012, texas instruments incorporated product folder links: TLC5949 '0' see note (2) sid data device junction temperature (t ) j lat out n gsclk 1 2 3 4 4093 4095 4094 4096 1 2 3 off on off sclk '0' tef in sid (internal data) '0' '1' '1' off on see note (5) see note (6) old latched gs data new latched gs data first gs data latch (internal) blank bit in first control data latch (internal) (1) '1' '0' ptw in sid (internal data) '0' '1' t < j ptw t t 3 j tef t t 3 j tef t t 3 j ptw t t < j tef - hyst t t t 3 j ptw t write data for first gs latch common shift register (internal) t < j ptw t see note (4) see note (3)
TLC5949 www.ti.com sbvs219a ? december 2012 ? revised december 2012 thermal shutdown (tsd) and thermal error flag (tef) the tsd function turns off all constant-current outputs on the device when the junction temperature (t j ) exceeds the threshold (t tef = +165 c, typ) and sets tef to '1'. all outputs are latched off when tef is set to '1' and remain off at least until the next gs cycle starts and the junction temperature drops below (t tef ? t hyst ). tef remains '1' until a lat rising edge occurs and the temperature is reduced. tef is set to '0' when the junction temperature drops below (t tef ? t hyst ), but the output does not turn on until the first gsclk in the next display period occurs even if tef is set to '0'. see figure 34 for a timing diagram; refer to table 15 for the tef truth table. noise reduction large surge currents may flow through the device and the board on which the device is mounted if all 16 outputs turn on simultaneously at the start of each gs cycle. these large current surges could introduce detrimental noise and electromagnetic interference (emi) into other circuits. the TLC5949 independently turns the outputs on with a delay for each group to provide a soft-start feature. the output current sinks are grouped into four groups in each color group. the first output group that is turned on/off are out0, out7, out8, and out15; the second output group is out1, out6, out9, and out14; the third output group is out2, out5, out10, and out13; and the fourth output group is out3, out4, out11, and out12. each output group is turned on and off sequentially with a small delay between the groups. however, each output on/off is controlled by the gs clock. copyright ? 2012, texas instruments incorporated submit documentation feedback 41 product folder links: TLC5949
TLC5949 sbvs219a ? december 2012 ? revised december 2012 www.ti.com revision history note: page numbers for previous revisions may differ from page numbers in the current version. changes from original (december 2012) to revision a page ? changed product status from mixed status to production data ............................................................................................ 1 ? deleted footnote 1 and gray shading from dbq rows in package and ordering information table ..................................... 2 42 submit documentation feedback copyright ? 2012, texas instruments incorporated product folder links: TLC5949
package option addendum www.ti.com 20-dec-2012 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish msl peak temp (3) samples (requires login) TLC5949dbq active ssop dbq 24 50 green (rohs & no sb/br) cu nipdau level-2-260c-1 year TLC5949dbqr active ssop dbq 24 2500 green (rohs & no sb/br) cu nipdau level-2-260c-1 year TLC5949pwp active htssop pwp 24 60 green (rohs & no sb/br) cu nipdau level-2-260c-1 year TLC5949pwpr active htssop pwp 24 2000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. -- the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant TLC5949dbqr ssop dbq 24 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 q1 TLC5949pwpr htssop pwp 24 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.0 q1 package materials information www.ti.com 20-dec-2012 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) TLC5949dbqr ssop dbq 24 2500 367.0 367.0 38.0 TLC5949pwpr htssop pwp 24 2000 367.0 367.0 38.0 package materials information www.ti.com 20-dec-2012 pack materials-page 2

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