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tms44400, tms44400p, TMS46400, TMS46400p 1048576-word by 4-bit dynamic random-access memories smhs562c may 1995 revised november 1996 1 post office box 1443 ? houston, texas 772511443 organizatio n...1048576 4 single 5-v power supply for tms44400 / p ( 10% tolerance) single 3.3-v power supply for TMS46400 / p ( 10% tolerance) low power dissipation ( TMS46400p only) 200- m a cmos standby 200- m a self refresh 300- m a extended-refresh battery backup performance ranges: access access access read time time time or write (t rac )(t cac )(t aa ) cycle (max) (max) (max) (min) '4x400/p-60 60 ns 15 ns 30 ns 110 ns '4x400/p-70 70 ns 18 ns 35 ns 130 ns '4x400/p-80 80 ns 20 ns 40 ns 150 ns enhanced page-mode operation for faster memory access cas -before-ras ( cbr) refresh long refresh period 1024-cycle refresh in 16 ms 128 ms (max) for low-power, self-refresh version ( tms4x400p) 3-state unlatched output texas instruments epic ? cmos process operating free-air temperature range 0 c to 70 c available options device power supply self-refresh battery backup refresh cycles tms44400 5 v e 1024 in 16 ms tms44400p 5 v yes 1024 in 128 ms TMS46400 3.3 v e 1024 in 16 ms TMS46400p 3.3 v yes 1024 in 128 ms these devices feature maximum ras access times of 60 ns, 70 ns, and 80 ns. all addresses and data-in lines are latched on chip to simplify system design. data out is unlatched to allow greater system flexibility. the tms4x400 and tms4x400p are offered in a 20 / 26-lead plastic small-outline ( tsop) package ( dga suffix) and a 300-mil 20 / 26-lead plastic surface-mount soj package ( dj suffix). both packages are characterized for operation from 0 c to 70 c. please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. advance information concerns new products in the sampling or preproduction phase of development. characteristic data and other specifications are subject to change without notice. pin nomenclature a0 a9 address inputs cas column-address strobe dq1 dq4 data in oe output enable ras row-address strobe v cc 5-v or 3.3-v supply v ss ground w write enable dj package ( top view ) v ss dq4 dq3 cas oe a8 a7 a6 a5 a4 26 25 24 23 22 18 17 16 15 14 1 2 3 4 5 9 10 11 12 13 dga package ( top view ) dq1 dq2 w ras a9 a0 a1 a2 a3 v cc v ss dq4 dq3 cas oe a8 a7 a6 a5 a4 26 25 24 23 22 18 17 16 15 14 1 2 3 4 5 9 10 11 12 13 dq1 dq2 w ras a9 a0 a1 a2 a3 v cc epic is a trademark of texas instruments incorporated. advance information description the tms4x400 series is a set of high-speed, 4 194 304-bit dynamic random-access memories (drams), organized as 1 048 576 words of four bits each. the tms4x400p series is a set of high-speed, low-power, self-refresh with extended-refresh, 4 194 304-bit drams, organized as 1 048 576 words of four bits each. both series employ state-of-the-art enhanced performance implanted cmos (epic ? ) technology for high performance, reliability, and low power. copyright ? 1996, texas instruments incorporated
tms44400, tms44400p, TMS46400, TMS46400p 1048576-word by 4-bit dynamic random-access memories smhs562c may 1995 revised november 1996 2 post office box 1443 ? houston, texas 772511443 logic symbol 2 a0 a1 a2 a3 a4 a5 a6 a7 a8 ras cas w oe 9 10 11 12 14 15 16 17 18 4 23 3 22 20d10/21d0 20d19/21d9 c20 [row] g23/[refresh row] 24 [pwr dwn] c21[column] g24 23c22 23,21d 24 ,25 en g25 a 0 1 048 575 ram 1024k 4 & a9 5 1 2 24 25 a,z26 a,22d 26 dq1 dq2 dq3 dq4 2 this symbol is in accordance with ansi / ieee std 91-1984 and iec publication 617-12. pin numbers shown are for the dj package. functional block diagram a0 a1 a9 16 timing and control column- address buffers row- address buffers i/o buffers 1 of 16 selection data- in reg. data- out reg. column decode sense amplifiers r o w d e c o d e 16 128k array 128k array 128k array 128k array 128k array 128k array ras cas w dq1 dq4 4 4 oe 2 8 10 10 16 16 2 advance information
tms44400, tms44400p, TMS46400, TMS46400p 1048576-word by 4-bit dynamic random-access memories smhs562c may 1995 revised november 1996 3 post office box 1443 ? houston, texas 772511443 operation enhanced page mode enhanced-page-mode operation allows faster memory access by keeping the same row address while selecting random column addresses. the time for row-address setup and hold and address multiplex is eliminated. the maximum number of columns that can be accessed is determined by the maximum ras low time and the cas page cycle time used. with minimum cas page cycle time, all 1024 columns specified by column addresses a0 through a9 can be accessed without intervening ras cycles. unlike conventional page-mode drams, the column-address buffers in this device are activated on the falling edge of ras . the buffers act as transparent or flow-through latches while cas is high. the falling edge of cas latches the column addresses. this feature allows the tms4x400 to operate at a higher data bandwidth than conventional page-mode parts because data retrieval begins as soon as the column address is valid rather than when cas transitions low. this performance improvement is referred to as enhanced page mode. a valid column address can be presented immediately after row-address hold time has been satisfied, usually well in advance of the falling edge of cas . in this case, data is obtained after t cac maximum (access time from cas low) if t aa maximum (access time from column address) has been satisfied. in the event that column addresses for the next cycle are valid at the time cas goes high, access time for the next cycle is determined by the later occurrence of t cac (acces time from cas low) or t cpa (access time from column precharge). address (a0 a9) twenty address bits are required to decode any one of the 1 048 576 storage-cell locations. ten row-address bits are set up on inputs a0 through a9 and latched onto the chip by ras . the ten column-address bits are set up on a0 through a9 and latched onto the chip by cas . all addresses must be stable on or before the falling edges of ras and cas . ras is similar to a chip enable because it activates the sense amplifiers as well as the row decoder. cas is used as a chip select, activating the output buffer, as well as latching the address bits into the column-address buffer. write enable (w ) the read or write mode is selected through w input. a logic high on w selects the read mode and a logic low selects the write mode. w can be driven from standard ttl circuits ( tms44400/ p) or low voltage ttl circuits ( TMS46400/ p) without a pullup resistor. the data input is disabled when the read mode is selected. when w goes low prior to cas (early write), data out remains in the high-impedance state for the entire cycle, permitting a write operation independent of the state of oe . this permits early-write operation to complete with oe grounded. data in / out (dq1 dq4) data out is the same polarity as data in. the output is in the high-impedance (floating) state until cas and oe are brought low. in a read cycle, the output becomes valid after all access times are satisfied. the output remains valid while cas and oe are low. cas or oe going high returns the output to a high-impedance state. this is accomplished by bringing oe high prior to applying data, satisfying the oe to data delay hold time (t oed ). output enable (oe ) oe controls the impedance of the output buffers. when oe is high, the buffers remain in the high-impedance state. bringing oe low during a normal cycle activates the output buffers, putting them in the low-impedance state. it is necessary for both ras and cas to be brought low for the output buffers to go into the low-impedance state. they remain in the low-impedance state until either oe or cas is brought high. advance information
tms44400, tms44400p, TMS46400, TMS46400p 1048576-word by 4-bit dynamic random-access memories smhs562c may 1995 revised november 1996 4 post office box 1443 ? houston, texas 772511443 refresh a refresh operation must be performed at least once every 16 ms (128 ms for tms4x400p) to retain data. this can be achieved by strobing each of the 1024 rows (a0 a9). a normal read or write cycle refreshes all bits in each row that is selected. a ras -only operation can be used by holding cas at the high (inactive) level, conserving power as the output buffer remains in the high-impedance state. externally generated addresses must be used for a ras -only refresh. hidden refresh can be performed while maintaining valid data at the output. this is accomplished by holding cas at v il after a read operation and cycling ras after a specified precharge period, similar to a ras -only refresh cycle. the external address is ignored during the hidden-refresh cycle. cas -before-ras (cbr) refresh cbr refresh is utilized by bringing cas low earlier than ras (see parameter t csr ) and holding it low after ras falls (see parameter t chr ). for successive cbr refresh cycles, cas can remain low while cycling ras . the external address is ignored and the refresh address is generated internally. a low-power battery-backup refresh mode that requires less than 300- m a (TMS46400p) or 500- m a (tms44400p) refresh current is available on the low-power devices. data integrity is maintained using cbr refresh with a period of 125 m s while holding ras low for less than 1 m s. to minimize current consumption, all input levels need to be at cmos levels ( v il 0.2 v, v ih v cc 0.2 v ). self refresh the self-refresh mode is entered by dropping cas low prior to ras going low. cas and ras are both held low for a minimum of 100 m s. the chip is then refreshed by an on-board oscillator. no external address is required since the cbr counter is used to keep track of the address. to exit the self-refresh mode, both ras and cas are brought high to satisfy t chs . upon exiting the self-refresh mode, a burst refresh (refresh a full set of row addresses) must be executed before continuing with normal operation, to ensure that the dram is fully refreshed. power up to achieve proper device operation, an initial pause of 200 m s followed by a minimum of eight initialization cycles is required after full v cc level is achieved. these eight initialization cycles must include at least one refresh ( ras -only or cbr) cycle. test mode the test mode is initiated with a cbr refresh cycle while simultaneously holding w low (wcbr). the entry cycle performs an internal refresh cycle while internally setting the device to perform parallel read or write on subsequent cycles. while in test mode, any desired data sequence can be performed on the device. the device exits test mode if a cbr refresh cycle with w held high or a ras -only refresh (ror) cycle is performed. the tms4x400 / p is configured as a 512k 8 bit device in test mode, where each dq pin has a separate 2-bit parallel read- and write-data bus. during a read cycle, the two internal bits are compared for each dq pin separately. if the two bits agree, the dq pin goes high; if not, the dq pin goes low. the two bits are written to reflect the state of their respective dq pins during a parallel-write operation. each dq pin is independent of the others, and any data pattern desired can be written on each dq pin. test time is reduced by a factor of 4 for this series. advance information
tms44400, tms44400p, TMS46400, TMS46400p 1048576-word by 4-bit dynamic random-access memories smhs562c may 1995 revised november 1996 5 post office box 1443 ? houston, texas 772511443 test mode (continued) test mode cycle entry cycle exit cycle normal mode ras cas w figure 1. test-mode cycle timing 2 2 the states of w , data in, and address are defined by the type of cycle used during test mode. absolute maximum ratings over operating free-air temperature range (unless otherwise noted) 3 supply voltage range, v cc : tms44400, tms44400p 1.0 v to 7.0 v . . . . . . . . . . . . . . . . . . . . . . . TMS46400, TMS46400p 0.5 v to 4.6 v . . . . . . . . . . . . . . . . . . . . . . . voltage range on any pin (see note 1) tms44400, tms44400p 1.0 v to 7.0 v . . . . . . . . . . . . . . . . . . . . . . . TMS46400, TMS46400p 0.5 v to 4.6 v . . . . . . . . . . . . . . . . . . . . . . . short-circuit output current 50 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . power dissipation 1 w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . operating free-air temperature range, t a 0 c to 70 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . storage temperature range, t stg 55 c to 150 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 stresses beyond those listed under aabsolute maximum ratingso may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated under arecommended operating conditi onso is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. note 1: all voltage values are with respect to v ss . recommended operating conditions tms44400 / p TMS46400 / p unit min nom max min nom max unit v cc supply voltage 4.5 5 5.5 3 3.3 3.6 v v ih high-level input voltage 2.4 6.5 2 v cc + 0.3 v v il low-level input voltage (see note 2) 1 0.8 0.3 0.8 v t a operating free-air temperature 0 70 0 70 c note 2: the algebraic convention, where the more negative (less positive) limit is designated as minimum, is used for logic-volt age levels only. advance information
tms44400, tms44400p, TMS46400, TMS46400p 1048576-word by 4-bit dynamic random-access memories smhs562c may 1995 revised november 1996 6 post office box 1443 ? houston, texas 772511443 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions '44400 - 60 '44400p - 60 '44400 - 70 '44400p - 70 '44400 - 80 '44400p - 80 unit conditions min max min max min max v oh high-level output voltage i oh = 5 ma 2.4 2.4 2.4 v v ol low-level output voltage i ol = 4.2 ma 0.4 0.4 0.4 v i i input current (leakage) v cc = 5.5 v, v i = 0 v to 6.5 v, all others = 0 v to v cc 10 10 10 m a i o output current (leakage) v cc = 5.5 v, v o = 0 v to v cc , cas high 10 10 10 m a i cc1 read- or write-cycle current (see note 3) v cc = 5.5 v, minimum cycle 105 90 80 ma after one memory cycle, ras and cas high, v ih = 2.4 v ( ttl) 2 2 2 ma i cc2 standby current after one memory cycle, ras and cas high '44400 1 1 1 ma high , v ih = v cc 0.2 v (cmos) '44400p 500 500 500 m a i cc3 average refresh current (ras only or cbr) (see note 4) v cc = 5.5 v, minimum cycle, ras cycling, cas high (ras only); ras low after cas low (cbr) 105 90 80 ma i cc4 average page current (see notes 3 and 5) v cc = 5.5 v, t pc = min, ras low, cas cycling 90 80 70 ma i cc6 2 self-refresh current (see note 3) cas 0.2 v, ras < 0.2 v, t ras and t cas > 1000 ms 500 500 500 m a i cc7 standby current, outputs enabled (see note 3) ras = v ih , cas = v il , data out = enabled 5 5 5 ma i cc10 2 battery-backup current (with cbr) t rc = 125 m s, t ras 1 ms, v cc 0.2 v v ih 6.5 v, 0 v v il 0.2 v, w and oe = v ih , address and data stable 500 500 500 m a 2 for tms44400p only notes: 3. i cc max is specified with no load connected. 4. measured with a maximum of one address change while ras = v il 5. measured with a maximum of one address change while cas = v ih advance information
tms44400, tms44400p, TMS46400, TMS46400p 1048576-word by 4-bit dynamic random-access memories smhs562c may 1995 revised november 1996 7 post office box 1443 ? houston, texas 772511443 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions '46400 - 60 '46400p - 60 '46400 - 70 '46400p - 70 '46400 - 80 '46400p - 80 unit conditions min max min max min max v oh high-level i oh = 2 ma (lvttl) 2.4 2.4 2.4 v v oh g output voltage i oh = 100 m a (lvcmos) v cc 0.2 v cc 0.2 v cc 0.2 v v ol low-level i ol = 2 ma (lvttl) 0.4 0.4 0.4 v v ol output voltage i ol = 100 m a (lvcmos) 0.2 0.2 0.2 v i i input current (leakage) v i = 0 v to 3.9 v, v cc = 3.6 v, all others = 0 v to v cc 10 10 10 m a i o output current (leakage) v o = 0 v to v cc ,v cc = 3.6 v, cas high 10 10 10 m a i cc1 read- or write-cycle current (see note 3) minimum cycle, v cc = 3.6 v 70 60 50 ma after one memory cycle, ras and cas high, v ih = 2 v (lvttl) 2 2 2 ma i cc2 standby current after one memory cycle, ras and cas high '46400 300 300 300 m a high , v ih = v cc 0.2 v (lvcmos) '46400p 200 200 200 m a i cc3 average refresh current (ras only or cbr) (see note 4) minimum cycle, v cc = 3.6 v, ras cycling, cas high (ras only); ras low after cas low (cbr) 70 60 50 ma i cc4 average page current (see notes 3 and 5) t pc = min, v cc = 3.6 v, ras low, cas cycling 60 50 40 ma i cc6 2 self-refresh current (see note 3) cas 0.2 v, ras < 0.2 v, t ras and t cas > 1000 ms 200 200 200 m a i cc7 standby current, outputs enabled (see note 3) ras = v ih , cas = v il , data out = enabled 5 5 5 ma i cc10 2 battery-backup current (with cbr) t rc = 125 m s, t ras 1 ms, v cc 0.2 v v ih 3.9 v, 0 v v il 0.2 v, w and oe = v ih , address and data stable 300 300 300 m a 2 for TMS46400p only notes: 3. i cc max is specified with no load connected. 4. measured with a maximum of one address change while ras = v il 5. measured with a maximum of one address change while cas = v ih advance information
tms44400, tms44400p, TMS46400, TMS46400p 1048576-word by 4-bit dynamic random-access memories smhs562c may 1995 revised november 1996 8 post office box 1443 ? houston, texas 772511443 capacitance over recommended ranges of supply voltage and operating free-air temperature, f = 1 mhz (see note 6) parameter min max unit c i(a) input capacitance, a0 a10 5 pf c i(rc) input capacitance, cas and ras 7 pf c i(oe) input capacitance, oe 7 pf c i(w) input capacitance, w 7 pf c o output capacitance 7 pf note 6: v cc = 5 v .5 v for the tms44400 devices, v cc = 3.3 v 0.3 v for the TMS46400 devices, and the bias on pins under test is 0 v. switching characteristics over recommended ranges of supply voltage and operating free-air temperature parameter '4x400 - 60 '4x400p - 60 '4x400 - 70 '4x400p - 70 '4x400 - 80 '4x400p - 80 unit min max min max min max t aa access time from column address 30 35 40 ns t cac access time from cas low 15 18 20 ns t cpa access time from column precharge 35 40 45 ns t rac access time from ras low 60 70 80 ns t oea access time from oe low 15 18 20 ns t clz cas to output in low impedance 0 0 0 ns t off output-disable time after cas high (see note 7) 0 15 0 18 0 20 ns t oez output-disable time after oe high (see note 7) 0 15 0 18 0 20 ns note 7: t off is specified when the output is no longer driven. advance information
tms44400, tms44400p, TMS46400, TMS46400p 1048576-word by 4-bit dynamic random-access memories smhs562c may 1995 revised november 1996 9 post office box 1443 ? houston, texas 772511443 timing requirements over recommended ranges of supply voltage and operating free-air temperature '4x400 - 60 '4x400p - 60 '4x400 - 70 '4x400p - 70 '4x6400 - 80 '4x400p - 80 unit min max min max min max t rc cycle time, random read or write (see note 8) 110 130 150 ns t rwc cycle time, read-write 155 181 205 ns t pc cycle time, page-mode read or write (see note 9) 40 45 50 ns t prwc cycle time, page-mode read-write 85 96 105 ns t rasp pulse duration, ras low, page mode (see note 10) 60 100 000 70 100 000 80 100 000 ns t ras pulse duration, ras low, nonpage mode (see note 10) 60 10 000 70 10 000 80 10 000 ns t rass pulse duration, ras low, self refresh 100 100 100 m s t cas pulse duration, cas low (see note 11) 10 10 000 18 10 000 20 10 000 ns t cp pulse duration, cas high 10 10 10 ns t rp pulse duration, ras high (precharge) 40 50 60 ns t rps precharge time after self refresh using ras 110 130 150 ns t wp pulse duration, write 10 10 10 ns t asc setup time, column address before cas low 0 0 0 ns t asr setup time, row address before ras low 0 0 0 ns t ds setup time, data (see note 12) 0 0 0 ns t rcs setup time, w high before cas low 0 0 0 ns t cwl setup time, w low before cas high 15 18 20 ns t rwl setup time, w low before ras high 15 18 20 ns t wcs setup time, w low before cas low (early-write operation only) 0 0 0 ns t wsr setup time, w high (cbr refresh only) 10 10 10 ns t wts setup time, w low (test mode only) 10 10 10 ns t cah hold time, column address after cas low 10 15 15 ns t dhr hold time, data after ras low (see note 13) 50 55 60 ns t dh hold time, data (see note 12) 10 15 15 ns t ar hold time, column address after ras low (see note 13) 50 55 60 ns t rah hold time, row address after ras low 10 10 10 ns t rch hold time, w high after cas high (see note 14) 0 0 0 ns t rrh hold time, w high after ras high (see note 14) 0 0 0 ns t wch hold time, w low after cas low (early-write operation only) 10 15 15 ns t wcr hold time, w low after ras low (see note 13) 50 55 60 ns t whr hold time, w high (cbr refresh only) 10 10 10 ns t wth hold time, w low (test mode only) 10 10 10 ns t chs hold time, cas low after ras high (self refresh) 50 50 50 ns t oeh hold time, oe command 15 18 20 ns t oed hold time, oe to data delay 15 18 20 ns notes: 8. all cycle times assume t t = 5 ns. 9. to ensure t pc min, t asc should be t cp . 10. in a read-write cycle, t rwd and t rwl must be observed. 11. in a read-write cycle, t cwd and t cwl must be observed. 12. referenced to the later of cas or w in write operations 13. the minimum value is measured when t rcd is set to t rcd min as a reference. 14. either t rrh or t rch must be satisfied for a read cycle. advance information
tms44400, tms44400p, TMS46400, TMS46400p 1048576-word by 4-bit dynamic random-access memories smhs562c may 1995 revised november 1996 10 post office box 1443 ? houston, texas 772511443 timing requirements over recommended ranges of supply voltage and operating free-air temperature (continued) '4x400 - 60 '4x400p - 60 '4x400 - 70 '4x400p - 70 '4x400 - 80 '4x400p - 80 unit min max min max min max t roh hold time, ras referenced to oe 10 10 10 ns t awd delay time, column address to w low (read-write operation only) 55 63 70 ns t chr delay time, ras low to cas high (cbr refresh only) 10 10 10 ns t crp delay time, cas high to ras low 0 0 0 ns t csh delay time, ras low to cas high 60 70 80 ns t csr delay time, cas low to ras low (cbr refresh only) 5 5 5 ns t cwd delay time, cas low to w low (read-write operation only) 40 46 50 ns t rad delay time, ras low to column address (see note 15) 15 30 15 35 15 40 ns t ral delay time, column address to ras high 30 35 40 ns t cal delay time, column address to cas high 30 35 40 ns t rcd delay time, ras low to cas low (see note 15) 20 45 20 52 20 60 ns t rpc delay time, ras high to cas low 0 0 0 ns t rsh delay time, cas low to ras high 15 18 20 ns t rwd delay time, ras low to w low (read-write operation only) 85 98 110 ns t taa access time from address (test mode) 35 40 45 ns t tcpa access time from column precharge (test mode) 40 45 50 ns t trac access time from ras (test mode) 65 75 85 ns t ref refresh time interval '4x400 16 16 16 ms t ref refresh time inter v al '4x400p 128 128 128 ms t t transition time 2 30 2 30 2 30 ns note 15: the maximum value is specified only to ensure access time. parameter measurement information 1.31 v v cc = 5 v c l = 100 pf (see note a) output under test output under test c l = 100 pf (see note a) (b) alternate load circuit (a) load circuit r l = 218 w r1 = 828 w r2 = 295 w note a: c l includes probe and fixture capacitance. figure 2. load circuits for timing parameters advance information
tms44400, tms44400p, TMS46400, TMS46400p 1048576-word by 4-bit dynamic random-access memories smhs562c may 1995 revised november 1996 11 post office box 1443 ? houston, texas 772511443 parameter measurement information 1.4 v v cc = 3.3 v c l = 100 pf (see note a) output under test output under test c l = 100 pf (see note a) (b) alternate load circuit (a) load circuit r l = 500 w r1 = 1178 w r2 = 868 w note a: c l includes probe and fixture capacitance. figure 3. low-voltage load circuits for timing parameters ras cas a0 a9 w dq1 dq4 t rc row column don't care don't care don't care t ras t rp t csh t rcd t rsh t crp t cas t rad t asc t ral t asr t rcs t cah t rrh t rch t cac t off t aa t clz t rac t cp see note a hi-z t ar t rah t cal valid data out don't care t oez t roh t oea don't care oe t t note a: output can go from the high-impedance state to an invalid-data state prior to the specified access time. figure 4. read-cycle timing advance information
tms44400, tms44400p, TMS46400, TMS46400p 1048576-word by 4-bit dynamic random-access memories smhs562c may 1995 revised november 1996 12 post office box 1443 ? houston, texas 772511443 parameter measurement information ras cas a0 a9 w dq1 dq4 t rc row column don't care don't care don't care valid data don't care t rp t ras t rsh t crp t cas t rcd t t t csh t asc t asr t rah t cah t cp t rad t cwl t rwl t wch t wcs t wp t dh t ds t dhr t wcr t ar t cal t ral don't care oe figure 5. early-write-cycle timing advance information
tms44400, tms44400p, TMS46400, TMS46400p 1048576-word by 4-bit dynamic random-access memories smhs562c may 1995 revised november 1996 13 post office box 1443 ? houston, texas 772511443 parameter measurement information ras cas a0 a9 w dq1 dq4 t rc row column don't care don't care don't care valid data don't care don't care t ras t rp t rsh t crp t cas t rcd t csh t t t asr t rah t asc t ral t cah t rad t cwl t rwl t wp t ds t dh t cp t dhr t wcr t ar t oeh t cal oe don't care don't care t oed figure 6. write-cycle timing advance information
tms44400, tms44400p, TMS46400, TMS46400p 1048576-word by 4-bit dynamic random-access memories smhs562c may 1995 revised november 1996 14 post office box 1443 ? houston, texas 772511443 parameter measurement information dq1 dq4 ras cas a0 a9 w oe t rwc t ras t rp t crp t cas t t t rcd t asr t rah t rad t ar t asc t cah t cp t t t cwl t rwl t wp t rcs t rwd t awd t cwd t cac t aa t clz t ds t dh t rac t oeh t oed t oez t oeh don't care don't care don't care don't care don't care row column see note a data in data out note a: output can go from the high-impedance state to an invalid-data state prior to the specified access time. figure 7. read-write-cycle timing advance information
tms44400, tms44400p, TMS46400, TMS46400p 1048576-word by 4-bit dynamic random-access memories smhs562c may 1995 revised november 1996 15 post office box 1443 ? houston, texas 772511443 parameter measurement information ras cas a0 a9 w dq1 dq4 t rp row column don't care valid out see note b valid out t rasp t rcd t csh t cas t cp t pc t rsh t crp t rah t asc t ral t asr t rrh t rch t rad t cac t aa t rac t clz t off column t ar t cah t rcs t cal t t don't care oe t oea t oez t oea t oez t cpa (see note a) t aa (see note a) notes: a. access time is t cpa or t aa dependent. b. output can go from the high-impedance state to an invalid-data state prior to the specified access time. figure 8. enhanced-page-mode read-cycle timing advance information
tms44400, tms44400p, TMS46400, TMS46400p 1048576-word by 4-bit dynamic random-access memories smhs562c may 1995 revised november 1996 16 post office box 1443 ? houston, texas 772511443 parameter measurement information ras cas a0 a9 w row column don't care see note a see note a valid in t rp valid data in don't care don't care don't care don't care column t rasp t csh t pc t crp t rsh t cas t rcd t rah t cah t cp t rad t cwl t wp t rwl t dh t dh t ds t ds t ral t ar t dhr t wcr see note a t cal dq1 dq4 don't care don't care oe t oeh t oed t oeh t asr t asc t cwl notes: a. referenced to cas or w , whichever occurs last b. a read cycle or a read-write cycle can be intermixed with write cycles as long as read and read-write timing specifications a re not violated. figure 9. enhanced-page-mode write-cycle timing advance information
tms44400, tms44400p, TMS46400, TMS46400p 1048576-word by 4-bit dynamic random-access memories smhs562c may 1995 revised november 1996 17 post office box 1443 ? houston, texas 772511443 parameter measurement information t rasp t rp ras cas a0 a9 w dq1 dq4 oe t csh t prwc t rcd t cas t rsh t crp t cp t asr t asc t ar t rad t cah row column column don't care t cwl t rwl t rah t cwd t awd t rwd t wp t rcs t aa t rac t cac t cpa t dh valid out (see note a) valid out valid in valid in t clz t oea t oez t oeh t oed t oeh t ds notes: a. output can go from the high-impedance state to an invalid-data state prior to the specified access time. b. a read or write cycle can be intermixed with read-write cycles as long as the read and write timing specifications are not vi olated. figure 10. enhanced-page-mode read-write-cycle timing advance information
tms44400, tms44400p, TMS46400, TMS46400p 1048576-word by 4-bit dynamic random-access memories smhs562c may 1995 revised november 1996 18 post office box 1443 ? houston, texas 772511443 parameter measurement information t rc t ras t rp t t t asr t rah t crp ras cas a0 a9 w dq1 dq4 oe don't care don't care row row don't care don't care don't care t rpc don't care figure 11. ras -only refresh-cycle timing advance information
tms44400, tms44400p, TMS46400, TMS46400p 1048576-word by 4-bit dynamic random-access memories smhs562c may 1995 revised november 1996 19 post office box 1443 ? houston, texas 772511443 parameter measurement information ras cas w a0 a9 dq1 dq4 t rc don't care don't care hi-z t ras t rp t csr t rpc t t t chr t wsr t whr oe figure 12. automatic-cbr-refresh-cycle timing ras cas w a0 a9 dq1 dq4 don't care don't care hi-z t rass t rp t csr t rpc t t t chs t wsr t whr oe t rps figure 13. self-refresh-cycle timing advance information
tms44400, tms44400p, TMS46400, TMS46400p 1048576-word by 4-bit dynamic random-access memories smhs562c may 1995 revised november 1996 20 post office box 1443 ? houston, texas 772511443 parameter measurement information ras cas a0 a10 row col don't care w dq1 dq4 oe valid data t ras t rp t rp t ras t cas t cah t asc t whr t whr t cac t aa t off t chr refresh cycle refresh cycle memory cycle t ar t whr t clz t oez t rah t asr t wsr t wsr t wsr t rac t rcs t rrh t oea figure 14. hidden-refresh-cycle (read) timing advance information
tms44400, tms44400p, TMS46400, TMS46400p 1048576-word by 4-bit dynamic random-access memories smhs562c may 1995 revised november 1996 21 post office box 1443 ? houston, texas 772511443 parameter measurement information t dhr ras cas a0 a9 w dq1 dq4 oe row col don't care don't care refresh cycle memory cycle refresh cycle t ras t rp t ras t rp t chr t cas t cah t asc t rah t wp t wsr t whr t dh t ds t wch t ar t wcr valid data don't care t rrh t wcs t asr figure 15. hidden-refresh-cycle (write) timing advance information
tms44400, tms44400p, TMS46400, TMS46400p 1048576-word by 4-bit dynamic random-access memories smhs562c may 1995 revised november 1996 22 post office box 1443 ? houston, texas 772511443 parameter measurement information ras cas w a0 a9 oe dq1 dq4 t rc don't care don't care hi-z t ras t rp t csr t rpc t t t chr t wts don't care t wth figure 16. test-mode entry-cycle timing device symbolization (tms44400 illustrated) speed ( - 60, - 70, - 80) package code low-power / self-refresh designator (blank or p) -ss tms44400 dj assembly site code lot traceability code year code die revision code wafer fab code p lll y b w m month code advance information
tms44400, tms44400p, TMS46400, TMS46400p 1048576-word by 4-bit dynamic random-access memories smhs562c may 1995 revised november 1996 23 post office box 1443 ? houston, texas 772511443 parameter measurement information dj (r-pdso-j20/26) plastic small-outline j-lead package 4040092-2 / b 10/94 0.330 (8,38) 0.340 (8,64) 0.106 (2,69) max 0.008 (0,20) nom 0.260 (6,60) 0.275 (6,99) seating plane 14 13 9 22 5 0.032 (0,81) 0.026 (0,66) 18 0.680 (17,27) 0.670 (17,02) 26 1 0.148 (3,76) 0.016 (0,41) 0.020 (0,51) 0.128 (3,25) 0.305 (7,75) 0.295 (7,49) 0.004 (0,10) m 0.007 (0,18) 0.050 (1,27) notes: a. all linear dimensions are in inches (millimeters). b. this drawing is subject to change without notice. c. plastic body dimensions do not include mold protrusion. maximum mold protrusion is 0.005 (0,125). advance information
tms44400, tms44400p, TMS46400, TMS46400p 1048576-word by 4-bit dynamic random-access memories smhs562c may 1995 revised november 1996 24 post office box 1443 ? houston, texas 772511443 mechanical data dga (r-pdso-g20/26) plastic small-outline package 4040265-2 / b 10/94 0.304 (7,72) 0.296 (7,52) 0.050 (1,27) max 0.004 (0,10) min 1 26 0.671 (17,04) 0.679 (17,24) 13 0.012 (0,30) 0.020 (0,50) 14 0.016 (0,40) seating plane 0.006 (0,15) nom 0.355 (9,02) 0.371 (9,42) gage plane 0.010 (0,25) 0.024 (0,60) 0.004 (0,10) m 0.008 (0,21) 0.050 (1,27) 0 5 notes: a. all linear dimensions are in inches (millimeters). b. this drawing is subject to change without notice. c. body dimensions do not include mold flash or protrusion. advance information
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