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to our customers, old company name in catalogs and other documents on april 1 st , 2010, nec electronics corporation merged with renesas technology corporation, and renesas electronics corporation took over all the business of both companies. therefore, although the old company name remains in this document, it is a valid renesas electronics document. we appreciate your understanding. renesas electronics website: http://www.renesas.com april 1 st , 2010 renesas electronics corporation issued by: renesas electronics corporation (http://www.renesas.com) send any inquiries to http://www.renesas.com/inquiry.
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the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all devices/types available in every country. please check with local nec representative for availability and additional information. ? 1999 mos integrated circuit pd16781 480 output tft-lcd source driver data sheet document no. s14634ej1v0ds00 (1st edition) date published february 2002 ns cp(k) printed in japan the mark ! ! ! ! shows major revised points. description the pd16781 is a source driver for 480-output tft-lcds, providing support for only striped pixel array lcd. the driver consists of a shift register for generating the sampling timing and sample & hold circuits for sampling the analog voltage. the high picture quality obtained by the alternate sample & hold execution of the two types of on-chip sample & hold circuits enables employment in applications such as car navigation panels. features ? 5.0 v drive (dynamic range 4.6 v p-p , v dd2 = 5.0 v) ? 480 output channel ? f clk = 20 mhz max. (v dd1 = 3.0 v) ? 1-phase/3-phase sampling clocks supported ? corresponds only to lcd of stripe array color filter ? two on-chip sample-and-hold circuits ? small output deviation between pins (deviation between chip pins: 20 mv max.) ? switch between right and left shift using the r,/l pin ? logic power supply voltage (v dd1 ): 3.0 to 5.5 v ? driver power supply voltage(v dd2 ): 5.0 0.5 v remark /xxx indicates active low si gnal. ordering information part number package pd16781n-xxx tcp (tab package) remark the tcp?s external shape is customized. to order the required shape, so please contact one of our sales representatives.
datasheet s14634ej1v0ds 2 pd16781 1. block diagram s 1 s 2 s 479 s 480 c 1 c 2 c 159 c 160 160-bit shift register level shifter sample and hold sthr sthl v dd1 (3.3/5.0 v) v ss1 v dd2 (5.0 v) v ss2 v ss3 r,/l clk 1 to clk 3 mode c 1 c 2 c 3 cx test input 2. sample-and hold circuit and output circuit ? + ? + sw sw s n c h1 v ss3 c h1 v ss3 sw s&h 1 sw s&h 2 video line (c n ) shpn cx
datasheet s14634ej1v0ds 3 pd16781 3. pin configuration ( pd16781n-xxx) (copper foil surface, face-up) s 480 s 479 s 478 sthl v dd2 v ss2 c 1 c 2 c 3 copper foil v dd1 surface clk 1 clk 2 clk 3 mode r,/l cx test v ss1 v ss3 v ss2 v dd2 s 3 sthr s 2 s 1 remark this figure does not specify the tcp package.
datasheet s14634ej1v0ds 4 pd16781 4. pin functions pin symbol pin name i/o description c 1 to c 3 video signal input i these pins are input video signals r, g, and b. s 1 to s 480 video signal output o these pins are output video signals, which have been sampled and hold. the relationship between the video signal input (c 1 to c 3 ) and video signal output is shown below. c 1 : s 3n 2 (n = 1, 2, 160) c 2 : s 3n 1 c 3 : s 3n sthr, sthl cascade i/o i/o these pins are inputs/outputs for the start pulse for sample and hold timing. high level of sthr/sthl is read at rising edge of clk and start sampling video signal. sthr serves as the input pin and sthl serves as output pin for the right shift. for left shift, sthl serves as the input pins and sthr serves as the output pin. r,/l shift direction control i the shift direction control pin of shift register. the shift directions of the shift registers are as follows. r,/l = h (right shift): sthr input, s 1 s 480 , sthl output. r,/l = l (left shift): sthl input, s 480 s 1 , sthr output. clk 1 to clk 3 shift clock input i the start pulse is read at rising edge of clk. the sampling pulse shpn is generated at rising edge of clk. for details, refer to 6. timing chart . the relationship between the clo cks and the output pins is shown below. (1) when mode = l or open (sequential sampling) clk 1 r,/l = h: s 3n 2 r,/l = l: s 3n clk 2 : s 3n 1 clk 3 r,/l = h: s 3n r,/l = l: s 3n 2 (1) when mode = h (simultaneous sampling) clk 1 : s 3n 2 , s 3n 1 , s 3n ( n = 1, 2,160) clk 2 : connect v dd1 or v ss1 clk 3 : connect v dd1 or v ss1 mode mode select signal input i this pin is used to select whether the three analog input signals, c 1 , c 2 , and c 3 are sampled simultaneously or sequentially (this pin is pulled down in the ic). mode = h: simultaneous sampling mode = l or open: sequential sampling cx hold capacitance control input i two sample & hold circuits are switched. cx = h s&h1: sampling, s&h2: output cx = l s&h1: output, s&h2: sampling test test i fix this pin to the l level. v dd1 logic power supply 3.0 to 5.5 v v dd2 driver power supply 5.0 0.5 v v ss1 logic ground grounding v ss2 driver ground grounding v ss3 sample & hold ground it is ground of sample & hold capacitance. supply this terminal with the stable gnd.
datasheet s14634ej1v0ds 5 pd16781 cautions 1. to prevent latch-up-breakdown, the power should be turned on in order v dd1 , logic input v dd2 , video signal input. it should be turned off in the opposite order. this relationship should be followed during transition periods as well. 2. the sampling of the video signal of this ic is only the simultaneous 3 output sampling of c 1 to c 3 . incidentally, it is designing abound of the input of the video signal in 10 mhz max. if a video signal with a higher frequency is input, the data may not be correctly displayed. 3. recommend a bypass capacitor of about 0.1 f with good high-frequency characteristics between v dd1 and v ss1 , and v dd2 and v ss2 in each driver ic. unless the power supply is reinforced, the supply voltage may fluctuate, making the sampling voltage abnormal. 4. if noise is superimposed on the start pulse pin, the data may not be displayed. for this reason, be sure to input cx signal during the vertical blanking period. 5. if the start pulse width is extended by half the clock or longer, the sampling start timing shp1 does not change from normal timing; therefore, the sampling operation is performed normally. 5. function description 5.1 switching of sample & hold circuits two sample-and-hold circuits are switched. cx output sample & hold operation l sample & hold circuit 1 (s&h 1 ) sample & hold circuit 2 (s&h 2 ) h sample & hold circuit 2 (s&h 2 ) sample & hold circuit 1 (s&h 1 ) 5.2 sample & hold and output relation between video signals c 1 , c 2 and c 3 and output pins and two sample & hold circuits. cx s 1 (s 480 )s 2 (s 479 )s 3 (s 478 )s 4 (s 477 )s 479 (s 2 )s 480 (s 1 ) l sampling c 1-2 (c 3-2 )c 2-2 (c 2-2 )c 3-2 (c 1-2 )c 1-2 (c 3-2 )c 2-2 (c 2-2 )c 3-2 (c 1-2 ) output c 1-1 (c 3-1 )c 2-1 (c 2-1 )c 3-1 (c 1-1 )c 1-1 (c 3-1 )c 2-1 (c 2-1 )c 3-1 (c 1-1 ) h sampling c 1-1 (c 3-1 )c 2-1 (c 2-1 )c 3-1 (c 1-1 )c 1-1 (c 3-1 )c 2-1 (c 2-1 )c 3-1 (c 1-1 ) output c 1-2 (c 3-2 )c 2-2 (c 2-2 )c 3-2 (c 1-2 )c 1-2 (c 3-2 )c 2-2 (c 2-2 )c 3-2 (c 1-2 ) remark c m-n = m: video input, n: sample & hold
datasheet s14634ej1v0ds 6 pd16781 6. timing chart 6.1 1-phase simultaneous sampling clk 1 sthr (sthl) sthr (sthl) shp 1 -shp 3 (shp 480 -shp 478 ) s 1 -s 3 (s 480 -s 478 ) s 1 -s 3 (s 480 -s 478 ) s 4 -s 6 (s 477 -s 475 ) s 475 -s 477 (s 6 -s 4 ) s 478 -s 480 (s 3 -s 1 ) s 4 -s 6 (s 477 -s 475 ) s 7 -s 9 (s 474 -s 472 ) shp 4 -shp 6 (shp 477 -shp 475 ) shp 1 -shp 3 (shp 480 -shp 478 ) shp 4 -shp 6 (shp 477 -shp 475 ) shp 475 -shp 477 (shp 6 -shp 4 ) shp 478 -shp 480 (shp 3 -shp 1 ) shp 7 -shp 9 (shp 474 -shp 472 ) 1 2 3 (1) (2) (3) 159 160
datasheet s14634ej1v0ds 7 pd16781 6.2 3-phase sequential sampling, right shift clk 1 sthr shp 2 shp 478 shp 479 shp 4 shp 1 123 160 4 clk 2 clk 3 shp 3 shp 480 s 478 s 479 s 480 s 1 s 2 s 3 s 4
datasheet s14634ej1v0ds 8 pd16781 6.3 3-phase sequential sampling, left shift clk 1 sthl shp 2 shp 478 shp 479 shp 1 123 160 4 clk 2 clk 3 shp 3 shp 480 s 1 s 2 s 3 shp 477 s 478 s 479 s 480 s 477
datasheet s14634ej1v0ds 9 pd16781 7. electrical specifications absolute maximum ratings (t a = +25 c, v ss1 =v ss2 = 0 v) parameter symbol rating unit logic part supply voltage v dd1 0.3 to +7.0 v driver part supply voltage v dd2 0.3 to +7.0 v input voltage v i 0.3 to v dd1/2 + 0.3 v output voltage v o 0.3 to v dd1/2 + 0.3 v operating ambient temperature t a 30 to +85 c storage temperature t stg 55 to +125 c caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. recommended operating range (t a = 30 to +85 c, v dd2 v dd1 , v ss1 = v ss2 = 0 v) parameter symbol conditions min. typ. max. unit logic part supply voltage v dd1 3.0 5.5 v driver part supply voltage v dd2 4.5 5.0 5.5 v video input voltage v vi v ss2 + 0.2 v dd2 0.2 v driver part output voltage v o2 v ss2 + 0.2 v dd2 0.2 v clock frequency f clk clk 1 to clk 3 20 mhz output load capacitance c l 1 output 50 pf
datasheet s14634ej1v0ds 10 pd16781 electrical characteristics (t a = ?30 to +85c, v dd1 = 3.0 to 5.5 v, v dd2 = 5.0 v 0.5 v, v dd2 v dd1 , v ss1 = v ss2 = 0 v) parameter symbol conditions min. typ. max. unit low-level driver part output voltage v vol v ss2 + 0.2 v high-level driver part output voltage v voh s 1 to s 480 v dd2 ? 0.2 v high-level input voltage v ih 0.7 v dd1 v dd1 v low-level input voltage v il clk, sthr (l), r,/l, o sel , cx v ss1 0.3 v dd1 v except for mode pin ?1.0 +1.0 a v i = 0 v ?10 +10 a input leak current i il mode pin v i = v dd1 = 5 v 30 300 a high-level output voltage v loh sthr (sthl), i oh = ?1.0 ma 0.85 v dd1 v low-level output voltage v loh sthr (sthl), i ol = +1.0 ma 0.15 v dd1 v v ref1 v dd2 = 5.0 v, v vi = 0.5 v, t a = 25c 0.5 v v ref2 v dd2 = 5.0 v, v vi = 2.5 v, t a = 25c 2.5 v reference voltage v ref3 v dd2 = 5.0 v, v vi = 4.5 v, t a = 25c 4.5 v v vo1 v dd2 = 5.0 v, v vi = 0.5 v, t a = 25c 20 mv v vo2 v dd2 = 5.0 v, v vi = 2.5 v, t a = 25c 20 mv output voltage deviation v vo3 v dd2 = 5.0 v, v vi = 4.5 v, t a = 25c 20 mv logic dynamic current consumption i dd1 v dd1 = 5.0 v, no load note 1.6 5.6 ma driver dynamic current consumption i dd2 v dd2 = 5.0 v, no load note 12.0 16.0 ma note f clk = 15 mhz, f cx = 17 khz.
datasheet s14634ej1v0ds 11 pd16781 switching characteristics (t a = ? 30 to +85 c, v dd1 = 3.0 to 5.5 v, v dd2 = 5.0 v 0.5 v, v dd2 v dd1 , v ss1 = v ss2 = 0 v) parameter symbol conditions min. typ. max. unit t phl1 743ns start pulse delay time t plh1 c l = 20 pf clk sthl (sthr) 743ns t plh2 8 s t plh3 16 s t phl2 8 s driver output delay time t phl3 v dd2 = 5.0 v r l = 2 k c l = 25 pf x 2 16 s c i1 sthr(sthl), t a =25 c1020pf c i2 c 1 to c 3 , t a =25 c4060pf input capacitance c i3 sthr (sthl), c 1 to c 3 excluded input, t a =25 c 715pf timing requirement (t a = ? 30 to +85 c, v dd1 = 3.0 to 5.5 v, v ss1 = 0 v) parameter symbol conditions min. typ. max. unit clock pulse width pw clk clk 1 to clk 3 50 ns clock pulse high period pw clk(h) 15 ns clock pulse low period pw clk(l) 15 ns clk-clk time t cl1-2 16.6 ns t cl2-3 2 pw clk start pulse setup time t setup 7ns start pulse setup time t hold 7ns start pulse-cx time t sth-cx 50 ns cx setup time t cxsetup 1.0 s cx hold time t cxhold 50 ns clk stop period t clkstop refer to 8. swithing characteristics waveform. remark unless otherwise specified, the input level is defined to be v ih = 0.7 v dd1 , v il = 0.3 v dd1 .
datasheet s14634ej1v0ds 12 pd16781 8. switching characteristics waveform (r,/l=h) unless otherwise specified, the input level is defined to be v ih = 0.7 v dd1 , v il = 0.3 v dd1 . 8.1 1-phase simultaneous sampling ? ? ? ? ? v dd1 2 1 0 481 480 479 162 161 160 3 2 1 0 t clkstop : it is possible for the clock among this to stop. v ss1 v dd1 v ss1 v dd1 v ss1 v dd1 v ss1 v dd1 v ss1 v dd1 v ss1 t plh3 t cxsetup invalid invalid t phl1 t plh1 t hold t setup pw clk pw clk(l) pw clk(h) t plh1 t phl1 s 1 to s 3 s 481 to s 483 s 478 to s 480 s 475 to s 477 s 7 to s 9 s 4 to s 6 s 1 to s 3 s 1438 to s 1440 s 1435 to s 1437 t cxhold t plh2 t phl2 target voltage 0.1 v dd1 target voltage 20 mv t phl3 clk1 sthr (1st dr.) c 1 to c 3 sthl (1st dr.) sthl (4th dr.) cx s n (v out ) t sth-cx
datasheet s14634ej1v0ds 13 pd16781 8.2 3-phase sequential sampling
v dd1 2 1 0 481 480 479 162 161 160 3 2 1 0 t clkstop : it is possible for the clock among this to stop. v ss1 v dd1 v ss1 v dd1 v ss1 v dd1 v ss1 v dd1 v ss1 v dd1 v ss1 t plh3 t cxsetup invalid invalid t phl1 t plh1 t hold t cl1-2 t cl2-3 t setup pw clk pw clk(l) pw clk(h) t plh1 t phl1 s 1 s 481 s 478 s 475 s 7 s 4 s 1 s 1438 s 1435 t cxhold t plh2 t phl2 target voltage 0.1 v dd1 target voltage 20 mv t phl3 clk 1 sthr (1st dr.) c 1 sthl (1st dr.) sthl (4th dr.) cx t sth-cx v dd1 2 1 0 481 480 479 162 161 160 3 2 1 0 v ss1 clk 2 v dd1 1 0 481 162 161 2 1 v ss1 clk 3 v dd1 v ss1 invalid invalid s 2 s 482 s 5 s 2 c 2 v dd1 v ss1 invalid invalid s 3 s 483 s 480 s 477 s 6 s 3 s 1440 s 1437 c 3 s 1436 s 1439 s 479 s 476 0 160 479 480 s n (v out )
datasheet s14634ej1v0ds 14 pd16781 9. recommended mounting conditions the following conditions must be met for mounting conditions of the pd16781. for more details, refer to the semiconductor device mounting technology manual (c10535e). please consult with our sales offices in case other mounting process is used, or in case the mounting is done under different conditions. pd16781n- xxx: tcp (tab pack age) mounting condition mounting method condition soldering heating tool 300 to 350 c, heating for 2 to 3 sec, pressure 100g (per solder). thermocompression acf (adhesive conductive film) temporaly bonding 70 to 100 c, pressure 3 to 8 kg/cm 2 , time 3 to 5 sec. real bonding 165 to 180 c, pressure 25 to 45 kg/cm 2 , time 30 to 40 sec (when using the anisotropy conductive film sumizac1003 of sumitomo bakelite, ltd). caution to find out the detailed conditions for mounting the acf part, please contact the acf manufacturing company. be sure to avoid using two or more mounting methods at a time.
datasheet s14634ej1v0ds 15 pd16781 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
pd16781 reference documents nec semiconductor device reliability/quality control system (c10983e) quality grades on nec semiconductor devices (c11531e) m8e 00. 4 the information in this document is current as of february, 2002. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec's data sheets or data books, etc., for the most up-to-date specifications of nec semiconductor products. not all products and/or types are available in every country. please check with an nec sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without prior written consent of nec. nec assumes no responsibility for any errors that may appear in this document. nec does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec semiconductor products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. nec assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec endeavours to enhance the quality, reliability and safety of nec semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. nec semiconductor products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. the recommended applications of a semiconductor product depend on its quality grade, as indicated below. customers must check the quality grade of each semiconductor product before using it in a particular application. "standard": computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "special": transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "specific": aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. the quality grade of nec semiconductor products is "standard" unless otherwise expressly specified in nec's data sheets or data books, etc. if customers wish to use nec semiconductor products in applications not intended by nec, they must contact an nec sales representative in advance to determine nec's willingness to support a given application. (note) (1) "nec" as used in this statement means nec corporation and also includes its majority-owned subsidiaries. (2) "nec semiconductor products" means any semiconductor product developed or manufactured by or for nec (as defined above).

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