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usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 revision: v1.20 date: ? e ??? a ?? 1 ?? 201 ? ? e ??? a ?? 1 ?? 201 ?
rev. 1.20 2 ? e ??? a ?? 1 ?? 201 ? rev. 1.20 3 ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu tal cs fas 7 cpu ? eat ?? es .............................................................................................................................. ? pe ? iphe ? al ? eat ?? es ...................................................................................................................... ? gene?al desc?iption ............................................................................................. 8 selection ta?le ..................................................................................................... 9 block diag?am ...................................................................................................... 9 pin assignment ........... ....................................................................................... 10 pin desc?iption .......... ........................................................................................ 1? a?sol?te maxim?m ratings .............................................................................. 29 d.c. cha?acte?istics ........................................................................................... 29 a.c. cha?acte?istics ........................................................................................... 32 a/d conve?te? elect?ical cha?acte?istics ........... .............................................. 33 lvr/lvd elect?ical cha?acte?istics .................................................................. 34 compa?ato? elect?ical cha?acte?istics ............................................................ 35 usb elect?ical cha?acte?istics .......... ............................................................... 3? constant c???ent led d?ive? elect?ical cha?acte?istics ........... ..................... 3? powe?-on reset cha?acte?istics ........... ............................................................ 3? s?stem a?chitect??e .......................................................................................... 3? clocking and pipelining .............................................................................................................. 3 ? p ? og ? am co ? nte ? ........................................................................................................................ 38 stack .......................................................................................................................................... 39 a ? ithmetic and logic unit C alu ................................................................................................ 39 ?lash p?og?am memo?? ..................................................................................... 40 st ?? ct ?? e ..................................................................................................................................... 40 special vecto ? s .......................................................................................................................... 41 look- ? p ta ? le ............. ................................................................................................................ 41 ta ? le p ? og ? am example ............................................................................................................. 42 in ci ? c ? it p ? og ? amming C icp .................................................................................................... 43 on-chip de ?? g s ? ppo ? t C ocds .............................................................................................. 43 in application p ? og ? amming C iap ............................................................................................. 44 in s ? stem p ? og ? amming C isp ................................................................................................... ? 1 data memo?? ...................................................................................................... ?2 st ?? ct ?? e ..................................................................................................................................... ? 2 data memo ?? add ? essing ........................................................................................................... ? 3 gene ? al p ?? pose data memo ?? ................................................................................................. ? 3 special p ?? pose data memo ?? .................................................................................................. ? 3 special ??nction registe? desc?iption ............................................................ ?? indi ? ect add ? essing registe ? s C iar0 ? iar1 ? iar2 .................................................................... ??
rev. 1.20 2 ?e???a?? 1?? 201? rev. 1.20 3 ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu memo ?? pointe ? s C mp0 ? mp1l ? mp1h ? mp2l ? mp2h .............................................................. ?? p ? og ? am memo ?? bank pointe ? C pbp ............. .......................................................................... ? 8 acc ? m ? lato ? C acc .................................................................................................................... ? 9 p ? og ? am co ? nte ? low registe ? C pcl ....................................................................................... ? 9 look- ? p ta ? le registe ? s C tblp ? tbhp ? tblh .......................................................................... ? 9 stat ? s registe ? C status ......................................................................................................... ? 0 eeprom data memo?? ........... ........................................................................... ?1 eeprom data memo ?? st ?? ct ?? e ............................................................................................. ? 1 eeprom registe ? s ............ ....................................................................................................... ? 1 reading data f ? om the eeprom .............................................................................................. ? 3 w ? iting data to the eeprom ..................................................................................................... ? 3 w ? ite p ? otection .......................................................................................................................... ? 3 eeprom inte ??? pt ............. ........................................................................................................ ? 3 p ? og ? amming conside ? ations ............. ........................................................................................ ? 4 oscillato?s .......... ................................................................................................ ?5 oscillato ? ove ? view ............. ....................................................................................................... ? 5 system clock confgurations ..................................................................................................... ? 5 inte ? nal pll ?? eq ? enc ? gene ? ato ? ............................................................................................. ?? exte ? nal c ?? stal/ce ? amic oscillato ? C hxt ................................................................................ ?? inte ? nal high speed rc oscillato ? C hirc ................................................................................ ? 8 inte ? nal 32khz oscillato ? C lirc ................................................................................................ ? 8 ope?ating modes and s?stem clocks ............................................................. ?9 s ? stem clocks ........................................................................................................................... ? 9 s ? stem ope ? ation modes ........................................................................................................... 80 cont ? ol registe ? s ....................................................................................................................... 81 ope ? ating mode switching ......................................................................................................... 84 stand ?? c ??? ent conside ? ations ................................................................................................ 88 wake- ? p ..................................................................................................................................... 88 watchdog time? ........... ...................................................................................... 89 watchdog time ? clock so ?? ce ................................................................................................... 89 watchdog time ? cont ? ol registe ? ............. ................................................................................. 89 watchdog time ? ope ? ation ........................................................................................................ 90 reset and initialisation ...................................................................................... 91 reset ?? nctions ............. ............................................................................................................ 91 reset initial conditions .............................................................................................................. 94 inp?t/o?tp?t po?ts ........................................................................................... 104 p ? ll-high resisto ? s ................................................................................................................... 10 ? i/o po ? t wake- ? p ...................................................................................................................... 10 ? po ? t a wake- ? p pola ? it ? cont ? ol registe ? ................................................................................ 10 ? i/o po ? t cont ? ol registe ? s ........................................................................................................ 109 po ? t a powe ? so ?? ce cont ? ol registe ? ............. ........................................................................ 109 i/o po ? t o ? tp ? t slew rate cont ? ol registe ? s ........................................................................... 109 i/o po ? t o ? tp ? t c ??? ent cont ? ol registe ? s ............................................................................... 114
rev. 1.20 4 ? e ??? a ?? 1 ?? 201 ? rev. 1.20 5 ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu pin-sha ? ed ?? nctions ............. .................................................................................................. 11 ? i/o pin st ?? ct ?? es ..................................................................................................................... 12 ? p ? og ? amming conside ? ations ............. ...................................................................................... 12 ? time? mod?les C tm .......... .............................................................................. 12? int ? od ? ction .............................................................................................................................. 12 ? tm ope ? ation ............. .............................................................................................................. 12 ? tm clock so ?? ce ............. ......................................................................................................... 12 ? tm inte ??? pts ............................................................................................................................ 128 tm exte ? nal pins ...................................................................................................................... 128 tm inp ? t/o ? tp ? t pin selection ................................................................................................. 128 p ? og ? amming conside ? ations ............. ...................................................................................... 129 standa?d t?pe tm C stm .......... ...................................................................... 130 standa ? d tm ope ? ation ............. ............................................................................................... 130 standa ? d t ? pe tm registe ? desc ? iption .................................................................................. 130 standa ? d t ? pe tm ope ? ation modes ....................................................................................... 135 pe?iodic t?pe tm C ptm .................................................................................. 145 pe ? iodic tm ope ? ation ............. ............................................................................................... 145 pe ? iodic t ? pe tm registe ? desc ? iption ................................................................................... 145 pe ? iodic t ? pe tm ope ? ating modes ........................................................................................ 150 analog to digital conve?te? .......... .................................................................. 159 a/d conve ? te ? ove ? view .......................................................................................................... 159 a/d conve ? te ? registe ? desc ? iption ......................................................................................... 1 ? 0 a/d conve ? te ? ope ? ation ......................................................................................................... 1 ? 3 a/d conve ? te ? refe ? ence voltage ............................................................................................ 1 ? 4 a/d conve ? te ? inp ? t signals ..................................................................................................... 1 ? 4 conve ? sion rate and timing diag ? am ..................................................................................... 1 ? 5 s ? mma ?? of a/d conve ? sion steps ............. ............................................................................. 1 ?? p ? og ? amming conside ? ations ............. ...................................................................................... 1 ?? a/d conve ? sion ?? nction ............. ............................................................................................ 1 ?? a/d conve ? sion p ? og ? amming examples ............. .................................................................... 1 ? 8 compa?ato?s .................................................................................................... 1?9 compa ? ato ? ope ? ation ............................................................................................................. 1 ? 9 compa ? ato ? registe ? s .............................................................................................................. 1 ? 0 compa ? ato ? inte ??? pt ................................................................................................................ 1 ? 1 p ? og ? amming conside ? ations ............. ...................................................................................... 1 ? 1 se?ial inte?face mod?le C sim ......................................................................... 1?1 spi inte ? face ............................................................................................................................ 1 ? 1 i 2 c inte ? face ............ ................................................................................................................. 180 se?ial pe?iphe?al inte?face C spia .................................................................. 189 spia inte ? face ope ? ation ......................................................................................................... 189 spia registe ? s ......................................................................................................................... 190 spia comm ? nication ............................................................................................................... 193 spia b ? s ena ? le/disa ? le ......................................................................................................... 195
rev. 1.20 4 ?e???a?? 1?? 201? rev. 1.20 5 ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu spia ope ? ation ........................................................................................................................ 195 e ?? o ? detection ......................................................................................................................... 19 ? uart inte?face ................................................................................................. 19? uart exte ? nal pins ............. .................................................................................................... 198 uart data t ? ansfe ? scheme ................................................................................................... 198 uart stat ? s and cont ? ol registe ? s ......................................................................................... 198 ba ? d rate gene ? ato ? ............................................................................................................... 204 uart set ? p and cont ? ol .......................................................................................................... 205 uart t ? ansmitte ? ..................................................................................................................... 20 ? uart receive ? ............. ........................................................................................................... 20 ? managing receive ? e ?? o ? s ....................................................................................................... 209 uart inte ??? pt st ?? ct ?? e .......................................................................................................... 209 uart powe ? down and wake- ? p ............................................................................................ 211 low voltage detecto? C lvd .......... ................................................................. 212 lvd registe ? ............. ............................................................................................................... 212 lvd ope ? ation .......................................................................................................................... 213 usb inte?face ................................................................................................... 214 powe ? plane ............................................................................................................................. 214 usb inte ? face ope ? ation ............. ............................................................................................. 214 usb inte ? face registe ? s ............. .............................................................................................. 215 usb inte ??? pts ............. ............................................................................................................. 22 ? pwm fo? rgb led ........................................................................................... 22? pwm registe ? s ........................................................................................................................ 228 led pwm mod ? les .................................................................................................................. 239 led com o ? tp ? t unit ............. ................................................................................................. 240 led ram & registe ? t ? ansfe ? unit .......................................................................................... 240 led inte ??? pt ............................................................................................................................ 242 led pwm timing ? wavefo ? m and ? low cha ? t ......................................................................... 242 constant c???ent led d?ive? .......................................................................... 244 inte???pts .......................................................................................................... 245 inte ??? pt registe ? s .................................................................................................................... 245 inte ??? pt ope ? ation ................................................................................................................... 252 exte ? nal inte ??? pts .................................................................................................................... 254 usb inte ??? pt ........................................................................................................................... 254 compa ? ato ? inte ??? pts .............................................................................................................. 254 sim inte ??? pt ............................................................................................................................ 254 spia inte ??? pt ........................................................................................................................... 255 time base inte ??? pts ................................................................................................................ 255 m ? lti-f ? nction inte ??? pts ............. ............................................................................................... 25 ? led ?? ame inte ??? pt ................................................................................................................ 25 ? led up/down inte ??? pt ............................................................................................................ 25 ? a/d conve ? te ? inte ??? pt ............................................................................................................ 25 ? uart inte ??? pt ............. ............................................................................................................ 258
rev. 1.20 ? ? e ??? a ?? 1 ?? 201 ? rev. 1.20 ? ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu eeprom inte ??? pt ............. ...................................................................................................... 258 lvd inte ??? pt ............................................................................................................................ 258 tm inte ??? pts ............................................................................................................................ 258 inte ??? pt wake- ? p ?? nction ...................................................................................................... 259 p ? og ? amming conside ? ations ............. ...................................................................................... 259 confguration options int ? od ? ction .............................................................................................................................. 2 ? 1 inst ?? ction timing ..................................................................................................................... 2 ? 1 moving and t ? ansfe ?? ing data .................................................................................................. 2 ? 1 a ? ithmetic ope ? ations ............................................................................................................... 2 ? 1 logical and rotate ope ? ation .................................................................................................. 2 ? 2 b ? anches and cont ? ol t ? ansfe ? ................................................................................................ 2 ? 2 bit ope ? ations .......................................................................................................................... 2 ? 2 ta ? le read ope ? ations ............................................................................................................ 2 ? 2 othe ? ope ? ations ............. ......................................................................................................... 2 ? 2 inst??ction set s?mma?? .......... ...................................................................... 2?3 ta ? le conventions .................................................................................................................... 2 ? 3 extended inst ?? ction set ............. ............................................................................................. 2 ? 5 instruction defnition extended instruction defnition ................................................................................................ 2 ?? package info?mation ....................................................................................... 283 48-pin lq ? p ( ? mm ? mm) o ? tline dimensions ..................................................................... 284 ? 4-pin lq ? p ( ? mm ? mm) o ? tline dimensions ..................................................................... 285 80-pin lq ? p (10mm 10mm) o ? tline dimensions ................................................................. 28 ? 128-pin lq ? p (14mm 14mm) o ? tline dimensions (exposed pad) ...................................... 28 ?
rev. 1.20 ? ?e???a?? 1?? 201? rev. 1.20 ? ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu fas cu fas ? operating voltage v dd (mcu): C f sys =6mhz: 2.2v~5.5v C f sys =12mhz: 2.7v~5.5v C f sys =16mhz: 3.3v~5.5v v dd (usb mode): C f sys =6mhz/12mhz/16mhz : 3.3v~5.5v ? up to 0.25s instruction cycle with 16mhz system clock at v dd =5v ? power down and wake-up functions to reduce power consumption ? oscillator types external high speed crystal C hxt internal high speed rc C hirc internal low speed 32khz rc C lirc ? multi-mode operation: normal, slow, idle and sleep ? fully integrated internal 12mhz oscillator requires no external components ? all instructions executed in 1~3 instruction cycles ? table read instructions ? 115 powerful instructions ? 12-level subroutine nesting ? bit manipulation instruction ? flash program memory: 8k16~32k16 ? data memory: 10248 ? led control memory: 5128~10248 ? true eeprom memory: 2568 ? watchdog t imer function ? up to 52 bidirectional i/o lines ? dual pin-shared external interrupts ? multiple t imer modules for time measurement, input capture, compare match output or pwm output or single pulse output function 1 standard type 16-bit t imer module C stm 3 periodic type 10-bit t imer modules C ptm0~ptm2 ? up to 48-pin 6-bit pwm outputs for rgb led application ? usb interface usb 2.0 full speed compatible 8 endpoints supported including endpoint 0 all endpoints except endpoint 0 can support interrupt and bulk transfer all endpoints except endpoint 0 can be confgured as 8, 16, 32, 64 bytes fifo size endpoint 0 support control transfer
rev. 1.20 8 ? e ??? a ?? 1 ?? 201 ? rev. 1.20 9 ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu endpoint 0 has 8 byte fifo support 3.3v ldo and internal udp 1.5k pull-up resistor internal 12mhz rc oscillator with 0.25% accuracy for all usb modes ? serial interface module C sim for spi or i 2 ? single serial peripheral interface C spia ? fully-duplex universal asynchronous receiver and t ransmitter interface C uart ? dual comparator functions ? dual t ime-base functions for generation of fxed time interrupt signals ? multi-channel 12-bit resolution a/d converter ? low voltage reset function ? low voltage detect function ? in application programming function C iap ? in system programing function C isp ? flash program memory can be re-programmed up to 100,000 times ? flash program memory data retention > 10 years ? true eeprom data memory can be re-programmed up to 1,000,000 times ? true eeprom data memory data retention > 10 years ? package types: 48/64/80-pin lqfp, 128-pin lqfp-ep general description these d evices a re fl ash me mory t ype 8 -bit h igh p erformance r isc a rchitecture m icrocontrollers with a usb i nterface a nd i ntegrated r gb c ontrol fu nctions. spe cifcally de signed fo r a pplications that inter face directly to analog signals, require a usb interface and also are required to drvie rgb leds, they of fer users the convenience of flash memory multi-programming features. the devices also inclu de a wide range of other useful functions and features. other memory includes an area of ram data memory as well as an area of true eeprom memory for storage of non-volatile data such as serial numbers, calibration data etc. analog features include a multi-channel 12-bit a/d converter and two comparators. multiple and extremely fexible t imer modules provide timing, pulse generation and pwm generation functions. there are multiple 6-bit pwm outputs specially provided for multiple rgb led applications. communication with the outside world is catered for by including fully integrated spi, i 2 c, uar t and usb interface functions, four popular interfaces which provide designers with a means of easy communication with external peripheral hardware. protective features such as an internal w atchdog timer, low v oltage reset and low v oltage detector coupled with excellent noise immunity and esd protection ensure that reliable operation is maintained in hostile electrical environments. the external interrupt can be triggered with falling edges or both falling and rising edges. a full choice of external, internal high and low oscillators is provided including two fully integrated system oscillators which require no external components for their implementation. the ability to operate a nd swi tch d ynamically b etween a r ange o f o perating m odes u sing d ifferent c lock so urces gives users the ability to optimise microcontroller operation and minimise power consumption. the inclusion of fexible i/o programming features along with many other features ensure that the devices w ill f nd s pecifc excellent us e in a w ide range of application pos sibilities s uch as s ensor signal processing, motor driving, industrial control, consumer products, subsystem controllers, etc.
rev. 1.20 8 ?e???a?? 1?? 201? rev. 1.20 9 ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu these devices are fully supported by the holtek range of fully functional development and programming tools, providing a means for fast and effcient product development cycles. most features are common to all devices and the main features distinguishing them are memory capacity, i/o count, a/d converter channel, pwm count for external rgb leds and package type. the following table summarises the main features of each device. ht ??? b5 ? 2 2.2v~5.5v 8k1 ? 10248 5128 25 ? 8 34 15 40 12- ? it8 ht ??? b5 ? 4 1 ? k1 ? 5128 38 24 ? 4 12- ? it12 ht ??? b5 ?? 32k1 ? 10248 52 48 128 12- ? it1 ? pa?t no. time? mod?les compa?ato? exte?nal inte???pts sim spia time base uart usb stacks package ht ??? b5 ? 2 1 ? - ? it stm1 10- ? it ptm3 2 2 2 12 48/ ? 4lq ? p ht ??? b5 ? 4 48/ ? 4/80lq ? p ht ??? b5 ?? 80lq ? p 128lq ? p-ep block diag?am 8-?it risc mcu co?e ?lash/eeprom p?og?amming ci?c?it?? usb 2.0 ??ll speed engine usb 2.0 xcvr 3.3v ldo ram data memo?? led data memo?? eeprom data memo?? ?lash p?og?am memo?? time bases time? mod?les i/o spia sim (spi/i 2 c) uart low voltage reset watchdog time? low voltage detect reset ci?c?it inte???pt cont?olle? inte?nal hirc/lirc oscillato?s exte?nal hxt oscillato? compa?ato?s 12-?it a/d conve?te? rgb led pwm
rev. 1.20 10 ? e ??? a ?? 1 ?? 201 ? rev. 1.20 11 ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ss pd0/ptp2/ptp2i/osc1 pa5/ptp0/ptp0i/c1+ ht???b5?2/ht??vb5?2 48 lq?p-a rext ledvss cco3 cco4 cco5 cco? cco? cco8 cco9 cco10 cco11 ccvdd ccvss ledvss udn/od0/icpda udp/od1 v33o avss/vss avdd/vdd pg?/com? pg?/com? pg5/com5 pg4/com4 pa?/int0 pa3/scka/c0- pa2/sdia/c0+ pa1/sdoa/c0x pa0/ptck0/ocdsda pg0/com0/an? pg1/com1 pg2/com2 pg3/com3 pe3/vr pb0/sdo/sda/an0 pe0/vddio/vre? cco12 ubus cco13 cco14 pc5/rx/an? pc4/tx/an5 pb1/sdi/scl/an1 pe2/vre?i pa?/stck/c1- res/icpck/ocdsck 1 2 3 4 5 ? ? 8 9 10 11 12 13 14 15 1? 1? 18 19 20 21 22 23 24 25 2? 2? 28 29 30 31 32 33 34 35 3? 45 4?4?48 3?38394041424344 pa4/scsa/stp/stpi/c1x pd0/ptp2_1/ptp2i_1/osc1 ht???b5?4/ht??vb5?4 48 lq?p-a rext ledvss cco? cco? cco8 cco9 cco10 cco11 cco12 cco13 cco14 ccvdd ccvss ledvss udn/od0/icpda udp/od1 v33o avss/vss avdd/vdd pg?/com? pg?/com? pg5/com5 pg4/com4 pa?/int0 pa0/ptck0/ocdsda pg0/com0/an? pg1/com1 pg2/com2 pg3/com3 pe3/vr pb0/sdo/sda/an0 pe0/vddio/vre? cco15 ubus cco1? cco1? pc5/rx/an? pc4/tx/an5 pb1/sdi/scl/an1 pe2/vre?i res/icpck/ocdsck 1 2 3 4 5 ? ? 8 9 10 11 12 13 14 15 1? 1? 18 19 20 21 22 23 24 25 2? 2? 28 29 30 31 32 33 34 35 3? 45 4?4?48 3?38394041424344 pa3/spisck/cmp0inn pa2/spisdi/cmp0inp pa1/spisdo/cmp0o pa5/ptp0_0/ptp0i_0/cmp1inp pa4/spiscs/stp0_0/stp0i_0/cmp1o pa?/stck0//cmp1inn
rev. 1.20 10 ?e???a?? 1?? 201? rev. 1.20 11 ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66b572 64 lf 1 2 3 4 5 ? ? 8 9 10 11 12 13 20 21 22 23 24 25 2? 2? 28 ?0 ?1?2 ?3?4 29 30 31 32 5253 54 555?5?58 59 14 15 1? 43 44 45 4? 4? 48 3? 3? 38 39 40 41 42 33 34 35 1? 18 19 5253 54 udn/od0/icpda udp/od1 v33o avss/vss pe3/vr pe2/vre?i pb0/sdo/sda/an0 pb1/sdi/scl/an1 pb2/sck/an2 pb4/stp/stpi/an4 avdd/vdd pc5/rx/an? rext ccvdd cco? cco0 cco5 cco? cco8 pg1/com1 pg2/com2 ledvss cco1 cco2 cco3 cco4 pg?/com? pg5/com5 cco9 cco10 cco11 cco12 cco13 ledvss pg4/com4 vdd vss pd5/ptp0/ptp0i pd0/ptp2/ptp2i/osc1 pd1/ptp1/ptp1i/osc2 pe0/vddio/vre? pa?/int0 pa?/stck/c1- pa5/ptp0/ptp0i/c1+ pa4/scsa/stp0/stp0i/c1x pa3/scka/c0- pa2/sdia/c0+ pa1/sdoa/c0x pa0/ptck0/ocdsda pe1/ptck2 pg0/com0/an? pg?/com? pd?/ptp2/ptp2i pd2/ptck1 ccvss cco14 pg3/com3 ubus pc4/tx/an5 pd?/ptp1/ptp1i pc3/int1 ledvss pb3/scs/an3 res/icpc k/ocdsck
rev. 1.20 12 ? e ??? a ?? 1 ?? 201 ? rev. 1.20 13 ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb574/ht66b574 64 lf 1 2 3 4 5 ? ? 8 9 10 11 12 13 20 21 22 23 24 25 2? 2? 28 ?0?1 ?2?3 ?4 29 30 31 32 5253 5455 5?5?5859 14 15 1? 43 44 45 4? 4? 48 3? 3? 38 39 40 41 42 33 34 35 1? 18 19 52 5354 udn/od0/icpda udp/od1 v33o avss/vss pe3/vr pe2/vre?i pb0/sdo/sda/an0 pb1/sdi/scl/an1 pb2/sck/an2 pb4/stp/stpi/an4 avdd/vdd pc5/rx/an? rext ccvdd cco10 cco3 cco8 cco9 cco11 pg1/com1 pg2/com2 ledvss cco4 cco5 cco? cco? pg?/com? pg5/com5 cco12 cco13 cco14 cco15 cco1? ledvss pg4/com4 vdd vss pd5/ptp0/ptp0i pd0/ptp2/ptp2i/osc1 pd1/ptp1/ptp1i/osc2 pe0/vddio/vre? pa?/int0 pa?/stck/c1- pa5/ptp0/ptp0i/c1+ pa3/scka/c0- pa2/sdia/c0+ pa1/sdoa/c0x pa0/ptck0/ocdsda pe1/ptck2 pg0/com0/an11 pg?/com? pd?/ptp2/ptp2i pd2/ptck1 ccvss cco1? pg3/com3 ubus pc4/tx/an? pd?/ptp1/ptp1i pc3/int1 ledvss pb3/scs/an3 res/icpck/ocdsck pa4/scsa/stp0/stp0i/c1x
rev. 1.20 12 ?e???a?? 1?? 201? rev. 1.20 13 ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu 4? 4? 45 44 43 42 41 1 2 3 4 5 ? ? 8 9 10 11 12 13 14 15 1? 1? 18 19 20 21 22 23 24 25 2? 2? 28 29 30 31 32 33 34 35 3? 3?38 39 40 80 ?9 ?8 ?? ?? ?5 ?4 ?3 ?2 ?1 ?0 ?9 ?8 ?? ?? ?5 ?4?3 ?2 ?1 ?0 59 58 5? 5? 55 54 53 52 51 40 49 48 ht???b5?4/ht??vb5?4 80 lq?p-a pg?/com? pg?/com? udp/od1 v33o avss/vss pe3/vr pe2/vre?i pb1/sdi/scl/an1 ubus rext cco0 cco1 cco2 cco3 cco10 cco11 cco12 cco13 cco14 cco1? cco1? cco18 cco19 cco20 ledvss ccvdd ccvss cco21 pg0/com0/an11 pg1/com1 pg2/com2 pg3/com3 pc5/rx/an? pc?/an8 pd4/an10 ledvss avdd/vdd cco? cco8 cco9 ledvss ledvss vdd vss vdd vss cco4 cco5 cco? cco15 cco22 cco23 pb2/sck/an2 pg5/com5 pg4/com4 udn/od0/icpda pb0/sdo/sda//an0 pd?/ptp1/ptp1i pd?/ptp2/ptp2i pd5/ptp0/ptp0i pd2/ptck1 pd0/ptp2/ptp2i/osc1 pd1/ptp1/ptp1i/osc2 pe0/vddio/vre? pa?/int0 pa?/stck/c1- pa5/ptp0/ptp0i/c1+ pa3/scka/c0- pa2/sdia/c0+ pa1/sdoa/c0x pa0/ptck0/ocdsda pe1/ptck2 pc3/int1 pd3/an9 pc4/tx/an? pb?/an5 res/icpck/ocdsck pb4/stp/stpi/an4 pb3/scs/an3 pa4/scsa/stp/stpi/c1x
rev. 1.20 14 ? e ??? a ?? 1 ?? 201 ? rev. 1.20 15 ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu 4? 4? 45 44 43 42 41 1 2 3 4 5 ? ? 8 9 10 11 12 13 14 15 1? 1? 18 19 20 21 22 23 24 25 2? 2? 28 29 30 31 32 33 34 35 3? 3?38 39 40 80 ?9 ?8 ?? ?? ?5 ?4 ?3 ?2 ?1 ?0 ?9 ?8 ?? ?? ?5 ?4?3 ?2 ?1 ?0 59 58 5? 5? 55 54 53 52 51 40 49 48 ht???b5??/ht??vb5?? 80 lq?p-a pg?/com? pg?/com? udp/od1 v33o avss/vss pe3/vr pe2/vre?i pb4/stp/stpi/an4 ubus rext cco9 cco10 cco11 cco15 cco22 cco23 cco24 cco25 cco2? cco28 cco29 cco42 cco43 cco44 ledvss ccvdd ccvss cco45 pg0/com0 pg1/com1 pg2/com2 pg3/com3 pc4/tx/an12 pc5/rx/an13 pd4/ptck2 ledvss avdd/vdd cco19 cco20 cco21 ledvss ledvss vdd vss pb?/int1/an? vdd vss cco1? cco1? cco18 cco2? cco4? cco4? pc?/an15 pb5/an5 pb?/an? pc0/an8 pc1/an9 pg5/com5 pg4/com4 udn/od0/icpda res/icpck/ocdsck pb3/scs/an3 pd?/ptp1/ptp1i pd?/ptp2/ptp2i pd5/ptp0/ptp0i pd2/ptck1 pd0/ptp2/ptp2i/osc1 pd1/ptp1/ptp1i/osc2 pe0/vddio/vre? pa?/int0 pa?/stck/c1- pa5/ptp0/ptp0i/c1+ pa3/scka/c0- pa2/sdia/c0+ pa1/sdoa/c0x pa0/ptck0/ocdsda pe1 pd3 pa4/scsa/stp/stpi/c1x
rev. 1.20 14 ?e???a?? 1?? 201? rev. 1.20 15 ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu HT66FB576/ht66b576 2 lfe cco4? vss vdd pg?/com? pg?/com? pg5/com5 pg4/com4 p?? p?? p?5 p?4 p?3 p?2 p?1 p?0 pd?/ptp1/ptp1i pd?/ptp2/ptp2i pd5/ptp0/ptp0i pe1 pd3 pd2/ptck1 pd0/ptp2/ptp2i/osc1 pd1/ptp1/ptp1i/osc2 pe0/vddio/vre? pa?/int0 pa?/stck/c1- pa5/ptp0/ptp0i/c1+ pa4/scsa/stp/stpi/c1x pa3/scka/c0- pa2/sdia/c0+ pa1/sdoa/c0x pa0/ptck0/ocdsda ccvss rext ccvdd cco24 cco25 cco2? cco2? nc ledvss cco28 cco29 cco30 cco31 cco32 cco33 cco34 cco35 ledvss cco3? cco3? cco38 cco39 cco40 cco41 cco42 cco43 ledvss nc nc cco44 cco45 cco4? udn/od0/icpda udp/od1 v33o ubus vdd avdd vss avss pe3/vr pe2/vre?i pb0/sdo/sda/an0 pb1/sdi/scl/an1 pb2/sck/an2 res/icpck/ocdsck pb3/scs/an3 pb4/stp/stpi/an4 pb5/an5 pb?/int1/an? pb?/an? pc0/an8 pc1/an9 pc2/an10 pc3/an11 pc4/tx/an12 pc5/rx/an13 pc?/an14 pc?/an15 pd4/ptck2 pg0/com0 pg1/com1 pg2/com2 pg3/com3 vdd vss cco0 cco1 cco2 cco3 nc ledvss cco4 cco5 cco? cco? cco8 cco9 cco10 cco11 ledvss cco12 cco13 cco14 cco15 cco1? cco1? cco18 cco19 ledvss nc nc cco20 cco21 cco22 cco23 1 2 3 4 5 ? ? 8 9 10 11 12 13 14 15 1? 1? 18 19 20 21 22 23 24 25 2? 2? 28 29 30 31 32 3334353?3?38394041424344454?4?48495051525354555?5?5859?0?1?2?3?4 ?5 ?? ?? ?8 ?9 ?0 ?1 ?2 ?3 ?4 ?5 ?? ?? ?8 ?9 80 81 82 83 84 85 8? 8? 88 89 90 91 92 93 94 95 9? 9? 98 99 10010110210310410510?10?10810911011111211311411511?11?11811912012112212312412512?12?128 note: 1. if the pin-shared pin functi ons have multiple outputs, the desired pin-shared function is determined by the corresponding software control bits. 2. the ocdsda and ocdsck pins are supplied for the ocds dedic ated pins and as such only available for the ht66vb572/ht66vb574/ht66vb576 devices which are the ocds ev chips for the ht66fb572/ht66fb574/HT66FB576 devices.
rev. 1.20 1 ? ? e ??? a ?? 1 ?? 201 ? rev. 1.20 1? ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ds the pins on the devices can be referenced by its port name, e.g. p a0, p a1 etc., which refer to the digital i/o functio n of the pins. however these port pins are also shared with other functions such as the analog to digital converter , serial port pins etc. the function of each pin is listed in the following table, however the details behind how each pin is confgured is contained in other sections of the datasheet. as the pin description table shows the situation for the package with the most pins, not all pins in the table will be available on smaller package sizes. pa0/ptck0/ ocdsda pa0 papu pawueg0 st cmos gene ? al p ?? pose i/o. registe ? ena ? led p ? ll- ? p and wake- ? p ptck0 st ptm0 clock inp ? t ocdsda st cmos ocds data/add ? ess pin ? fo ? ev chip onl ? . pa1/sdoa/c0x pa1 papu pawueg0 pas0 st cmos gene ? al p ?? pose i/o. registe ? ena ? led p ? ll- ? p and wake- ? p sdoa pas0 cmos spia se ? ial data o ? tp ? t c0x pas0 cmos compa ? ato ? 0 o ? tp ? t pa2/sdia/c0+ pa2 papu pawueg0 pas0 st cmos gene ? al p ?? pose i/o. registe ? ena ? led p ? ll- ? p and wake- ? p sdia pas0 st spia se ? ial data inp ? t c0+ pas0 an compa ? ato ? 0 positive inp ? t pa3/scka/c0- pa3 papu pawueg0 pas0 st cmos gene ? al p ?? pose i/o. registe ? ena ? led p ? ll- ? p and wake- ? p scka pas0 st cmos spia se ? ial clock c0- pas0 an compa ? ato ? 0 negative inp ? t pa4/ scsa/stp/ stpi/c1x pa4 papu pawueg1 pas1 st cmos gene ? al p ?? pose i/o. registe ? ena ? led p ? ll- ? p and wake- ? p scsa pas1 st cmos spia slave select stp pas1 cmos stm o ? tp ? t stpi pas1 i ? s st stm capt ?? e inp ? t c1x pas1 cmos compa ? ato ? 1 o ? tp ? t pa5/ptp0/ptp0i/ c1+ pa5 papu pawueg1 pas1 st cmos gene ? al p ?? pose i/o. registe ? ena ? led p ? ll- ? p and wake- ? p ptp0 pas1 cmos ptm0 o ? tp ? t ptp0i pas1 i ? s st ptm0 capt ?? e inp ? t c1+ pas1 an compa ? ato ? 1 positive inp ? t pa ? /stck/c1- pa ? papu pawueg1 pas1 st cmos gene ? al p ?? pose i/o. registe ? ena ? led p ? ll- ? p and wake- ? p stck pas1 st stm clock inp ? t c1- pas1 an compa ? ato ? 1 negative inp ? t
rev. 1.20 1? ?e???a?? 1?? 201? rev. 1.20 1 ? ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu a f t /t /t ds pa ? /int0 pa ? papu pawueg1 st cmos gene ? al p ?? pose i/o. registe ? ena ? led p ? ll- ? p and wake- ? p int0 integ intc0 st exte ? nal inte ??? pt 0 inp ? t pb0/sdo/sda/an0 pb0 pbpu pbwu pbs0 st cmos gene ? al p ?? pose i/o. registe ? ena ? led p ? ll- ? p and wake- ? p sdo pbs0 cmos spi se ? ial data o ? tp ? t sda pbs0 st nmos i 2 c data line an0 pbs0 an a/d conve ? te ? exte ? nal inp ? t 0 pb1/sdi/scl/an1 pb1 pbpu pbwu pbs0 st cmos gene ? al p ?? pose i/o. registe ? ena ? led p ? ll- ? p and wake- ? p sdi pbs0 st spi se ? ial data inp ? t scl pbs0 st nmos i 2 c clock line an1 pbs0 an a/d conve ? te ? exte ? nal inp ? t 1 pb2/sck/an2 pb2 pbpu pbwu pbs0 st cmos gene ? al p ?? pose i/o. registe ? ena ? led p ? ll- ? p and wake- ? p sck pbs0 st cmos spi se ? ial clock an2 pbs0 an a/d conve ? te ? exte ? nal inp ? t 2 pb3/scs/an3 pb3 pbpu pbwu pbs0 st cmos gene ? al p ?? pose i/o. registe ? ena ? led p ? ll- ? p and wake- ? p scs pbs0 st cmos spi slave select an3 pbs0 an a/d conve ? te ? exte ? nal inp ? t 3 pb4/stp/stpi/an4 pb4 pbpu pbwu pbs1 st cmos gene ? al p ?? pose i/o. registe ? ena ? led p ? ll- ? p and wake- ? p stp pbs1 cmos stm o ? tp ? t stpi pbs1 i ? s st stm capt ?? e inp ? t an4 pbs1 an a/d conve ? te ? exte ? nal inp ? t 4 pc3/int1 pc3 pcpu pcwu pcs0 st cmos gene ? al p ?? pose i/o. registe ? ena ? led p ? ll- ? p and wake- ? p int1 integ intc0 st exte ? nal inte ??? pt 1 inp ? t pc4/tx/an5 pc4 pcpu pcwu pcs1 st cmos gene ? al p ?? pose i/o. registe ? ena ? led p ? ll- ? p and wake- ? p tx pcs1 cmos uart tx se ? ial data o ? tp ? t an5 pcs1 an a/d conve ? te ? exte ? nal inp ? t 5 pc5/rx/an ? pc5 pcpu pcwu pcs1 st cmos gene ? al p ?? pose i/o. registe ? ena ? led p ? ll- ? p and wake- ? p rx pcs1 st uart rx se ? ial data inp ? t an ? pcs1 an a/d conve ? te ? exte ? nal inp ? t ?
rev. 1.20 18 ? e ??? a ?? 1 ?? 201 ? rev. 1.20 19 ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu a f t /t /t ds pd0/ptp2/ptp2i/ osc1 pd0 pdpu pdwu pds0 st cmos gene ? al p ?? pose i/o. registe ? ena ? led p ? ll- ? p and wake- ? p ptp2 pds0 cmos ptm2 o ? tp ? t ptp2i pds0 i ? s st ptm2 capt ?? e inp ? t osc1 pds0 hxt hxt oscillato ? pin pd1/ptp1/ptp1i/ osc2 pd1 pdpu pdwu pds0 st cmos gene ? al p ?? pose i/o. registe ? ena ? led p ? ll- ? p and wake- ? p ptp1 pds0 cmos ptm1 o ? tp ? t ptp1i pds0 i ? s st ptm1 capt ?? e inp ? t osc2 pds0 hxt hxt oscillato ? pin pd2/ptck1 pd2 pdpu pdwu st cmos gene ? al p ?? pose i/o. registe ? ena ? led p ? ll- ? p and wake- ? p ptck1 st ptm1 clock inp ? t pd5/ptp0/ptp0i pd5 pdpu pdwu pds1 st cmos gene ? al p ?? pose i/o. registe ? ena ? led p ? ll- ? p and wake- ? p ptp0 pds1 cmos ptm0 o ? tp ? t ptp0i pds1 i ? s st ptm0 capt ?? e inp ? t pd ? /ptp2/ptp2i pd ? pdpu pdwu pds1 st cmos gene ? al p ?? pose i/o. registe ? ena ? led p ? ll- ? p and wake- ? p ptp2 pds1 cmos ptm2 o ? tp ? t ptp2i pds1 i ? s st ptm2 capt ?? e inp ? t pd ? /ptp1/ptp1i pd ? pdpu pdwu pds1 st cmos gene ? al p ?? pose i/o. registe ? ena ? led p ? ll- ? p and wake- ? p ptp1 pds1 cmos ptm1 o ? tp ? t ptp1i pds1 i ? s st ptm1 capt ?? e inp ? t pe0/vddio/vre ? pe0 pepu pewu pes0 st cmos gene ? al p ?? pose i/o. registe ? ena ? led p ? ll- ? p and wake- ? p vddio pes0 pwr pa exte ? nal powe ? inp ? t vre ? pes0 an a/d conve ? te ? exte ? nal ? efe ? ence voltage inp ? t pe1/ptck2 pe1 pepu pewu st cmos gene ? al p ?? pose i/o. registe ? ena ? led p ? ll- ? p and wake- ? p ptck2 st ptm2 clock inp ? t pe2/vre ? i pe2 pepu pewu pes0 st cmos gene ? al p ?? pose i/o. registe ? ena ? led p ? ll- ? p and wake- ? p vre ? i pes0 an a/d conve ? te ? pga inp ? t pe3/vr pe3 pepu pewu pes0 st cmos gene ? al p ?? pose i/o. registe ? ena ? led p ? ll- ? p and wake- ? p vr pes0 an a/d conve ? te ? ? efe ? ence voltage o ? tp ? t
rev. 1.20 18 ?e???a?? 1?? 201? rev. 1.20 19 ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu a f t /t /t ds pg0/com0/an ? pg0 pgpu pgwu pgs0 st cmos gene ? al p ?? pose i/o. registe ? ena ? led p ? ll- ? p and wake- ? p com0 pgs0 an led com0 o ? tp ? t an ? pgs0 an a/d conve ? te ? exte ? nal inp ? t ? pg1/com1 pg1 pgpu pgwu pgs0 st cmos gene ? al p ?? pose i/o. registe ? ena ? led p ? ll- ? p and wake- ? p com1 pgs0 an led com1 o ? tp ? t pg2/com2 pg2 pgpu pgwu pgs0 st cmos gene ? al p ?? pose i/o. registe ? ena ? led p ? ll- ? p and wake- ? p com2 pgs0 an led com2 o ? tp ? t pg3/com3 pg3 pgpu pgwu pgs0 st cmos gene ? al p ?? pose i/o. registe ? ena ? led p ? ll- ? p and wake- ? p com3 pgs0 an led com3 o ? tp ? t pg4/com4 pg4 pgpu pgwu pgs1 st cmos gene ? al p ?? pose i/o. registe ? ena ? led p ? ll- ? p and wake- ? p com4 pgs1 an led com4 o ? tp ? t pg5/com5 pg5 pgpu pgwu pgs1 st cmos gene ? al p ?? pose i/o. registe ? ena ? led p ? ll- ? p and wake- ? p com5 pgs1 an led com5 o ? tp ? t pg ? /com ? pg ? pgpu pgwu pgs1 st cmos gene ? al p ?? pose i/o. registe ? ena ? led p ? ll- ? p and wake- ? p com ? pgs1 an led com ? o ? tp ? t pg ? /com ? pg ? pgpu pgwu pgs1 st cmos gene ? al p ?? pose i/o. registe ? ena ? led p ? ll- ? p and wake- ? p com ? pgs1 an led com ? o ? tp ? t ubus* ubus pwr usb sie powe ? s ? ppl ? v33o v33o pwr usb 3.3v ? eg ? lato ? o ? tp ? t udn/od0/icpda udn st cmos usb udn line od0 st nmos nmos open d ? ain i/o pin icpda st cmos icp add ? ess/data udp/od1 udp st cmos usb udp line od1 st nmos nmos open d ? ain i/o pin res/icpck/ ocdsck res st exte ? nal ? eset inp ? t icpck st icp clock ocdsck st ocds clock pin ? fo ? ev chip onl ? vdd vdd pwr digital positive powe ? s ? ppl ? iovdd pwr i/o positive powe ? s ? ppl ? avdd avdd pwr analog positive powe ? s ? ppl ? ccvdd ccvdd pwr constant c ??? ent positive powe ? s ? ppl ? vss vss pwr digital negative powe ? s ? ppl ?? g ? o ? nd. iovss pwr i/o negative powe ? s ? ppl ?? g ? o ? nd. hvss pwr hirc oscillato ? negative powe ? s ? ppl ?? g ? o ? nd. avss avss pwr analog negative powe ? s ? ppl ?? g ? o ? nd. ccvss ccvss pwr constant c ??? ent negative powe ? s ? ppl ?? g ? o ? nd.
rev. 1.20 20 ? e ??? a ?? 1 ?? 201 ? rev. 1.20 21 ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu a f t /t /t ds ledvss ledvss pwr negative powe ? s ? ppl ? fo ? led cco0~cco14 o ? tp ? t cco0~cco14 ccon an led pwm constant c ??? ent o ? tp ? t rext rext an exte ? nal ? esisto ? inp ? t pin to set ? p o ? tp ? t c ??? ent fo ? all ccon o ? tp ? t legend: i/t: input type; o/t: output type; opt: optional by register option; pwr: power; st: schmitt t rigger input; cmos: cmos output; nmos: nmos output; an: analog signal; hxt: high frequency crystal oscillator; *: ubus pin needs to be connected to vdd for icp mode. pa0/ptck0/ ocdsda pa0 papu pawueg0 st cmos gene ? al p ?? pose i/o. registe ? ena ? led p ? ll- ? p and wake- ? p ptck0 st ptm0 clock inp ? t ocdsda st cmos ocds data/add ? ess pin ? fo ? ev chip onl ? . pa1/sdoa/c0x pa1 papu pawueg0 pas0 st cmos gene ? al p ?? pose i/o. registe ? ena ? led p ? ll- ? p and wake- ? p sdoa pas0 cmos spia se ? ial data o ? tp ? t c0x pas0 cmos compa ? ato ? 0 o ? tp ? t pa2/sdia/c0+ pa2 papu pawueg0 pas0 st cmos gene ? al p ?? pose i/o. registe ? ena ? led p ? ll- ? p and wake- ? p sdia pas0 st spia se ? ial data inp ? t c0+ pas0 an compa ? ato ? 0 positive inp ? t pa3/scka/c0- pa3 papu pawueg0 pas0 st cmos gene ? al p ?? pose i/o. registe ? ena ? led p ? ll- ? p and wake- ? p scka pas0 st cmos spia se ? ial clock c0- pas0 an compa ? ato ? 0 negative inp ? t pa4/ scsa/stp/ stpi/c1x pa4 papu pawueg1 pas1 st cmos gene ? al p ?? pose i/o. registe ? ena ? led p ? ll- ? p and wake- ? p scsa pas1 st cmos spia slave select stp pas1 cmos stm o ? tp ? t stpi pas1 i ? s st stm capt ?? e inp ? t c1x pas1 cmos compa ? ato ? 1 o ? tp ? t pa5/ptp0/ptp0i/ c1+ pa5 papu pawueg1 pas1 st cmos gene ? al p ?? pose i/o. registe ? ena ? led p ? ll- ? p and wake- ? p ptp0 pas1 cmos ptm0 o ? tp ? t ptp0i pas1 i ? s st ptm0 capt ?? e inp ? t c1+ pas1 an compa ? ato ? 1 positive inp ? t pa ? /stck/c1- pa ? papu pawueg1 pas1 st cmos gene ? al p ?? pose i/o. registe ? ena ? led p ? ll- ? p and wake- ? p stck pas1 st stm clock inp ? t c1- pas1 an compa ? ato ? 1 negative inp ? t
rev. 1.20 20 ?e???a?? 1?? 201? rev. 1.20 21 ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu a f t /t /t ds pa ? /int0 pa ? papu pawueg1 st cmos gene ? al p ?? pose i/o. registe ? ena ? led p ? ll- ? p and wake- ? p int0 integ intc0 st exte ? nal inte ??? pt 0 inp ? t pb0/sdo/sda/an0 pb0 pbpu pbwu pbs0 st cmos gene ? al p ?? pose i/o. registe ? ena ? led p ? ll- ? p and wake- ? p sdo pbs0 cmos spi se ? ial data o ? tp ? t sda pbs0 st nmos i 2 c data line an0 pbs0 an a/d conve ? te ? exte ? nal inp ? t 0 pb1/sdi/scl/an1 pb1 pbpu pbwu pbs0 st cmos gene ? al p ?? pose i/o. registe ? ena ? led p ? ll- ? p and wake- ? p sdi pbs0 st spi se ? ial data inp ? t scl pbs0 st nmos i 2 c clock line an1 pbs0 an a/d conve ? te ? exte ? nal inp ? t 1 pb2/sck/an2 pb2 pbpu pbwu pbs0 st cmos gene ? al p ?? pose i/o. registe ? ena ? led p ? ll- ? p and wake- ? p sck pbs0 st cmos spi se ? ial clock an2 pbs0 an a/d conve ? te ? exte ? nal inp ? t 2 pb3/scs/an3 pb3 pbpu pbwu pbs0 st cmos gene ? al p ?? pose i/o. registe ? ena ? led p ? ll- ? p and wake- ? p scs pbs0 st cmos spi slave select an3 pbs0 an a/d conve ? te ? exte ? nal inp ? t 3 pb4/stp/stpi/an4 pb4 pbpu pbwu pbs1 st cmos gene ? al p ?? pose i/o. registe ? ena ? led p ? ll- ? p and wake- ? p stp pbs1 cmos stm o ? tp ? t stpi pbs1 i ? s st stm capt ?? e inp ? t an4 pbs1 an a/d conve ? te ? exte ? nal inp ? t 4 pb ? /an5 pb ? pbpu pbwu pbs1 st cmos gene ? al p ?? pose i/o. registe ? ena ? led p ? ll- ? p and wake- ? p an5 pbs1 an a/d conve ? te ? exte ? nal inp ? t 5 pc3/int1 pc3 pcpu pcwu pcs0 st cmos gene ? al p ?? pose i/o. registe ? ena ? led p ? ll- ? p and wake- ? p int1 integ intc0 st exte ? nal inte ??? pt 1 inp ? t pc4/tx/an ? pc4 pcpu pcwu pcs1 st cmos gene ? al p ?? pose i/o. registe ? ena ? led p ? ll- ? p and wake- ? p tx pcs1 cmos uart tx se ? ial data o ? tp ? t an ? pcs1 an a/d conve ? te ? exte ? nal inp ? t ? pc5/rx/an ? pc5 pcpu pcwu pcs1 st cmos gene ? al p ?? pose i/o. registe ? ena ? led p ? ll- ? p and wake- ? p rx pcs1 st uart rx se ? ial data inp ? t an ? pcs1 an a/d conve ? te ? exte ? nal inp ? t ?
rev. 1.20 22 ? e ??? a ?? 1 ?? 201 ? rev. 1.20 23 ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu a f t /t /t ds pc ? /an8 pc ? pcpu pcwu pcs1 st cmos gene ? al p ?? pose i/o. registe ? ena ? led p ? ll- ? p and wake- ? p an8 pcs1 an a/d conve ? te ? exte ? nal inp ? t 8 pd0/ptp2/ptp2i/ osc1 pd0 pdpu pdwu pds0 st cmos gene ? al p ?? pose i/o. registe ? ena ? led p ? ll- ? p and wake- ? p ptp2 pds0 cmos ptm2 o ? tp ? t ptp2i pds0 i ? s st ptm2 capt ?? e inp ? t osc1 pds0 hxt hxt oscillato ? pin pd1/ptp1/ptp1i/ osc2 pd1 pdpu pdwu pds0 st cmos gene ? al p ?? pose i/o. registe ? ena ? led p ? ll- ? p and wake- ? p ptp1 pds0 cmos ptm1 o ? tp ? t ptp1i pds0 i ? s st ptm1 capt ?? e inp ? t osc2 pds0 hxt hxt oscillato ? pin pd2/ptck1 pd2 pdpu pdwu st cmos gene ? al p ?? pose i/o. registe ? ena ? led p ? ll- ? p and wake- ? p ptck1 st ptm1 clock inp ? t pd3/an9 pd3 pdpu pdwu st cmos gene ? al p ?? pose i/o. registe ? ena ? led p ? ll- ? p and wake- ? p an9 an a/d conve ? te ? exte ? nal inp ? t 9 pd4/an10 pd4 pdpu pdwu st cmos gene ? al p ?? pose i/o. registe ? ena ? led p ? ll- ? p and wake- ? p an10 an a/d conve ? te ? exte ? nal inp ? t 10 pd5/ptp0/ptp0i pd5 pdpu pdwu pds1 st cmos gene ? al p ?? pose i/o. registe ? ena ? led p ? ll- ? p and wake- ? p ptp0 pds1 cmos ptm0 o ? tp ? t ptp0i pds1 i ? s st ptm0 capt ?? e inp ? t pd ? /ptp2/ptp2i pd ? pdpu pdwu pds1 st cmos gene ? al p ?? pose i/o. registe ? ena ? led p ? ll- ? p and wake- ? p ptp2 pds1 cmos ptm2 o ? tp ? t ptp2i pds1 i ? s st ptm2 capt ?? e inp ? t pd ? /ptp1/ptp1i pd ? pdpu pdwu pds1 st cmos gene ? al p ?? pose i/o. registe ? ena ? led p ? ll- ? p and wake- ? p ptp1 pds1 cmos ptm1 o ? tp ? t ptp1i pds1 i ? s st ptm1 capt ?? e inp ? t pe0/vddio/vre ? pe0 pepu pewu pes0 st cmos gene ? al p ?? pose i/o. registe ? ena ? led p ? ll- ? p and wake- ? p vddio pes0 pwr pa exte ? nal powe ? inp ? t vre ? pes0 an a/d conve ? te ? exte ? nal ? efe ? ence voltage inp ? t pe1/ptck2 pe1 pepu pewu st cmos gene ? al p ?? pose i/o. registe ? ena ? led p ? ll- ? p and wake- ? p ptck2 st ptm2 clock inp ? t
rev. 1.20 22 ?e???a?? 1?? 201? rev. 1.20 23 ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu a f t /t /t ds pe2/vre ? i pe2 pepu pewu pes0 st cmos gene ? al p ?? pose i/o. registe ? ena ? led p ? ll- ? p and wake- ? p vre ? i pes0 an a/d conve ? te ? pga inp ? t pe3/vr pe3 pepu pewu pes0 st cmos gene ? al p ?? pose i/o. registe ? ena ? led p ? ll- ? p and wake- ? p vr pes0 an a/d conve ? te ? ? efe ? ence voltage o ? tp ? t pg0/com0/an11 pg0 pgpu pgwu pgs0 st cmos gene ? al p ?? pose i/o. registe ? ena ? led p ? ll- ? p and wake- ? p com0 pgs0 an led com0 o ? tp ? t an11 pgs0 an a/d conve ? te ? exte ? nal inp ? t 11 pg1/com1 pg1 pgpu pgwu pgs0 st cmos gene ? al p ?? pose i/o. registe ? ena ? led p ? ll- ? p and wake- ? p com1 pgs0 an led com1 o ? tp ? t pg2/com2 pg2 pgpu pgwu pgs0 st cmos gene ? al p ?? pose i/o. registe ? ena ? led p ? ll- ? p and wake- ? p com2 pgs0 an led com2 o ? tp ? t pg3/com3 pg3 pgpu pgwu pgs0 st cmos gene ? al p ?? pose i/o. registe ? ena ? led p ? ll- ? p and wake- ? p com3 pgs0 an led com3 o ? tp ? t pg4/com4 pg4 pgpu pgwu pgs1 st cmos gene ? al p ?? pose i/o. registe ? ena ? led p ? ll- ? p and wake- ? p com4 pgs1 an led com4 o ? tp ? t pg5/com5 pg5 pgpu pgwu pgs1 st cmos gene ? al p ?? pose i/o. registe ? ena ? led p ? ll- ? p and wake- ? p com5 pgs1 an led com5 o ? tp ? t pg ? /com ? pg ? pgpu pgwu pgs1 st cmos gene ? al p ?? pose i/o. registe ? ena ? led p ? ll- ? p and wake- ? p com ? pgs1 an led com ? o ? tp ? t pg ? /com ? pg ? pgpu pgwu pgs1 st cmos gene ? al p ?? pose i/o. registe ? ena ? led p ? ll- ? p and wake- ? p com ? pgs1 an led com ? o ? tp ? t ubus* ubus pwr usb sie powe ? s ? ppl ? v33o v33o pwr usb 3.3v ? eg ? lato ? o ? tp ? t udn/od0/icpda udn st cmos usb udn line od0 st nmos nmos open d ? ain i/o pin icpda st cmos icp add ? ess/data udp/od1 udp st cmos usb udp line od1 st nmos nmos open d ? ain i/o pin res/icpck/ ocdsck res st exte ? nal ? eset inp ? t icpck st icp clock ocdsck st ocds clock pin ? fo ? ev chip onl ? vdd vdd pwr digital positive powe ? s ? ppl ? iovdd pwr i/o positive powe ? s ? ppl ?
rev. 1.20 24 ? e ??? a ?? 1 ?? 201 ? rev. 1.20 25 ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu a f t /t /t ds avdd avdd pwr analog positive powe ? s ? ppl ? ccvdd ccvdd pwr constant c ??? ent positive powe ? s ? ppl ? vss vss pwr digital negative powe ? s ? ppl ?? g ? o ? nd. iovss pwr i/o negative powe ? s ? ppl ?? g ? o ? nd. hvss pwr hirc oscillato ? negative powe ? s ? ppl ?? g ? o ? nd. avss avss pwr analog negative powe ? s ? ppl ?? g ? o ? nd. ccvss ccvss pwr constant c ??? ent negative powe ? s ? ppl ?? g ? o ? nd. ledvss ledvss pwr negative powe ? s ? ppl ? fo ? led cco0~cco23 o ? tp ? t cco0~cco23 ccon an led pwm constant c ??? ent o ? tp ? t rext rext an exte ? nal ? esisto ? inp ? t pin to set ? p o ? tp ? t c ??? ent fo ? all ccon o ? tp ? t legend: i/t: input type; o/t: output type; opt: optional by register option; pwr: power; st: schmitt t rigger input; cmos: cmos output; nmos: nmos output; an: analog signal; hxt: high frequency crystal oscillator; *: ubus pin needs to be connected to vdd for icp mode. pa0/ptck0/ ocdsda pa0 papu pawueg0 st cmos gene ? al p ?? pose i/o. registe ? ena ? led p ? ll- ? p and wake- ? p ptck0 st ptm0 clock inp ? t ocdsda st cmos ocds data/add ? ess pin ? fo ? ev chip onl ? . pa1/sdoa/c0x pa1 papu pawueg0 pas0 st cmos gene ? al p ?? pose i/o. registe ? ena ? led p ? ll- ? p and wake- ? p sdoa pas0 cmos spia se ? ial data o ? tp ? t c0x pas0 cmos compa ? ato ? 0 o ? tp ? t pa2/sdia/c0+ pa2 papu pawueg0 pas0 st cmos gene ? al p ?? pose i/o. registe ? ena ? led p ? ll- ? p and wake- ? p sdia pas0 st spia se ? ial data inp ? t c0+ pas0 an compa ? ato ? 0 positive inp ? t pa3/scka/c0- pa3 papu pawueg0 pas0 st cmos gene ? al p ?? pose i/o. registe ? ena ? led p ? ll- ? p and wake- ? p scka pas0 st cmos spia se ? ial clock c0- pas0 an compa ? ato ? 0 negative inp ? t pa4/ scsa/stp/ stpi/c1x pa4 papu pawueg1 pas1 st cmos gene ? al p ?? pose i/o. registe ? ena ? led p ? ll- ? p and wake- ? p scsa pas1 st cmos spia slave select stp pas1 cmos stm o ? tp ? t stpi pas1 i ? s st stm capt ?? e inp ? t c1x pas1 cmos compa ? ato ? 1 o ? tp ? t
rev. 1.20 24 ?e???a?? 1?? 201? rev. 1.20 25 ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu a f t /t /t ds pa5/ptp0/ptp0i/ c1+ pa5 papu pawueg1 pas1 st cmos gene ? al p ?? pose i/o. registe ? ena ? led p ? ll- ? p and wake- ? p ptp0 pas1 cmos ptm0 o ? tp ? t ptp0i pas1 i ? s st ptm0 capt ?? e inp ? t c1+ pas1 an compa ? ato ? 1 positive inp ? t pa ? /stck/c1- pa ? papu pawueg1 pas1 st cmos gene ? al p ?? pose i/o. registe ? ena ? led p ? ll- ? p and wake- ? p stck pas1 st stm clock inp ? t c1- pas1 an compa ? ato ? 1 negative inp ? t pa ? /int0 pa ? papu pawueg1 st cmos gene ? al p ?? pose i/o. registe ? ena ? led p ? ll- ? p and wake- ? p int0 integ intc0 st exte ? nal inte ??? pt 0 inp ? t pb0/sdo/sda/an0 pb0 pbpu pbwu pbs0 st cmos gene ? al p ?? pose i/o. registe ? ena ? led p ? ll- ? p and wake- ? p sdo pbs0 cmos spi se ? ial data o ? tp ? t sda pbs0 st nmos i 2 c data line an0 pbs0 an a/d conve ? te ? exte ? nal inp ? t 0 pb1/sdi/scl/an1 pb1 pbpu pbwu pbs0 st cmos gene ? al p ?? pose i/o. registe ? ena ? led p ? ll- ? p and wake- ? p sdi pbs0 st spi se ? ial data inp ? t scl pbs0 st nmos i 2 c clock line an1 pbs0 an a/d conve ? te ? exte ? nal inp ? t 1 pb2/sck/an2 pb2 pbpu pbwu pbs0 st cmos gene ? al p ?? pose i/o. registe ? ena ? led p ? ll- ? p and wake- ? p sck pbs0 st cmos spi se ? ial clock an2 pbs0 an a/d conve ? te ? exte ? nal inp ? t 2 pb3/scs/an3 pb3 pbpu pbwu pbs0 st cmos gene ? al p ?? pose i/o. registe ? ena ? led p ? ll- ? p and wake- ? p scs pbs0 st cmos spi slave select an3 pbs0 an a/d conve ? te ? exte ? nal inp ? t 3 pb4/stp/stpi/an4 pb4 pbpu pbwu pbs1 st cmos gene ? al p ?? pose i/o. registe ? ena ? led p ? ll- ? p and wake- ? p stp pbs1 cmos stm o ? tp ? t stpi pbs1 i ? s st stm capt ?? e inp ? t an4 pbs1 an a/d conve ? te ? exte ? nal inp ? t 4 pb5/an5 pb5 pbpu pbwu pbs1 st cmos gene ? al p ?? pose i/o. registe ? ena ? led p ? ll- ? p and wake- ? p an5 pbs1 an a/d conve ? te ? exte ? nal inp ? t 5
rev. 1.20 2 ? ? e ??? a ?? 1 ?? 201 ? rev. 1.20 2? ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu a f t /t /t ds pb ? /int1/an ? pb ? pbpu pbwu pbs1 st cmos gene ? al p ?? pose i/o. registe ? ena ? led p ? ll- ? p and wake- ? p int1 pbs1 integ intc0 st exte ? nal inte ??? pt 1 inp ? t an ? pbs1 an a/d conve ? te ? exte ? nal inp ? t ? pb ? /an ? pb ? pbpu pbwu pbs1 st cmos gene ? al p ?? pose i/o. registe ? ena ? led p ? ll- ? p and wake- ? p an ? pbs1 an a/d conve ? te ? exte ? nal inp ? t ? pc0/an8 pc0 pcpu pcwu pcs0 st cmos gene ? al p ?? pose i/o. registe ? ena ? led p ? ll- ? p and wake- ? p an8 pcs0 an a/d conve ? te ? exte ? nal inp ? t 8 pc1/an9 pc1 pcpu pcwu pcs0 st cmos gene ? al p ?? pose i/o. registe ? ena ? led p ? ll- ? p and wake- ? p an9 pcs0 an a/d conve ? te ? exte ? nal inp ? t 9 pc2/an10 pc2 pcpu pcwu pcs0 st cmos gene ? al p ?? pose i/o. registe ? ena ? led p ? ll- ? p and wake- ? p an10 pcs0 an a/d conve ? te ? exte ? nal inp ? t 10 pc3/an11 pc3 pcpu pcwu pcs0 st cmos gene ? al p ?? pose i/o. registe ? ena ? led p ? ll- ? p and wake- ? p an11 pcs0 an a/d conve ? te ? exte ? nal inp ? t 11 pc4/tx/an12 pc4 pcpu pcwu pcs1 st cmos gene ? al p ?? pose i/o. registe ? ena ? led p ? ll- ? p and wake- ? p tx pcs1 cmos uart tx se ? ial data o ? tp ? t an12 pcs1 an a/d conve ? te ? exte ? nal inp ? t 12 pc5/rx/an13 pc5 pcpu pcwu pcs1 st cmos gene ? al p ?? pose i/o. registe ? ena ? led p ? ll- ? p and wake- ? p rx pcs1 st uart rx se ? ial data inp ? t an13 pcs1 an a/d conve ? te ? exte ? nal inp ? t 13 pc ? /an14 pc ? pcpu pcwu pcs1 st cmos gene ? al p ?? pose i/o. registe ? ena ? led p ? ll- ? p and wake- ? p an14 pcs1 an a/d conve ? te ? exte ? nal inp ? t 14 pc ? /an15 pc ? pcpu pcwu pcs1 st cmos gene ? al p ?? pose i/o. registe ? ena ? led p ? ll- ? p and wake- ? p an15 pcs1 an a/d conve ? te ? exte ? nal inp ? t 15 pd0/ptp2/ptp2i/ osc1 pd0 pdpu pdwu pds0 st cmos gene ? al p ?? pose i/o. registe ? ena ? led p ? ll- ? p and wake- ? p ptp2 pds0 cmos ptm2 o ? tp ? t ptp2i pds0 i ? s st ptm2 capt ?? e inp ? t osc1 pds0 hxt hxt oscillato ? pin
rev. 1.20 2? ?e???a?? 1?? 201? rev. 1.20 2 ? ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu a f t /t /t ds pd1/ptp1/ptp1i/ osc2 pd1 pdpu pdwu pds0 st cmos gene ? al p ?? pose i/o. registe ? ena ? led p ? ll- ? p and wake- ? p ptp1 pds0 cmos ptm1 o ? tp ? t ptp1i pds0 i ? s st ptm1 capt ?? e inp ? t osc2 pds0 hxt hxt oscillato ? pin pd2/ptck1 pd2 pdpu pdwu st cmos gene ? al p ?? pose i/o. registe ? ena ? led p ? ll- ? p and wake- ? p ptck1 st ptm1 clock inp ? t pd3 pd3 pdpu pdwu st cmos gene ? al p ?? pose i/o. registe ? ena ? led p ? ll- ? p and wake- ? p pd4/ptck2 pd4 pdpu pdwu st cmos gene ? al p ?? pose i/o. registe ? ena ? led p ? ll- ? p and wake- ? p ptck2 st ptm2 clock inp ? t pd5/ptp0/ptp0i pd5 pdpu pdwu pds1 st cmos gene ? al p ?? pose i/o. registe ? ena ? led p ? ll- ? p and wake- ? p ptp0 pds1 cmos ptm0 o ? tp ? t ptp0i pds1 i ? s st ptm0 capt ?? e inp ? t pd ? /ptp2/ptp2i pd ? pdpu pdwu pds1 st cmos gene ? al p ?? pose i/o. registe ? ena ? led p ? ll- ? p and wake- ? p ptp2 pds1 cmos ptm2 o ? tp ? t ptp2i pds1 i ? s st ptm2 capt ?? e inp ? t pd ? /ptp1/ptp1i pd ? pdpu pdwu pds1 st cmos gene ? al p ?? pose i/o. registe ? ena ? led p ? ll- ? p and wake- ? p ptp1 pds1 cmos ptm1 o ? tp ? t ptp1i pds1 i ? s st ptm1 capt ?? e inp ? t pe0/vddio/vre ? pe0 pepu pewu pes0 st cmos gene ? al p ?? pose i/o. registe ? ena ? led p ? ll- ? p and wake- ? p vddio pes0 pwr pa exte ? nal powe ? inp ? t vre ? pes0 an a/d conve ? te ? exte ? nal ? efe ? ence voltage inp ? t pe1 pe1 pepu pewu st cmos gene ? al p ?? pose i/o. registe ? ena ? led p ? ll- ? p and wake- ? p pe2/vre ? i pe2 pepu pewu pes0 st cmos gene ? al p ?? pose i/o. registe ? ena ? led p ? ll- ? p and wake- ? p vre ? i pes0 an a/d conve ? te ? pga inp ? t pe3/vr pe3 pepu pewu pes0 st cmos gene ? al p ?? pose i/o. registe ? ena ? led p ? ll- ? p and wake- ? p vr pes0 an a/d conve ? te ? ? efe ? ence voltage o ? tp ? t p ? 0~p ?? p ? n p ? pu p ? wu st cmos gene ? al p ?? pose i/o. registe ? ena ? led p ? ll- ? p and wake- ? p pg0/com0 pg0 pgpu pgwu pgs0 st cmos gene ? al p ?? pose i/o. registe ? ena ? led p ? ll- ? p and wake- ? p com0 pgs0 an led com0 o ? tp ? t
rev. 1.20 28 ? e ??? a ?? 1 ?? 201 ? rev. 1.20 29 ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu a f t /t /t ds pg1/com1 pg1 pgpu pgwu pgs0 st cmos gene ? al p ?? pose i/o. registe ? ena ? led p ? ll- ? p and wake- ? p com1 pgs0 an led com1 o ? tp ? t pg2/com2 pg2 pgpu pgwu pgs0 st cmos gene ? al p ?? pose i/o. registe ? ena ? led p ? ll- ? p and wake- ? p com2 pgs0 an led com2 o ? tp ? t pg3/com3 pg3 pgpu pgwu pgs0 st cmos gene ? al p ?? pose i/o. registe ? ena ? led p ? ll- ? p and wake- ? p com3 pgs0 an led com3 o ? tp ? t pg4/com4 pg4 pgpu pgwu pgs1 st cmos gene ? al p ?? pose i/o. registe ? ena ? led p ? ll- ? p and wake- ? p com4 pgs1 an led com4 o ? tp ? t pg5/com5 pg5 pgpu pgwu pgs1 st cmos gene ? al p ?? pose i/o. registe ? ena ? led p ? ll- ? p and wake- ? p com5 pgs1 an led com5 o ? tp ? t pg ? /com ? pg ? pgpu pgwu pgs1 st cmos gene ? al p ?? pose i/o. registe ? ena ? led p ? ll- ? p and wake- ? p com ? pgs1 an led com ? o ? tp ? t pg ? /com ? pg ? pgpu pgwu pgs1 st cmos gene ? al p ?? pose i/o. registe ? ena ? led p ? ll- ? p and wake- ? p com ? pgs1 an led com ? o ? tp ? t ubus* ubus pwr usb sie powe ? s ? ppl ? v33o v33o pwr usb 3.3v ? eg ? lato ? o ? tp ? t udn/od0/icpda udn st cmos usb udn line od0 st nmos nmos open d ? ain i/o pin icpda st cmos icp add ? ess/data udp/od1 udp st cmos usb udp line od1 st nmos nmos open d ? ain i/o pin res/icpck/ ocdsck res st exte ? nal ? eset inp ? t icpck st icp clock ocdsck st ocds clock pin ? fo ? ev chip onl ? vdd vdd pwr digital positive powe ? s ? ppl ? iovdd pwr i/o positive powe ? s ? ppl ? avdd avdd pwr analog positive powe ? s ? ppl ? ccvdd ccvdd pwr constant c ??? ent positive powe ? s ? ppl ? vss vss pwr digital negative powe ? s ? ppl ?? g ? o ? nd. iovss pwr i/o negative powe ? s ? ppl ?? g ? o ? nd. hvss pwr hirc oscillato ? negative powe ? s ? ppl ?? g ? o ? nd. avss avss pwr analog negative powe ? s ? ppl ?? g ? o ? nd. ccvss ccvss pwr constant c ??? ent negative powe ? s ? ppl ?? g ? o ? nd. ledvss ledvss pwr negative powe ? s ? ppl ? fo ? led cco0~cco4 ? o ? tp ? t cco0~cco4 ? ccon an led pwm constant c ??? ent o ? tp ? t
rev. 1.20 28 ?e???a?? 1?? 201? rev. 1.20 29 ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu a f t /t /t ds rext rext an exte ? nal ? esisto ? inp ? t pin to set ? p o ? tp ? t c ??? ent fo ? all ccon o ? tp ? t legend: i/t: input type; o/t: output type; opt: optional by register option; pwr: power; st: schmitt t rigger input; cmos: cmos output; nmos: nmos output; an: analog signal; hxt: high frequency crystal oscillator; *: ubus pin needs to be connected to vdd for icp mode. supply v oltage .............. .................................................................................... v ss ?0.3v to v ss +6.0v input v oltage .............. ...................................................................................... v ss ?0.3v to v dd +0.3v storage t emperature ............... ...................................................................................... -50c to 125c operating t emperature .............. ..................................................................................... -40c to 85c i oh t otal .............. ...................................................................................................................... -100ma i ol t otal .............. ........................................................................................... 350ma (for ht66fb572) i ol t otal .............. ........................................................................................... 700ma (for ht66fb574) i ol t otal .............. ......................................................................................... 1400ma (for HT66FB576) total power dissipation .............. ................................................................. 450mw (for ht66fb572) total power dissipation .............. ................................................................. 800mw (for ht66fb574) total power dissipation .............. ............................................................... 1500mw (for HT66FB576) note: these are stress ratings only . stresses exceeding the range specified under "absolute maximum ra tings" m ay c ause subst antial da mage t o t he de vices. func tional ope ration of these devices at other conditions beyond those listed in the specifcation is not implied and prolonged exposure to extreme conditions may affect device reliability. ta=25c s?m?ol pa?amete? test conditions min. t?p. max. unit v dd conditions v dd ope ? ating voltage (hxt) f sys =f hxt = ? mhz 2.2 5.5 v f sys =f hxt =12mhz 2. ? 5.5 ope ? ating voltage (hirc) f sys =f hirc =12mhz 2. ? 5.5 v ope ? ating voltage (lirc) f sys =f lirc =32khz 2.2 5.5 v ope ? ating voltage (pll) f sys =f pll = ? mhz ? pllen=1 2.2 5.5 v f sys =f pll =12mhz ? pllen=1 2. ? 5.5 f sys =f pll =1 ? mhz ? pllen=1 3.3 5.5
rev. 1.20 30 ? e ??? a ?? 1 ?? 201 ? rev. 1.20 31 ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu sl aa ts cs m t ma u dd cs i dd ope ? ating c ??? ent (hxt) 3v f sys =f hxt = ? mhz ? no load ? all pe ? iphe ? als off 0. ? 1.5 ma 5v 1. ? 3 3v f sys =f hxt =12mhz ? no load ? all pe ? iphe ? als off 1.3 3 ma 5v 2. ? ? 3.3v f sys =f hxt =1 ? mhz ? no load ? all pe ? iphe ? als off 3.0 ? .0 ma 5v 5.0 9.5 ope ? ating c ??? ent (hirc) 3v f sys =f hirc =12mhz ? no load ? all pe ? iphe ? als off 1. ? 3 ma 5v 2.8 ? ope ? ating c ??? ent (lirc) 3v f sys =f lirc =32khz ? no load ? all pe ? iphe ? als off 1 ? 30 a 5v 28 50 ope ? ating c ??? ent (pll) 3v f sys =f pll = ? mhz ? pllen=1 ? no load ? all pe ? iphe ? als off 1.5 2 ma 5v 3 4 3v f sys =f pll =12mhz ? pllen=1 ? no load ? all pe ? iphe ? als off 2.1 3.5 ma 5v 3.8 ? 3.3v f sys =f pll =1 ? mhz ? pllen=1 ? no load ? all pe ? iphe ? als off 3.2 ? .5 ma 5v 4.5 9.0 i stb stand ?? c ??? ent (sleep mode) 3v f sys off ? f sub o ff ? no load ? all pe ? iphe ? als off ? wdt disa ? le ? ta=25 c 0.2 0.8 a 5v 0.5 1 3v f sys off ? f sub o ff ? no load ? all pe ? iphe ? als off ? wdt disa ? le ? ta=-40 c~85c 1 a 5v 2 3v f sys off ? f sub =f lirc on ? no load ? all pe ? iphe ? als off ? wdt ena ? le 3 a 5v 5 stand ?? c ??? ent (idle0 mode) 3v f sys off ? f sub =f lirc on ? no load ? all pe ? iphe ? als off 1.5 3 a 5v 2.8 5 stand ?? c ??? ent (idle1 mode) 3v f sys =f hirc =12mhz on ? f sub on ? no load ? all pe ? iphe ? als off 0. ? 5 1.4 ma 5v 1.3 3 3v f sys =f hxt =12mhz on ? f sub on ? no load ? all pe ? iphe ? als off 0.9 1.5 ma 5v 1.4 3 3v f sys =f pll = ? mhz on ? f sub on ? pllen=1 ? no load ? all pe ? iphe ? als off 1.0 2.5 ma 5v 2.0 3.5 3v f sys =f pll =12mhz on ? f sub on ? pllen=1 ? no load ? all pe ? iphe ? als off 1.5 3 ma 5v 2.5 4 5v f sys =f pll =1 ? mhz on ? f sub on ? pllen=1 ? no load ? all pe ? iphe ? als off 3 5 ma v il inp ? t low voltage fo ? i/o po ? t s 5v 0 1.5 v 0 0.2v dd inp ? t low voltage fo ? res pin 0 0.4v dd v v ih inp ? t high voltage fo ? i/o po ? t s 5v 3.5 5 v 0.8v dd v dd inp ? t high voltage fo ? res pin 0.9v dd v dd v r ph p ? ll-high resistance fo ? i/o po ? t s 3v 20 ? 0 100 k 5v 10 30 50 i leak inp ? t leakage c ??? ent 3v v in =v dd o ? v in =v ss 1 a 5v 1
rev. 1.20 30 ?e???a?? 1?? 201? rev. 1.20 31 ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu sl aa ts cs m t ma u dd cs sr rise o ? tp ? t rising edge slew rate fo ? i/o po ? t s 3v slewcn [m+1 ? m]=00b ( n=0 ? 1... ? m=0 o ? 2 o ? 4 o ? ? ) ? 0.1v dd to 0.9v dd o ? 0.9v dd to 0.1v dd ? c load =2 0p ? 150 v/s 5v 380 3v slewcn [m+1 ? m]=01b ( n=0 ? 1... ? m=0 o ? 2 o ? 4 o ? ? ) ? 0.1v dd to 0.9v dd o ? 0.9v dd to 0.1v dd ? c load =2 0p ? 8 ? v/s 5v 240 3v slewcn [m+1 ? m]= 10b ( n=0 ? 1... ? m=0 o ? 2 o ? 4 o ? ? ) ? 0.1v dd to 0.9v dd o ? 0.9v dd to 0.1v dd ? c load =2 0p ? 45 v/s 5v 120 3v slewcn [m+1 ? m]= 11 b ( n=0 ? 1... ? m=0 o ? 2 o ? 4 o ? ? ) ? 0.1v dd to 0.9v dd o ? 0.9v dd to 0.1v dd ? c load =2 0p ? 20 v/s 5v ? 0 sr ? all o ? tp ? t ? alling edge slew rate fo ? i/o po ? t s 3v slewcn [m+1 ? m]=00b ( n=0 ? 1... ? m=0 o ? 2 o ? 4 o ? ? ) ? 0.1v dd to 0.9v dd o ? 0.9v dd to 0.1v dd ? c load =2 0p ? 200 v/s 5v 500 3v slewcn [m+1 ? m]=01b ( n=0 ? 1... ? m=0 o ? 2 o ? 4 o ? ? ) ? 0.1v dd to 0.9v dd o ? 0.9v dd to 0.1v dd ? c load =2 0p ? ? 1 v/s 5v 180 3v slewcn [m+1 ? m]= 10b ( n=0 ? 1... ? m=0 o ? 2 o ? 4 o ? ? ) ? 0.1v dd to 0.9v dd o ? 0.9v dd to 0.1v dd ? c load =2 0p ? 29 v/s 5v 90 3v slewcn [m+1 ? m]= 11 b ( n=0 ? 1... ? m=0 o ? 2 o ? 4 o ? ? ) ? 0.1v dd to 0.9v dd o ? 0.9v dd to 0.1v dd ? c load =2 0p ? 15 v/s 5v 45 i ol sink c ??? ent fo ? i/o po ? t s 3v v ol =0.1v dd ? drvcc n[m]=0 ( n=0 ? 1... ? m=0 ? 1 ? ... ?? ) 1 2 ma 5v 2 4 3v v ol =0.1v dd ? drvcc n[m]=1 ( n=0 ? 1... ? m=0 ? 1 ? ... ?? ) 5 10 ma 5v 10 20 i oh so ?? ce c ??? ent fo ? i/o po ? t s 3v v ol =0.9v dd ? drvcc n[m]=0 ( n=0 ? 1... ? m=0 ? 1 ? ... ?? ) -1 -2 ma 5v -2 -4 3v v ol =0.9v dd ? drvcc n[m]=1 ( n=0 ? 1... ? m=0 ? 1 ? ... ?? ) -1 -5 ma 5v -5 -10 v ol o ? tp ? t low voltage fo ? i/o po ? t s 3v i ol =1ma ? drvcc n[m]=0 ( n=0 ? 1... ? m=0 ? 1 ? ... ?? ) 0.3 v 5v i ol =2ma ? drvcc n[m]=0 ( n=0 ? 1... ? m=0 ? 1 ? ... ?? ) 0.5 v 3v i ol =5ma ? drvcc n[m]=1 ( n=0 ? 1... ? m=0 ? 1 ? ... ?? ) 0.3 v 5v i ol =10ma ? drvcc n[m]=1 ( n=0 ? 1... ? m=0 ? 1 ? ... ?? ) 0.5 v
rev. 1.20 32 ? e ??? a ?? 1 ?? 201 ? rev. 1.20 33 ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu sl aa ts cs m t ma u dd cs v oh o ? tp ? t high voltage fo ? i/o po ? t s 3v i oh =-1ma ? drvcc n[m]=0 ( n=0 ? 1... ? m=0 ? 1 ? ... ?? ) 2. ? v 5v i oh =-2ma ? drvcc n[m]=0 ( n=0 ? 1... ? m=0 ? 1 ? ... ?? ) 4.5 v 3v i oh =-1ma ? drvcc n[m]=1 ( n=0 ? 1... ? m=0 ? 1 ? ... ?? ) 2. ? v 5v i oh =-5ma ? drvcc n[m]=1 ( n=0 ? 1... ? m=0 ? 1 ? ... ?? ) 4.5 v a.c. cha?acte?istics ta=25c s?m?ol pa?amete? test conditions min. t?p. max. unit v dd conditions f sys s ? stem clock (hxt) 2.2v~5.5v f sys =f hxt = ? mhz ? mhz 2. ? v~5.5v f sys =f hxt =12mhz 12 mhz 3.3v~5.5v f sys =f hxt =1 ? mhz 1 ? mhz s ? stem clock (hirc) 2. ? v~5.5v f sys =f hirc =12mhz 12 mhz s ? stem clock (lirc) 2.2v~5.5v f sys =f lirc =32khz 32 khz f hirc high speed inte ? nal rc oscillato ? (hirc ? t ? im 12mhz at v dd =5v) 4.4v~5.25v usb mode and clkadj=1 ? udp/udn pl ? g in the host ? ta=-40c~85c -0.25% 12 +0.25% mhz 5v ta=25c -2% 12 +2% mhz ta=0c ~ ? 0c -3% 12 +3% mhz ta=-40c ~85c -5% 12 +5% mhz 2. ? v~5.5v ta=0c ~ ? 0c - ? % 12 + ? % mhz ta=-40c ~85c -10% 12 +10% mhz f lirc low speed inte ? nal rc oscillato ? (lirc) 2.2v~5.5v ta=25c -5% 32 +5% khz ta=-40c ~85c -10% 32 +10% t tck stck ? ptckn inp ? t pin minim ? m p ? lse width 0.3 s t tpi stpi ? ptpni inp ? t pin minim ? m p ? lse width 0.3 s t int exte ? nal inte ??? pt minim ? m p ? lse width 10 s t res exte ? nal reset minim ? m low p ? lse width 10 s t sst s ? stem sta ? t- ? p time ? pe ? iod (wake- ? p f ? om powe ? down mode and f sys off ? res pin reset) f sys =f hxt ~ f hxt / ? 4 128 t sys f sys =f hirc ~ f hirc / ? 4 1 ? t sys f pll off on (pllf=1) 25 ? 0 t pll (48mhz) f sys =f lirc 2 t sys s ? stem sta ? t- ? p time ? pe ? iod (slow mode ? normal mode, o ? f h =f hirc ? f hxt ) f hxt off on (hxtf=1) 1024 t hxt f hirc off on (hircf=1) 1 ? t hirc f pll off on (pllf=1) 25 ? 0 t pll (48mhz) s ? stem sta ? t- ? p time ? pe ? iod (wake- ? p f ? om powe ? down mode and f sys on) f sys =f h ~ f h / ? 4 ? f h =f hxt o ? f hirc o ? f pll 2 t sys f sys =f lirc 2 t sys
rev. 1.20 32 ?e???a?? 1?? 201? rev. 1.20 33 ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu sl aa ts cs m t ma u dd cs t rstd s ? stem reset dela ? time (powe ? -on reset ? lvr ha ? dwa ? e reset ? lvr softwa ? e reset ? wdt softwa ? e reset) 25 50 100 ms s ? stem reset dela ? time (res pin reset ? wdt time-o ? t ha ? dwa ? e cold reset) 8.3 1 ? . ? 33.3 ms t sreset minim ? m softwa ? e reset width to reset 45 90 120 s t dew data eeprom w ? ite time 2 4 ms a/d conve?te? elect?ical cha?acte?istics ta=-40c~85c ? ? nless othe ? wise specif ? s?m?ol pa?amete? test conditions min. t?p. max. unit v dd conditions v dd ope ? ating voltage 2.2 5.5 v v adi inp ? t voltage 0 v re ? v v re ? refe ? ence voltage 2 v dd v dnl diffe ? ential non - linea ? it ? 3v sains[3:0 ]=0000b ? savrs [1:0 ]=01b ? v re ? =v dd ? t adck =0.5s 3 lsb 5v 3v sains[3:0 ]=0000b ? savrs [1:0 ]=01b ? v re ? =v dd ? t adck =10s 5v inl integ ? al non - linea ? it ? 3v sains[3:0 ]=0000b ? savrs [1:0 ]=01b ? v re ? =v dd ? t adck =0.5s 4 lsb 5v 3v sains[3:0 ]=0000b ? savrs [1:0 ]=01b ? v re ? =v dd ? t adck =10s 5v i adc additional c ??? ent cons ? mption fo ? a/d conve ? te ? ena ? le 3v no load ? t adck =0.5s 0.2 0.4 ma 5v 0.3 0. ? ma t adck clock pe ? iod 0.5 10 s t on2st a/d conve ? te ? on-to-sta ? t time 4 s t ads sampling time 4 t adck t adc conve ? sion time (incl ? ding a/d conve ? te ? sample and hold time) 1 ? t adck gerr a/d conve ? sion g ain e ?? o ? 3v sains[3:0 ]=0000b ? savrs [1:0 ]=01b ? v re ? =v dd -4 +4 lsb 5v -4 +4 osrr a/d conve ? sion o ffset e ?? o ? 3v sains[3:0 ]=0000b ? savrs [1:0 ]=01b ? v re ? =v dd -4 +4 lsb 5v -4 +4 i pga additional c ??? ent fo ? pga e na ? le 3v no load 250 400 a 5v 400 550
rev. 1.20 34 ? e ??? a ?? 1 ?? 201 ? rev. 1.20 35 ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu sl aa ts cs m t ma u dd cs v cm i pga c ommon mode voltage range (ht ??? b5 ? 2/ht ??? b5 ? 4) 3v v ss +0.1 v dd -1.4 v 5v v ss +0.1 v dd -1.4 v cmi pga c ommon mode voltage range (ht ??? b5 ?? ) 3v v ss +0.02 v dd -1.4 v 5v v ss +0.02 v dd -1.4 v or pga m axim ? m o ? tp ? t v oltage range 3v v ss +0.1 v dd -0.1 v 5v v ss +0.1 v dd -0.1 v vr ? ix voltage o ? tp ? t of pga 2.2v~5.5v v ri =v bgre ? (pgais=1) -1% 2 +1% v 3.2v~5.5v v ri =v bgre ? (pgais=1) -1% 3 +1% 4.2v~5.5v v ri =v bgre ? (pgais=1) -1% 4 +1% i vr v r maxim ? m o ? tp ? t c ??? ent 2.2v v vr =2v ? v vr =-1% 100 200 a v ir pga i np ? t v oltage range 3v gain=1 ? pgais=0 relative gain gain e ?? o ? <5% v ss +0.1 v dd -1.4 v 5v v ss +0.1 v dd -1.4 v lvr/lvd elect?ical cha?acte?istics ta=25c s?m?ol pa?amete? test conditions min. t?p. max. unit v dd conditions v lvr low voltage reset voltage lvr ena ? le ? voltage select 2.1v -5% 2.1 +5% v lvr ena ? le ? voltage select 2.55v -5% 2.55 +5% lvr ena ? le ? voltage select 3.15v -5% 3.15 +5% lvr ena ? le ? voltage select 3.8v -5% 3.8 +5% v lvd low voltage detection voltage lvd ena ? le ? voltage select 2.0v -5% 2.0 +5% v lvd ena ? le ? voltage select 2.2v -5% 2.2 +5% lvd ena ? le ? voltage select 2.4v -5% 2.4 +5% lvd ena ? le ? voltage select 2. ? v -5% 2. ? +5% lvd ena ? le ? voltage select 3.0v -5% 3.0 +5% lvd ena ? le ? voltage select 3.3v -5% 3.3 +5% lvd ena ? le ? voltage select 3. ? v -5% 3. ? +5% lvd ena ? le ? voltage select 4.0v -5% 4.0 +5% i lvrlvdbg ope ? ating c ??? ent 3v lvd ena ? le ? lvr ena ? le ? vbgen=0 20 a 5v 20 25 3v lvd ena ? le ? lvr ena ? le ? vbgen=1 25 a 5v 25 30 t lvds lvdo sta ? le time ? o ? lvr ena ? le ? vbgen=0 ? lvd off on 15 s ? o ? lvr disa ? le ? vbgen=0 ? lvd off on 150 t lvr minim ? m low voltage width to reset 120 240 480 s t lvd minim ? m low voltage width to inte ??? pt ? 0 120 240 s i lvr additional c ??? ent fo ? lvr ena ? le lvd disa ? le ? vbgen=0 20 a
rev. 1.20 34 ?e???a?? 1?? 201? rev. 1.20 35 ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu sl aa ts cs m t ma u dd cs i lvd additional c ??? ent fo ? lvd ena ? le lvr disa ? le ? vbgen=0 25 a ta=25 c all measurement is under cn input oltage = (v dd d uhpd vd s pete et cntn mn m unt v dd cntn v dd compa ? ato ? ope ? ating voltage 2.2 5.5 v i cmp compa ? ato ? ope ? ating c ??? ent 3v 200 a 5v 200 v os compa ? ato ? inp ? t offset voltage 3v -10 +10 mv 5v -10 +10 v hys h ? ste ? esis width 3v h ? ste ? esis disa ? le cmpnhyen =0 0 0 5 mv h ? ste ? esis ena ? le cmpnhyen= 1 12 24 3 ? 5v h ? ste ? esis disa ? le cmpnhyen =0 0 0 5 mv h ? ste ? esis ena ? le cmpnhyen =1 20 40 ? 0 v cm inp ? t common mode voltage range 3v v ss v dd -1.4 v 5v v ss v dd -1.4 a ol compa ? ato ? open loop gain 3v ? 0 80 db 5v ? 0 80 t pd compa ? ato ? response time 2.2v~5.5v with 10mv ove ? d ? ive 2 s 3v with 100mv ove ? d ? ive (note) 200 400 ns 5v 1rwh 0hdvxuhg zlwk ?rpsdudwru rqh lqsxw slq dw 9 cm = (v dd oh h hu s s udv iup ss cm p u iup dd cm p
rev. 1.20 3 ? ? e ??? a ?? 1 ?? 201 ? rev. 1.20 3? ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu usb elal chaass ta=25c s?m?ol pa?amete? test conditions min. t?p. max. unit v dd conditions i dd ope ? ating c ??? ent (usb) 3v f sys =f pll = ? mhz ? no load ? usb and pll on ? othe ? pe ? iphe ? als off 4.5 9 ma 5v 9.5 15 3v f sys =f pll =12mhz ? no load ? usb and pll on ? othe ? pe ? iphe ? als off 5 10 ma 5v 10.5 1 ? 5v f sys =f pll =1 ? mhz ? no load ? usb and pll on ? othe ? pe ? iphe ? als off 11 18 ma i sus s ? spend c ??? ent (usb) (idle0 mode) 5v f h off ? f sub =f lirc on ? no load ? mcu powe ? ed down ? usb and pll on ? othe ? pe ? iphe ? als off ? susp2=0 3 ? 0 450 a 5v f h off ? f sub =f lirc on ? no load ? mcu powe ? ed down ? usb and pll on ? othe ? pe ? iphe ? als off ? susp2=1 240 330 a v v33o 3.3v reg ? lato ? o ? tp ? t voltage 5v i v33o = ? 0ma 3.0 3.3 3. ? v r udp p ? ll-high resistance of udp to v33o 3.3v -5% 1.5 +5% k p ? ll-high resistance of udp to ubus 5v rctrl=1 5.9 9.2 12.5 k r udpn p ? ll-high resistance of udp/udn to ubus 5v pu=1 300 ? 50 1000 k r pl p ? ll-low resistance of ubus 5v susp2=1 ? rubus=0 0.5 1 1.5 m r od p ? ll-high resistance of od0/od1 to vdd 5v ums[2:0]=001b 2 4. ? 8 k i ol_od sink c ??? ent of od0/od1 5v ums[2:0]=001b ? v ol =0.1v dd 8 12 ma v ih inp ? t high voltage of od0/od1 5v ums[2:0]=001b ? od1o/od0o=11b 2 5 v v il inp ? t low voltage of od0/od1 5v ums[2:0]=001b ? od1o/od0o=11b 0 0.8 v 1rwh )ru ? sus d udp d uhvvu vo h hh hhh 1 s d 1 cntnt cent d de et ctet ta=25c s?m?ol pa?amete? test conditions min. t?p. max. unit v dd conditions v dd constant c ??? ent led d ? ive ? ope ? ating voltage 2. 7 5.5 v pwm fo ? rgb led ope ? ating voltage 2. ? 5.5 v i ccs additional c ??? ent fo ? constant c ??? ent ?? nction ena ? le 3v r ext =open ? ccon=off 1. ? 2.3 ma r ext =1500, ccon=off 3.5 4 r ext =620, ccon=off 5.5 ? 5v r ext =open ? ccon=off 2 2.8 ma r ext =1500, ccon=off 4 4.8 r ext =620, ccon=off ? ? .8 i cco ccon o ? tp ? t sink c ??? ent c ??? ent ? ange 8 ? 0 ma acc ? ccon o ? tp ? t c ??? ent acc ?? ac ? r ext =1800 - ? + ? % di cco c ??? ent skew (channel) 3v/5v i ccon =30ma ? v ccon =0. ? v 1.5 3 % c ??? ent skew (ic) 3v/5v i ccon =30ma ? v ccon =0. ? v 3 ? %
rev. 1.20 3? ?e???a?? 1?? 201? rev. 1.20 3 ? ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu sl aa ts cs m t ma u dd cs %/dv cco o ? tp ? t c ??? ent vs. o ? tp ? t voltage reg ? lation 3v/5v v ccon =0. ? v~3.0v ? i ccon =30ma 0.1 %/v %/dv dd o ? tp ? t c ??? ent vs. s ? ppl ? voltage reg ? lation v dd =2. ? v~5.5v ? v ccon =0. ? v 1.0 5.0 %/v note: %/dv cco = {[i ccon (at v ccon =3.0v) - i ccon (at v ccon =0.7v)] / i ccon (at v ccon =1.5v)} 100% / (3.0v-0.7v) %/dv dd = {[i ccon (at v dd =5.5v) - i ccon (at v dd =2.7v)] / i ccon (at v dd =4v)} 100% / (5.5v-2.7v) the r ext should be a precision resistance with an error of 1%. ta=25c s?m?ol pa?amete? test conditions min. t?p. max. unit v dd conditions v por v dd sta ? t voltage to ens ?? e powe ? -on reset 100 mv rr por v dd rising rate to ens ?? e powe ? -on reset 0.035 v/ms t por minim ? m time fo ? v dd sta ? s at v por to ens ?? e powe ? -on reset 1 ms v dd t por rr por v por time s?stem a?chitect??e a key factor in the high-performan ce features of the holtek range of microcontrollers is attributed to their internal system architecture . the devices take advantage of the usual features found within risc microcontrollers providing increased speed of operation and enhanced performance. the pipelining scheme is implemented in such a way that instruction fetching and instruction execution are overlapped, hence instructions are ef fectively executed in one or two cycles for most of the standard or extend ed instructions respectively . the exceptions to this are branch or call instructions which need one more cycle. an 8-bit wide alu is used in practically all instruction set operations, which carries out arithmetic operations, logic operations, rotation, increment, decrement, branch decisions, etc. the internal data path is simplified by moving data through the accumulator and the alu. certain internal registers are implemented in the data memory and can be directly or indirectly addresse d. the simple addressi ng methods of these registers along with additi onal architectural features ensure that a minimum of external components is required to provide a functional i/o and a/d control system with maximum reliability and flexibility . this makes the devices suitable for low-cost, high-volume production for controller applications. the main system clock, derived from either a hxt , hirc or lirc oscillator is subdivided into four internally generated non-overlapping clocks, t1~t4. the program counter is incremented at the beginning of the t1 clock during which time a new instruction is fetched. the remaining t2~t4 clocks carry out the decoding and execution functions. in this way , one t1~t4 clock cycle forms
rev. 1.20 38 ? e ??? a ?? 1 ?? 201 ? rev. 1.20 39 ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu one instruction cycle. although the fetching and execution of instructio ns takes place in consecutive instruction c ycles, t he pi pelining st ructure of t he m icrocontroller e nsures t hat i nstructions a re effectively executed in one instruction cycle. the exception to this are instructions where the contents of the program counter are changed, such as subroutine calls or jumps, in which case the instruction will take one more instruction cycle to execute. for instructions involving branches, such as jump or call instructions, two machine cycles are required to complete instruction execution. an extra cycle is required as the program takes one cycle t o frst obt ain t he a ctual j ump or c all a ddress a nd t hen a nother c ycle t o a ctually e xecute t he branch. the requirement for this extra cycle should be taken into account by programmers in timing sensitive applications. ?etch inst. (pc) (s?stem clock) f sys phase clock t1 phase clock t2 phase clock t3 phase clock t4 p?og?am co?nte? pc pc+1 pc+2 pipelining exec?te inst. (pc-1) ?etch inst. (pc+1) exec?te inst. (pc) ?etch inst. (pc+2) exec?te inst. (pc+1) s?stem clocking and pipelining ?etch inst. 1 1 mov a?[12h] 2 call delay 3 cpl [12h] 4 : 5 : ? delay: nop exec?te inst. 1 ?etch inst. 2 exec?te inst. 2 ?etch inst. 3 ?l?sh pipeline ?etch inst. ? exec?te inst. ? ?etch inst. ? inst??ction ?etching p?og?am co?nte? during pro gram e xecution, t he progr am co unter i s use d t o ke ep t rack of t he a ddress of t he next instruction to be executed. it is automatically incremented by one each time an instruction is executed except for instructions, such as jmp or call that demand a jump to a non- consecutive program memory address. as the ht66fb574 and HT66FB576 devices memory capacity is greater than 8k words, the program memory address may be located in a certain program memory bank which is selected by the program memory bank pointer register pbp . only the lower 8 bits, known as the program counter low register , are directly addressable by the application program. when executi ng instructions re quiring jumps to non-consecutive addresses suc h as a jump instruction, a subrout ine c all, i nterrupt or re set, e tc., t he m icrocontroller m anages progra m c ontrol by loading the required address into the program counter . for conditional skip instructions, once the condition has been met, the next instruction, which has already been fetched during the present instruction execut ion, is discarded and a dummy cycle takes its place while the correct instruction is obtained.
rev. 1.20 38 ?e???a?? 1?? 201? rev. 1.20 39 ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu d a c a c hh b cl rs ht ??? b5 ? 2 pc12~pc8 pcl ? ~pcl0 ht ??? b5 ? 4 pbp0 ? pc12~pc8 ht ??? b5 ?? pbp1~pbp0 ? pc12~pc8 p?og?am co?nte? the lower byte of the program counter , known as the program counter low register or pcl, is available for program control and is a readable and writeable register . by transferring data directly into t his r egister, a sh ort p rogram j ump c an b e e xecuted d irectly; h owever, a s o nly t his l ow b yte is available for manipulation, the jumps are limited to the present page of memory that is 256 locations. when such program jumps are executed it should also be noted that a dummy cycle will be inserted. manipulating the pcl register may cause program branching, so an extra cycle is needed to pre-fetch. this is a special part of the memory which is used to save the contents of the program counter only . the st ack i s o rganized i nto 1 2 l evels a nd n either p art o f t he d ata n or p art o f t he p rogram sp ace, and is neither readable nor writeable. the activated level is indexed by the stack pointer , and is neither readable nor writeable. at a subroutine call or interrupt acknowledge signal, the contents of the program counter are pushed onto the stack. at the end of a subroutine or an interrupt routine, signaled by a return instruction, ret or reti, the program counter is restored to its previous value from the stack. after a device reset, the stack pointer will point to the top of the stack. if the stack is full and an enabled interrupt takes place, the interrupt request fag will be recorded but the acknowledge signal will be inhibited. when the stack pointer is decremented, by ret or reti, the interrupt will be serviced. this feature prevents stack overfow allo wing the programmer to use the struct ure more easily . however , when the stack is full, a call subroutine instruction can still be execu ted which will result in a stack overfow . precautions should be taken to avoid such cases which might cause unpredictable program branching. if the stack is overfow, the frst program counter save in the stack will be lost. stack pointe? stack level 2 stack level 1 stack level 3 : : : stack level 12 p?og?am memo?? p?og?am co?nte? bottom of stack top of stack a?ithmetic and logic unit C alu the arith metic-logic unit or alu is a critical area of the microcontrol ler that carries out arithmetic and logic operations of the instructi on set. connected to the main micro controller data bus, the alu receives related ins truction codes and performs the required arithmetic or logical operations after which the result will be placed in the specifed register . as these alu calculation or operations may result in carry , borrow or other status changes, the status register will be correspondingly updated to refect these changes. the alu supports the following functions:
rev. 1.20 40 ? e ??? a ?? 1 ?? 201 ? rev. 1.20 41 ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ? arithmetic operations: add, addm, adc, adcm, sub, subm, sbc, sbcm, daa, ladd, laddm, ladc, ladcm, lsub, lsubm, lsbc, lsbcm, ldaa ? logic operations: and, or, xor, andm, orm, xorm, cpl, cpla, land, landm, lor, lorm, lxor, lxorm, lcpl, lcpla ? rotation: rra, rr, rrca, rrc, rla, rl, rlca, rlc, lrra, lrr, lrrca, lrrc, lrla, lrl, lrlca, lrlc ? increment and decrement: inca, inc, deca, dec, linca, linc, ldeca, ldec ? branch decision: jmp, sz, sza, snz, siz, sdz, siza, sdza, call, ret, reti, lsnz, lsz, lsza, lsiz, lsiza, lsdz, lsdza the program memory is the location where the user code or program is stored. for these devices the program memory is flash type, which means it can be programmed and re-programmed a large number of times, allowing the user the convenience of code modifcation on the same device. by using the appropriate programming tools, these flash devices of fer users the flexibility to conveniently debug and develop their applications while also of fering a means of feld programming and updating. ht ??? b5 ? 2 8k1 ? 0 ht ??? b5 ? 4 1 ? k1 ? 0~1 ht ??? b5 ?? 32k1 ? 0~3 st??ct??e the program memory has a capacit y of 8k16 to 32k16 bits. the program memory is addressed by the program counter and also contains data, table information and interrupt entries. t able data, which c an b e se tup i n a ny l ocation wi thin t he pro gram me mory, i s a ddressed b y a se parate t able pointer register.
rev. 1.20 40 ?e???a?? 1?? 201? rev. 1.20 41 ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu reset bank 0 inte???pt vecto?s bank 1 bank 2 bank 3 5???h ????h 4000h ?000h ht???b5?? 3???h 2000h reset bank 0 inte???pt vecto?s bank 1 ht???b5?4 0000h 0004h 003ch 1???h reset inte???pt vecto?s 1? ?its ht???b5?2 1? ?its 1? ?its bank 0 p?og?am memo?? st??ct??e special vecto?s within the program memory , certai n locations are reserved for the reset and interrupts. the location 0000h is reserved for use by these devices reset for program initialisation. after a device reset is initiated, the program will jump to this location and begin execution. any location within the program memory can be defned as a look-up table where programmers can store fxed data. t o use the look-up table, the table pointer must frst be setup by placing the address of the look up data to be retrieved in the table pointer register , tblp and tbhp . these registers defne the total address of the look-up table. after se tting u p t he t able p ointer, t he t able d ata c an b e r etrieved f rom t he pr ogram me mory u sing the corresponding table read instruction such as t abrd [m] when the memory [m] is located in sector 0. if the memory [m] is located in other sectors, the data can be retrieved from the program memory using the corresponding extended table read instruction such as l tabrd [m]. when the instruction is exec uted, the lower order table byte from the program memory will be transferred to the u ser d efned da ta me mory r egister [ m] a s sp ecifed i n t he i nstruction. t he h igher o rder t able d ata byte from the program memory will be transferred to the tblh special register. the accompanying diagram illustrates the addressing data fow of the look-up table. last page o? tbhp registe? add?ess tblp registe? data 1? ?its p?og?am memo?? registe? tblh use? selected registe? high b?te low b?te
rev. 1.20 42 ? e ??? a ?? 1 ?? 201 ? rev. 1.20 43 ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu tal a eal the following example shows how the table pointer and table data is defned and retrieved from the microcontroller. this example uses raw table data located in the program memory which is stored there using the org statement. the value at this org statement is 1f00h which is located in rom bank 3 and refers to the start address of the last page within the 32k words program memory of the HT66FB576 device if the isp bootloader provided by holtek ide tool is not used. the table pointer low byte register is setup here to have an initial value of 06h. this will ensure that the frst data read from the data table will be at the program memory address 7f06h or 6 locations after the start of the last page. note that the value for the table pointer is referenced to the frst address of the present page pointed by the tbhp register if the t abrd [m] instruction is being used. the high byte of the table data which in this case is equal to zero will be transferred to the tblh register automatically when the t abrd [m] instruction is executed. because the tblh register is a read/write register and can be restored, care should be taken to ensure its protection if both the main routine and interrupt s ervice routine us e table read instructions. if using the table read instructions, the interrupt service routines may change the value of the tblh and subsequently cause errors if used again by the main routine. as a rule it is recommended that simultaneous use of the table read instructions should be avoided. however , in situations where simultaneous use cannot be avoided, the interrupts should be disabled prior to the execution of any main routine table-read instructions. note that all table related instructions require two instruction cycles to complete their operation. rombank 3 code3 ds .section 'data' tempreg1 db ? ; temporary register#1 tempreg2 db ? ; temporary register#2 : : code0 .section 'code' mov a,06h ; initialise table pointer - note that this address is referenced mov tblp,a ; to the last page or the page that tbhp pointed mov a,7fh ; initialise high table pointer mov tbhp,a : : tabrd tempreg1 ; transfers value in table referenced by table pointer ; data at program memory address 7f06h transferred to ; tempreg1 and tblh dec tblp ; reduce value of table pointer by one tabrd tempreg2 ; transfers value in table referenced by table pointer ; data at program memory address 7f05h transferred to ; tempreg2 and tblh ; in this example the data 1ah is transferred to ; tempreg1 and data 0fh to tempreg2 ; the value 00h will be transferred to the high byte register tblh : : code3 .section 'code' org 1f00h ; sets initial address of last page dc 00ah,00bh,00ch,00dh,00eh,00fh,01ah,01bh
rev. 1.20 42 ?e???a?? 1?? 201? rev. 1.20 43 ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu c a c the p rovision o f fl ash t ype pr ogram me mory p rovides t he u ser wi th a m eans o f c onvenient a nd easy upgrades and modifcations to their programs on the same device. as an additional convenience, holtek has provided a means of programming the microcontroller in- circuit using a 4-pin interface. this provides manufacturers with the possibility of manufacturing their circuit boards complete with a programmed or un-programmed microcontroller , and then programming o r u pgrading t he p rogram a t a l ater st age. t his enables product m anufacturers to e asily keep thei r manufa ctured products supplied with the latest program releases without removal and re- insertion of the device. icpda udn p ? og ? amming se ? ial data/add ? ess icpck res p ? og ? amming clock vdd vdd & ubus powe ? s ? ppl ? vss vss g ? o ? nd the prog ram me mory a nd e eprom da ta me mory c an be pr ogrammed se rially i n-circuit usi ng this 4-wi re inte rface. dat a is downloaded and upl oaded serial ly on a single pin wit h an additi onal line for the clock. t wo additional lines are required for the power supply and one line for the reset. the techn ical deta ils regarding the in-circuit programming of the device is beyond the scope of this document and will be supplied in supplementary literature. during t he pr ogramming p rocess, t he use r m ust t ake c are of t he udn a nd res pi ns fo r da ta a nd clock programming purposes to ensure that no other outputs are connected to these two pins. * w?ite?_vdd icpda icpck w?ite?_vss to othe? ci?c?it vdd udn res vss w?ite? connecto? signals mcu p?og?amming pins ubus note: * may be resistor or capacitor . the resistance of * must be greater than 300 or the capacitance of * must be less than 1nf. there are ev chips named ht66vb572/ht66vb574/ht66vb576 which are used to emulate the ht66fb572/ht66fb574/HT66FB576 devices. the ev chip device also provides an on- chip debug function to debug the real mcu device during the development process. the ev chip and the real m cu device are almos t functionally compatible except for o n-chip d ebug function. users can use the ev chip device to emulate the real chip device behavior by connecting the ocdsda and ocdsck pins to the holtek ht -ide development tools. the ocdsda pin is the ocds data/address input/output pin while the ocdsck pin is the ocds clock input pin. when users use the ev chip for debugging, other functions which are shared with the ocdsda
rev. 1.20 44 ? e ??? a ?? 1 ?? 201 ? rev. 1.20 45 ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu and ocdsck pins in the devices will have no ef fect in the ev chip. however , the two ocds pins which are pin-shared with the icp programming pins are still used as the flash memory programming pins for icp . for more detailed ocds information, refer to the corresponding document named holtek e-link for 8-bit mcu ocds users guide. ocdsda ocdsda on-chip de ?? g s ? ppo ? t data/add ? ess inp ? t/o ? tp ? t ocdsck ocdsck on-chip de ?? g s ? ppo ? t clock inp ? t vdd vdd powe ? s ? ppl ? vss vss g ? o ? nd in application p?og?amming C iap flash type program memory provides the user with a means of convenient and easy upgrades and modifcations to their programs on the same device. the provision of not only an iap function but also an additional isp function of fers users the convenience of flash memory multi-programming features. the convenience of the iap function is that it can execute the updated program procedure using its internal frmware, without requiring an external program w riter or pc. in addition, the iap interface can also be any type of communication protocol, such as uar t or usb, using i/o pins. regarding the internal frmware, the user can select versions provided by holtek or create their own. the following section illustrates the procedures regarding how to implement the iap frmware. the flash memory erase and w rite operations are carried out in a page format while the read operation is carrie d out in a word format. the page size and write buf fer size are both assigned with a capacit y of 32 or 64 words respectively . note that the erase operation should be executed before the w rite operation is executed. when the flash memory erase/w rite function is successfully enabled, the cfwen bit will be set high. when the cfwen bit is set high, the data can be written into the write buf fer. the fwt bit is used to initiate the write process and then indicate the write operation status. this bit is set high by application programs to initiate a write process and will be cleared by hardware if the write process is fnished. the read operation can be carried out by executing a specifc read procedure. the frden bit is used to enable the read function and the frd bit is used to initiate the read process by application programs and then indicate the read operation status. when the read process is fnished, this bit will be cleared by hardware. ht ??? b5 ? 2 8k 1 ? 32 wo ? ds/page 32 wo ? ds/time 1 wo ? d/time 32 wo ? ds ht ??? b5 ? 4 1 ? k 1 ? ? 4 wo ? ds/page ? 4 wo ? ds/time 1 wo ? d/time ? 4 wo ? ds ht ??? b5 ?? 32k 1 ? iap ope?ation ?o?mat
rev. 1.20 44 ?e???a?? 1?? 201? rev. 1.20 45 ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu eas a frh frl 75 frl 4 0 0000 0000 000 x xxxx 1 0000 0000 001 x xxxx 2 0000 0000 010 x xxxx 3 0000 0000 011 x xxxx 4 0000 0001 100 x xxxx : : : : : : : : 254 0001 1111 110 x xxxx 255 0001 1111 111 x xxxx x: dont ca ? e ht???b5?2 e?ase page n?m?e? and selection e?ase page ?arh ?arl [?:?] ?arl [5:0] 0 0000 0000 00 xx xxxx 1 0000 0000 01 xx xxxx 2 0000 0000 10 xx xxxx 3 0000 0000 11 xx xxxx 4 0000 0001 00 xx xxxx : : : : : : : : 254 0011 1111 10 xx xxxx 255 0011 1111 11 xx xxxx x: dont ca ? e ht???b5?4 e?ase page n?m?e? and selection e?ase page ?arh ?arl [?:?] ?arl [5:0] 0 0000 0000 00 xx xxxx 1 0000 0000 01 xx xxxx 2 0000 0000 10 xx xxxx 3 0000 0000 11 xx xxxx 4 0000 0001 00 xx xxxx : : : : : : : : 510 0111 1111 10 xx xxxx 511 0111 1111 11 xx xxxx x: dont ca ? e ht???b5?? e?ase page n?m?e? and selection
rev. 1.20 4 ? ? e ??? a ?? 1 ?? 201 ? rev. 1.20 4? ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ?lash memo?? w?ite b?ffe? ?d0h ?d0l clwb ?lash memo?? ?d0h ?d0l read data wo?d to ?d0h/?d0l w?ite page data to ?d0l/?d0h (32 wo?ds/page) ?arh/?arl =a12~a0 ?arh/?arl =a12~a0 w?ite ??ffe? add?. =a4~a0 wo?d m page n note: n is specified ?? a12~a5 note: m is specified ?? a12~a0 page add?. =a12~a5 11111? 00000? ?lash memo?? iap read/w?ite st??ct??e C ht???b5?2 ?lash memo?? w?ite b?ffe? ?d0h ?d0l clwb ?lash memo?? ?d0h ?d0l read data wo?d to ?d0h/?d0l w?ite page data to ?d0l/?d0h (?4 wo?ds/page) ?arh/?arl =a13~a0 ?arh/?arl =a13~a0 w?ite ??ffe? add?. =a5~a0 wo?d m page n note: n is specified ?? a13~a? note: m is specified ?? a13~a0 page add?. =a13~a? 111111? 000000? ?lash memo?? iap read/w?ite st??ct??e C ht???b5?4 ?lash memo?? w?ite b?ffe? ?d0h ?d0l clwb ?lash memo?? ?d0h ?d0l read data wo?d to ?d0h/?d0l w?ite page data to ?d0l/?d0h (?4 wo?ds/page) ?arh/?arl =a14~a0 ?arh/?arl =a14~a0 w?ite ??ffe? add?. =a5~a0 wo?d m page n note: n is specified ?? a14~a? note: m is specified ?? a14~a0 page add?. =a14~a? 111111? 000000? ?lash memo?? iap read/w?ite st??ct??e C ht???b5?? w?ite b?ffe? ?kh zulwh exi ihu lv xvhg wr vwruh wkh zulwwhq gdwd whpsrudulo zkhq h[h?xwlqj wkh zulwh rshudwlrq ?kh : ulwh %xi ihu ?dq eh oohg zlwk zulwwhq gdwd diwhu wkh )odvk 0hpru (udvh: ulwh )xq?wlrq kdv ehhq vx??hvvixoo hqdeohg e h[h?xwlqj wkh )odvk 0hpru (udvh: ulwh )xq?wlrq (qdeoh sur?hgxuh ?kh zulwh exi ihu ?dq eh ?ohduhg e ?rqjxulqj wkh &/ :% elw lq wkh )5&5 uhjlvwhu ?kh &/ :% elw ?dq eh vhw kljk wr hqdeoh wkh &ohdu : ulwh %xi ihu sur?hgxuh :khq wkh sur?hgxuh lv qlvkhg wklv elw zloo eh ?ohduhg wr orz e wkh kdugzduh ?w lv uh?rpphqghg wkdw wkh zulwh exi ihu vkrxog eh ?ohduhg e vhwwlqj wkh &/ :% elw kljk ehiruh wkh zulwh exi ihu lv xvhg iru wkh uvw wlph ru zkhq wkh gdwd lq wkh zulwh exiihu lv xsgdwhg
rev. 1.20 4? ?e???a?? 1?? 201? rev. 1.20 4 ? ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu the write buf fer size is 32 or 64 words corresponding to a page respectively . the write buf fer address is mapped to a specifc fash memory page specifed by the memory address bits, a12~a5, a13~a6 or a14~a6. the data written into the fd0l and fd0h registers will be loaded into the write buf fer. when data is written into the high byte data register , fd0h, it will result in the data stored in the high and low byte data registers both being written into the write buf fer. it will also cause t he f lash m emory a ddress t o b e i ncremented b y o ne, a fter wh ich t he n ew a ddress wi ll b e loaded into the f arh and f arl address registers. when the fash mem ory address reaches the page boundary, 1 1111b of a page with 32 words or 1 11111b of a page with 64 words, the address will now not b e i ncremented b ut wi ll st op a t t he l ast a ddress o f t he p age. at t his p oint a n ew p age a ddress should be specifed for any other erase/write operations. after a write process is fnished, the write buffer will automatically be cleared by the hardware. note that the write buf fer should be clea red manually by the application program when the data written into the fash memory is incorrect in the data verifcation step. the data should again be written into the write buf fer after the write buf fer has been cleared when the data is found to be incorrect during the data verifcation step. there are two address registers, four 16-bit data registers and two control registers. the address and da ta hi gh by te re gisters t ogether wi th t he c ontrol re gisters a re l ocated i n se ctor 1 whi le ot her registers a re l ocated i n sec tor 0. re ad a nd w rite ope rations t o t he fla sh m emory a re c arried out using 16-bit data operations using the address and data registers and the control register . several registers control the overall operati on of the internal flash program memory . the address registers are name d f arl and f arh, the data registers are named fdnl and fdnh and the control registers are named fcr and frcr. as the f arl and fdnl registers are located in sector 0, they can be d irectly a ccessed i n t he sa me wa y a s a ny o ther sp ecial fu nction r egister. t he f arh, fdn h, fcr and frcr registers, being located in sector 1, can be addressed directly only using the corresponding extended instructions or can be read from or written to indirectly using the mp1h/ mp1l or mp2h/mp2l memory pointer pairs and indirect addressing register, iar1 or iar2. ? cr c ? wen ? mod2 ? mod1 ? mod0 bwt ? wt ? rden ? rd ? rcr d ? d ? ?e d4 clwb ? arl a ? a ? a5 a4 a3 a2 a1 a0 ? arh (ht ??? b5 ? 2) a12 a11 a10 a9 a8 ? arh (ht ??? b5 ? 4) a13 a12 a11 a10 a9 a8 ? arh (ht ??? b5 ?? ) a14 a13 a12 a11 a10 a9 a8 ? d0l d ? d ? d5 d4 d3 d2 d1 d0 ? d0h d15 d14 d13 d12 d11 d10 d9 d8 ? d1l d ? d ? d5 d4 d3 d2 d1 d0 ? d1h d15 d14 d13 d12 d11 d10 d9 d8 ? d2l d ? d ? d5 d4 d3 d2 d1 d0 ? d2h d15 d14 d13 d12 d11 d10 d9 d8 ? d3l d ? d ? d5 d4 d3 d2 d1 d0 ? d3h d15 d14 d13 d12 d11 d10 d9 d8 iap registe?s list
rev. 1.20 48 ? e ??? a ?? 1 ?? 201 ? rev. 1.20 49 ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ? name a ? a ? a5 a4 a3 a2 a1 a0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 flash memory address bit 7 ~ bit 0 ? name a12 a11 a10 a9 a8 r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 bit 7~5 unimplemented, read as 0 bit 4~0 flash memory address bit 12 ~ bit 8 ? name a13 a12 a11 a10 a9 a8 r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7~6 unimplemented, read as 0 bit 5~0 flash memory address bit 13 ~ bit 8 ? name a14 a13 a12 a11 a10 a9 a8 r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 bit 7 unimplemented, read as 0 bit 6~0 flash memory address bit 14 ~ bit 8 ? name d ? d ? d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 the frst flash memory data word bit 7 ~ bit 0 note that data written into the low byte data register fd0l will only be stored in the fd0l register and not loaded into the lower 8-bit write buffer.
rev. 1.20 48 ?e???a?? 1?? 201? rev. 1.20 49 ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ? name d15 d14 d13 d12 d11 d10 d9 d8 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 the frst flash memory data word bit 15 ~ bit 8 note that when 8-bit data is written into the high byte data register fd0h, the whole 16-bits of data stored in the fd0h and fd0l registers will simultaneo usly be loaded into the 16-bit write buf fer after which the contents of the flash memory address register pair, farh and farl, will be incremented by one. ? name d ? d ? d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 the second flash memory data word bit 7 ~ bit 0 ? name d15 d14 d13 d12 d11 d10 d9 d8 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 the second flash memory data word bit 15 ~ bit 8 ? name d ? d ? d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 the third flash memory data word bit 7 ~ bit 0 ? name d15 d14 d13 d12 d11 d10 d9 d8 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 the third flash memory data word bit 15 ~ bit 8 ? name d ? d ? d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 the fourth flash memory data word bit 7 ~ bit 0
rev. 1.20 50 ? e ??? a ?? 1 ?? 201 ? rev. 1.20 51 ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ? name d15 d14 d13 d12 d11 d10 d9 d8 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 the fourth flash memory data word bit 15 ~ bit 8 ? name c ? wen ? mod2 ? mod1 ? mod0 bwt ? wt ? rden ? rd r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 cfwen : flash memory erase/write function enable control 0: flash memory erase/write function is disabled 1: flash memory erase/write function has been successfully enabled when this bit is cleared to 0 by application program, the flash memory erase/write function is disabled. note that this bit cannot be set high by application programs. writing a 1 i nto t his b it r esults i n n o a ction. t his b it i s u sed t o i ndicate t he fl ash memory erase/write function status. when this bit is set to 1 by the hardware, it means that the flash memory erase/write function is enabled successfully . otherwise, the flash memory erase/write function is disabled if the bit is zero. bit 6~4 fmod2~fmod0 : flash memory mode selection 000: w rite mode 001: page erase mode 010: reserved 011: read mode 100: reserved 101: reserved 110: flash memory erase/write function enable mode 111: reserved these bits are used to select the flash memory operation modes. note that the flash memory e rase/write func tion e nable mode shoul d fi rst be suc cessfully e nabled before the erase or w rite flash memory operation is executed. bit 3 bwt : flash memory erase/write function enable procedure t rigger 0: erase/write function enable procedure is not triggered or procedure timer times out 1: erase/write function enable procedure is triggered and procedure timer starts to count this bit is used to activate the fash memory erase/w rite function enable procedure and an internal tim er. it is set by the application programs and cleared by the hardware after 1ms when the internal timer times out. the correct patterns should be written into the fd1l/fd1h, fd2l/fd2h and fd3l/fd3h register pairs respectively within the internal timer time-out period of 1ms. bit 2 fwt : flash memory write initiate control 0: do not initiate flash memory write or indicating that a flash memory write process has completed 1: initiate flash memory write process this bit is set by software and clear ed by the hardware when the flash memory write process has completed. note that all cpu operations will temporarily cease when this bit is set to 1.
rev. 1.20 50 ?e???a?? 1?? 201? rev. 1.20 51 ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu bit 1 : flash memory read enable control 0: flash memory read disable 1: flash memory read enable this is the fla sh mem ory read enabl e bit which must be set high before any fla sh memory rea d opera tions a re c arried out. cl earing t his bit t o z ero wi ll i nhibit fl ash memory read operations. bit 0 : flash memory read initiate control 0: do not initiate flash memory read or indicating that a flash memory read process has completed 1: initiate flash memory read process this bit is set by software and cleared by the hardware when the flash memory read process has completed. note that all cpu operations will temporarily cease when this bit is set to 1. note: the fwt , frden and frd bits cannot be set to "1" at the same time with a single instruction. ? frcr register bit 7 6 5 4 3 2 1 0 name d ? d ? d4 clwb r/w r/w r r/w r/w por 0 0 0 0 bit 7 : reserved bit, cannot be used and must be fxed at 0 bit 6 : reserved bit bit 5 unimplemented, read as 0 bit 4 : reserved bit, cannot be used and must be fxed at 0 bit 3~1 unimplemented, read as 0 bit 0 : flash memory w rite buffer clear control 0: do not initiate a w rite buffer clear process or indicating that a w rite buffer clear process has completed 1: initiate w rite buffer clear process this bi t i s se t by soft ware a nd c leared by ha rdware whe n t he w rite buf fer cl ear process has completed. flash memory erase/write flow it is important to understand the flash memory erase/w rite fow before the flash memory contents are updated. users can refer to the corresponding operation procedure s when developing their iap program to ensure that the fash memory contents are correctly updated. ? flash memory erase/write flow descriptions 1. ac tivate t he fl ash me mory e rase/write func tion e nable proc edure fi rst. w hen t he fl ash memory erase/w rite function is successfully enabled, the cfwen bit in the fcr register will automatically be set high by hardw are. after this, erase or w rite operations can be executed on the fl ash m emory. refe r t o t he fla sh me mory era se/write func tion ena ble proce dure for details. 2. confgure the fash memory address to select the desired erase page and then erase this page. 3. execut e a blank check operation to ensure whether the page erase operation is successful or not. the t abrd instruction should be executed to read the fash memory contents and to check if the contents is 0000h or not. if the fash memory page erase operation fails, users should go back to step 2 and execute the page erase operation again. 4. w rite data into the specifc page. refer to the flash memory w rite procedure for details.
rev. 1.20 52 ? e ??? a ?? 1 ?? 201 ? rev. 1.20 53 ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu 5. execut e the t abrd instructio n to read the fash memory contents and check if the written data is correct or not. if the data read from the fash memory is different from the written data, it means that the page write operation has failed. the cl wb bit should be set high to clear the write buf fer and then write the data into the specifc page again if the write operation has failed. 6. clear the cfwen bit to disable the flash memory erase/w rite function enable mode if the current page erase and w rite operations are complete if no more pages need to be erased or written. ?lash memo?? e?ase/w?ite ?low clea? c?wen ?it disa?le ?lash memo?? e?ase/w?ite ??nction end blank check page data =0000h? yes no ve?if? page data co??ect? yes no ?lash memo?? (page) w?ite p?oced??e (*) page e?ase ?lash memo?? ?lash memo?? e?ase/w?ite ??nction ena?le p?oced??e (*) (c?wen=1) set clwb ?it ?lash memo?? e?ase/w?ite ?low note: the flash memory erase/w rite function enable procedure and flash memory w rite procedure will be described in the following sections.
rev. 1.20 52 ?e???a?? 1?? 201? rev. 1.20 53 ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu flash m eas/ f eal the fl ash me mory e rase/write func tion e nable mode i s spe cially de signed t o pre vent t he fa sh memory contents from being wrongly modifed. in order to allow users to change the flash memory data using the iap control registers, users must frst enable the flash memory erase/write function. ? 1. w rite data 1 10 to the fmod [2:0] bits in the fcr register to select the flash memory erase/ write function enable mode. 2. set the bwt bit in the fcr register to 1 to activate the flash memory erase/w rite function. this will also activate an internal timer with a time-out period of 1ms. 3. w rite the correct data pattern into the flash data registers, fd1l~fd3l and fd1h~fd3h, within the time-out period of 1ms. the enable flash memory erase/write function data pattern is 00h, 0dh, c3h, 04h, 09h and 40h corresponding to the fd1l~fd3l and fd1h~fd3h registers respectively. 4. once the 1ms timer has timed out, the bwt bit will automatically be cleared to 0 by hardware regardless of the input data pattern. 5. if the written data pattern is incorrect, the flash memory erase/write function will not be enabled successfully and the above steps should be repeated. if the written data pattern is correct, the flash memory erase/write function will be enabled successfully. 6. once the flash memory erase/write function is enabled, the flash memory contents can be updated by executing the page erase and write operations using the iap control registers. 7. t o disable the flash memory erase/write function, the cfwen bit in the fcr register can be cleared. there is no need to execute the above procedure.
rev. 1.20 54 ? e ??? a ?? 1 ?? 201 ? rev. 1.20 55 ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ?lash memo?? e?ase/w?ite ??nction ena?le p?oced??e ?mod[2:0]=110 set bwt=1 ha?dwa?e sta?t a time? w?tie the following patte?n to ?lash data ?egiste? ?d1l=00h? ?d1h=04h ?d2l=0dh? ?d2h=09h ?d3l=c3h? ?d3h=40h is patte?n co??ect? c?wen=0 ?lash memo?? e?ase/w?ite ??nction disa?led no c?wen=1 ?lash memo?? e?ase/w?ite ??nction ena?led yes end is time? time-o?t bwt=0? no yes ?lash memo?? e?ase/w?ite ??nction ena?le p?oced??e
rev. 1.20 54 ?e???a?? 1?? 201? rev. 1.20 55 ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu flash m after the flash memory erase/write function has been successfully enabled as the cfwen bit is set high, the data to be written into the fash memory can be loaded into the write buf fer. the selected fash memory page data should be erased by properly confguring the iap control registers before the data write procedure is executed. the write buf fer size is 32 or 64 words respectively , known as a page, whose address is mapped to a specifc fash mem ory page specifed by the memory address bits, a12~a5, a13~a6 or a14~a6. it is important to ensure that the page where the write buf fer data is locat ed is the same one which the memory address bits, specify. ? the m aximum a mount of wri te da ta i s 32 or 64 words for e ach wri te ope ration. t he wri te buf fer address will be automatically increm ented by one when consecutive write operations are executed. the start address of a specifc page should frst be written into the f arl and f arh registers. then the data word should frst be written into the fd0l register and then the fd0h register . at the same time the write buf fer address will be incremented by one and then the next data word can be written into the fd0l and fd0h registers for the next address without modifying the address register pair , farh and f arl. when the write buf fer address reaches the page boundary the address will not be further incremented but will stop at the last address of the page. 1. activate the flash memory erase/w rite function enable procedure. check the cfwen bit value and then execute the erase/write operations if the cfwen bit is set high. refer to the flash memory erase/write function enable procedure for more details. 2. se t t he fmod fi eld t o 001 t o se lect t he e rase op eration. se t t he fw t bi t hi gh t o e rase t he desired page which is specifed by the f arh and f arl registers. w ait until the fwt bit goes low. 3. execute a blank check operation using the table read instruction to ensure that the erase operation has successfully completed. go to step 2 if the erase operation is not successful. go to step 4 if the erase operation is successful. 4. set the fmod feld to 000 to select the write operation. 5. setup the desired start address in the f arh and f arl registers. w rite the desired data words consecutively into the fd0l and fd0h registers within a page as specifed by their consecutive addresses. the maximum written data number is 32 or 64 words. 6. set the fwt bit high to write the data words from the write buf fer to the fash memory . w ait until the fwt bit goes low. 7. v erify the data using the table read instruction to ensure that the write operation has successfully completed. if the write operation has not successfully completed, set the cl wb bit high to clear the write buffer and then go to step 5. go to step 8 if the write operation is successful. 8. clear the cfwen bit low to disable the flash memory erase/write function.
rev. 1.20 5 ? ? e ??? a ?? 1 ?? 201 ? rev. 1.20 5? ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu w?ite ?lash memo?? ?lash memo?? e?ase/w?ite ??nction ena?le p?oced??e ?wt = 1 page e?ase ?arh = xxh? ?arl = xxh ?mod[2:0] = 001 ?wt = 1 ?wt = 0 ? yes no w?ite ?mod[2:0]= 000 clea? c?wen ?it end w?ite ?inish ? yes no w?ite data to w?ite b?ffe? ?d0l = xxh? ?d0h = xxh w?ite to b?ffe? ?inish? no w?ite anothe? page w?ite next data yes ?wt = 0 ? no yes ve?if? data with ta?le read inst??ction data co??ect ? no yes blank check with ta?le read inst??ction no blank check page data=0000h? set clwb ?it specif? ?lash memo?? add?ess ?arh = xxh? ?arl = xxh ?lash memo?? consec?tive w?ite p?oced??e note: when the fwt bit is set to 1 all cpu operations will temporarily cease.
rev. 1.20 5? ?e???a?? 1?? 201? rev. 1.20 5 ? ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ? the m ain d ifference b etween fl ash me mory c onsecutive a nd no n-consecutive w rite o perations is whether the data words to be written are located in consecutive addresses or not. if the data to be written is not loca ted in consecutive addresses the desired address should be re-assigned after a data word is successfully written into the flash memory. a two data word non-consecutive write operation is taken as an example here and described as follows: 1. activate the flash memory erase/w rite function enable procedure. check the cfwen bit value and then execute the erase/write operation if the cfwen bit is set high. refer to the flash memory erase/write function enable procedure for more details. 2. se t t he fmod fi eld t o 001 t o se lect t he e rase op eration. se t t he fw t bi t hi gh t o e rase t he desired page which is specifed by the f arh and f arl registers. w ait until the fwt bit goes low. 3. execute a blank check operation using the table read instruction to ensure that the erase operation has successfully completed. go to step 2 if the erase operation is not successful. go to step 4 if the erase operation is successful. 4. set the fmod feld to 000 to select the write operation. 5. setup the desired address addr1 in t he farh and frarl registers. w rite the desired data word data1 frst into the fd0l register and then into the fd0h register. 6. set the fwt bit high to transfer the data word from the write buf fer to the fash memory . w ait until the fwt bit goes low. 7. v erify the data using the table read instruction to ensure that the write operation has successfully completed. if t he wri te operat ion ha s not suc cessfully c ompleted, set t he cl wb bi t hi gh t o c lear t he wri te buffer and then go to step 5. go to step 8 if the write operation is successful. 8. setup the desired address addr2 in t he farh and frarl registers. w rite the desired data word data2 frst into the fd0l register and then into the fd0h register. 9. set the fwt bit high to transfer the data word from the write buf fer to the fash memory . w ait until the fwt bit goes low. 10. v erify the data using the table read instruction to ensure that the write operation has successfully completed. if the write operation has not successfully completed, set the cl wb bit high to clear the write buffer and then go to step 8. go to step 11 if the write operation is successful. 11. clear the cfwen bit low to disable the flash memory erase/write function.
rev. 1.20 58 ? e ??? a ?? 1 ?? 201 ? rev. 1.20 59 ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu w?ite ?lash memo?? ?lash memo?? e?ase/w?ite ??nction ena?le p?oced??e ?wt = 1 page e?ase ?arh = xxh? ?arl = xxh ?mod[2:0] = 001 ?wt = 1 ?wt = 0 ? yes no w?ite ?mod[2:0]= 000 clea? c?wen ?it end w?ite anothe? data wo?d ? yes no w?ite data to w?ite b?ffe? ?d0l = xxh? ?d0h = xxh ?wt = 0 ? no yes ve?if? data with ta?le read inst??ction data co??ect ? no yes blank check with ta?le read inst??ction no blank check page data=0000h? set clwb ?it specif? ?lash memo?? add?ess ?arh = xxh? ?arl = xxh w?ite anothe? wo?d ?lash memo?? non-consec?tive w?ite p?oced??e note: when the fwt bit is set to 1 all cpu operations will temporarily cease.
rev. 1.20 58 ?e???a?? 1?? 201? rev. 1.20 59 ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ? 1. the flash memory erase/w rite function enable procedure must be successfully activated before the flash memory erase/write operation is executed. 2. the flash memory erase operation is executed to erase a whole page. 3. t he who le wri te b uffer d ata wi ll b e wri tten i nto t he fl ash m emory i n a pa ge fo rmat. t he corresponding address cannot exceed the page boundary. 4. bit 7 ~ bit 1 in the frcr register must remain at 0 to avoid unpredictable errors during the iap supported operations. 5. after the data is written into the fash memory the fash memory contents must be read out using the table read instruction, t abrd, and checked if it is correct or not. if the data written into the fash mem ory is incorrect, the write buf fer should be cleared by setting the cl wb bit high and then writing the data again into the write buf fer. then activate a write operation on the same fash memory page without erasing it. the data check, buf fer clear and data re-write steps should be repeatedly executed until the data written into the fash memory is correct. 6. the system frequency should be setup to the maximum application frequency when data write and data check operations are executed using the iap function. to activate the flash memory read procedure, the fmod field should be set to 01 1 to select the fl ash m emory re ad m ode a nd t he frde n bi t sho uld be se t hi gh t o e nable t he re ad fu nction. the desired fash memory address should be written into the f arh and f arl registers and then the frd bit s hould be s et high. a fter this the fas h memory read operation w ill be activated. the data stored in the specifed address can be read from the data registers, fd0h and fd0l, when the frd bit goes low . there is no need to frst activate the flash memory erase/w rite function enable procedure before the fash memory read operation is executed.
rev. 1.20 ? 0 ? e ??? a ?? 1 ?? 201 ? rev. 1.20 ?1 ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu read ?lash memo?? ?rden=0 end read ?inish ? ?es no ?mod[2:0]=011 ?rden=1 ?lash add?ess ?egiste?: ?arh=xxh? ?arl=xxh ?rd=0 ? ?es no read val?e: ?d0l=xxh? ?d0h=xxh ?rd=1 ?lash memo?? read p?oced??e note: when the frd bit is set to 1 all cpu operations will temporarily cease.
rev. 1.20 ?0 ?e???a?? 1?? 201? rev. 1.20 ? 1 ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ss a s as an additional convenience, holtek has provided a means of programming the microcontroller in-system using a two-line usb interface. this provides manufacturers with the possibility of manufacturing their circuit boards complete with a programmed or un-programmed microcontroller and then programming or upgrading the program at a later stage. this enables product manufacturers to easily keep their manufactured products supplied with the latest program releases without removal and re-insertion of the microcontroller device. the program memory can be programmed serially in-system using the usb interface, namely using the udn and udp pins. the power is supplied by the ubus pin. the technical details regarding the in-system programming are beyond the scope of this document and will be supplied in supplementary literature. the flash program memory read/w rite function is implemented using a series of registers. an isp bootloade r function is provided to upgrade the software in the flash memory . the user can utilise either the isp bootloader application software provided by the holtek ide tools or to create their o wn b ootloader so ftware. w hen t he ho ltek b ootloader so ftware i s se lected n ote t hat i t wi ll occupy an area of 0.5k capacity area in the flash memory . the accompanying diagram illustrates the flash memory structure including the holtek bootloader software. 0000h bootloade? bank 0 1???h bank 1 bank 2 3???h last page ?d00h ?d??h bank 3 5???h ht???b5?? 0000h bootloade? bank 0 1???h bank 1 last page 3d00h 3d??h ht???b5?4 0000h bootloade? last page 1d00h 1d??h ht???b5?2 ?lash p?og?am memo?? st??ct??e incl?ding bootloade?
rev. 1.20 ? 2 ? e ??? a ?? 1 ?? 201 ? rev. 1.20 ?3 ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu daa m the data memory is a volatile area of 8-bit wide ram internal memory and is the location where temporary information is stored. categorized into three types, the frst of these is an area of ram, known as the special function data mem ory. t hese re gisters ha ve fxe d l ocations a nd a re ne cessary for c orrect opera tion of t he devices. many of these registers can be read from and written to directly under program control, however, some remain protected from user manipulation. the second area of data memory is known as the general purpose data memory , which is reserved for general purpose use. all locations within this area are read and write accessible under program control. the third area is reserved for the led memory . the addresses of the led memory area overlap those in the general purpose data memory area. switching betwee n the dif ferent data memory sectors is achieved by properly setting the memory pointers to the correct value if using the indirect addressing method. the da ta me mory i s subdi vided i nto se veral se ctors, a ll of wh ich a re i mplemented i n 8-b it wi de ram. each of the d ata m emory s ector is categorized into tw o types , the s pecial p urpose d ata memory and the general purpose data memory. the address range of the special purpose data memory for these devices is from 00h to 7fh. the general purpose data memory and the led memory address range is from 80h to ffh. ht ??? b5 ? 2 0 ? 1 ? 2 10248 0: 80h~ ?? h 1: 80h~ ?? h : : ? : 80h~ ?? h ? : 80h~ ?? h 5128 8: 80h~ ?? h 9: 80h~ ?? h 10: 80h~ ?? h 11: 80h~ ?? h ht ??? b5 ? 4 5128 8: 80h~ ?? h 9: 80h~ ?? h 10: 80h~ ?? h 11: 80h~ ?? h ht ??? b5 ?? 10248 8: 80h~ ?? h 9: 80h~ ?? h : : 14: 80h~ ?? h 15: 80h~ ?? h data memo?? s?mma??
rev. 1.20 ?2 ?e???a?? 1?? 201? rev. 1.20 ? 3 ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu secto? 8 secto? n 00h ??h 80h ??h special p??pose data memo?? (secto? 0 ~ secto? 2) gene?al p??pose data memo?? (secto? 0 ~ secto? ?) secto? 0 secto? 1 secto? ? led data memo?? (secto? 8 ~ secto? n) note: n=11 for ht66fb572/ht66fb574, while n=15 for HT66FB576. for these devices that support the extended instructions, there is no bank pointer for data memory . the bank pointer , pbp , is only available for the ht66fb574/HT66FB576 devices program memory. for da ta me mory t he de sired se ctor i s poi nted by t he mp1 h or mp2 h re gister a nd t he certain data memory address in the selected sector is specifed by the mp1l or mp2l register when using indirect addressing access. direct addressing can be used in all sectors using the corresponding instruction which can address all available data memory space. for the accessed data memory which is located in any data memory sectors e xcept se ctor 0, t he e xtended i nstructions c an be use d t o a ccess t he da ta m emory i nstead of u sing t he i ndirect a ddressing a ccess. t he m ain d ifference b etween st andard i nstructions a nd extended instructions is that the data memory address m in the extended instructions has 12 valid bits for the HT66FB576 device, the high byte indicates a sector and the low byte indicates a specifc address. all microcontroller programs require an area of read/write memory where temporary data can be stored and retrieve d for use later . it is this area of ram memory that is known as general purpose data memory . this area of data memory is fully accessible by the user programing for both reading and wr iting o perations. b y u sing t he b it o peration i nstructions i ndividual b its c an b e se t o r r eset under program control giving the user a lar ge range of fexibility for bit manipulation in the data memory. this area of data memory is where registers, necessary for the correct operation of the microcontroller, are stored. most of the registers are both readable and writeable but some are protected and are readable only , the details of which are located under the relevant special function register section. note that for locat ions that are unused, any read instruction to these addresses will return the value 00h.
rev. 1.20 ? 4 ? e ??? a ?? 1 ?? 201 ? rev. 1.20 ?5 ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu 00h 01h 02h 03h 04h 05h 0?h 0?h 08h 09h 0ah 0bh 0ch 0dh 0eh 0?h 10h 11h 12h 19h 18h 1bh 1ah 1dh 1ch 1?h 13h 14h 15h 1?h 1?h 40h 41h 42h 43h 44h 45h 4?h 4?h 48h 49h 4ah 4bh 4ch 4dh 4eh 4?h 50h 51h 52h 53h 54h 1eh 55h 5?h 5?h 58h 59h 5ah 5bh 5ch 5dh 5eh 5?h 20h 21h 22h 29h 28h 2bh 2ah 2dh 2ch 2?h 2eh 23h 24h 25h 2?h 2?h 30h 31h 32h 38h 3ch 33h 34h 35h 3?h 3?h 3bh 39h 3ah 3dh 3?h 3eh ?0h ?1h ?2h ?3h ?4h ?5h ??h ??h ?8h ?9h ?ah ?bh ?ch ?dh ?eh ??h ?0h ?1h ?2h ?3h ?4h ?5h ??h ?bh ??h ??h ?8h ?9h ?ah ?ch ?dh ?eh status pawueg0 rst?c pbc pbpu pawueg1 pb intc3 pa pac papu secto? 0 pc pcc pbwu iar2 mp2l mp2h pcpu intc0 intc1 intc2 lvdc ucr1 stmc1 usr stmc0 stmdl spiac0 spiad lvrc ucr2 pcwu pe spiac1 txr_rxr pec pepu pewu brg stmdh stmal stmah stmrp eea eed ptm0c0 ptm0c1 ptm0dl ptm0dh ptm0al ptm0ah ptm0rpl ptm0rph secto? 0 uint usc uesr ucc awr stli stlo sies pllc tb0c tb1c sysc usb_stat misc u?ien u?oen u?c0 u?c1 u?c2 ?arl ?d0l ?d1l ?d2l ?d3l ptm2c0 ptm2c1 ptm2dl ptm2dh ptm2al ptm2ah ptm2rpl ptm2rph wdtc sadol sadoh sadc0 sadc1 sadc2 scc hircc hxtc ?i?o1 ?i?o0 ?i?o2 ?i?o3 ?i?o4 ?i?o5 ?i?o? ?i?o? simc0 simd simc1 sima/simc2 simtoc : un?sed? ?ead as 00h secto? 1 integ pd pdc pdpu pdwu pg pgc pgpu pgwu slewc1 slewc2 slewc3 m?i0 m?i1 m?i3 m?i4 m?i2 m?i5 pmps drvcc0 drvcc1 i?s slewc0 pas0 pas1 pbs0 pbs1 pcs1 pds0 pds1 pes0 pgs0 pgs1 ptm1c0 ptm1c1 ptm1dl ptm1dh ptm1al ptm1ah ptm1rpl ptm1rph eec secto? 2 secto? 1 pscr ?rcr ?arh ?d0h ?d1h ?d2h ?d3h ?cr cmp0c secto? 2 rac0e0 iar0 mp0 iar1 mp1l acc pcl tblp tblh tbhp mp1h lcio0 lcio1 l?cr pwmctl0 pwmctl1 pwmilm pwmalm pwmblm pwmclm pwmihm pwmahm pwmbhm pwmchm hlmos hlmd llmd ccs vbgrc lm0ir lm0car lm0cbr lm0ccr lm1ir lm1car lm1cbr lm1ccr lm2ir lm2car lm2cbr lm2ccr lm3ir lm3car lm3cbr lm3ccr lm4ir lm4car lm4cbr lm4ccr rac2e0 rac1e0 rac3e0 rac4e0 rac5e0 rac?e0 rac?e0 rbc0e0 rbc2e0 rbc1e0 rbc3e0 rbc4e0 rbc5e0 rbc?e0 rbc?e0 cmp1c special p??pose data memo?? C ht???b5?2
rev. 1.20 ?4 ?e???a?? 1?? 201? rev. 1.20 ? 5 ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu 00h 01h 02h 03h 04h 05h 0?h 0?h 08h 09h 0ah 0bh 0ch 0dh 0eh 0?h 10h 11h 12h 19h 18h 1bh 1ah 1dh 1ch 1?h 13h 14h 15h 1?h 1?h 40h 41h 42h 43h 44h 45h 4?h 4?h 48h 49h 4ah 4bh 4ch 4dh 4eh 4?h 50h 51h 52h 53h 54h 1eh 55h 5?h 5?h 58h 59h 5ah 5bh 5ch 5dh 5eh 5?h 20h 21h 22h 29h 28h 2bh 2ah 2dh 2ch 2?h 2eh 23h 24h 25h 2?h 2?h 30h 31h 32h 38h 3ch 33h 34h 35h 3?h 3?h 3bh 39h 3ah 3dh 3?h 3eh ?0h ?1h ?2h ?3h ?4h ?5h ??h ??h ?8h ?9h ?ah ?bh ?ch ?dh ?eh ??h ?0h ?1h ?2h ?3h ?4h ?5h ??h ?bh ??h ??h ?8h ?9h ?ah ?ch ?dh ?eh status pawueg0 rst?c pbc pbpu pawueg1 pb intc3 pa pac papu secto? 0 pc pcc pbwu iar2 mp2l mp2h pcpu intc0 intc1 pbp intc2 lvdc ucr1 stmc1 usr stmc0 stmdl spiac0 spiad lvrc ucr2 pcwu pe spiac1 txr_rxr pec pepu pewu brg stmdh stmal stmah stmrp eea eed ptm0c0 ptm0c1 ptm0dl ptm0dh ptm0al ptm0ah ptm0rpl ptm0rph secto? 0 uint usc uesr ucc awr stli stlo sies pllc tb0c tb1c sysc usb_stat misc u?ien u?oen u?c0 u?c1 u?c2 ?arl ?d0l ?d1l ?d2l ?d3l ptm2c0 ptm2c1 ptm2dl ptm2dh ptm2al ptm2ah ptm2rpl ptm2rph wdtc sadol sadoh sadc0 sadc1 sadc2 scc hircc hxtc ?i?o1 ?i?o0 ?i?o2 ?i?o3 ?i?o4 ?i?o5 ?i?o? ?i?o? simc0 simd simc1 sima/simc2 simtoc : un?sed? ?ead as 00h secto? 1 integ pd pdc pdpu pdwu pg pgc pgpu pgwu slewc1 slewc2 slewc3 m?i0 m?i1 m?i3 m?i4 m?i2 m?i5 pmps drvcc0 drvcc1 i?s slewc0 pas0 pas1 pbs0 pbs1 pcs1 pds0 pds1 pes0 pgs0 pgs1 ptm1c0 ptm1c1 ptm1dl ptm1dh ptm1al ptm1ah ptm1rpl ptm1rph eec secto? 2 secto? 1 pscr ?rcr ?arh ?d0h ?d1h ?d2h ?d3h ?cr cmp0c secto? 2 iar0 mp0 iar1 mp1l acc pcl tblp tblh tbhp mp1h lcio0 lcio1 l?cr pwmctl0 pwmctl1 pwmilm pwmalm pwmblm pwmclm pwmihm pwmahm pwmbhm pwmchm hlmos hlmd llmd ccs vbgrc lm0ir lm0car lm0cbr lm0ccr lm1ir lm1car lm1cbr lm1ccr lm2ir lm2car lm2cbr lm2ccr lm3ir lm3car lm3cbr lm3ccr lm4ir lm4car lm4cbr lm4ccr lm5ir lm5car lm5cbr lm5ccr lm?ir lm?car lm?cbr lm?ccr lm?ir lm?car lm?cbr lm?ccr cmp1c rac0e0 rac2e0 rac1e0 rac3e0 rac4e0 rac5e0 rac?e0 rac?e0 rbc0e0 rbc2e0 rbc1e0 rbc3e0 rbc4e0 rbc5e0 rbc?e0 rbc?e0 special p??pose data memo?? C ht???b5?4
rev. 1.20 ?? ? e ??? a ?? 1 ?? 201 ? rev. 1.20 ?? ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu 00h 01h 02h 03h 04h 05h 0?h 0?h 08h 09h 0ah 0bh 0ch 0dh 0eh 0?h 10h 11h 12h 19h 18h 1bh 1ah 1dh 1ch 1?h 13h 14h 15h 1?h 1?h 40h 41h 42h 43h 44h 45h 4?h 4?h 48h 49h 4ah 4bh 4ch 4dh 4eh 4?h 50h 51h 52h 53h 54h 1eh 55h 5?h 5?h 58h 59h 5ah 5bh 5ch 5dh 5eh 5?h 20h 21h 22h 29h 28h 2bh 2ah 2dh 2ch 2?h 2eh 23h 24h 25h 2?h 2?h 30h 31h 32h 38h 3ch 33h 34h 35h 3?h 3?h 3bh 39h 3ah 3dh 3?h 3eh ?0h ?1h ?2h ?3h ?4h ?5h ??h ??h ?8h ?9h ?ah ?bh ?ch ?dh ?eh ??h ?0h ?1h ?2h ?3h ?4h ?5h ??h ?bh ??h ??h ?8h ?9h ?ah ?ch ?dh ?eh status pawueg0 rst?c pbc pbpu pawueg1 pb intc3 pa pac papu secto? 0 pc pcc pbwu iar2 mp2l mp2h pcpu intc0 intc1 pbp intc2 lvdc ucr1 stmc1 usr stmc0 stmdl spiac0 spiad lvrc ucr2 pcwu pe spiac1 txr_rxr pec pepu pewu brg stmdh stmal stmah stmrp eea eed ptm0c0 ptm0c1 ptm0dl ptm0dh ptm0al ptm0ah ptm0rpl ptm0rph secto? 0 uint usc uesr ucc awr stli stlo sies pllc tb0c tb1c sysc usb_stat misc u?ien u?oen u?c0 u?c1 u?c2 ?arl ?d0l ?d1l ?d2l ?d3l ptm2c0 ptm2c1 ptm2dl ptm2dh ptm2al ptm2ah ptm2rpl ptm2rph wdtc sadol sadoh sadc0 sadc1 sadc2 scc hircc hxtc ?i?o1 ?i?o0 ?i?o2 ?i?o3 ?i?o4 ?i?o5 ?i?o? ?i?o? simc0 simd simc1 sima/simc2 simtoc : un?sed? ?ead as 00h secto? 1 integ pd pdc pdpu pdwu p?c p?pu p? p?wu pg pgc pgpu pgwu slewc1 slewc2 slewc3 m?i0 m?i1 m?i3 m?i4 m?i2 m?i5 pmps drvcc0 drvcc1 i?s slewc0 pas0 pas1 pbs0 pbs1 pcs0 pcs1 pds0 pds1 pes0 pgs0 pgs1 ptm1c0 ptm1c1 ptm1dl ptm1dh ptm1al ptm1ah ptm1rpl ptm1rph eec secto? 2 secto? 1 pscr ?rcr ?arh ?d0h ?d1h ?d2h ?d3h ?cr cmp0c secto? 2 rac0e0 rac0e1 iar0 mp0 iar1 mp1l acc pcl tblp tblh tbhp mp1h lcio0 lcio1 l?cr pwmctl0 pwmctl1 pwmilm pwmalm pwmblm pwmclm pwmihm pwmahm pwmbhm pwmchm hlmos hlmd llmd ccs vbgrc lm0ir lm0car lm0cbr lm0ccr lm1ir lm1car lm1cbr lm1ccr lm2ir lm2car lm2cbr lm2ccr lm3ir lm3car lm3cbr lm3ccr lm4ir lm4car lm4cbr lm4ccr lm5ir lm5car lm5cbr lm5ccr lm?ir lm?car lm?cbr lm?ccr lm?ir lm?car lm?cbr lm?ccr lm8ir lm8car lm8cbr lm8ccr lm9ir lm9car lm9cbr lm9ccr lmair lmacar lmacbr lmaccr lmbir lmbcar lmbcbr lmbccr lmcir lmccar lmccbr lmcccr lmdir lmdcar lmdcbr lmdccr lmeir lmecar lmecbr lmeccr lm?ir lm?car lm?cbr lm?ccr rac2e0 rac2e1 rac1e0 rac1e1 rac3e0 rac3e1 rac4e0 rac4e1 rac5e0 rac5e1 rac?e0 rac?e1 rac?e0 rac?e1 rbc0e0 rbc0e1 rbc2e0 rbc2e1 rbc1e0 rbc1e1 rbc3e0 rbc3e1 rbc4e0 rbc4e1 rbc5e0 rbc5e1 rbc?e0 rbc?e1 rbc?e0 rbc?e1 cmp1c special p??pose data memo?? C ht???b5??
rev. 1.20 ?? ?e???a?? 1?? 201? rev. 1.20 ?? ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu sal f rs ds most of t he spe cial func tion re gister de tails wi ll be de scribed i n t he re levant funct ional sec tion; however several registers require a separate description in this section. the indirect addressing registers, iar0, iar1 and iar2, although having their locations in normal ram r egister sp ace, d o n ot a ctually p hysically e xist a s n ormal r egisters. t he m ethod o f i ndirect addressing for ram da ta m anipulation use s t hese indi rect addre ssing re gisters a nd me mory pointers, i n c ontrast t o di rect m emory a ddressing, where t he a ctual m emory a ddress i s spe cifed. actions on t he iar0, iar1 a nd iar2 re gisters wi ll re sult i n no a ctual re ad or writ e ope ration t o these registers but rather to the memory location specifed by their corresponding memory pointers, mp0, mp1l/mp1h or mp2l/mp2h. acting as a pair , iar0 and mp0 can together access data only from sector 0 while the iar1 register together with the mp1l/mp1h register pair and iar2 register together with the mp2l/mp2h register pair can access data from any data memory sector . as the indirec t addressing re gisters are not physi cally i mplemented, rea ding t he indirec t addressing registers will return a result of 00h and writing to the registers will result in no operation. five memory pointers, known as mp0, mp1l, mp1h, mp2l, mp2h, are provided. these memory pointers are physically implemente d in the data memory and can be manipulated in the same way as n ormal r egisters p roviding a c onvenient wa y wi th wh ich t o a ddress a nd t rack d ata. w hen a ny operation to the relevant indirect addressing registers is carried out, the actual address that the microcontroller is directed to is the address specifed by the related memory pointer . mp0, together with indirect addressing register , iar0, are used to access data from sector 0, while mp1l/mp1h together with iar1 and mp2l/mp2h together with iar2 are used to access data from all sectors according t o t he c orresponding mp1h or mp2h regi ster. di rect addre ssing ca n be use d i n a ll sectors using the extended instructions which can address all available data memory space. the following example shows how to clear a section of four data memory locations already defned as locations adres1 to adres4. data .section data adres1 d b ? adres2 d b ? adres3 d b ? adres4 d b ? block d b ? code .section at 0 code org 00h start: m ov a, 04h ; setup size of block m ov block, a mov a , o ffset ad res1 ; a ccumulator l oaded w ith f rst r am ad dress mov m p0, a ; s etup m emory po inter wi th f rst r am a ddress loop: clr i ar0 ; c lear t he d ata a t ad dress d efned b y m p0 i nc mp0 ; increment memory pointer s dz block ; check if last memory location has been cleared jm p loop continue:
rev. 1.20 ? 8 ? e ??? a ?? 1 ?? 201 ? rev. 1.20 ?9 ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ss a eal 2 data .section data adres1 d b ? adres2 d b ? adres3 d b ? adres4 d b ? block d b ? code .section at 0 code org 00h start: m ov a, 04h ; setup size of block m ov block, a m ov a, 01h ; setup the memory sector m ov mp1h, a mov a , o ffset ad res1 ; a ccumulator l oaded w ith f rst r am ad dress mov m p1l, a ; s etup m emory po inter wi th f rst r am a ddress loop: clr i ar1 ; c lear t he d ata a t a ddress d efned b y m p1l inc m p1l ; i ncrement m emory po inter m p1l s dz block ; check if last memory location has been cleared jm p loop continue: the important point to note here is that in the example shown above, no reference is made to specifc data memory addresses. data .section data temp db ? code .section at 0 code org 00h start: l mov a, [m] ; move [m] data to acc l sub a, [m+1] ; compare [m] and [m+1] data s nz c ; [m]>[m+1]? j mp continue ; no l mov a, [m] ; yes, exchange [m] and [m+1] data m ov temp, a l mov a, [m+1] l mov [m], a m ov a, temp l mov [m+1], a continue: note: here m is a data memory address located in any data memory sectors. for example, m=1f0h, it indicates address 0f0h in sector 1. for the ht66fb574/HT66FB576 devices, the program memory is divided into several banks. selecting the required program memory area is achieved using the program memory bank pointer , pbp. the pbp register should be properly confgured before the ht66fb574/HT66FB576 devices execute the branch operation using the jmp or call instructio n. after that a jump to a non- consecutive program memory address which is located in a certain bank selected by the program memory bank pointer bits will occur.
rev. 1.20 ?8 ?e???a?? 1?? 201? rev. 1.20 ? 9 ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu b rs ht66fb574 b 7 6 5 4 2 name pbp0 r/w r/w por 0 bit 7~1 unimplemented, read as 0 bit 0 pbp0 : program memory bank pointer bit 0 0: bank 0 1: bank 1 name pbp1 pbp0 r/w r/w r/w por 0 0 bit 7~2 unimplemented, read as 0 bit 1~0 pbp1~pbp0 : program memory bank pointer bit 1~ bit 0 00: bank 0 01: bank 1 10: bank 2 11: bank 3 the a ccumulator is central to the operation of any microcontroller and is clos ely related w ith operations carried out by the alu. the accumulator is the place where all intermediate results from the alu are stored. w ithout the accumulator it would be necessary to write the result of each c alculation or l ogical ope ration suc h a s a ddition, subt raction, shi ft, e tc., t o t he da ta me mory resulting i n highe r program ming and t iming overheads. da ta t ransfer operat ions usual ly i nvolve the t emporary st orage func tion of t he ac cumulator; for e xample, wh en t ransferring da ta be tween one user -defined register and another , it is necessary to do this by passing the data through the accumulator as no direct transfer between two registers is permitted. to provide additional program control functions, the low byte of the program counter is made accessible to programmers by locating it within the special purpose area of the data memory . by manipulating this register , direct jumps to other program locations are easily implemented. loading a value directly into this pcl register will cause a jump to the specifed program memory location, however, as the register is only 8-bit wide, only jumps within the current program memory page are permitted. when such operations are used, note that a dummy cycle will be inserted. these three special function registers are used to cont rol operation of the look-up table which is stored i n t he progra m me mory. t blp a nd t bhp a re t he t able poi nters a nd i ndicate t he l ocation where the table data is located. their value must be setup before any table read commands are executed. their value can be changed, for example using the inc or dec instructions, allowing for easy table data pointing and reading. tblh is the location where the high order byte of the table data is stored afte r a table read data instruction has been executed. note that the lower order table data byte is transferred to a user defned location.
rev. 1.20 ? 0 ? e ??? a ?? 1 ?? 201 ? rev. 1.20 ?1 ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu sas rs sttus this 8-bit register contains the sc fag, cz fag, zero fag (z), carry fag (c), auxiliary carry fag (ac), overfow fag (ov), power down fag (pdf), and watchdog time-out fag (t o). these arithmetic/ logical o peration a nd sy stem m anagement fa gs a re u sed t o r ecord t he st atus a nd o peration o f t he microcontroller. with the exception of the sc, cz, t o and pdf fags, bits in the stat us regi ster can be al tered by instructions like most other registers. any data written into the status register will not change the to or pdf fag. in addition, operati ons related to the status register may give dif ferent results due to the dif ferent instruction operations. the t o fag can be af fected only by a system power -up, a wdt time-out or by executing the clr wdt or hal t instruction. the pdf fag is af fected only by executing the halt or clr wdt instruction or during a system power-up. the z, ov, ac, c, sc and cz fags generally refect the status of the latest operations. ? sc is the result of the xor operation which is performed by the ov fag and the msb of the current instruction operation result. ? cz is the operational result of dif ferent flags for dif ferent instructions. refer to register defnitions for more details. ? c is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise c is cleared. c is also af fected by a rotate through carry instruction. ? ac is set if an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction; otherwise ac is cleared. ? z is set if the result of an arithmetic or logical operation is zero; otherwise z is cleared. ? ov is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise ov is cleared. ? pdf is cleared by a system power -up or executing the clr wdt instruction. pdf is set by executing the halt instruction. ? to is cle ared by a system power -up or executing the clr wdt or hal t instruction. to is set by a wdt time-out. in additio n, on entering an interrup t sequence or executing a subroutine call, the status register will not be pushed onto the stack automatically . if the contents of the status registers are important and if the subroutine can corrupt the status register, precautions must be taken to correctly save it. name sc cz to pd ? ov z ac c r/w r r r r r/w r/w r/w r/w por x x 0 0 x x x x "x": ? nknown bit 7 sc : the result of the xor operation which is performed by the ov fag and the msb of the instruction operation result. bit 6 cz : the operational result of different fags for different instructions. for sub/subm/lsub/lsubm instructions, the cz fag is equal to the z fag. for sbc/sbcm/lsbc/lsbcm instructions, the cz flag is the and operation result which is performed by the previous operation cz fag and current operation zero fag. for other instructions, the cz fag will not be affected.
rev. 1.20 ?0 ?e???a?? 1?? 201? rev. 1.20 ? 1 ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu bit 5 : w atchdog t ime-out fag 0: after power up or executing the clr wdt or halt instruction 1: a watchdog time-out occurred. bit 4 : power down fag 0: after power up or executing the clr wdt instruction 1: by executing the halt instruction bit 3 : overfow fag 0: no overfow 1: an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit or vice versa. bit 2 : zero fag 0: the result of an arithmetic or logical operation is not zero 1: the result of an arithmetic or logical operation is zero bit 1 : auxiliary fag 0: no auxiliary carry 1: an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction bit 0 : carry fag 0: no carry-out 1: an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation the c fag is also affected by a rotate through carry instruction. eeprom data memory these d evices c ontain a n a rea o f i nternal e eprom da ta me mory. e eprom, wh ich st ands f or electrically e rasable progra mmable re ad onl y me mory, i s by i ts na ture a non-vol atile form of re-programmable memory , with data retention even when its power supply is removed. by incorporating this kind of data memory , a w hole new hos t of application pos sibilities are made available to the designer . the avail ability of eeprom storage allows information such as product identification numbers, calibration values, specific user data, system setup data or other product information to be stored directly within the product microcontroller . the process of reading and writing data to the eeprom memory has been reduced to a very trivial affair. eeprom data memory structure the eeprom data memory capac ity is 2568 bits for these devices. unlike the program memory and ram data memory, the eeprom data memory is not directly mapped into memory space and is therefore not directly addressable in the same way as the other types of memory . read and w rite operations to the eeprom are carried out in single byte operations using an address and a data register in sector 0 and a single control register in sector 1. eeprom registers three registers control the overall operation of the internal eeprom data memory . these are the address register , eea, the data register , eed and a single control register , eec. as both the eea and eed registers are located in sector 0, they can be directly accessed in the same way as many other special function registers. the eec register however , being located in sector 1, can be read from or written to directly using the extended instructions, or indirectly using the mp1l/mp1h or mp2l /mp2h me mory poi nter a nd indi rect addressi ng regi ster, iar1/ iar2. if usi ng i ndirect addressing to acce ss the eec control register , as it is located at address 3eh in sector 1, the mp1l or mp2l me mory poi nter m ust fi rst be se t t o t he va lue 3e h a nd t he mp1h or mp2h me mory pointer high byte set to the value, 01h, before any operations on the eec register are executed.
rev. 1.20 ? 2 ? e ??? a ?? 1 ?? 201 ? rev. 1.20 ?3 ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu rs a b 7 6 5 4 2 eea eea ? eea ? eea5 eea4 eea3 eea2 eea1 eea0 eed eed ? eed ? eed5 eed4 eed3 eed2 eed1 eed0 eec wren wr rden rd eeprom registe?s list eea registe? bit ? ? 5 4 3 2 1 0 name eea ? eea ? eea5 eea4 eea3 eea2 eea1 eea0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 eea7~eea0 : data eeprom address bit 7 ~ bit 0 name eed ? eed ? eed5 eed4 eed3 eed2 eed1 eed0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 eed7~eed0 : data eeprom data bit 7 ~ bit 0 name wren wr rden rd r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~4 unimplemented, read as 0 bit 3 wren : data eeprom w rite enable 0: disable 1: enable this is the d ata eep rom w rite enable bit w hich mus t be s et high before d ata eeprom write operations are carried out. clearing this bit to zero will inhibit data eeprom write operations. bit 2 wr : eeprom w rite control 0: w rite cycle has fnished 1: activate a write cycle this i s t he da ta e eprom w rite c ontrol b it a nd wh en se t h igh b y t he a pplication program will activ ate a write cycle. this bit will be automatically reset to zero by the hardware after the write cycle has fnished. setting this bit high will have no ef fect if the wren has not frst been set high. bit 1 rden : data eeprom read enable 0: disable 1: enable this is the data eeprom read enable bit which must be set high before data eeprom read operations are carried out. clearing this bit to zero w ill inhibit d ata eeprom read operations. bit 0 rd : eeprom read control 0: read cycle has fnished 1: activate a read cycle this is the data eeprom read control bit and when set high by the applic ation
rev. 1.20 ?2 ?e???a?? 1?? 201? rev. 1.20 ? 3 ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu program will activ ate a read cycle. this bit will be automatically reset to zero by the hardware after the read cycle has fnished. setting this bit high will have no ef fect if the rden has not frst been set high. note: the wren, wr, rden and rd cannot be set high at the same time in one instruction. the wr and rd cannot be set high at the same time. to read data from the eep rom, the read enable bit, rden , in the eec register must frs t be set high to enable the read function. the eeprom address of the data to be read must then be placed in the eea register . if the rd bit in the eec register is now set high, a read cycle will be initiated. setting the rd bit high will not initiate a read operation if the rden bit has not been set. when the read cycle term inates, the rd bit will be automatically cleared to zero, after which the data can be read from the eed register . the data will remain in the eed register until another read or write operation i s e xecuted. t he a pplication pr ogram c an po ll t he r d bi t t o de termine whe n t he da ta i s valid for reading. the eeprom address of the data to be written must frst be placed in the eea register and the data placed in the eed register . t o write data to the eeprom, the write enable bit, wren, in the eec register must frst be set high to enable the write function. after this, the wr bit in the eec register must be immediately set high to initiate a write cycle. these two instructions must be executed consecutively. the global interrupt bit emi should als o frst be cleared before implementing any write operat ions, and then set aga in aft er the writ e cyc le has start ed. note that setting the wr bi t high will not initiate a write cycle if the wren bit has not been set. as the eeprom write cycle is controlled using an internal timer whose operation is asynchronous to microcontroller system clock, a certain time will elapse before the data will have been written into the eeprom. detecting when the write cycle has fnished can be implemented either by polling the wr bit in the eec register or by using the eeprom interrupt. when the write cycle terminates, the wr bit will be automatically cleared to zero by the microcontroller , informing the user that the data has been written to the eeprom. the application program can therefore poll the wr bit to determine when the write cycle has ended. protection against inadvertent write operation is provided in several ways . after the devices are powered-on the w rite enable bit in the control register will be cleared preventing any write operations. also at power -on the memory pointer high byte register , mp1h or mp2h, will be reset to zero, which means that data memory sector 0 will be selected. as the eeprom control register is located in sector 1, this adds a further measure of protection against spurious write operations. during normal program operati on, ensuring that the w rite enable bit in the cont rol re gister is cleared will safeguard against incorrect write operations. the eeprom write interrupt is generated when an eeprom write cycle has ended. the eeprom interrupt must frst be enabled by setting the dee bit in the relevant interrupt register . however as the eeprom is contained within a multi-function interrupt, the associated multi-function interrupt enable bit must als o be set. when an eeprom w rite cycle ends, the d ef reques t flag and its associated multi-function interrupt request fag will both be set. if the global, eeprom and multi- function interrupts are enabled and the stack is not full, a jump to the associated multi-function interrupt vector will take place. when the interrupt is serviced only the multi-function interrupt fag
rev. 1.20 ? 4 ? e ??? a ?? 1 ?? 201 ? rev. 1.20 ?5 ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu will be automatically reset, the eeprom interrupt fag must be manually reset by the application program. more details can be obtained in the interrupt section. care must be taken that data is not inadvertently written to the eeprom. protection can be enhanced by ensuring that the w rite enable bit is normally cleared to zero when not writing. also the memory pointer high byte register , mp1h or mp2h, could be normally cleared to zero as this would inhibit access to sector 1 where the eeprom control register exists. although certainly not necessary, consideration might be given in the application program to the checking of the validity of new write data by a simple read back process. when writing data the wr bit must be set high immediately after the wren bit has been set high, to ensure the write cycle executes correctly . the global interrupt bit emi should also be cleared before a write cycle is executed and then re-enabled after the write cycl e starts. note that the devices should not enter the id le or sleep mode until the eeprom read or write operation is totally complete. otherwise, the eeprom read or write operation will fail. mov a, ee prom_adres ; u ser d efned ad dress mov eea, a mov a, 0 3eh ; s etup m emory po inter m p1l mov mp1l, a ; mp1l p oints t o e ec r egister mov a, 0 1h ; se tup m emory p ointer m p1h mov mp1h, a set iar1.1 ; s et r den b it, e nable r ead o perations set iar1.0 ; s tart r ead c ycle - s et r d b it back: sz iar1.0 ; c heck f or re ad c ycle e nd jmp back clr iar1 ; d isable ee prom re ad/write clr mp1h mov a, ee d ; m ove re ad d ata t o re gister mov read_data, a mov a, ee prom_adres ; u ser d efned ad dress mov eea, a mov a, e eprom_data ; u ser d efned da ta mov eed, a mov a, 0 3eh ; s etup m emory po inter m p1l mov mp1l, a ; mp1l p oints t o e ec r egister mov a, 0 1h ; se tup m emory p ointer m p1h mov mp1h, a clr emi set iar1.3 ; s et w ren b it, e nable w rite o perations set iar1.2 ; s tart w rite c ycle - s et w r b it e xecuted i mmediately ; a fter s et w ren b it set emi back: sz iar1.2 ; c heck f or wr ite c ycle e nd jmp back clr iar1 ; d isable ee prom re ad/write clr mp1h
rev. 1.20 ?4 ?e???a?? 1?? 201? rev. 1.20 ? 5 ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu sllas various oscillator options of fer the user a wide range of functions according to their various application requirements. the flexible features of the oscillator functions ensure that the best optimisation can be achieved in terms of speed and power saving. oscillator selections and operation are selected through a combination of confguration options and the relevant control registers. in additio n to being the source of the main system clock the oscillators also provide clock sources for t he w atchdog t imer a nd t ime b ase i nterrupts. e xternal o scillators r equiring so me e xternal components as well as fully integrated internal oscillators, requiring no external components, are provided t o fo rm a wi de ra nge of bo th fa st a nd sl ow syst em osc illators. al l osc illator op tions a re selected through configuration options and the relevant control registers. the higher frequency oscillators provide higher performance but carry with it the disadvantage of higher power requirements, wh ile t he o pposite i s o f c ourse t rue f or t he l ower f requency o scillators. w ith t he capability of dy namically swi tching be tween fa st a nd sl ow syst em c lock, t hese de vices ha ve t he fexibility to optim ize the performance/power ratio, a feature especially important in power sensitive portable applicatio ns. for usb applications, the hxt pins must be connected to a 6mhz or 12mhz crystal if the hxt oscillator is selected to be used. exte ? nal high speed c ?? stal hxt ? mhz o ? 12mhz osc1/osc2 inte ? nal high speed rc hirc 12mhz inte ? nal low speed rc lirc 32khz oscillato? t?pes system clock confgurations there are s everal os cillator s ources, tw o high s peed os cillators and one low s peed os cillator. the high speed system clocks are sourced from the external crystal/ceramic oscillator , hxt , and the internal 12mhz rc oscillator , hirc. the low speed oscillator is the internal 32khz rc oscillator, lirc. selecting whether the low or high speed oscillator is used as the system oscillator is implemented using the cks2~cks0 bits in the scc register and as the system clock can be dynamically selected. the actua l source clock used for the high speed oscillator the source clock is selected by the fhs bit in the scc register . the frequency of the slow speed or high speed system clock is also determined using the cks2~cks0 bits in the scc register . note that two oscillator selections must be made namely one high speed and one low speed system oscillators. it is not possible to choose a no- oscillator selection for either the high or low speed oscillator. in addition, the internal pll frequency generator, wh ose c lock so urce i s su pplied b y a n e xternal c rystal o scillator, c an b e e nabled b y a software control bit to generate various frequencies for the usb interface and system clock.
rev. 1.20 ?? ? e ??? a ?? 1 ?? 201 ? rev. 1.20 ?? ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu p?escale? f sub idle2 sleep cks[2:0] f h f h /2 f h /4 f h /8 f h /1? f h /32 f h /?4 idle0 sleep f sub pll f hosc ?mhz 12mhz 1?mhz 48mhz pllen pllos[2:0] pllis f hosc config.option selections ?/12mhz hxt high speed oscillato?s ?hs low speed oscillato? f sys hxt hxten hircen hirc f pll_48mhz lirc f wdt system clock confgurations the i nternal pl l fre quency ge nerator i s used t o ge nerate t he fre quency for t he usb i nterface and t he syst em c lock. t his pl l ge nerator c an be e nabled or di sabled by t he pl l c ontrol bi t pllen i n t he pl lc re gister. aft er a p ower o n r eset, t he pl l c ontrol b it wi ll b e se t t o 1 t o t urn on t he pl l ge nerator. t he pl l ge nerator wi ll provi de t he fi xed 48mhz freque ncy for t he usb operating fre quency a nd a nother fre quency for t he syst em c lock so urce wh ich c an be 6mhz , 12mhz or 16mhz. the selection of this system frequency is implemented using the pllen and pllos2~pllos0 bits in the pllc register. the following table illustrates the high frequency system clock f h selected by the related control bits. h 0 x x x f hosc C hxt o ? hirc ? depending on the ? hs ? it in the scc ? egiste ? . 1 0 x x f hosc C hxt o ? hirc ? depending on the ? hs ? it in the scc ? egiste ? . 1 1 0 0 f pll = ? mhz 1 1 0 1 f pll = 12mhz 1 1 1 0 f pll = 1 ? mhz 1 1 1 1 rese ? ved x: dont ca ? e pllc registe? bit ? ? 5 4 3 2 1 0 name d ? pllis pllos2 pllos1 pllos0 pll ? pllen r/w r/w r/w r/w r/w r/w r r/w por 0 0 0 0 0 0 1 bit 7 d7 : reserved bit, cannot be used and must be fxed at 0 bit 6 unimplemented, read as 0 bit 5 pllis : pll input clock source selection 0: 12mhz clock 1: 6mhz clock if fhs=1, when a 12mhz crystal or resonator is used, the hxt frequency is divided by 2 and then multiplied by 8 using the internal pll circuit, when a 6mhz crystal or
rev. 1.20 ?? ?e???a?? 1?? 201? rev. 1.20 ?? ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu resonator is used, the hxt frequency is directly multiplied by 8 using the internal pll circuit. if fhs=0, the 12mhz hirc is selected, this bit will be automatically cleared to zero by the hardware. bit 4~2 : f hosc or f pll for f h clock source selection 0xx: f hosc 100: f pll =6mhz 101: f pll =12mhz 110: f pll =16mhz 111: reserved bit 1 : pll clock stable fag 0: unstable 1: stable this bit is used to indicate whether the pll clock is stable or not. when the pllen bit is set to 1 to enable the pll clock, the pllf bit will frst be cleare d to 0 and then set to 1 after the pll clock is stable. bit 0 : pll enable control 0: disable 1: enable the exte rnal crystal/ceramic system oscillator is one of the high frequency oscillators. for most crystal oscillator configurations, the simple connection of a crystal across osc1 and osc2 will create the necessary phase shift and feedback for oscillation, without requiring external capacitors. however, for some crystal types and frequencies, to ensure oscillation , it may be necessary to add two small value capacitors, c1 and c2. using a ceramic resonator will usually require two small value capacitors, c1 and c2, to be connected as shown for oscillation to occur . the values of c1 and c2 should be selected in consultation with the crystal or resonator manufacturer's specifcation. for usb a pplications, t he hxt pi ns m ust be c onnected t o a 6mhz or 12mhz c rystal i f t he hxt oscillator is selected to be used. for oscillator stability and to minimise the ef fects of noise and crosstalk, it is important to ensure that the crystal and any associated resistors and capacitors along with interconnecting lines are all located as close to the mcu as possible. note: 1. r p is no?mall? not ?eq?i?ed. c1 and c2 a?e ?eq?i?ed. 2. altho?gh not shown osc1/osc2 pins have a pa?asitic capacitance of a?o?nd ?p?. to inte?nal ci?c?its inte?nal oscillato? ci?c?it c1 c2 osc1 osc2 r ? r p c??stal/resonato? oscillato? C hxt
rev. 1.20 ? 8 ? e ??? a ?? 1 ?? 201 ? rev. 1.20 ?9 ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu csal slla c a c2 als csal f c c2 12mhz 0p ? 0p ? 8mhz 0p ? 0p ? ? mhz 0p ? 0p ? 4mhz 0p ? 0p ? 1mhz 100p ? 100p ? note: c1 and c2 val ? es a ? e fo ? g ? idance onl ? . c??stal recommended capacito? val?es inte?nal high speed rc oscillato? C hirc the internal rc oscillator is a fully integrated system oscillator requiring no external components. the internal rc oscillator has a fixed frequency of 12mhz. device trimming during the manufacturing process and the inclusion of internal frequency compensati on circuits are used to ensure that the infuence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. note that if this internal system clock option is selected, as it requires no external pins for its operation, i/o pins pd0 and pd1 are free for use as normal i/o pins. the internal 32khz system oscillator is a low frequency oscillator . it is a fully integrated rc oscillator with a typical frequency of 32khz at 5v , requiring no external components for its implementation. device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the infuence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised.
rev. 1.20 ?8 ?e???a?? 1?? 201? rev. 1.20 ? 9 ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu a ms a ss cls present day appl ications require that their mi crocontrollers have high performance but often sti ll demand that they consume as little power as possible, conficting requirements that are especially true i n ba ttery powe red por table a pplications. t he fa st c locks re quired for hi gh pe rformance wi ll by t heir na ture i ncrease c urrent c onsumption a nd of c ourse vi ce ve rsa, l ower spe ed c locks re duce current consumption. as holtek has provided thes e devices with both high and low speed clock sources and the means to switch between them dynamically , the user can optimise the operation of their microcontroller to achieve the best performance/power ratio. these devices have many dif ferent clock sources for both the cpu and peripheral functi on operation. by providing the user with a wide range of clock options using configuration options and register programming, a clock system can be configured to obtain maximum application performance. the main system clock, can come from a high frequency , f h , or low frequency , f sub , source, and is se lected u sing t he c ks2~cks0 b its i n t he sc c r egister. t he h igh sp eed sy stem c lock c an b e sourced from an hxt or hirc oscillator or the usb pll output clock, selected via confguring the fhs bit in the scc register together with the pllen and pllos2~pllos0 bits in the pllc register. the low speed system clock source can be sourced from the lirc oscillator . the other choice, which is a divided version of the high speed system oscillator has a range of f h /2~f h /64. p?escale? f sub idle2 sleep cks[2:0] f h f h /2 f h /4 f h /8 f h /1? f h /32 f h /?4 idle0 sleep f sub pll f hosc ?mhz 12mhz 1?mhz 48mhz pllen pllos[2:0] pllis f hosc config.option selections ?/12mhz hxt high speed oscillato?s ?hs f sys hxt hxten hircen hirc to usb ci?c?its usbcken wdt f sub f sys /4 f sys clksel0[1:0] f psc p?escale? time base 0 time base 1 tb0on tb1on tb1[2:0] tb0[2:0] f wdt low speed oscillato? lirc device clock confgurations note: when the system clock source f sys is switched to f sub from f h , the high speed oscillat or will stop to conserve the power or continue to oscillate to provide the clock source, f h ~ f h /64, for peripheral circuit to use, which is determined by confguring the corresponding high speed oscillator enable control bit .
rev. 1.20 80 ? e ??? a ?? 1 ?? 201 ? rev. 1.20 81 ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ss a ms there are six dif ferent modes of operation for the microcontroller , each one with its ow n special characteristics and which can be chosen according to the specific performance and power requirements of the appl ication. there are two modes all owing normal operati on of the microcontroller, the normal mode and slow mode. the remaining four modes, the sleep , idle0, idle1 and idl e2 mode are used when the microcontroller cpu i s switched off t o conserve power. normal on x x 000~110 f h ~f h / ? 4 on on on on slow on x x 111 f sub on/off (1) on on on/off (3) idle0 off 0 1 000~110 off off on on off (4) 111 on idle1 off 1 1 xxx on on on on on idle2 off 1 0 000~110 on on off on/off (2) on 111 off sleep off 0 0 xxx off off off on/off (2) off (4) x: dont ca ? e note: 1. the f h clock will be swit ched on or of f by configuring the corresponding oscill ator enable bit in the slow mode. 2. the f wdt clock can be switched on or of f which is controlled by the wdt function being enabled or disabled. 3. the f pll clock can be switched on or of f which is controlled by the pllen bit in the pllc register in the slow mode. 4. the usb function is inactive in idle0 and sleep mode. as the name suggests this is one of the main operating modes where the microcontroller has all of its functions operational and where the system clock is provided by one of the high speed oscillators. this mode operate s allowing the microcontroller to operate normally with a clock source will come from one of the high speed oscillators, either the hxt or hirc oscillators. the high speed oscillator will however first be divided by a ratio ranging from 1 to 64, the actual ratio being selected by the cks2~cks0 bits in the scc register . although a high speed oscillator is used, running the microcontroller a t a di vided c lock ra tio re duces t he ope rating c urrent. in t he usb m ode, t he pl l circuit of which the clock source can be derived from the hxt or hirc oscillator can generate a clock with a frequency of 6mhz, 12mhz, or 16mhz as the devices system clock. this is also a mode where the microcontroller operates normally altho ugh now with a slower speed clock sou rce. t he c lock sou rce u sed wi ll b e fr om f sub . t he f sub c lock i s d erived fr om t he l irc oscillator. the sleep mode is entered when an hal t instruction is executed and when the fhiden and fsiden bit are low . in the sleep mode the cpu will be stopped. the f sub clock provided to the peripheral function will also be stopped, too. however the f wdt clock can continues to operate if the wdt function is enabled.
rev. 1.20 80 ?e???a?? 1?? 201? rev. 1.20 81 ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu dle m the idle0 mode is entered when an hal t instruction is executed and when the fhiden bit in the s cc regis ter is low and the f siden bit in the s cc regis ter is high. in the id le0 m ode the cpu wi ll be swi tched of f but t he l ow spe ed osc illator wi ll be t urned on t o dri ve som e pe ripheral functions. the idle1 mode is entered when an hal t instruction is executed and when the fhiden bit in the scc register is high and the fsiden bit in the scc register is high. in the idle1 mode the cpu will be switched of f but both the high and low speed oscillators will be turned on to provide a clock source to keep some peripheral functions operational. the idle2 mode is entered when an hal t instruction is executed and when the fhiden bit in the scc register is high and the fsiden bit in the scc register is low . in the idle2 mode the cpu will be switched of f but the high speed oscillator will be turned on to provide a clock source to keep some peripheral functions operational. the registers, scc, hircc, hxtc and pllc, are used to control the system clock and the corresponding oscillator confgurations. scc cks2 cks1 cks0 ? hs ? hiden ? siden hircc clkadj clkadj ? clk ? ix hirc ? hircen hxtc hxtm hxt ? hxten pllc d ? pllis pllos2 pllos1 pllos0 pll ? pllen s?stem ope?ating mode cont?ol registe?s list scc registe? bit ? ? 5 4 3 2 1 0 name cks2 cks1 cks0 ? hs ? hiden ? siden r/w r/w r/w r/w r/w r/w r/w por 0 1 0 0 0 0 bit 7~5 cks2~cks0 : system clock selection 000: f 001: f /2 010: f /4 011: f /8 100: f 101: f /32 110: f /64 111: f sub these three bits are used to select which clock is used as the system clock source. in addition to the system clock source directly derived from f or f sub , a divided version of the high speed system oscillator can also be chosen as the system clock source. bit 4 unimplemented, read as 0 bit 3 fhs : high frequency clock, f , selection 0: hirc 1: hxt
rev. 1.20 82 ? e ??? a ?? 1 ?? 201 ? rev. 1.20 83 ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu bit 2 unimplemented, read as 0 bit 1 : high frequency oscillator control when cpu is switched off 0: disable 1: enable this bit is used to control whether the high speed oscillator is activated or stopped when the cpu is switched off by executing an halt instruction. bit 0 : low frequency oscillator control when cpu is switched off 0: disable 1: enable this bi t i s use d t o cont rol whe ther t he l ow spe ed osc illator i s ac tivated or st opped when the cpu is switched off by executing an halt instruction. the low frequency oscillator is controlled by this bit together with the wdt function enable control. if this bi t i s c leared t o 0 but t he w dt fun ction i s e nabled, t he f wdt c lock wi ll a lso be enabled. hircc register bit 7 6 5 4 3 2 1 0 name clkadj clkadj ? clk ? ix hirc ? hircen r/w r/w r/w r/w r r/w por 0 0 0 0 1 bit 7 : hirc clock automatic adjustment function control in the usb mode 0: disable 1: enable note that if the user selects the hirc as the system clock, the clkadj bit must be set to 1 to adjust the pll frequency automatically. bit 6 : hirc clock automatic adjustment stable fag 0: unstable 1: stable the clkadjf bit indicates whether the hirc frequency adjusting operation is completed or not when the clkadj bit is set to 1. users can continuously monitor the clkadjf bit by application programs to make sure that the hirc frequency accuracy is stably adjusted in the range of 0.25%. the clkadjf bit can be cleared by the application program. bit 5 : hirc clock fx automatic adjustment function control 0: disable 1: enable note that when clkadjf=1, the clkfix bit can be set high to fx the hirc frequency accuracy in the range of 0.25%. bit 4~2 unimplemented, read as 0 bit 1 : hirc oscillator stable fag 0: hirc unstable 1: hirc stable this bit is used to indi cate whe ther the hirc oscilla tor is stable or not. when the hircen bit is s et to 1 to enable the h irc os cillator, the h ircf bit w ill firs t be cleared to 0 and then set to 1 after the hirc oscillator is stable. bit 0 : hirc oscillator enable control 0: disable 1: enable
rev. 1.20 82 ?e???a?? 1?? 201? rev. 1.20 83 ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu htc rs b 7 6 5 4 2 name hxtm hxt ? hxten r/w r/w r r/w por 0 0 0 bit 7~3 unimplemented, read as 0 bit 2 hxtm : hxt mode selection 0: hxt frequency 10mhz 1: hxt frequency > 10mhz this bit is used to select the hxt oscillator operating mode. note that this bit must be properly confgured before the hxt is enabled. when the osc1 and osc2 pins are enabled and the hxten bit is set to 1 to enable the hxt oscillator , it is invalid to change the value of this bit. otherwise, this bit value can be changed with no operation on the hxt function. bit 1 hxtf : hxt oscillator stable fag 0: hxt unstable 1: hxt stable this bit is used to indicate whether the hxt oscillator is stable or not. when the hxten bit is set to 1 to enable the hxt oscillator , the hxtf bit will frst be cleared to 0 and then set to 1 after the hxt oscillator is stable. bit 0 hxten : hxt oscillator enable control 0: disable 1: enable name d ? pllis pllos2 pllos1 pllos0 pll ? pllen r/w r/w r/w r/w r/w r/w r r/w por 0 0 0 0 0 0 1 bit 7 d7 : reserved bit, cannot be used and must be fxed at 0 bit 6 unimplemented, read as 0 bit 5 pllis : pll input clock source selection 0: 12mhz clock 1: 6mhz clock if fhs=1, when a 12mhz crystal or resonator is used, the hxt frequency is divided by 2 and then multiplied by 8 using the internal pll circuit, when a 6mhz crystal or resonator is used, the hxt frequency is directly multiplied by 8 using the internal pll circuit. if fhs=0, the 12mhz hirc is selected, this bit will be automatically cleared to zero by the hardware. bit 4~2 pllos2~pllos0 : f or f pll for f clock source selection 0xx: f 100: f pll 101: f pll =12mhz 110: f pll 111: reserved bit 1 pllf : pll clock stable fag 0: unstable 1: stable this bit is used to indicate whether the pll clock is stable or not. when the pllen bit is set to 1 to enable the pll clock, the pllf bit will frst be cleare d to 0 and then set to 1 after the pll clock is stable.
rev. 1.20 84 ? e ??? a ?? 1 ?? 201 ? rev. 1.20 85 ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu bit 0 : pll enable control 0: disable 1: enable operating mode switching the d evices c an swi tch b etween o perating m odes d ynamically a llowing t he u ser t o se lect t he b est performance/power ratio for the pres ent task in hand. in this w ay microcontroller operations that do not require high performance can be executed using slower clocks thus requiring less operating current and prolonging battery life in portable applications. in simple terms, mode switching between the normal mode and slow mode is executed using the cks2~cks0 bits in the scc register while mode switching from the normal/slow modes to t he sl eep/idle mode s i s e xecuted vi a t he hal t i nstruction. w hen a n hal t i nstruction i s executed, whet her t he de vices e nter t he idl e mode or t he sle ep mode i s de termined by t he condition of the fhiden and fsiden bits in the scc register. normal f sys =f h ~f h /?4 f h on cpu ??n f sys on f sub on slow f sys =f sub f sub on cpu ??n f sys on f h on/off idle0 halt inst??ction exec?ted cpu stop ?hiden=0 ?siden=1 f h off f sub on idle1 halt inst??ction exec?ted cpu stop ?hiden=1 ?siden=1 f h on f sub on idle2 halt inst??ction exec?ted cpu stop ?hiden=1 ?siden=0 f h on f sub off sleep halt inst??ction exec?ted cpu stop ?hiden=0 ?siden=0 f h off f sub off
rev. 1.20 84 ?e???a?? 1?? 201? rev. 1.20 85 ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu rml m sl m sh when r unning i n t he nor mal mo de, wh ich u ses t he h igh sp eed sy stem o scillator, a nd t herefore consumes m ore powe r, t he syste m c lock c an swit ch t o run i n t he sl ow mode by se t t he cks2~cks0 b its t o 111 i n t he sc c r egister. t his wi ll t hen u se t he l ow sp eed sy stem o scillator which wi ll c onsume l ess po wer. use rs m ay de cide t o do t his fo r c ertain op erations whi ch do no t require high performance and can subsequently reduce power consumption. the slow mode is sourced from the lirc oscillator and therefore requires this oscillator to be stable before full mode switching occurs. cks2~cks0 = 111 sleep mode ?hiden=0? ?siden=0 halt inst??ction is exec?ted idle0 mode ?hiden=0? ?siden=1 halt inst??ction is exec?ted idle1 mode ?hiden=1? ?siden=1 halt inst??ction is exec?ted idle2 mode ?hiden=1? ?siden=0 halt inst??ction is exec?ted
rev. 1.20 8 ? ? e ??? a ?? 1 ?? 201 ? rev. 1.20 8? ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu sl m rml m sh in slow mode the system clock is derived from f sub . when system clock is switched back to the normal mode from f sub , the cks2~cks0 bits should be set to 000~1 10 and then the system clock will respectively be switched to f h ~f h /64. however, i f f h i s not use d i n sl ow m ode a nd t hus swi tched of f, i t wi ll t ake som e t ime t o re - oscillate and stabilise when switching to the normal mode from the slow mode. this is monitored using the hxtf bit in the hxtc register or the hircf bit in the hircc register or the pllf bit in the pllc register . the time duration required for the high speed system oscillator stabilization is specifed in the a.c. characteristics. cks2~cks0 = 000~110 sleep mode ?hiden=0? ?siden=0 halt inst??ction is exec?ted idle0 mode ?hiden=0? ?siden=1 halt inst??ction is exec?ted idle1 mode ?hiden=1? ?siden=1 halt inst??ction is exec?ted idle2 mode ?hiden=1? ?siden=0 halt inst??ction is exec?ted ente?ing the sleep mode there is only one way for the devic es to enter the sleep mode and that is to execute the "hal t" instruction in the application program with both the fhiden and fsiden bits in the scc register equal to 0. in this mode all the clocks and functions will be switched off except the wdt function. when this instruction is executed under the conditions described above, the following will occur: ? the syst em c lock wi ll be st opped a nd t he a pplication progra m wi ll st op a t t he "hal t" instruction. ? the data memory contents and registers will maintain their present condition. ? the i/o ports will maintain their present conditions. ? in the status register , the power down fag, pdf , will be set and the w atchdog time-out fag, t o, will be cleared. ? the wdt will be cleared and resume counting if the wdt function is enabled. if the wdt function is disabled, the wdt will be cleared and then stopped. ? the usb will enter the suspend mode if the usb function is enabled.
rev. 1.20 8? ?e???a?? 1?? 201? rev. 1.20 8 ? ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu e h dle m there is only one way for the devices to enter the idle0 mode and that is to execute the "hal t" instruction in the application program with the fhiden bit in the scc register equal to 0 and the fsiden bit in the scc register equal to 1. when this instruction is executed under the conditions described above, the following will occur: ? the f h clock will be stopped and the applic ation program will stop at the "hal t" instruction, but the f sub clock will be on. ? the data memory contents and registers will maintain their present condition. ? the i/o ports will maintain their present conditions. ? in the status register , the power down fag, pdf , will be set and the w atchdog time-out fag, t o, will be cleared. ? the wdt will be cleared and resume counting if the wdt function is enabled. if the wdt function is disabled, the wdt will be cleared and then stopped. ? the usb will enter the suspend mode if the usb function is enabled. there is only one way for the devices to enter the idle1 mode and that is to execute the "hal t" instruction in the application program with both the fhiden and fsiden bits in the scc register equal to 1. when this instruction is executed under the conditions described above, the following will occur: ? the f h and f sub clocks will be on but the application program will stop at the "halt" instruction. ? the data memory contents and registers will maintain their present condition. ? the i/o ports will maintain their present conditions. ? in the status register , the power down fag, pdf , will be set and the w atchdog time-out fag, t o, will be cleared. ? the wdt will be cleared and resume counting if the wdt function is enabled. if the wdt function is disabled, the wdt will be cleared and then stopped. there is only one way for the devices to enter the idle2 mode and that is to execute the "hal t" instruction in the application program with the fhiden bit in the scc register equal to 1 and the fsiden bit in the scc register equal to 0. when this instruction is executed under the conditions described above, the following will occur: ? t he f h clock will be on but the f sub clock will be of f and the applicatio n program will stop at the "halt" instruction. ? the data memory contents and registers will maintain their present condition. ? the i/o ports will maintain their present conditions. ? in the status register , the power down fag, pdf , will be set and the w atchdog time-out fag, t o, will be cleared. ? the wdt will be cleared and resume counting if the wdt function is enabled. if the wdt function is disabled, the wdt will be cleared and then stopped.
rev. 1.20 88 ? e ??? a ?? 1 ?? 201 ? rev. 1.20 89 ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu sa c csas as the main reason for entering the sleep or idle mode is to keep the current consumption of the devices to as low a value as possible, perhaps only in the order of several micro-amps except in the idle1 and idle2 mode, there are other considerations which must also be taken into account by the circuit designer if the power consumption is to be minimised. special attention must be made to t he i /o p ins o n t he d evices. al l h igh-impedance i nput p ins m ust b e c onnected t o e ither a fx ed high or low level as any foating input pins could create internal oscillations and result in increased current consumption. this also applies to the devices which have dif ferent package types, as there may be unbonded pins. these must either be setup as outputs or if setup as inputs must have pull- high resistors connected. care must also be taken with the loads, which are connected to i/o pins, which are setup as outputs. these should be placed in a condition in which minimum current is drawn or connected only to external circuits that do not draw current, such as other cmos inputs. also note that additional standby current will also be required if the lirc oscillator has enabled. in the idle1 and idle2 mode the high speed oscillator is on, if the peripheral function clock source is derived from the high speed oscillator , the additional standby current will also be perhaps in the order of several hundred micro-amps. to minimise power consumption the devices can ent er the sleep or any idle mode, where the cpu will be switched off. however, when the devices are woken up again, it will take a considerable time for the original system oscillator to restart, stabilise and allow normal operation to resume. after the system enters the sleep or idle mode, it can be woken up from one of various sources listed as follows: ? an external pin reset ? an usb reset signal reset ? an external active trigger edge on i/o port ? a system interrupt ? a wdt overfow if the system is woken up by an external pin or usb reset, the devices will experience a full system reset, however , if the devices are woken up by a wdt overfow , a w atchdog t imer reset will be initiated. although both of these wake-up methods will initiate a reset operation, the actual source of the wake-up can be determined by examining the t o and pdf fags. the pdf fag is cleared by a system power -up or executing the clear w atchdog t imer instructions and is set when executing the halt instruction. the t o fag is set if a wdt time-out occurs, and causes a wake-up that only resets the program counter and stack pointer, the other fags remain in their original status. each p in o n i/ o po rt c an b e se tup u sing t he p awueg0, p awueg1 o r pb wu~pgwu re gister to permit an active trigger edge transition on the pin to wake-up the system. when a pin wake-up occurs, the program will resume execution at the instruction following the hal t instruction. if the system is woken up by an interrupt, then two possible situations may occur . the frst is where the related interrupt is disabled or the interrupt is enabled but the stack is full, in which case the program will resume execution at the instruction following the hal t instruction. in this situation, the interrupt which woke-up the devices will not be immediately serviced, but will rather be serviced later wh en t he r elated i nterrupt i s f inally e nabled o r wh en a st ack l evel b ecomes f ree. t he o ther situation is where the related interrupt is enabled and the stack is not full, in which case the regular interrupt response takes place. if an interrupt request fag is set high before entering the sleep or idle mode, the wake-up function of the related interrupt will be disabled.
rev. 1.20 88 ?e???a?? 1?? 201? rev. 1.20 89 ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ah t the w atchdog t imer is provided to prevent program malfunctions or sequences from jumping to unknown locations, due to certain uncontrollable external events such as electrical noise. the w atchdog t imer clock source is provided by the internal clock, f wdt , which is sourced from the lirc oscillator . the lirc internal oscillator has an approximate frequency of 32khz and this specifed internal clock period can vary with v dd , temperature and process variations. the w atchdog timer source clock is then subdivided by a ratio of 2 8 to 2 18 to give longer timeouts, the actual value being chosen using the ws2~ws0 bits in the wdtc register. a single register , wdtc, controls the required timeout period as well as the enable/disable operation. name we4 we3 we2 we1 we0 ws2 ws1 ws0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 1 0 1 0 0 1 1 bit 7~3 : wdt function software control 10101: disable 01010: enable other values: reset mcu when t hese b its a re c hanged t o a ny o ther v alues d ue t o e nvironmental n oise t he microcontroller will be reset; this reset operation will be activated after a delay time, t sreset , and the wrf bit in the rstfc register will be set high. bit 2~0 : wdt time-out period selection 000: 2 8 /f wdt 001: 2 10 /f wdt 010: 2 12 /f wdt 011: 2 14 /f wdt 100: 2 15 /f wdt 101: 2 16 /f wdt 110: 2 17 /f wdt 111: 2 18 /f wdt these three bits determine the divis ion ratio of the w atchdog t imer s ource clock, which in turn determines the timeout period. name lvr ? lr ? wr ? r/w r/w r/w r/w por x 0 0 x: ? nknown bit 7~3 unimplemented, read as 0 bit 2 : lvr function reset fag described elsewhere. bit 1 : lvr control register software reset fag described elsewhere.
rev. 1.20 90 ? e ??? a ?? 1 ?? 201 ? rev. 1.20 91 ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu bit 0 : wdt control register software reset fag 0: not occurred 1: occurred this bit is set to 1 by the wdt control register software reset and cleared by the application pr ogram. not e t hat t his bi t c an on ly be c leared t o 0 by t he a pplication program. watchdog timer operation the w atchdog t imer ope rates by provi ding a de vice re set whe n i ts t imer ove rfows. t his m eans that i n t he a pplication pro gram a nd dur ing nor mal ope ration t he use r ha s t o st rategically c lear t he watchdog t imer before it overfows to prevent the w atchdog t imer from executing a reset. this is done using the cle ar watchdog instructions. if the program malfunction s for whatever reason, jumps to an unknow n location, or enters an endles s loop, these clear ins tructions w ill not be executed in the correc t manne r, in which case the w atchdog t imer will overfow and reset the devices. there are fve bits, we4~we0, in the wdtc register to of fer the enable/disable control and reset control of the w atchdog t imer. the wdt function will be disabled when the we4~we0 bits are set to a value of 10101b whi le t he w dt func tion wi ll be e nabled i f t he w e4~we0 bi ts a re e qual t o 01010b. if the we4~we0 bits are set to any other values, other than 01010b and 10101b, it will reset the devices after a delay time, sreset . after power on these bits will have a value of 01010b. we4~we0 bits wdt function 10101b disa ? le 01010b ena ? le an ? othe ? val ? es reset mcu watchdog timer enable/disable control under norm al progra m ope ration, a w atchdog t imer t ime-out wi ll i nitialise a de vice re set a nd se t the status bit t o. however , if the system is in the sleep or idle mode, when a w atchdog t imer time-out occurs, the t o bit in the status register will be set and only the program counter and stack pointer will be reset. four methods can be adopted to clear the contents of the w atchdog t imer. the frst is a wdt reset, which means a certain value except 01010b and 10101b written into the we4~we0 bits, the second is using the w atchdog t imer software cle ar instruction, the third is via a hal t instruction and the fourth is an external hardware reset, which means a low level on the external res pin. there is only one method of using software instruction to clear the w atchdog t imer. that is to use the single clr wdt instruction to clear the wdt . the maximum time-out period is when the 2 18 division ratio is selected. as an example, with a 32khz lirc oscillator as its source clock, this will give a maximum watchdog period of around 8 second for the 2 18 division ratio, and a minimum timeout of 8ms for the 2 8 division ration. clr wdt inst??ction we4~we0 ?its wdtc registe? reset mcu f wdt clr halt inst??ction 8-stage divide? wdt p?escale? f wdt /2 8 8-to-1 mux ws2~ws0 wdt time-o?t (2 8 /f wdt ~ 2 18 /f wdt ) res pin ?eset watchdog timer
rev. 1.20 90 ?e???a?? 1?? 201? rev. 1.20 91 ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu rs a alsa a reset function is a fundamental part of any microcontroller ensuring that the devices can be set to some predetermined condition irrespective of outside parameters. the most important reset condition is after power is frst applied to the microcontroller . in this case, internal circuitry will ensure that the mi crocontroller, after a short delay , wil l be in a well -defined stat e and re ady to execute t he fr st p rogram i nstruction. af ter t his p ower-on r eset, c ertain i mportant i nternal r egisters will be set to defned states before the program commences. one of these registers is the program counter, which will be reset to zero forcing the microcontroller to begin program execution from the lowest program memory address. in addition to the power -on reset, situations may arise where it is necessary to forcefully apply a reset c ondition whe n t he de vices a re runni ng. one e xample of t his i s whe re a fter powe r ha s be en applied and the devices are already running, the res line is forcefully pulled low . in such a case, known as a normal operation reset, some of the registers remain unchanged allowing the devices to proceed with normal operation after the reset line is allowed to return high. another type of reset is w hen the w atchdog t imer overflow s and resets the microcontroller . a ll types of reset operations result in dif ferent register conditions being setup. another reset exists in the form of a low v oltage reset, l vr, where a full reset, similar to the res reset is implemented in situations where the power supply voltage falls below a certain threshold. there are several w ays in w hich a microcontroller res et can occur , through events occurring both internally and externally: the m ost fund amental a nd una voidable re set i s t he one t hat oc curs a fter powe r i s frst a pplied t o the microcontroller . as well as ensuring that the program memory begins execution from the frst memory address, a pow er-on reset also ensures that certain other registers are preset to known conditions. all the i/o port and port control registers will power up in a high condition ensuring that all pins will be frst set to inputs. v dd t rstd +t sst res inte?nal reset 0.9v dd note: t rstd is power-on delay specifed in a.c. characteristics. although t he m icrocontroller ha s a n i nternal rc re set func tion, i f t he v dd powe r suppl y ri se t ime is not fas t enough or does not s tabilise quickly at pow er-on, the internal res et function may be incapable of providing proper reset operation. for this reason it is recommended that an external rc network is connected to the res pin, whose additional time delay will ensure that the res pin remains low for an extended period to allow the power supply to stabilise. during this time delay , normal operation of the microcontroller will be inhibited. after the res line reaches a certain voltage value, the reset delay time t rstd is invoked to provide an extra delay time after which the microcontroller will begin normal operation. the abbreviation sst in the fgures stands for system start-up t imer.
rev. 1.20 92 ? e ??? a ?? 1 ?? 201 ? rev. 1.20 93 ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu for most applicati ons a resistor connected between vdd and the res pin and a capacitor connected between vss and the res pin will provide a suitable external reset circuit. any wiring connected to the res pin should be kept as short as possible to minimise any stray noise interference. for applications that operate within an environment where more noise is present the enhanced reset circuit shown is recommended. vdd v dd res 10k ? ~ 100k ? 0.01f** 1n4148* vss 0.1f~1f 300 ? * note: * it is recommended that this component is added for added esd protection. ** it is recommended that this component is added in environments where power line noise is signifcant. pulling the res pin low using exter nal hardware will also execute a device reset. in this case, as in the case of other resets, the program counter will reset to zero and program execution initiated from this point. inte?nal reset t rstd +t sst res 0.9v dd 0.4v dd note: t rstd is power-on delay specifed in a.c. characteristics. the micr ocontroller contains a low voltage reset circuit in order to monitor the supply voltage of the devices and provides an mcu reset should the value fall below a certain predefned level. the l vr function is always enabled with a specifc l vr voltage v lvr . if the supply voltage of the devices drops to withi n a range of 0.9v~v lvr such as might occur when changing the bat tery in battery powered applications, the l vr will automatically reset the devices internally and the l vrf bit in the rstfc register will also be set to 1. for a valid l vr signal, a low supply voltage, i.e., a voltage in the range between 0.9v~v lvr must exist for a time greater than that specifed by t lvr in the l vr/lvd e lectrical c haracteristics. i f t he l ow su pply v oltage st ate d oes n ot e xceed t his v alue, the l vr will ignore the low supply voltage and will not perform a reset function. the actual v lvr value can be selec ted by the l vs bits in the l vrc register . if the l vs7~lvs0 bits are changed to some d ifferent v alues b y e nvironmental n oise, t he l vr wi ll r eset t he d evices a fter a d elay t ime, t sreset . when this happens, the lrf bit in the rstfc register will be set to 1. after power on the register will have the value of 01010101b. note that the l vr function will be automatically disabled when the devices enter the power down mode.
rev. 1.20 92 ?e???a?? 1?? 201? rev. 1.20 93 ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu lvr inte?nal reset t rstd + t sst note: t rstd is power-on delay specifed in a.c. characteristics. ? name lvs ? lvs ? lvs5 lvs4 lvs3 lvs2 lvs1 lvs0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 1 0 1 0 1 0 1 bit 7~0 lvs7~lvs0 : lvr v oltage select control 01010101: 2.1v 00110011: 2.55v 10011001: 3.15v 10101010: 3.8v any other value: generates mcu reset C register is reset to por value when an actual low voltage condit ion occurs, as specifed by one of the four defned lvr voltage values above, an mcu reset will be generated. the reset operation will be activa ted the low voltage condition keeps more than a t lvr time . in this situation the register contents will remain the same after such a reset occurs. any register value, other than the four defned l vr values above, will also result in the generation of an m cu res et. the res et operation w ill be activated after a delay time, sreset . however in this situation the register contents will be reset to the por value. ? name lvr ? lr ? wr ? r/w r/w r/w r/w por x 0 0 x: ? nknown bit 7~3 unimplemented, read as 0 bit 2 lvrf : lvr function reset fag 0: not occur 1: occurred this bit is set to 1 when a specifc low v oltage reset situation condition occurs. this bit can only be cleared to 0 by the application program. bit 1 lrf : lvr control register software reset fag 0: not occur 1: occurred this bit is set to 1 if the l vrc register contains any non-defned l vr voltage register values. this in ef fect acts like a software-reset function. this bit can only be cleared to 0 by the application program. bit 0 wrf : wdt control register software reset fag describe elsewhere.
rev. 1.20 94 ? e ??? a ?? 1 ?? 201 ? rev. 1.20 95 ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ah t rs al a the w atchdog time-out reset during normal operation is the same as a hardware res pin reset except that the w atchdog time-out fag t o will be set to 1. wdt time-o?t inte?nal reset t rstd + t sst note: t rstd is power-on delay specifed in a.c. characteristics. the w atchdog time-out reset during sleep or idle mode is a little dif ferent from other kinds of re set. mo st of t he c onditions re main unc hanged e xcept t hat t he pro gram count er a nd t he st ack pointer will be cle ared to 0 and the t o fag will be set to 1. refer to the a.c. characteristics for t sst details. wdt time-o?t inte?nal reset t sst wdt time-o?t reset d??ing sleep o? idle timing cha?t reset initial conditions the dif ferent types of reset described af fect the reset fags in dif ferent ways. these fags, known as p df and t o are located in the s tatus regis ter and are controlled by various microcontroller operations, su ch a s t he sl eep o r i dle mo de f unction o r w atchdog t imer. t he r eset f lags a re shown in the table: 0 0 powe ? -on ? eset ? ? res ? lvr o ? usb ? eset d ?? ing normal o ? slow mode ope ? ation 1 ? wdt time-o ? t ? eset d ?? ing normal o ? slow mode ope ? ation 1 1 wdt time-o ? t ? eset d ?? ing idle o ? sleep mode ope ? ation ? stands fo ? ? nchanged the following table indicates the way in which the various components of the microcontroller are affected after a power-on reset occurs. p ? og ? am co ? nte ? reset to ze ? o inte ??? pts all inte ??? pts will ? e disa ? led wdt ? time bases clea ? afte ? ? eset ? wdt ? egins co ? nting time ? mod ? les time ? mod ? les will ? e t ?? ned off inp ? t/o ? tp ? t po ? ts i/o po ? ts will ? e set ? p as inp ? ts stack pointe ? stack pointe ? will point to the top of the stack the dif ferent kinds of resets all af fect the internal registers of the microcontroller in dif ferent ways. to ensure reliable continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller is in after a particular reset occurs. the following table describes how each type of reset affects each of the microcontroller internal registers. note that where more than one package type exists the table will refect the situation for the larger package type.
rev. 1.20 94 ?e???a?? 1?? 201? rev. 1.20 95 ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu rs ht66fb572 ht66fb574 HT66FB576 rs res rs al a dt t al a dt t dle/slee usbs al a usbs dle/slee iar0 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 mp0 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 iar1 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 mp1l 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 mp1h 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 acc xxxx xxxx ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? pcl 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 tblp xxxx xxxx ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? tblh xxxx xxxx ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? tbhp ---x xxxx --- ? ???? --- ? ???? --- ? ???? --- ? ???? --- ? ???? tbhp --xx xxxx -- ?? ???? -- ?? ???? -- ?? ???? -- ?? ???? -- ?? ???? tbhp -xxx xxxx - ??? ???? - ??? ???? - ??? ???? - ??? ???? - ??? ???? status xx00 xxxx ???? ???? xx1 ? ???? ?? 11 ???? xx ?? ???? xx ?? ???? pbp ---- ---0 ---- --- ? ---- --- ? ---- --- ? ---- --- ? ---- --- ? pbp ---- --00 ---- -- ?? ---- -- ?? ---- -- ?? ---- -- ?? ---- -- ?? iar2 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 mp2l 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 mp2h 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 rst ? c ---- -x00 ---- - ??? ---- - ??? ---- - ??? ---- - ??? ---- - ??? intc0 -000 0000 -000 0000 -000 0000 - ??? ???? -000 0000 -000 0000 intc1 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 intc2 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 intc3 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 pa 1111 1111 1111 1111 1111 1111 ???? ???? 1111 1111 1111 1111 pac 1111 1111 1111 1111 1111 1111 ???? ???? 1111 1111 1111 1111 papu 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 pawueg0 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 pawueg1 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 pb ---1 1111 ---1 1111 ---1 1111 --- ? ???? ---1 1111 ---1 1111 pb -1-1 1111 -1-1 1111 -1-1 1111 - ? - ? ???? -1-1 1111 -1-1 1111 pb 1111 1111 1111 1111 1111 1111 ???? ???? 1111 1111 1111 1111 pbc ---1 1111 ---1 1111 ---1 1111 --- ? ???? ---1 1111 ---1 1111 pbc -1-1 1111 -1-1 1111 -1-1 1111 - ? - ? ???? -1-1 1111 -1-1 1111 pbc 1111 1111 1111 1111 1111 1111 ???? ???? 1111 1111 1111 1111 pbpu ---0 0000 ---0 0000 ---0 0000 --- ? ???? ---0 0000 ---0 0000 pbpu -0-0 0000 -0-0 0000 -0-0 0000 - ? - ? ???? -0-0 0000 -0-0 0000 pbpu 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 pbwu ---0 0000 ---0 0000 ---0 0000 --- ? ???? ---0 0000 ---0 0000 pbwu -0-0 0000 -0-0 0000 -0-0 0000 - ? - ? ???? -0-0 0000 -0-0 0000 pbwu 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000
rev. 1.20 9 ? ? e ??? a ?? 1 ?? 201 ? rev. 1.20 9? ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu rs ht66fb572 ht66fb574 HT66FB576 rs res rs al a dt t al a dt t dle/slee usbs al a usbs dle/slee pc --11 1--- --11 1--- --11 1--- -- ?? ? --- --11 1--- --11 1--- pc -111 1--- -111 1--- -111 1--- - ??? ? --- -111 1--- -111 1--- pc 1111 1111 1111 1111 1111 1111 ???? ???? 1111 1111 1111 1111 pcc --11 1--- --11 1--- --11 1--- -- ?? ? --- --11 1--- --11 1--- pcc -111 1--- -111 1--- -111 1--- - ??? ? --- -111 1--- -111 1--- pcc 1111 1111 1111 1111 1111 1111 ???? ???? 1111 1111 1111 1111 pcpu --00 0--- --00 0--- --00 0--- -- ?? ? --- --00 0--- --00 0--- pcpu -000 0--- -000 0--- -000 0--- - ??? ? --- -000 0--- -000 0--- pcpu 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 pcwu --00 0--- --00 0--- --00 0--- -- ?? ? --- --00 0--- --00 0--- pcwu -000 0--- -000 0--- -000 0--- - ??? ? --- -000 0--- -000 0--- pcwu 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 pe ---- 1111 ---- 1111 ---- 1111 ---- ???? ---- 1111 ---- 1111 pec ---- 1111 ---- 1111 ---- 1111 ---- ???? ---- 1111 ---- 1111 pepu ---- 0000 ---- 0000 ---- 0000 ---- ???? ---- 0000 ---- 0000 pewu ---- 0000 ---- 0000 ---- 0000 ---- ???? ---- 0000 ---- 0000 spiac0 111- --00 111- --00 111- --00 ??? - -- ?? 111- --00 111- --00 spiac1 --00 0000 --00 0000 --00 0000 -- ?? ???? --00 0000 --00 0000 spiad xxxx xxxx xxxx xxxx xxxx xxxx ???? ???? xxxx xxxx xxxx xxxx lvrc 0101 0101 0101 0101 0101 0101 ???? ???? 0101 0101 0101 0101 lvdc --00 0000 --00 0000 --00 0000 -- ?? ???? --00 0000 --00 0000 usr 0000 1011 0000 1011 0000 1011 ???? ???? 0000 1011 0000 1011 ucr1 0000 00x0 0000 00x0 0000 00x0 ???? ???? 0000 00x0 0000 00x0 ucr2 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 txr_rxr xxxx xxxx xxxx xxxx xxxx xxxx ???? ???? xxxx xxxx xxxx xxxx brg xxxx xxxx xxxx xxxx xxxx xxxx ???? ???? xxxx xxxx xxxx xxxx stmc0 0000 0--- 0000 0--- 0000 0--- ???? ? --- 0000 0--- 0000 0--- stmc1 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 stmdl 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 stmdh 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 stmal 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 stmah 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 stmrp 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 ptm0c0 0000 0--- 0000 0--- 0000 0--- ???? ? --- 0000 0--- 0000 0--- ptm0c1 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 ptm0dl 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 ptm0dh ---- --00 ---- --00 ---- --00 ---- -- ?? ---- --00 ---- --00 ptm0al 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 ptm0ah ---- --00 ---- --00 ---- --00 ---- -- ?? ---- --00 ---- --00 ptm0rpl 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000
rev. 1.20 9? ?e???a?? 1?? 201? rev. 1.20 9 ? ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu rs ht66fb572 ht66fb574 HT66FB576 rs res rs al a dt t al a dt t dle/slee usbs al a usbs dle/slee ptm0rph ---- --00 ---- --00 ---- --00 ---- -- ?? ---- --00 ---- --00 eea 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 eed 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 ? arl 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 ? d0l 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 ? d1l 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 ? d2l 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 ? d3l 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 ptm2c0 0000 0--- 0000 0--- 0000 0--- ???? ? --- 0000 0--- 0000 0--- ptm2c1 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 ptm2dl 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 ptm2dh ---- --00 ---- --00 ---- --00 ---- -- ?? ---- --00 ---- --00 ptm2al 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 ptm2ah ---- --00 ---- --00 ---- --00 ---- -- ?? ---- --00 ---- --00 ptm2rpl 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 ptm2rph ---- --00 ---- --00 ---- --00 ---- -- ?? ---- --00 ---- --00 wdtc 0101 0011 0101 0011 0101 0011 ???? ???? 0101 0011 0101 0011 sadol xxxx ---- xxxx ---- xxxx ---- ???? ---- (adr ? s=0) xxxx ---- xxxx ---- ???? ???? (adr ? s=1) sadoh xxxx xxxx xxxx xxxx xxxx xxxx ???? ???? (adr ? s=0) xxxx xxxx xxxx xxxx ---- ???? (adr ? s=1) sadc0 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 sadc1 0000 -000 0000 -000 0000 -000 ???? - ??? 0000 -000 0000 -000 sadc2 0--0 0000 0--0 0000 0--0 0000 ? -- ? ???? 0--0 0000 0--0 0000 scc 010- 0-00 010- 0-00 010- 0-00 ??? - ? - ?? 010- 0-00 010- 0-00 hircc 000- --01 ??? - --01 ??? - --01 ??? - -- ?? ??? - --01 ??? - --01 hxtc ---- -000 ---- -000 ---- -000 ---- - ??? ---- -000 ---- -000 vbgrc ---- ---0 ---- ---0 ---- ---0 ---- --- ? ---- ---0 ---- ---0 pllc 0-00 0001 0- ?? ?? 0 ? 0- ?? ?? 0 ? ? - ?? ???? 0- ?? ?? 0 ? 0- ?? ?? 0 ? tb0c 0--- -000 0--- -000 0--- -000 ? --- - ??? 0--- -000 0--- -000 tb1c 0--- -000 0--- -000 0--- -000 ? --- - ??? 0--- -000 0--- -000 sysc -000 --0x -000 --0x -000 --0x - ??? -- ? x -000 --0x -000 --0x usb_stat 11xx 000- ?? xx ??? - ?? xx ??? - ?? xx ??? - ?? xx ??? - ?? xx ??? - uint 0000 0000 ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? usc 1000 xxxx ???? x ?? x ???? x ?? x ???? x ?? x ???? 0100 ???? 0100 uesr xxxx xxxx ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ucc 0-0x 0xxx ? - ?? ???? ? - ?? ???? ? - ?? ???? ? - ? 0 ? 000 ? - ? 0 ? 000
rev. 1.20 98 ? e ??? a ?? 1 ?? 201 ? rev. 1.20 99 ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu rs ht66fb572 ht66fb574 HT66FB576 rs res rs al a dt t al a dt t dle/slee usbs al a usbs dle/slee awr xxxx xxxx ???? ???? ???? ???? ???? ???? 0000 0000 0000 0000 stli xxxx xxxx ???? ???? ???? ???? ???? ???? 0000 0000 0000 0000 stlo xxxx xxx- ???? ??? - ???? ??? - ???? ??? - 0000 000- 0000 000- sies xxxx xxxx ? xxx x ??? ? xxx x ??? ? xxx x ??? 0000 0000 0000 0000 misc xxx0 -xxx xx ?? - ? xx xx ?? - ? xx xx ?? - ? xx 000 ? -000 000 ? -000 u ? ien 0000 0000 ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? u ? oen 0000 0000 ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? u ? c0 0000 00-- ???? ?? -- ???? ?? -- ???? ?? -- ???? ?? -- ???? ?? -- u ? c1 0000 0000 ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? u ? c2 ---- 0000 ---- ???? ---- ???? ---- ???? ---- ???? ---- ???? ? i ? o0 xxxx xxxx ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ? i ? o1 xxxx xxxx ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ? i ? o2 xxxx xxxx ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ? i ? o3 xxxx xxxx ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ? i ? o4 xxxx xxxx ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ? i ? o5 xxxx xxxx ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ? i ? o ? xxxx xxxx ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ? i ? o ? xxxx xxxx ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? simc0 111- 0000 111- 0000 111- 0000 ??? - ???? 111- 0000 111- 0000 simc1 1000 0001 1000 0001 1000 0001 ???? ???? 1000 0001 1000 0001 simd xxxx xxxx xxxx xxxx xxxx xxxx ???? ???? xxxx xxxx xxxx xxxx sima/ simc2 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 simtoc 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 slewc0 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 slewc1 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 slewc2 0000 --00 0000 --00 0000 --00 ???? -- ?? 0000 --00 0000 --00 slewc3 ---- 0000 ---- 0000 ---- 0000 ---- ???? ---- 0000 ---- 0000 m ? i0 --00 --00 --00 --00 --00 --00 -- ?? -- ?? --00 --00 --00 --00 m ? i1 --00 --00 --00 --00 --00 --00 -- ?? -- ?? --00 --00 --00 --00 m ? i2 --00 --00 --00 --00 --00 --00 -- ?? -- ?? --00 --00 --00 --00 m ? i3 --00 --00 --00 --00 --00 --00 -- ?? -- ?? --00 --00 --00 --00 m ? i4 --00 --00 --00 --00 --00 --00 -- ?? -- ?? --00 --00 --00 --00 m ? i5 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 pmps ---- 0000 ---- 0000 ---- 0000 ---- ???? ---- 0000 ---- 0000 drvcc0 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 drvcc1 --00 ---0 --00 ---0 --00 ---0 -- ?? --- ? --00 ---0 --00 ---0 drvcc1 --00 00-0 --00 00-0 --00 00-0 -- ?? ?? - ? --00 00-0 --00 00-0 i ? s ---- 0000 ---- 0000 ---- 0000 ---- ???? ---- 0000 ---- 0000 integ ---- 0000 ---- 0000 ---- 0000 ---- ???? ---- 0000 ---- 0000
rev. 1.20 98 ?e???a?? 1?? 201? rev. 1.20 99 ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu rs ht66fb572 ht66fb574 HT66FB576 rs res rs al a dt t al a dt t dle/slee usbs al a usbs dle/slee pd 111- -111 111- -111 111- -111 ??? - - ??? 111- -111 111- -111 pd 1111 1111 1111 1111 1111 1111 ???? ???? 1111 1111 1111 1111 pdc 111- -111 111- -111 111- -111 ??? - - ??? 111- -111 111- -111 pdc 1111 1111 1111 1111 1111 1111 ???? ???? 1111 1111 1111 1111 pdpu 000- -000 000- -000 000- -000 ??? - - ??? 000- -000 000- -000 pdpu 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 pdwu 000- -000 000- -000 000- -000 ??? - - ??? 000- -000 000- -000 pdwu 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 p ? 1111 1111 1111 1111 1111 1111 ???? ???? 1111 1111 1111 1111 p ? c 1111 1111 1111 1111 1111 1111 ???? ???? 1111 1111 1111 1111 p ? pu 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 p ? wu 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 pg 1111 1111 1111 1111 1111 1111 ???? ???? 1111 1111 1111 1111 pgc 1111 1111 1111 1111 1111 1111 ???? ???? 1111 1111 1111 1111 pgpu 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 pgwu 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 pas0 0000 00-- 0000 00-- 0000 00-- ???? ?? -- 0000 00-- 0000 00-- pas1 --00 0000 --00 0000 --00 0000 -- ?? ???? --00 0000 --00 0000 pbs0 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 pbs1 ---- --00 ---- --00 ---- --00 ---- -- ?? ---- --00 ---- --00 pbs1 --00 --00 --00 --00 --00 --00 -- ?? -- ?? --00 --00 --00 --00 pbs1 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 pcs0 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 pcs1 ---- 0000 ---- 0000 ---- 0000 ---- ???? ---- 0000 ---- 0000 pcs1 --00 0000 --00 0000 --00 0000 -- ?? ???? --00 0000 --00 0000 pcs1 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 pds0 ---- 0000 ---- 0000 ---- 0000 ---- ???? ---- 0000 ---- 0000 pds0 00-- 0000 00-- 0000 00-- 0000 ?? -- ???? 00-- 0000 00-- 0000 pds1 0000 00-- 0000 00-- 0000 00-- ???? ?? -- 0000 00-- 0000 00-- pds1 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 pes0 0000 --00 0000 --00 0000 --00 ???? -- ?? 0000 --00 0000 --00 pgs0 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 pgs1 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 ptm1c0 0000 0--- 0000 0--- 0000 0--- ???? ? --- 0000 0--- 0000 0--- ptm1c1 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 ptm1dl 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 ptm1dh ---- --00 ---- --00 ---- --00 ---- -- ?? ---- --00 ---- --00 ptm1al 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 ptm1ah ---- --00 ---- --00 ---- --00 ---- -- ?? ---- --00 ---- --00 ptm1rpl 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000
rev. 1.20 100 ? e ??? a ?? 1 ?? 201 ? rev. 1.20 101 ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu rs ht66fb572 ht66fb574 HT66FB576 rs res rs al a dt t al a dt t dle/slee usbs al a usbs dle/slee ptm1rph ---- --00 ---- --00 ---- --00 ---- -- ?? ---- --00 ---- --00 eec ---- 0000 ---- 0000 ---- 0000 ---- ???? ---- 0000 ---- 0000 ? rcr 00-0 ---0 00- ? ---0 00- ? ---0 ?? - ? --- ? 00- ? ---0 00- ? ---0 ? cr 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 ? arh ---0 0000 ---0 0000 ---0 0000 --- ? ???? ---0 0000 ---0 0000 ? arh --00 0000 --00 0000 --00 0000 -- ?? ???? --00 0000 --00 0000 ? arh -000 0000 -000 0000 -000 0000 -000 0000 - ??? ???? -000 0000 ? d0h 0000 0000 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 ? d1h 0000 0000 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 ? d2h 0000 0000 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 ? d3h 0000 0000 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 cmp0c -000 ---1 -000 ---1 -000 ---1 - ??? --- ? -000 ---1 -000 ---1 cmp1c -000 ---1 -000 ---1 -000 ---1 - ??? --- ? -000 ---1 -000 ---1 pscr ---- --00 ---- --00 ---- --00 ---- -- ?? ---- --00 ---- --00 lm0ir 0-00 0000 0-00 0000 0-00 0000 ? - ?? ???? 0-00 0000 0-00 0000 lm0car 0-00 0000 0-00 0000 0-00 0000 ? - ?? ???? 0-00 0000 0-00 0000 lm0cbr 0-00 0000 0-00 0000 0-00 0000 ? - ?? ???? 0-00 0000 0-00 0000 lm0ccr 0-00 0000 0-00 0000 0-00 0000 ? - ?? ???? 0-00 0000 0-00 0000 lm1ir 0-00 0000 0-00 0000 0-00 0000 ? - ?? ???? 0-00 0000 0-00 0000 lm1car 0-00 0000 0-00 0000 0-00 0000 ? - ?? ???? 0-00 0000 0-00 0000 lm1cbr 0-00 0000 0-00 0000 0-00 0000 ? - ?? ???? 0-00 0000 0-00 0000 lm1ccr 0-00 0000 0-00 0000 0-00 0000 ? - ?? ???? 0-00 0000 0-00 0000 lm2ir 0-00 0000 0-00 0000 0-00 0000 ? - ?? ???? 0-00 0000 0-00 0000 lm2car 0-00 0000 0-00 0000 0-00 0000 ? - ?? ???? 0-00 0000 0-00 0000 lm2cbr 0-00 0000 0-00 0000 0-00 0000 ? - ?? ???? 0-00 0000 0-00 0000 lm2ccr 0-00 0000 0-00 0000 0-00 0000 ? - ?? ???? 0-00 0000 0-00 0000 lm3ir 0-00 0000 0-00 0000 0-00 0000 ? - ?? ???? 0-00 0000 0-00 0000 lm3car 0-00 0000 0-00 0000 0-00 0000 ? - ?? ???? 0-00 0000 0-00 0000 lm3cbr 0-00 0000 0-00 0000 0-00 0000 ? - ?? ???? 0-00 0000 0-00 0000 lm3ccr 0-00 0000 0-00 0000 0-00 0000 ? - ?? ???? 0-00 0000 0-00 0000 lm4ir 0-00 0000 0-00 0000 0-00 0000 ? - ?? ???? 0-00 0000 0-00 0000 lm4car 0-00 0000 0-00 0000 0-00 0000 ? - ?? ???? 0-00 0000 0-00 0000 lm4cbr 0-00 0000 0-00 0000 0-00 0000 ? - ?? ???? 0-00 0000 0-00 0000 lm4ccr 0-00 0000 0-00 0000 0-00 0000 ? - ?? ???? 0-00 0000 0-00 0000 lm5ir 0-00 0000 0-00 0000 0-00 0000 ? - ?? ???? 0-00 0000 0-00 0000 lm5car 0-00 0000 0-00 0000 0-00 0000 ? - ?? ???? 0-00 0000 0-00 0000 lm5cbr 0-00 0000 0-00 0000 0-00 0000 ? - ?? ???? 0-00 0000 0-00 0000 lm5ccr 0-00 0000 0-00 0000 0-00 0000 ? - ?? ???? 0-00 0000 0-00 0000 lm ? ir 0-00 0000 0-00 0000 0-00 0000 ? - ?? ???? 0-00 0000 0-00 0000 lm ? car 0-00 0000 0-00 0000 0-00 0000 ? - ?? ???? 0-00 0000 0-00 0000
rev. 1.20 100 ?e???a?? 1?? 201? rev. 1.20 101 ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu rs ht66fb572 ht66fb574 HT66FB576 rs res rs al a dt t al a dt t dle/slee usbs al a usbs dle/slee lm ? cbr 0-00 0000 0-00 0000 0-00 0000 ? - ?? ???? 0-00 0000 0-00 0000 lm ? ccr 0-00 0000 0-00 0000 0-00 0000 ? - ?? ???? 0-00 0000 0-00 0000 lm ? ir 0-00 0000 0-00 0000 0-00 0000 ? - ?? ???? 0-00 0000 0-00 0000 lm ? car 0-00 0000 0-00 0000 0-00 0000 ? - ?? ???? 0-00 0000 0-00 0000 lm ? cbr 0-00 0000 0-00 0000 0-00 0000 ? - ?? ???? 0-00 0000 0-00 0000 lm ? ccr 0-00 0000 0-00 0000 0-00 0000 ? - ?? ???? 0-00 0000 0-00 0000 lm8ir 0-00 0000 0-00 0000 0-00 0000 ? - ?? ???? 0-00 0000 0-00 0000 lm8car 0-00 0000 0-00 0000 0-00 0000 ? - ?? ???? 0-00 0000 0-00 0000 lm8cbr 0-00 0000 0-00 0000 0-00 0000 ? - ?? ???? 0-00 0000 0-00 0000 lm8ccr 0-00 0000 0-00 0000 0-00 0000 ? - ?? ???? 0-00 0000 0-00 0000 lm9ir 0-00 0000 0-00 0000 0-00 0000 ? - ?? ???? 0-00 0000 0-00 0000 lm9car 0-00 0000 0-00 0000 0-00 0000 ? - ?? ???? 0-00 0000 0-00 0000 lm9cbr 0-00 0000 0-00 0000 0-00 0000 ? - ?? ???? 0-00 0000 0-00 0000 lm9ccr 0-00 0000 0-00 0000 0-00 0000 ? - ?? ???? 0-00 0000 0-00 0000 lmair 0-00 0000 0-00 0000 0-00 0000 ? - ?? ???? 0-00 0000 0-00 0000 lmacar 0-00 0000 0-00 0000 0-00 0000 ? - ?? ???? 0-00 0000 0-00 0000 lmacbr 0-00 0000 0-00 0000 0-00 0000 ? - ?? ???? 0-00 0000 0-00 0000 lmaccr 0-00 0000 0-00 0000 0-00 0000 ? - ?? ???? 0-00 0000 0-00 0000 lmbir 0-00 0000 0-00 0000 0-00 0000 ? - ?? ???? 0-00 0000 0-00 0000 lmbcar 0-00 0000 0-00 0000 0-00 0000 ? - ?? ???? 0-00 0000 0-00 0000 lmbcbr 0-00 0000 0-00 0000 0-00 0000 ? - ?? ???? 0-00 0000 0-00 0000 lmbccr 0-00 0000 0-00 0000 0-00 0000 ? - ?? ???? 0-00 0000 0-00 0000 lmcir 0-00 0000 0-00 0000 0-00 0000 ? - ?? ???? 0-00 0000 0-00 0000 lmccar 0-00 0000 0-00 0000 0-00 0000 ? - ?? ???? 0-00 0000 0-00 0000 lmccbr 0-00 0000 0-00 0000 0-00 0000 ? - ?? ???? 0-00 0000 0-00 0000 lmcccr 0-00 0000 0-00 0000 0-00 0000 ? - ?? ???? 0-00 0000 0-00 0000 lmdir 0-00 0000 0-00 0000 0-00 0000 ? - ?? ???? 0-00 0000 0-00 0000 lmdcar 0-00 0000 0-00 0000 0-00 0000 ? - ?? ???? 0-00 0000 0-00 0000 lmdcbr 0-00 0000 0-00 0000 0-00 0000 ? - ?? ???? 0-00 0000 0-00 0000 lmdccr 0-00 0000 0-00 0000 0-00 0000 ? - ?? ???? 0-00 0000 0-00 0000 lmeir 0-00 0000 0-00 0000 0-00 0000 ? - ?? ???? 0-00 0000 0-00 0000 lmecar 0-00 0000 0-00 0000 0-00 0000 ? - ?? ???? 0-00 0000 0-00 0000 lmecbr 0-00 0000 0-00 0000 0-00 0000 ? - ?? ???? 0-00 0000 0-00 0000 lmeccr 0-00 0000 0-00 0000 0-00 0000 ? - ?? ???? 0-00 0000 0-00 0000 lm ? ir 0-00 0000 0-00 0000 0-00 0000 ? - ?? ???? 0-00 0000 0-00 0000 lm ? car 0-00 0000 0-00 0000 0-00 0000 ? - ?? ???? 0-00 0000 0-00 0000 lm ? cbr 0-00 0000 0-00 0000 0-00 0000 ? - ?? ???? 0-00 0000 0-00 0000 lm ? ccr 0-00 0000 0-00 0000 0-00 0000 ? - ?? ???? 0-00 0000 0-00 0000 rac0e0 ---0 0000 ---0 0000 ---0 0000 --- ? ???? ---0 0000 ---0 0000 rac0e0 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000
rev. 1.20 102 ? e ??? a ?? 1 ?? 201 ? rev. 1.20 103 ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu rs ht66fb572 ht66fb574 HT66FB576 rs res rs al a dt t al a dt t dle/slee usbs al a usbs dle/slee rac0e1 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 rac1e0 ---0 0000 ---0 0000 ---0 0000 --- ? ???? ---0 0000 ---0 0000 rac1e0 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 rac1e1 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 rac2e0 ---0 0000 ---0 0000 ---0 0000 --- ? ???? ---0 0000 ---0 0000 rac2e0 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 rac2e1 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 rac3e0 ---0 0000 ---0 0000 ---0 0000 --- ? ???? ---0 0000 ---0 0000 rac3e0 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 rac3e1 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 rac4e0 ---0 0000 ---0 0000 ---0 0000 --- ? ???? ---0 0000 ---0 0000 rac4e0 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 rac4e1 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 rac5e0 ---0 0000 ---0 0000 ---0 0000 --- ? ???? ---0 0000 ---0 0000 rac5e0 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 rac5e1 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 rac ? e0 ---0 0000 ---0 0000 ---0 0000 --- ? ???? ---0 0000 ---0 0000 rac ? e0 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 rac ? e1 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 rac ? e0 ---0 0000 ---0 0000 ---0 0000 --- ? ???? ---0 0000 ---0 0000 rac ? e0 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 rac ? e1 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 rbc0e0 ---0 0000 ---0 0000 ---0 0000 --- ? ???? ---0 0000 ---0 0000 rbc0e0 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 rbc0e1 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 rbc1e0 ---0 0000 ---0 0000 ---0 0000 --- ? ???? ---0 0000 ---0 0000 rbc1e0 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 rbc1e1 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 rbc2e0 ---0 0000 ---0 0000 ---0 0000 --- ? ???? ---0 0000 ---0 0000 rbc2e0 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 rbc2e1 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 rbc3e0 ---0 0000 ---0 0000 ---0 0000 --- ? ???? ---0 0000 ---0 0000 rbc3e0 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 rbc3e1 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 rbc4e0 ---0 0000 ---0 0000 ---0 0000 --- ? ???? ---0 0000 ---0 0000 rbc4e0 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 rbc4e1 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 rbc5e0 ---0 0000 ---0 0000 ---0 0000 --- ? ???? ---0 0000 ---0 0000 rbc5e0 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 rbc5e1 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000
rev. 1.20 102 ?e???a?? 1?? 201? rev. 1.20 103 ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu rs ht66fb572 ht66fb574 HT66FB576 rs res rs al a dt t al a dt t dle/slee usbs al a usbs dle/slee rbc ? e0 ---0 0000 ---0 0000 ---0 0000 --- ? ???? ---0 0000 ---0 0000 rbc ? e0 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 rbc ? e1 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 rbc ? e0 ---0 0000 ---0 0000 ---0 0000 --- ? ???? ---0 0000 ---0 0000 rbc ? e0 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 rbc ? e1 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 lcio0 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 lcio1 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 l ? cr 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 pwmctl0 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 pwmctl1 0100 0000 0100 0000 0100 0000 ???? ???? 0100 0000 0100 0000 pwmilm --00 0000 --00 0000 --00 0000 -- ?? ???? --00 0000 --00 0000 pwmalm --00 0000 --00 0000 --00 0000 -- ?? ???? --00 0000 --00 0000 pwmblm --00 0000 --00 0000 --00 0000 -- ?? ???? --00 0000 --00 0000 pwmclm --00 0000 --00 0000 --00 0000 -- ?? ???? --00 0000 --00 0000 pwmihm --11 1111 --11 1111 --11 1111 -- ?? ???? --11 1111 --11 1111 pwmahm --11 1111 --11 1111 --11 1111 -- ?? ???? --11 1111 --11 1111 pwmbhm --11 1111 --11 1111 --11 1111 -- ?? ???? --11 1111 --11 1111 pwmchm --11 1111 --11 1111 --11 1111 -- ?? ???? --11 1111 --11 1111 hlmos 0000 0000 0000 0000 0000 0000 ???? ???? 0000 0000 0000 0000 hlmd --11 1111 --11 1111 --11 1111 -- ?? ???? --11 1111 --11 1111 llmd --00 0000 --00 0000 --00 0000 -- ?? ???? --00 0000 --00 0000 ccs 0010 --01 0010 --01 0010 --01 ???? -- ?? 0010 --01 0010 --01 note: u stands for unchanged x stands for unknown - stands for unimplemented
rev. 1.20 104 ? e ??? a ?? 1 ?? 201 ? rev. 1.20 105 ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu / s holtek m icrocontrollers of fer c onsiderable fe xibility on t heir i/ o port s. w ith t he i nput or out put designation of every pin fully under user program control, pull-high selections for all ports and wake-up selections on certain pins, the user is provided with an i/o structure to meet the needs of a wide range of application possibilities. the de vices pro vide bi directional i nput/output l ines l abeled wi th por t na mes p a~pg. t hese i/ o ports are mapped to the ram data memory with specifc addresses as shown in the special purpose data memory table. a ll of thes e i/o ports can be used for input and output operations. for input operation, these ports are non-latch ing, which means the inputs must be ready at the t2 rising edge of instruction mov a, [m], where m denotes the port address. for output operation, all the data is latched and remains unchanged until the output latch is rewritten. pa pa ? pa ? pa5 pa4 pa3 pa2 pa1 pa0 pac pac ? pac ? pac5 pac4 pac3 pac2 pac1 pac0 papu papu ? papu ? papu5 papu4 papu3 papu2 papu1 papu0 pawueg0 pawueg0 ? pawueg0 ? pawueg05 pawueg04 pawueg03 pawueg02 pawueg01 pawueg00 pawueg1 pawueg1 ? pawueg1 ? pawueg15 pawueg14 pawueg13 pawueg12 pawueg11 pawueg10 pb pb4 pb3 pb2 pb1 pb0 pbc pbc4 pbc3 pbc2 pbc1 pbc0 pbpu pbpu4 pbpu3 pbpu2 pbpu1 pbpu0 pbwu pbwu4 pbwu3 pbwu2 pbwu1 pbwu0 pc pc5 pc4 pc3 pcc pcc5 pcc4 pcc3 pcpu pcpu5 pcpu4 pcpu3 pcwu pcwu5 pcwu4 pcwu3 pd pd ? pd ? pd5 pd2 pd1 pd0 pdc pdc ? pdc ? pdc5 pdc2 pdc1 pdc0 pdpu pdpu ? pdpu ? pdpu5 pdpu2 pdpu1 pdpu0 pdwu pdwu ? pdwu ? pdwu5 pdwu2 pdwu1 pdwu0 pe pe3 pe2 pe1 pe0 pec pec3 pec2 pec1 pec0 pepu pepu3 pepu2 pepu1 pepu0 pewu pewu3 pewu2 pewu1 pewu0 pg pg ? pg ? pg5 pg4 pg3 pg2 pg1 pg0 pgc pgc ? pgc ? pgc5 pgc4 pgc3 pgc2 pgc1 pgc0 pgpu pgpu ? pgpu ? pgpu5 pgpu4 pgpu3 pgpu2 pgpu1 pgpu0 pgwu pgwu ? pgwu ? pgwu5 pgwu4 pgwu3 pgwu2 pgwu1 pgwu0 i/o logic ??nction registe?s list C ht???b5?2
rev. 1.20 104 ?e???a?? 1?? 201? rev. 1.20 105 ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu rs a b 7 6 5 4 2 pa pa ? pa ? pa5 pa4 pa3 pa2 pa1 pa0 pac pac ? pac ? pac5 pac4 pac3 pac2 pac1 pac0 papu papu ? papu ? papu5 papu4 papu3 papu2 papu1 papu0 pawueg0 pawueg0 ? pawueg0 ? pawueg05 pawueg04 pawueg03 pawueg02 pawueg01 pawueg00 pawueg1 pawueg1 ? pawueg1 ? pawueg15 pawueg14 pawueg13 pawueg12 pawueg11 pawueg10 pb pb ? pb4 pb3 pb2 pb1 pb0 pbc pbc ? pbc4 pbc3 pbc2 pbc1 pbc0 pbpu pbpu ? pbpu4 pbpu3 pbpu2 pbpu1 pbpu0 pbwu pbwu ? pbwu4 pbwu3 pbwu2 pbwu1 pbwu0 pc pc ? pc5 pc4 pc3 pcc pcc ? pcc5 pcc4 pcc3 pcpu pcpu ? pcpu5 pcpu4 pcpu3 pcwu pcwu ? pcwu5 pcwu4 pcwu3 pd pd ? pd ? pd5 pd4 pd3 pd2 pd1 pd0 pdc pdc ? pdc ? pdc5 pdc4 pdc3 pdc2 pdc1 pdc0 pdpu pdpu ? pdpu ? pdpu5 pdpu4 pdpu3 pdpu2 pdpu1 pdpu0 pdwu pdwu ? pdwu ? pdwu5 pdwu4 pdwu3 pdwu2 pdwu1 pdwu0 pe pe3 pe2 pe1 pe0 pec pec3 pec2 pec1 pec0 pepu pepu3 pepu2 pepu1 pepu0 pewu pewu3 pewu2 pewu1 pewu0 pg pg ? pg ? pg5 pg4 pg3 pg2 pg1 pg0 pgc pgc ? pgc ? pgc5 pgc4 pgc3 pgc2 pgc1 pgc0 pgpu pgpu ? pgpu ? pgpu5 pgpu4 pgpu3 pgpu2 pgpu1 pgpu0 pgwu pgwu ? pgwu ? pgwu5 pgwu4 pgwu3 pgwu2 pgwu1 pgwu0 i/o logic ??nction registe?s list C ht???b5?4
rev. 1.20 10 ? ? e ??? a ?? 1 ?? 201 ? rev. 1.20 10? ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu rs a b 7 6 5 4 2 pa pa ? pa ? pa5 pa4 pa3 pa2 pa1 pa0 pac pac ? pac ? pac5 pac4 pac3 pac2 pac1 pac0 papu papu ? papu ? papu5 papu4 papu3 papu2 papu1 papu0 pawueg0 pawueg0 ? pawueg0 ? pawueg05 pawueg04 pawueg03 pawueg02 pawueg01 pawueg00 pawueg1 pawueg1 ? pawueg1 ? pawueg15 pawueg14 pawueg13 pawueg12 pawueg11 pawueg10 pb pb ? pb ? pb5 pb4 pb3 pb2 pb1 pb0 pbc pbc ? pbc ? pbc5 pbc4 pbc3 pbc2 pbc1 pbc0 pbpu pbpu ? pbpu ? pbpu5 pbpu4 pbpu3 pbpu2 pbpu1 pbpu0 pbwu pbwu ? pbwu ? pbwu5 pbwu4 pbwu3 pbwu2 pbwu1 pbwu0 pc pc ? pc ? pc5 pc4 pc3 pc2 pc1 pc0 pcc pcc ? pcc ? pcc5 pcc4 pcc3 pcc2 pcc1 pcc0 pcpu pcpu ? pcpu ? pcpu5 pcpu4 pcpu3 pcpu2 pcpu1 pcpu0 pcwu pcwu ? pcwu ? pcwu5 pcwu4 pcwu3 pcwu2 pcwu1 pcwu0 pd pd ? pd ? pd5 pd4 pd3 pd2 pd1 pd0 pdc pdc ? pdc ? pdc5 pdc4 pdc3 pdc2 pdc1 pdc0 pdpu pdpu ? pdpu ? pdpu5 pdpu4 pdpu3 pdpu2 pdpu1 pdpu0 pdwu pdwu ? pdwu ? pdwu5 pdwu4 pdwu3 pdwu2 pdwu1 pdwu0 pe pe3 pe2 pe1 pe0 pec pec3 pec2 pec1 pec0 pepu pepu3 pepu2 pepu1 pepu0 pewu pewu3 pewu2 pewu1 pewu0 p ? p ?? p ?? p ? 5 p ? 4 p ? 3 p ? 2 p ? 1 p ? 0 p ? c p ? c ? p ? c ? p ? c5 p ? c4 p ? c3 p ? c2 p ? c1 p ? c0 p ? pu p ? pu ? p ? pu ? p ? pu5 p ? pu4 p ? pu3 p ? pu2 p ? pu1 p ? pu0 p ? wu p ? wu ? p ? wu ? p ? wu5 p ? wu4 p ? wu3 p ? wu2 p ? wu1 p ? wu0 pg pg ? pg ? pg5 pg4 pg3 pg2 pg1 pg0 pgc pgc ? pgc ? pgc5 pgc4 pgc3 pgc2 pgc1 pgc0 pgpu pgpu ? pgpu ? pgpu5 pgpu4 pgpu3 pgpu2 pgpu1 pgpu0 pgwu pgwu ? pgwu ? pgwu5 pgwu4 pgwu3 pgwu2 pgwu1 pgwu0 : unimplemented ? ? ead as 0 i/o logic ??nction registe?s list C ht???b5??
rev. 1.20 10? ?e???a?? 1?? 201? rev. 1.20 10 ? ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu llhh rsss many product applications require pull-high resistors for their switch inputs usually requiring the use of an external resistor . t o eliminate the need for these external resistors, all i/o pins, when confgured as an input have the capability of being connected to an internal pull-high resistor . these pull-high resistors are selected using registers, namely p apu~pgpu, and are implemented using weak pmos transistors. note that the pull-high resistor can be controlled by the relevant pull-high control register only when the pin-shared functional pin is selected as an input or nmos output. otherwise, the pull-high resistors cannot be enabled. name pxpu ? pxpu ? pxpu5 pxpu4 pxpu3 pxpu2 pxpu1 pxpu0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 pxpun : i/o port x pin pull-high function control 0: disable 1: enable the pxpun bit is used to control the pin pull-high function. here the x can be a, b, c, d, e, f and g. however, the actual available bits for each i/o port may be different. the hal t instruction forces the microcontroller into the sleep or idle mode which preserves power, a feature that is important for battery and other low-power applications. v arious methods exist to wake-up the microcontroller, one of which is to change the logic condition on one of the port b ~ port g pins from high to low , while from high to low or from low to high or both on one of the port a pins. this function is especially suitable for applications that can be woken up via external switches. each pin on p a~pg can be selected individually to have this wake-up feature using the pawueg0, pawueg1, pbwu~pgwu registers. note t hat t he wa ke-up f unction c an b e c ontrolled b y t he wa ke-up c ontrol r egisters o nly wh en t he pin-shared functio nal pin is selected as general purpose input/output and the mcu enters the power down mode. name pxwu ? pxwu ? pxwu5 pxwu4 pxwu3 pxwu2 pxwu1 pxwu0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 pxwun : i/o port x pin wake-up function control 0: disable 1: enable the pxwun bit is used to control the pin wake-up function. here the x can be b, c, d, e, f and g. however, the actual available bits for each i/o port may be different. the port a can be setup to have a choice of wake-up polarity using specifc registers. each pin on port a c an be se lected i ndividually t o ha ve t his w ake-up pol arity fe ature usi ng t he p awueg0 or pawueg1 register.
rev. 1.20 108 ? e ??? a ?? 1 ?? 201 ? rev. 1.20 109 ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ueg rs b 7 6 5 4 2 name pawueg0 ? pawueg0 ? pawueg05 pawueg04 pawueg03 pawueg02 pawueg01 pawueg00 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 pawueg07~pawueg06 : pa3 wake-up edge control 00: disable 01: rising edge trigger 10: falling edge trigger 11: rising and falling edges trigger bit 5~4 pawueg05~pawueg04 : pa2 wake-up edge control 00: disable 01: rising edge trigger 10: falling edge trigger 11: rising and falling edges trigger bit 3~2 pawueg03~pawueg02 : pa1 wake-up edge control 00: disable 01: rising edge trigger 10: falling edge trigger 11: rising and falling edges trigger bit 1~0 pawueg01~pawueg00 : pa0 wake-up edge control 00: disable 01: rising edge trigger 10: falling edge trigger 11: rising and falling edges trigger name pawueg1 ? pawueg1 ? pawueg15 pawueg14 pawueg13 pawueg12 pawueg11 pawueg10 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 pawueg17~pawueg16 : pa7 wake-up edge control 00: disable 01: rising edge trigger 10: falling edge trigger 11: rising and falling edges trigger bit 5~4 pawueg15~pawueg14 : pa6 wake-up edge control 00: disable 01: rising edge trigger 10: falling edge trigger 11: rising and falling edges trigger bit 3~2 pawueg13~pawueg12 : pa5 wake-up edge control 00: disable 01: rising edge trigger 10: falling edge trigger 11: rising and falling edges trigger bit 1~0 pawueg11~pawueg10 : pa4 wake-up edge control 00: disable 01: rising edge trigger 10: falling edge trigger 11: rising and falling edges trigger
rev. 1.20 108 ?e???a?? 1?? 201? rev. 1.20 109 ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu / cl rss each i/o port has its ow n control register known as p ac~pgc, to control the input/output configuration. w ith this control register , each cmos output or input can be reconfigured dynamically under software control. each pin of the i/o ports is directly mapped to a bit in its associated port control register . for the i/o pin to function as an input, the corresponding bit of the control register must be written as a 1. this will then allow the logic state of the input pin to be directly read by instructions. when the corresponding bit of the control register is written as a 0, the i/o pin will be setup as a cmos output. if the pin is currently setup as an output, instructions can still be used to read the output register . however , it should be noted that the program will in fact only read the status of the output data latch and not the actual logic status of the output pin. name pxc ? pxc ? pxc5 pxc4 pxc3 pxc2 pxc1 pxc0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 1 1 pxcn : i/o port x pin type selection 0: output 1: input the pxcn bit is used to control the pin type selection. here the x can be a, b, c, d, e, f and g. however, the actual available bits for each i/o port may be different. the port a can be setup to have a choice of various power source using specifc register . the port a must be selected by nibble pins to have various power sources using the pmps register. name pmps3 pmps2 pmps1 pmps0 r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~4 unimplemented, read as 0 bit 3~2 pmps3~pmps2 : pa7~pa4 power supply selection 00: v 01: v 10: v 11: v 33o , 3.3v regulator output bit 1~0 pmps1~pmps0 : pa3~pa0 power supply selection 00: v 01: v 10: v 11: v 33o , 3.3v regulator output the i/o ports, p a~pg, can be setup to have a choice of various slew rate using specifc registers. the p a~pg must be selected by nibble pins to have various slew rate using the slewc0~slewc3 registers. users should refer to the d.c. characteristics section to obtain the exact value for dif ferent applications.
rev. 1.20 110 ? e ??? a ?? 1 ?? 201 ? rev. 1.20 111 ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu rs a b 7 6 5 4 2 slewc0 slewc0 ? slewc0 ? slewc05 slewc04 slewc03 slewc02 slewc01 slewc00 slewc1 slewc1 ? slewc1 ? slewc15 slewc14 slewc13 slewc12 slewc11 slewc10 slewc2(ht ??? b5 ? 2/ ht ??? b5 ? 4) slewc21 slewc20 slewc2(ht ??? b5 ?? ) slewc2 ? slewc2 ? slewc25 slewc24 slewc21 slewc20 slewc3 slewc33 slewc32 slewc31 slewc30 o?tp?t slew rate cont?ol registe?s list slewc0 registe? C ht???b5?2 bit ? ? 5 4 3 2 1 0 name slewc0 ? slewc0 ? slewc05 slewc04 slewc03 slewc02 slewc01 slewc00 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 slewc07~slewc06 : pb4 output slew rate selection 00: slew rate = level 0 01: slew rate = level 1 10: slew rate = level 2 11: slew rate = level 3 bit 5~4 slewc05~slewc04 : pb3~pb0 output slew rate selection 00: slew rate = level 0 01: slew rate = level 1 10: slew rate = level 2 11: slew rate = level 3 bit 3~2 slewc03~slewc02 : pa7~pa4 output slew rate selection 00: slew rate = level 0 01: slew rate = level 1 10: slew rate = level 2 11: slew rate = level 3 bit 1~0 slewc01~slewc00 : pa3~pa0 output slew rate selection 00: slew rate = level 0 01: slew rate = level 1 10: slew rate = level 2 11: slew rate = level 3 name slewc0 ? slewc0 ? slewc05 slewc04 slewc03 slewc02 slewc01 slewc00 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 slewc07~slewc06 : pb6 and pb4 output slew rate selection 00: slew rate = level 0 01: slew rate = level 1 10: slew rate = level 2 11: slew rate = level 3 bit 5~4 slewc05~slewc04 : pb3~pb0 output slew rate selection 00: slew rate = level 0 01: slew rate = level 1 10: slew rate = level 2 11: slew rate = level 3
rev. 1.20 110 ?e???a?? 1?? 201? rev. 1.20 111 ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu bit 3~2 : pa7~pa4 output slew rate selection 00: slew rate = level 0 01: slew rate = level 1 10: slew rate = level 2 11: slew rate = level 3 bit 1~0 : pa3~pa0 output slew rate selection 00: slew rate = level 0 01: slew rate = level 1 10: slew rate = level 2 11: slew rate = level 3 slewc0 register C HT66FB576 bit 7 6 5 4 3 2 1 0 name slewc0 ? slewc0 ? slewc05 slewc04 slewc03 slewc02 slewc01 slewc00 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 : pb7~pb4 output slew rate selection 00: slew rate = level 0 01: slew rate = level 1 10: slew rate = level 2 11: slew rate = level 3 bit 5~4 : pb3~pb0 output slew rate selection 00: slew rate = level 0 01: slew rate = level 1 10: slew rate = level 2 11: slew rate = level 3 bit 3~2 : pa7~pa4 output slew rate selection 00: slew rate = level 0 01: slew rate = level 1 10: slew rate = level 2 11: slew rate = level 3 bit 1~0 : pa3~pa0 output slew rate selection 00: slew rate = level 0 01: slew rate = level 1 10: slew rate = level 2 11: slew rate = level 3 slewc1 register C ht66fb572 bit 7 6 5 4 3 2 1 0 name slewc1 ? slewc1 ? slewc15 slewc14 slewc13 slewc12 slewc11 slewc10 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 : pd7~pd5 output slew rate selection 00: slew rate = level 0 01: slew rate = level 1 10: slew rate = level 2 11: slew rate = level 3 bit 5~4 : pd2~pd0 output slew rate selection 00: slew rate = level 0 01: slew rate = level 1 10: slew rate = level 2 11: slew rate = level 3
rev. 1.20 112 ? e ??? a ?? 1 ?? 201 ? rev. 1.20 113 ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu bit 3~2 : pc5~pc4 output slew rate selection 00: slew rate = level 0 01: slew rate = level 1 10: slew rate = level 2 11: slew rate = level 3 bit 1~0 : pc3 output slew rate selection 00: slew rate = level 0 01: slew rate = level 1 10: slew rate = level 2 11: slew rate = level 3 slewc1 register C ht66fb574 bit 7 6 5 4 3 2 1 0 name slewc1 ? slewc1 ? slewc15 slewc14 slewc13 slewc12 slewc11 slewc10 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 : pd7~pd4 output slew rate selection 00: slew rate = level 0 01: slew rate = level 1 10: slew rate = level 2 11: slew rate = level 3 bit 5~4 : pd3~pd0 output slew rate selection 00: slew rate = level 0 01: slew rate = level 1 10: slew rate = level 2 11: slew rate = level 3 bit 3~2 : pc6~pc4 output slew rate selection 00: slew rate = level 0 01: slew rate = level 1 10: slew rate = level 2 11: slew rate = level 3 bit 1~0 : pc3 output slew rate selection 00: slew rate = level 0 01: slew rate = level 1 10: slew rate = level 2 11: slew rate = level 3 slewc1 register C HT66FB576 bit 7 6 5 4 3 2 1 0 name slewc1 ? slewc1 ? slewc15 slewc14 slewc13 slewc12 slewc11 slewc10 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 : pd7~pd4 output slew rate selection 00: slew rate = level 0 01: slew rate = level 1 10: slew rate = level 2 11: slew rate = level 3 bit 5~4 : pd3~pd0 output slew rate selection 00: slew rate = level 0 01: slew rate = level 1 10: slew rate = level 2 11: slew rate = level 3
rev. 1.20 112 ?e???a?? 1?? 201? rev. 1.20 113 ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu bit 3~2 : pc7~pc4 output slew rate selection 00: slew rate = level 0 01: slew rate = level 1 10: slew rate = level 2 11: slew rate = level 3 bit 1~0 : pc3~pc0 output slew rate selection 00: slew rate = level 0 01: slew rate = level 1 10: slew rate = level 2 11: slew rate = level 3 slewc2 register C ht66fb572/ht66fb574 bit 7 6 5 4 3 2 1 0 name slewc21 slewc20 r/w r/w r/w por 0 0 bit 7~2 unimplemented, read as 0 bit 1~0 : pe3~pe0 output slew rate selection 00: slew rate = level 0 01: slew rate = level 1 10: slew rate = level 2 11: slew rate = level 3 slewc2 register C HT66FB576 bit 7 6 5 4 3 2 1 0 name slewc2 ? slewc2 ? slewc25 slewc24 slewc21 slewc20 r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7~6 : pf7~pf4 output slew rate selection 00: slew rate = level 0 01: slew rate = level 1 10: slew rate = level 2 11: slew rate = level 3 bit 5~4 : pf3~pf0 output slew rate selection 00: slew rate = level 0 01: slew rate = level 1 10: slew rate = level 2 11: slew rate = level 3 bit 3~2 unimplemented, read as 0 bit 1~0 : pe3~pe0 output slew rate selection 00: slew rate = level 0 01: slew rate = level 1 10: slew rate = level 2 11: slew rate = level 3 slewc3 register bit 7 6 5 4 3 2 1 0 name slewc33 slewc32 slewc31 slewc30 r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~4 unimplemented, read as 0
rev. 1.20 114 ? e ??? a ?? 1 ?? 201 ? rev. 1.20 115 ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu bit 3~2 : pg7~pg4 output slew rate selection 00: slew rate = level 0 01: slew rate = level 1 10: slew rate = level 2 11: slew rate = level 3 bit 1~0 : pg3~pg0 output slew rate selection 00: slew rate = level 0 01: slew rate = level 1 10: slew rate = level 2 11: slew rate = level 3 i/o port output current control registers the i/o ports, p a~pg, can be setup to have a choice of high or low drive currents using specifc registers. the p a~pg must be selected by nibble pins to have various output current using the drvcc0 and drvcc1 registers. users should refer to the d.c. characteristics section to obtain the exact value for different applications. register name bit 7 6 5 4 3 2 1 0 drvcc0 drvcc0 ? drvcc0 ? drvcc05 drvcc04 drvcc03 drvcc02 drvcc01 drvcc00 drvcc1 drvcc15 drvcc14 drvcc13 drvcc12 drvcc10 output current control registers list drvcc0 register C ht66fb572 bit 7 6 5 4 3 2 1 0 name drvcc0 ? drvcc0 ? drvcc05 drvcc04 drvcc03 drvcc02 drvcc01 drvcc00 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 : pd7~pd5 source & sink current selection 0: source & sink current = level 0 (min.) 1: source & sink current = level 1 (max.) bit 6 : pd2~pd0 source & sink current selection 0: source & sink current = level 0 (min.) 1: source & sink current = level 1 (max.) bit 5 : pc5~pc4 source & sink current selection 0: source & sink current = level 0 (min.) 1: source & sink current = level 1 (max.) bit 4 : pc3 source & sink current selection 0: source & sink current = level 0 (min.) 1: source & sink current = level 1 (max.) bit 3 : pb4 source & sink current selection 0: source & sink current = level 0 (min.) 1: source & sink current = level 1 (max.) bit 2 : pb3~pb0 source & sink current selection 0: source & sink current = level 0 (min.) 1: source & sink current = level 1 (max.) bit 1 : pa7~pa4 source & sink current selection 0: source & sink current = level 0 (min.) 1: source & sink current = level 1 (max.) bit 0 : pa3~pa0 source & sink current selection 0: source & sink current = level 0 (min.) 1: source & sink current = level 1 (max.)
rev. 1.20 114 ?e???a?? 1?? 201? rev. 1.20 115 ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu drcc rs ht66fb574 b 7 6 5 4 2 name drvcc0 ? drvcc0 ? drvcc05 drvcc04 drvcc03 drvcc02 drvcc01 drvcc00 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 drvcc07 : pd7~pd4 source & sink current selection 0: source & sink current = level 0 (min.) 1: source & sink current = level 1 (max.) bit 6 drvcc06 : pd3~pd0 source & sink current selection 0: source & sink current = level 0 (min.) 1: source & sink current = level 1 (max.) bit 5 drvcc05 : pc6~pc4 source & sink current selection 0: source & sink current = level 0 (min.) 1: source & sink current = level 1 (max.) bit 4 drvcc04 : pc3 source & sink current selection 0: source & sink current = level 0 (min.) 1: source & sink current = level 1 (max.) bit 3 drvcc03 : pb6 and pb4 source & sink current selection 0: source & sink current = level 0 (min.) 1: source & sink current = level 1 (max.) bit 2 drvcc02 : pb3~pb0 source & sink current selection 0: source & sink current = level 0 (min.) 1: source & sink current = level 1 (max.) bit 1 drvcc01 : pa7~pa4 source & sink current selection 0: source & sink current = level 0 (min.) 1: source & sink current = level 1 (max.) bit 0 drvcc00 : pa3~pa0 source & sink current selection 0: source & sink current = level 0 (min.) 1: source & sink current = level 1 (max.) name drvcc0 ? drvcc0 ? drvcc05 drvcc04 drvcc03 drvcc02 drvcc01 drvcc00 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 drvcc07 : pd7~pd4 source & sink current selection 0: source & sink current = level 0 (min.) 1: source & sink current = level 1 (max.) bit 6 drvcc06 : pd3~pd0 source & sink current selection 0: source & sink current = level 0 (min.) 1: source & sink current = level 1 (max.) bit 5 drvcc05 : pc7~pc4 source & sink current selection 0: source & sink current = level 0 (min.) 1: source & sink current = level 1 (max.) bit 4 drvcc04 : pc3~pc0 source & sink current selection 0: source & sink current = level 0 (min.) 1: source & sink current = level 1 (max.) bit 3 drvcc03 : pb7~pb4 source & sink current selection 0: source & sink current = level 0 (min.) 1: source & sink current = level 1 (max.)
rev. 1.20 11 ? ? e ??? a ?? 1 ?? 201 ? rev. 1.20 11 ? ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu bit 2 : pb3~pb0 source & sink current selection 0: source & sink current = level 0 (min.) 1: source & sink current = level 1 (max.) bit 1 : pa7~pa4 source & sink current selection 0: source & sink current = level 0 (min.) 1: source & sink current = level 1 (max.) bit 0 : pa3~pa0 source & sink current selection 0: source & sink current = level 0 (min.) 1: source & sink current = level 1 (max.) drvcc1 register C ht66fb572/ht66fb574 bit 7 6 5 4 3 2 1 0 name drvcc15 drvcc14 drvcc10 r/w r/w r/w r/w por 0 0 0 bit 7~6 unimplemented, read as 0 bit 5 : pg7~pg4 source & sink current selection 0: source & sink current = level 0 (min.) 1: source & sink current = level 1 (max.) bit 4 : pg3~pg0 source & sink current selection 0: source & sink current = level 0 (min.) 1: source & sink current = level 1 (max.) bit 3~1 unimplemented, read as 0 bit 0 : pe3~pe0 source & sink current selection 0: source & sink current = level 0 (min.) 1: source & sink current = level 1 (max.) drvcc1 register C HT66FB576 bit 7 6 5 4 3 2 1 0 name drvcc15 drvcc14 drvcc13 drvcc12 drvcc10 r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 bit 7~6 unimplemented, read as 0 bit 5 : pg7~pg4 source & sink current selection 0: source & sink current = level 0 (min.) 1: source & sink current = level 1 (max.) bit 4 : pg3~pg0 source & sink current selection 0: source & sink current = level 0 (min.) 1: source & sink current = level 1 (max.) bit 3 : pf7~pf4 source & sink current selection 0: source & sink current = level 0 (min.) 1: source & sink current = level 1 (max.) bit 2 : pf3~pf0 source & sink current selection 0: source & sink current = level 0 (min.) 1: source & sink current = level 1 (max.) bit 1 unimplemented, read as 0 bit 0 : pe3~pe0 source & sink current selection 0: source & sink current = level 0 (min.) 1: source & sink current = level 1 (max.)
rev. 1.20 11 ? ?e???a?? 1?? 201? rev. 1.20 11 ? ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu sha fs the fexibility of the microcontroller range is greatly enhanced by the use of pins that have more than one function. limited numbers of pins can force serious design constraints on designers but by supplying pins with multi-functions , many of these diffculties can be overcome. for these pins, the desired function of the multi-functio n i/o pins is selected by a series of registers via the application program control. the limited number of supplied pins in a package can i mpose restrictions on the amount of functions a certain device can contain. however by allowing the same pins to share several dif ferent functions and providing a means of function selection, a wide range of dif ferent functions can be incorporated into e ven r elatively sm all p ackage si zes. t he d evices i nclude po rt x ou tput fu nction se lection register n, label ed as pxsn, and input function selection register , labeled as ifs, which can select the desired functions of the multi-function pin-shared pins. when t he pi n-shared i nput funct ion i s se lected t o be use d, t he c orresponding i nput a nd output functions selection should be properly managed. for example, if the periodic t ype tm capture input mode is used, the corresponding output pin-shared function should be confgured as the periodic type tm function by confguring the pxsn register and the capture input should be properly selected using the ifs register . however , if the external interrupt function is selected to be used, the relevant output pin-shared function should be selected as an i/o function and the interrupt input signal should be selected. the m ost i mportant p oint t o n ote i s t o m ake sur e t hat t he d esired p in-shared f unction i s p roperly selected and also d eselected. fo r most pin-shared fu nctions, t o select the desired p in-shared function, the pin-shared function should frst be correctly selected using the corresponding pin-shared control register. after that the corresponding peripheral functional setting should be confgured and then the peripheral function can be enabled. however , special point must be noted for some digital input pins, such as intn, xtckn, xtpni, etc, which share the same pin-shared control confguration with their corresponding general purpose i/o functions when setting the relevant pin-shared control bit felds. t o select these pin functions, in addition to the necessary pin-shared control and peripheral functional se tup a forementioned, t hey m ust a lso b e se tup a s i nput b y se tting t he c orresponding b it in the i/o port control register . t o correctly deselect the pin-shared function, the peripheral function should first be disabled and then the corresponding pin-shared function control register can be modifed to select other pin-shared functions. pas0 pas0 ? pas0 ? pas05 pas04 pas03 pas02 pas1 pas15 pas14 pas13 pas12 pas11 pas10 pbs0 pbs0 ? pbs0 ? pbs05 pbs04 pbs03 pbs02 pbs01 pbs00 pbs1 pbs11 pbs10 pcs1 pcs13 pcs12 pcs11 pcs10 pds0 pds03 pds02 pds01 pds00 pds1 pds1 ? pds1 ? pds15 pds14 pds13 pds12 pes0 pes0 ? pes0 ? pes05 pes04 pes01 pes00 pgs0 pgs0 ? pgs0 ? pgs05 pgs04 pgs03 pgs02 pgs01 pgs00 pgs1 pgs1 ? pgs1 ? pgs15 pgs14 pgs13 pgs12 pgs11 pgs10 i ? s ptp2ips ptp1ips ptp0ips stpips pin-sha?ed ??nction selection registe?s list C ht???b5?2
rev. 1.20 118 ? e ??? a ?? 1 ?? 201 ? rev. 1.20 119 ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu rs a b 7 6 5 4 2 pas0 pas0 ? pas0 ? pas05 pas04 pas03 pas02 pas1 pas15 pas14 pas13 pas12 pas11 pas10 pbs0 pbs0 ? pbs0 ? pbs05 pbs04 pbs03 pbs02 pbs01 pbs00 pbs1 pbs15 pbs14 pbs11 pbs10 pcs1 pcs15 pcs14 pcs13 pcs12 pcs11 pcs10 pds0 pds0 ? pds0 ? pds03 pds02 pds01 pds00 pds1 pds1 ? pds1 ? pds15 pds14 pds13 pds12 pds11 pds10 pes0 pes0 ? pes0 ? pes05 pes04 pes01 pes00 pgs0 pgs0 ? pgs0 ? pgs05 pgs04 pgs03 pgs02 pgs01 pgs00 pgs1 pgs1 ? pgs1 ? pgs15 pgs14 pgs13 pgs12 pgs11 pgs10 i ? s ptp2ips ptp1ips ptp0ips stpips pin-sha?ed ??nction selection registe?s list C ht???b5?4 registe? name bit ? ? 5 4 3 2 1 0 pas0 pas0 ? pas0 ? pas05 pas04 pas03 pas02 pas1 pas15 pas14 pas13 pas12 pas11 pas10 pbs0 pbs0 ? pbs0 ? pbs05 pbs04 pbs03 pbs02 pbs01 pbs00 pbs1 pbs1 ? pbs1 ? pbs15 pbs14 pbs13 pbs12 pbs11 pbs10 pcs0 pcs0 ? pcs0 ? pcs05 pcs04 pcs03 pcs02 pcs01 pcs00 pcs1 pcs1 ? pcs1 ? pcs15 pcs14 pcs13 pcs12 pcs11 pcs10 pds0 pds03 pds02 pds01 pds00 pds1 pds1 ? pds1 ? pds15 pds14 pds13 pds12 pes0 pes0 ? pes0 ? pes05 pes04 pes01 pes00 pgs0 pgs0 ? pgs0 ? pgs05 pgs04 pgs03 pgs02 pgs01 pgs00 pgs1 pgs1 ? pgs1 ? pgs15 pgs14 pgs13 pgs12 pgs11 pgs10 i ? s ptp2ips ptp1ips ptp0ips stpips pin-sha?ed ??nction selection registe?s list C ht???b5?? ? name pas0 ? pas0 ? pas05 pas04 pas03 pas02 r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7~6 pas07~pas06 : pa3 pin-shared function selection 00/01: pa3 10: scka 11: c0- bit 5~4 pas05~pas04 : pa2 pin-shared function selection 00/01: pa2 10: sdia 11: c0+ bit 3~2 pas03~pas02 : pa1 pin-shared function selection 00/01: pa1 10: sdoa 11: c0x bit 1~0 unimplemented, read as 0
rev. 1.20 118 ?e???a?? 1?? 201? rev. 1.20 119 ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ? name pas15 pas14 pas13 pas12 pas11 pas10 r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7~6 unimplemented, read as 0 bit 5~4 pas15~pas14 : pa6 pin-shared function selection 00/01/10: pa6/stck 11: c1- bit 3~2 pas13~pas12 : pa5 pin-shared function selection 00/01: pa5/ptp0i 10: ptp0 11: c1+ bit 1~0 pas11~pas10 : pa4 pin-shared function selection 00: pa4/stpi 01: scsa 10: stp 11: c1x ? name pbs0 ? pbs0 ? pbs05 pbs04 pbs03 pbs02 pbs01 pbs00 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 pbs07~pbs06 : pb3 pin-shared function selection 00/01: pb3 10: 11: an3 bit 5~4 pbs05~pbs04 : pb2 pin-shared function selection 00/01: pb2 10: sck 11: an2 bit 3~2 pbs03~pbs02 : pb1 pin-shared function selection 00/01: pb1 10: sdi/scl 11: an1 bit 1~0 pbs01~pbs00 : pb0 pin-shared function selection 00/01: pb0 10: sdo/sda 11: an0 ? name pbs11 pbs10 r/w r/w r/w por 0 0 bit 7~2 unimplemented, read as 0 bit 1~0 pbs11~pbs10 : pb4 pin-shared function selection 00/01: pb4/stpi 10: stp 11: an4
rev. 1.20 120 ? e ??? a ?? 1 ?? 201 ? rev. 1.20 121 ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ? name pbs15 pbs14 pbs11 pbs10 r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~6 unimplemented, read as 0 bit 5~4 pbs15~pbs14 : pb6 pin-shared function selection 00/01/10: pb6 11: an5 bit 3~2 unimplemented, read as 0 bit 1~0 pbs11~pbs10 : pb4 pin-shared function selection 00/01: pb4/stpi 10: stp 11: an4 ? name pbs1 ? pbs1 ? pbs15 pbs14 pbs13 pbs12 pbs11 pbs10 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 pbs17~pbs16 : pb7 pin-shared function selection 00/01/10: pb7 11: an7 bit 5~4 pbs15~pbs14 : pb6 pin-shared function selection 00/01/10: pb6/int1 11: an6 bit 3~2 pbs13~pbs12 : pb5 pin-shared function selection 00/01/10: pb5 11: an5 bit 1~0 pbs11~pbs10 : pb4 pin-shared function selection 00/01: pb4/stpi 10: stp 11: an4 ? name pcs0 ? pcs0 ? pcs05 pcs04 pcs03 pcs02 pcs01 pcs00 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 pcs07~pcs06 : pc3 pin-shared function selection 00/01/10: pc3 11: an1 1 bit 5~4 pcs05~pcs04 : pc2 pin-shared function selection 00/01/10: pc2 11: an10 bit 3~2 pcs03~pcs02 : pc1 pin-shared function selection 00/01/10: pc1 11: an9 bit 1~0 pcs01~pcs00 : pc0 pin-shared function selection 00/01/10: pc0 11: an8
rev. 1.20 120 ?e???a?? 1?? 201? rev. 1.20 121 ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ? name pcs13 pcs12 pcs11 pcs10 r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~4 unimplemented, read as 0 bit 3~2 pcs13~pcs12 : pc5 pin-shared function selection 00/01: pc5 10: rx 11: an6 bit 1~0 pcs11~pcs10 : pc4 pin-shared function selection 00/01: pc4 10: tx 11: an5 ? name pcs15 pcs14 pcs13 pcs12 pcs11 pcs10 r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7~6 unimplemented, read as 0 bit 5~4 pcs15~pcs14 : pc6 pin-shared function selection 00/01/10: pc6 11: an8 bit 3~2 pcs13~pcs12 : pc5 pin-shared function selection 00/01: pc5 10: rx 11: an7 bit 1~0 pcs11~pcs10 : pc4 pin-shared function selection 00/01: pc4 10: tx 11: an6 ? name pcs1 ? pcs1 ? pcs15 pcs14 pcs13 pcs12 pcs11 pcs10 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 pcs17~pcs16 : pc7 pin-shared function selection 00/01/10: pc7 11: an15 bit 5~4 pcs15~pcs14 : pc6 pin-shared function selection 00/01/10: pc6 11: an14 bit 3~2 pcs13~pcs12 : pc5 pin-shared function selection 00/01: pc5 10: rx 11: an13 bit 1~0 pcs11~pcs10 : pc4 pin-shared function selection 00/01: pc4 10: tx 11: an12
rev. 1.20 122 ? e ??? a ?? 1 ?? 201 ? rev. 1.20 123 ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ? name pds03 pds02 pds01 pds00 r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~4 unimplemented, read as 0 bit 3~2 pds03~pds02 : pd1 pin-shared function selection 00/01: pd1/ptp1i 10: ptp1 11: osc2 bit 1~0 pds01~pds00 : pd0 pin-shared function selection 00/01: pd0/ptp2i 10: ptp2 11: osc1 ? name pds0 ? pds0 ? pds03 pds02 pds01 pds00 r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7~6 pds07~pds06 : pd3 pin-shared function selection 00/01/10: pd3 11: an9 bit 5~4 unimplemented, read as 0 bit 3~2 pds03~pds02 : pd1 pin-shared function selection 00/01: pd1/ptp1i 10: ptp1 11: osc2 bit 1~0 pds01~pds00 : pd0 pin-shared function selection 00/01: pd0/ptp2i 10: ptp2 11: osc1 ? name pds1 ? pds1 ? pds15 pds14 pds13 pds12 r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7~6 pds17~pds16 : pd7 pin-shared function selection 00/01/10: pd7/ptp1i 11: ptp1 bit 5~4 pds15~pds14 : pd6 pin-shared function selection 00/01/10: pd6/ptp2i 11: ptp2 bit 3~2 pds13~pds12 : pd5 pin-shared function selection 00/01/10: pd5/ptp0i 11: ptp0 bit 1~0 unimplemented, read as 0
rev. 1.20 122 ?e???a?? 1?? 201? rev. 1.20 123 ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ? name pds1 ? pds1 ? pds15 pds14 pds13 pds12 pds11 pds10 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 pds17~pds16 : pd7 pin-shared function selection 00/01/10: pd7/ptp1i 11: ptp1 bit 5~4 pds15~pds14 : pd6 pin-shared function selection 00/01/10: pd6/ptp2i 11: ptp2 bit 3~2 pds13~pds12 : pd5 pin-shared function selection 00/01/10: pd5/ptp0i 11: ptp0 bit 1~0 pds11~pds10 : pd4 pin-shared function selection 00/01/10: pd4 11: an10 ? name pes0 ? pes0 ? pes05 pes04 pes01 pes00 r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7~6 pes07~pes06 : pe3 pin-shared function selection 00/01/10: pe3 11: vr bit 5~4 pes05~pes04 : pe2 pin-shared function selection 00/01/10: pe2 11: vrefi bit 3~2 unimplemented, read as 0 bit 1~0 pes01~pes00 : pe0 pin-shared function selection 00/01: pe0 10: vddio 11: vref ? name pgs0 ? pgs0 ? pgs05 pgs04 pgs03 pgs02 pgs01 pgs00 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 pgs07~pgs06 : pg3 pin-shared function selection 00/01/10: pg3 11: com3 bit 5~4 pgs05~pgs04 : pg2 pin-shared function selection 00/01/10: pg2 11: com2 bit 3~2 pgs03~pgs02 : pg1 pin-shared function selection 00/01/10: pg1 11: com1
rev. 1.20 124 ? e ??? a ?? 1 ?? 201 ? rev. 1.20 125 ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu bit 1~0 : pg0 pin-shared function selection 00/01: pg0 10 : an7 11: com0 ? pgs0 register C ht66fb574 bit 7 6 5 4 3 2 1 0 name pgs0 ? pgs0 ? pgs05 pgs04 pgs03 pgs02 pgs01 pgs00 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 : pg3 pin-shared function selection 00/01/10: pg3 11: com3 bit 5~4 : pg2 pin-shared function selection 00/01/10: pg2 11: com2 bit 3~2 : pg1 pin-shared function selection 00/01/10: pg1 11: com1 bit 1~0 : pg0 pin-shared function selection 00/01: pg0 10 : an1 1 11: com0 ? pgs0 register CHT66FB576 bit 7 6 5 4 3 2 1 0 name pgs0 ? pgs0 ? pgs05 pgs04 pgs03 pgs02 pgs01 pgs00 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 : pg3 pin-shared function selection 00/01/10: pg3 11: com3 bit 5~4 : pg2 pin-shared function selection 00/01/10: pg2 11: com2 bit 3~2 : pg1 pin-shared function selection 00/01/10: pg1 11: com1 bit 1~0 : pg0 pin-shared function selection 00/01/10: pg0 11: com0 ? pgs1 register bit 7 6 5 4 3 2 1 0 name pgs1 ? pgs1 ? pgs15 pgs14 pgs13 pgs12 pgs11 pgs10 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 : pg7 pin-shared function selection 00/01/10: pg7 11: com7
rev. 1.20 124 ?e???a?? 1?? 201? rev. 1.20 125 ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu bit 5~4 : pg6 pin-shared function selection 00/01/10: pg6 11: com6 bit 3~2 : pg5 pin-shared function selection 00/01/10: pg5 11: com5 bit 1~0 : pg4 pin-shared function selection 00/01/10: pg4 11: com4 ? ifs register bit 7 6 5 4 3 2 1 0 name ptp2ips ptp1ips ptp0ips stpips r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~4 unimplemented, read as 0 bit 3 : ptp2i input source pin selection 0: pd6 1: pd0 bit 2 : ptp1i input source pin selection 0: pd7 1: pd1 bit 1 : ptp0i input source pin selection 0: pa5 1: pd5 bit 0 : stpi input source pin selection 0: pa4 1: pb4
rev. 1.20 12 ? ? e ??? a ?? 1 ?? 201 ? rev. 1.20 12? ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu / ss the acco mpanying diagram illustra tes the internal structure of the i/o logic function. as the exact logical construction of the i/o pin will dif fer from this drawing, it is supplied as a guide only to assist with the functional understanding of the logic function i/o pins. the wide range of pin-shared structures does not permit all types to be shown. m u x vdd cont?ol bit data bit data b?s w?ite cont?ol registe? chip reset read cont?ol registe? read data registe? w?ite data registe? s?stem wake-?p wake-?p select i/o pin weak p?ll-?p p?ll-high registe? select q d ck q d ck q q s s pa onl? logic ??nction inp?t/o?tp?t st??ct??e p?og?amming conside?ations within the user program, one of the frs t things to consider is port initialisation. after a res et, all of the i/o data and port control registers will be set high. this means that all i/o pins will default to an input stat e, the level of whi ch de pends on the ot her connected circuitry and whe ther pull - high selections have been chosen. if the port control registers are then programmed to setup some pins as outputs, these output pins will have an initial high output value unless the associated port data regis ters are frst programmed. selecting which pins are inputs and which are outputs can be achieved byt e-wide by l oading t he c orrect va lues i nto t he a ppropriate port c ontrol re gister or by programming i ndividual bi ts i n t he port c ontrol re gister usi ng t he set [m ].i a nd clr [m ].i instructions. note that when using these bit control instructions, a read-modify-write operation takes place. the microcontroller must frst read in the data on the entire port, modify it to the required new bit values and then rewrite this data back to the output ports. all ports have the additional capabi lity of providing wake-up function . when the devices are in the sleep or idle mode, various methods are available to wake the devices up. one of these is any edge transitions on the p a pins or a high to low transition on the pb~pg pins. single or multiple pins on ports can be setup to have this function.
rev. 1.20 12? ?e???a?? 1?? 201? rev. 1.20 12 ? ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu t mls tm one of the most fundamental functions in any microcontroller devices is the ability to control and measure time. t o implement time related functions the devices include several t imer modules, abbreviated t o t he na me t m. t he t ms a re m ulti-purpose t iming un its a nd se rve t o pr ovide operations such as t imer/counter, input capture, compare match output and single pulse output as we ll a s be ing t he fun ctional uni t for t he ge neration of pw m si gnals. e ach of t he t ms ha s t wo individual interrupts. the addition of input and output pins for each tm ensures that users are provided with timing units with a wide and fexible range of features. the common features of the dif ferent tm types are described here with more detailed information provided in the individual standard and periodic tm sections. the devices conta in four tms and each individual tm can be categorised as a certain type, namely standard t ype tm or periodic t ype tm. although similar in nature, the dif ferent tm types vary in t heir fe ature c omplexity. t he c ommon fe atures t o a ll of t he st andard a nd pe riodic t ms wi ll be described in this section. the detailed operation regarding each of the tm types will be described in separate sections. the main features and dif ferences between the two types of tms are summarised in the accompanying table. time ? /co ? nte ? inp ? t capt ?? e compa ? e match o ? tp ? t pwm channels 1 1 single p ? lse o ? tp ? t 1 1 pwm alignment edge edge pwm adj ? stment pe ? iod & d ? t ? d ? t ? o ? pe ? iod d ? t ? o ? pe ? iod tm ??nction s?mma?? tm ope?ation the d ifferent t ypes o f t m o ffer a d iverse r ange o f f unctions, f rom si mple t iming o perations t o pwm signal generation. the key to understanding how the tm operates is to see it in terms of a fre e runni ng c ounter who se va lue i s t hen c ompared wi th t he va lue of pre -programmed i nternal comparators. when the free running counter has the same value as the pre-programmed comparator , known a s a c ompare m atch si tuation, a t m i nterrupt si gnal wi ll be ge nerated whi ch c an c lear t he counter a nd pe rhaps a lso c hange t he c ondition of t he t m ou tput pi n. t he i nternal t m c ounter i s driven by a user selectable clock source, which can be an internal clock or an external pin. the c lock so urce wh ich d rives t he m ain c ounter i n e ach t m c an o riginate f rom v arious so urces. the selection of the required clock source is implemented using the xtnck2~xtnck0 bits in the xtm control registers, where x stands for s or p type tm and n stands for the specifc tm serial number. for stm there is no serial number n in the relevant pin or control bits since there is only one stm in the devices. the clock source can be a ratio of the system clock f sys or the internal high clock f h , the f sub clock source or the external xtckn pin. the xtckn pin clock source is used to allow an external signal to drive the tm as an external clock source or for event counting.
rev. 1.20 128 ? e ??? a ?? 1 ?? 201 ? rev. 1.20 129 ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu tm s the standard and periodic type tms each have two internal interrupts, one for each of the internal comparator a or comparator p , which generate a tm interrupt when a compare match condition occurs. when a tm interrupt is generated it can be used to clear the counter and also to change the state of the tm output pin. each of the tms, irrespective of what type, has two tm input pins, with the label xtckn and xtpni respectively. the xtmn input pin, xtckn, is essentially a clock source for the xtmn and is selected using the xtnck2~xtnck0 bits in the xtmnc0 register . this external tm input pin allows an external clock source to drive the internal tm. the xtckn input pin can be chosen to have either a rising or falling active edge. the xtckn pin is also used as the extern al trigger input pin in single pulse output mode. the other xtmn input pin, xtpni, is the capture input whos e active edge can be a rising edge, a falling edge or both rising and fallin g edges and the active edge transit ion type is selected using the xtnio1~xtnio0 bits in the xtmnc1 register . there is another capture input, ptckn, for ptmn capture input mode, which can be used as the external trigger input source except the ptpni pin. the tms each have one output pin with the label xtpn. the tm output pins can be selected using the corresponding pin-shared function selection bits described in the pin-shared function section. when the tm is in the compare match output mode, these pins can be controlled by the tm to switch to a high or low level or to toggle when a compare match situation occurs. the external xtpn output p in i s a lso t he p in wh ere t he t m g enerates t he pw m o utput wa veform. as t he t m o utput pins are pin-shared with other functions, the tm output function must frst be setup using relevant pin-shared function selection register. ht ??? b5 ? 2 ht ??? b5 ? 4 ht ??? b5 ?? stck ? stpi stp ptck0 ? ptp0i ptck1 ? ptp1i ptck2 ? ptp2i ptp0 ptp1 ptp2 tm exte?nal pins tm inp?t/o?tp?t pin selection selecting t o ha ve a t m i nput/output or whe ther t o re tain i ts ot her sha red func tion i s i mplemented using t he r elevant p in-shared f unction se lection r egisters, wi th t he c orresponding se lection b its i n each pin-shared function register corresponding to a tm input/output pin. confguring the selection bits correctly will setup the corresponding pin as a tm input/output. the details of the pin-shared function selection are described in the pin-shared function section. stck stp stpi ccr capt??e inp?t ccr o?tp?t stm ??nction pin cont?ol block diag?am
rev. 1.20 128 ?e???a?? 1?? 201? rev. 1.20 129 ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu tm ptckn ptpn ptpni ccr capt??e inp?t ccr o?tp?t ptm ??nction pin cont?ol block diag?am (n=0~2) p?og?amming conside?ations the tm counter registers and the capture/compare ccra and ccrp registers, all have a low and high byte structure. the high bytes can be directly accessed, but as the low bytes can only be accessed via an internal 8-bit buf fer, reading or writing to these registe r pairs must be carried out in a specifc way . the important point to note is that data transfer to and from the 8-bit buf fer and its related l ow b yte o nly t akes p lace wh en a wr ite o r r ead o peration t o i ts c orresponding h igh b yte i s executed. as the ccra and ccrp registers are implemented in the way shown in the following diagram and accessing these register pairs is carried out in a specifc way as described above, it is recommended to us e the " mov" instruction to access the ccra and ccrp low byte registers, named xtmnal and ptmnrpl, using the following access procedures. acces sing the ccra or ccrp low byte registers without following these access procedures will result in unpredictable values. data b?s 8-?it b?ffe? xtmndh xtmndl xtmnah xtmnal xtmn co?nte? registe? (read onl?) xtmn ccra registe? (read/w?ite) ptmnrph ptmnrpl ptmn ccrp registe? (read/w?ite) the following steps show the read and write procedures: ? writing data to ccra ? step 1. w rite data to low byte xtmnal or ptmnrpl C note that here data is only written to the 8-bit buffer. ? step 2. w rite data to high byte xtmnah or ptmnrph C here data is written directly to the high byte registers and simultaneously data is latched from the 8-bit buffer to the low byte registers. ? reading data from the counter registers and or ccra ? step 1. read data from the high byte xtmndh, xtmnah or ptmnrph C here data is read directly from the high byte registers and simultaneously data is latched from the low byte register into the 8-bit buffer. ? step 2. read data from the low byte xtmndl, xtmnal or ptmnrpl C this step reads data from the 8-bit buffer.
rev. 1.20 130 ? e ??? a ?? 1 ?? 201 ? rev. 1.20 131 ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu saa t tm stm the standard t ype tm contains fve operating modes, which are compare match output, t imer/ event counter , capture input, single pulse output and pwm output modes. the standard tm can also be controlled with two external input pins and can drive an external output pin. ht ??? b5 ? 2 ht ??? b5 ? 4 ht ??? b5 ?? 1 ? - ? it ctm stck ? stpi stp f sys f sys /4 f h /?4 f h /1? f sub stck 000 001 010 011 100 101 110 111 stck2~stck0 1?-?it co?nt-?p co?nte? 8-?it compa?ato? p ccrp ?8~?15 ?0~?15 1?-?it compa?ato? a ston stpau compa?ato? a match compa?ato? p match co?nte? clea? 0 1 o?tp?t cont?ol pola?it? cont?ol pin cont?ol stp stoc stm1? stm0 stio1? stio0 stma? inte???pt stmp? inte???pt stpol pxsn ccra stcclr edge detecto? stio1? stio0 f sub pin cont?ol stpi pxsn i?s pin cont?ol pxsn standa?d t?pe tm block diag?am standa?d tm ope?ation the size of standard tm is 16-bit wide and its core is a 16-bit count-up counter which is driven by a user selectable internal or externa l clock source. there are also two internal comparators with the names, comparato r a and comparator p . these comparators will compare the value in the counter with ccrp and ccra registers. the ccrp comparator is 8-bit wide whose value is compared with the highest 8 bits in the counter while the ccra is the sixteen bits and therefore compares all counter bits. the onl y way of changing the value of the 16-bit counte r using the appl ication program , is to clear t he c ounter b y c hanging t he st on b it f rom l ow t o h igh. t he c ounter wi ll a lso b e c leared automatically by a counter overfow or a compare match with one of its associated comparators. when these conditions occur , a stm interrupt signal will also usually be generated. the standard type tm can operate in a number of dif ferent operational modes, can be driven by dif ferent clock sources including an input pin and can also control an output pin. all operating setup conditions are selected using relevant internal registers. overall operation of the standard tm is controlled using a series of registers. a read only register pair e xists t o st ore t he i nternal c ounter 16 -bit va lue, whi le a re ad/write re gister pa ir e xists t o st ore the internal 16-bit ccra value. the stmrp register is used to store the 8-bit ccrp value. the remaining two registers are control registers which setup the different operating and control modes.
rev. 1.20 130 ?e???a?? 1?? 201? rev. 1.20 131 ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu rs a b 7 6 5 4 2 stmc0 stpau stck2 stck1 stck0 ston stmc1 stm1 stm0 stio1 stio0 stoc stpol stdpx stcclr stmdl d ? d ? d5 d4 d3 d2 d1 d0 stmdh d15 d14 d13 d12 d11 d10 d9 d8 stmal d ? d ? d5 d4 d3 d2 d1 d0 stmah d15 d14 d13 d12 d11 d10 d9 d8 stmrp d ? d ? d5 d4 d3 d2 d1 d0 1?-?it standa?d tm registe?s list stmc0 registe? bit ? ? 5 4 3 2 1 0 name stpau stck2 stck1 stck0 ston r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 bit 7 stpau : stm counter pause control 0: run 1: pause the c ounter c an be pa used by se tting t his bi t hi gh. cl earing t he bi t t o z ero re stores normal c ounter ope ration. w hen i n a pa use c ondition t he st m wi ll rem ain powe red up a nd c ontinue t o c onsume po wer. t he c ounter wi ll re tain i ts re sidual va lue whe n this bit changes from low to high and res ume counting from this value w hen the bit changes to a low value again. bit 6~4 stck2~stck0 : select stm counter clock 000: f /4 001: f 010: f 011: f /64 100: f sub 101: f sub 110: stck rising edge clock 111: stck falling edge clock these three bits are used to select the clock source for the stm. the external pin clock source can be chosen to be active on the rising or falling edge. the cloc k source f is the system clock, while f and f sub are other internal clocks, the detai ls of which can be found in the oscillator section. bit 3 ston : stm counter on/off control 0: off 1: on this bit controls the overall on/of f function of the stm. setting the bit high enables the counter to run while clearing the bit disables the stm. clearing this bit to zero will stop the counter from counting and turn of f the stm which will reduce its power consumption. when the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low , the internal counter will retain its residual value until the bit returns high again. if the stm is in the compare match output mode, pwm output mode or single pulse output mode then the stm output pin will be reset to its initial condition, as specifed by the st oc bit, when the ston bit changes from low to high. bit 2~0 unimplemented, read as 0
rev. 1.20 132 ? e ??? a ?? 1 ?? 201 ? rev. 1.20 133 ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu stmc rs b 7 6 5 4 2 name stm1 stm0 stio1 stio0 stoc stpol stdpx stcclr r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 stm1~stm0 : select stm operating mode 00: compare match output mode 01: capture input mode 10: pwm output mode or single pulse output mode 11: t imer/counter mode these bits setup the required operating mode for the stm. t o ensure reliable operation the stm should be switched of f before any changes are made to the stm1 and stm0 bits. in the t imer/counter mode, the stm output pin control will be disabled. bit 5~4 stio1~stio0 : select stm external pin (stp or stpi) function compare match output mode 00: no change 01: output low 10: output high 11: t oggle output pwm output mode/single pulse output mode 00: pwm output inactive state 01: pwm output active state 10: pwm output 11: single pulse output capture input mode 00: input capture at rising edge of stpi 01: input capture at falling edge of stpi 10: input capture at rising/falling edge of stpi 11: input capture disabled timer/counter mode unused these two bits are used to determine how the stm output pin changes state when a certain condition is reached. the function that these bits select depends upon in which mode the stm is running. in t he com pare mat ch out put mode , t he st io1 a nd st io0 bi ts de termine how t he stm output pin changes state when a compare match occurs from the comparator a. the tm output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the comparator a. when the bits are both zero, then no change will take place on the output. the initial value of the stm output pin sh ould b e se tup u sing t he st oc b it i n t he st mc1 r egister. no te t hat t he o utput level requested by the stio1 and stio0 bits must be dif ferent from the initial value setup using the st oc bit otherwise no change will occur on the stm output pin when a compare match occurs. after the stm output pin changes state, it can be reset to its initial level by changing the level of the ston bit from low to high. in t he pw m output mode, t he st io1 and st io0 bit s det ermine how t he st m output pin changes state when a certain compare match condition occurs. the pwm output function is modifed by changing these two bits. it is necessary to only change the va lues of t he st io1 a nd st io0 bi ts on ly a fter t he st m ha s be en swi tched of f. unpredictable pw m out puts wi ll oc cur i f t he st io1 a nd st io0 bi ts a re c hanged when the stm is running. bit 3 stoc : stm stp output control compare match output mode 0: initial low 1: initial high
rev. 1.20 132 ?e???a?? 1?? 201? rev. 1.20 133 ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu pwm output mode/single pulse output mode 0: active low 1: active high this is the output control bit for the stm output pin. its operation depends upon whether st m i s b eing u sed i n t he c ompare ma tch ou tput mo de o r i n t he pw m output mode/single pulse output mode. it has no ef fect if the stm is in the t imer/ counter mod e. in t he c ompare ma tch out put mod e i t de termines t he l ogic l evel of the stm output pin before a compare match occurs. in the pwm output mode it determines if the pwm signal is active high or active low . in the single pulse output mode it determine s the logic level of the stm output pin when the st on bit changes from low to high. bit 2 : stm stp output polarity control 0: non-inverted 1: inverted this bit controls the polarity of the stp output pin. when the bit is set high the stm output pin will be inverted and not inverted when the bit is zero. it has no ef fect if the stm is in the t imer/counter mode. bit 1 : stm pwm duty/period control 0: ccrp C period; ccra C duty 1: ccrp C duty; ccra C period this b it d etermines wh ich o f t he c cra a nd c crp r egisters a re u sed f or p eriod a nd duty control of the pwm waveform. bit 0 : stm counter clear condition selection 0: comparator p match 1: comparator a match this bi t i s use d t o se lect t he m ethod whi ch c lears t he c ounter. re member t hat t he standard tm contains two comparators, comparator a and comparator p , either of which can be selected to clear the internal counter . w ith the stcclr bit set high, the counter will be cleared when a compare match occurs from the comparator a. when the bit is low , the counter will be cleared when a compare match occurs from the comparator p or with a counter overfow . a counter overfow clearing method can only be implemented if the ccrp bits are all cleared to zero. the stcclr bit is not used in the pwm output, single pulse output or capture input mode. stmdl register bit 7 6 5 4 3 2 1 0 name d ? d ? d5 d4 d3 d2 d1 d0 r/w r r r r r r r r por 0 0 0 0 0 0 0 0 bit 7~0 : stm counter low byte register bit 7 ~ bit 0 stm 16-bit counter bit 7 ~ bit 0 stmdh register bit 7 6 5 4 3 2 1 0 name d15 d14 d13 d12 d11 d10 d9 d8 r/w r r r r r r r r por 0 0 0 0 0 0 0 0 bit 7~0 : stm counter high byte register bit 7 ~ bit 0 stm 16-bit counter bit 15 ~ bit 8
rev. 1.20 134 ? e ??? a ?? 1 ?? 201 ? rev. 1.20 135 ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu stml rs b 7 6 5 4 2 name d ? d ? d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 d7~d0 : stm ccra low byte register bit 7 ~ bit 0 stm 16-bit ccra bit 7 ~ bit 0 name d15 d14 d13 d12 d11 d10 d9 d8 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 d15~d8 : stm ccra high byte register bit 7 ~ bit 0 stm 16-bit ccra bit 15 ~ bit 8 name d ? d ? d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 d7~d0 : stm ccrp 8-bit register, compared with the stm counter bit 15~bit 8 comparator p match period = 0: 65536 stm clocks 1~255: (1~255) 256 stm clocks these eight bits are used to setup the value on the internal ccrp 8-bit register , which are t hen c ompared wi th t he i nternal c ounter's h ighest e ight b its. t he r esult o f t his comparison ca n be se lected to cl ear the int ernal counte r if t he st cclr bit is se t t o zero. se tting the st cclr bit to ze ro ensures tha t a compa re ma tch wi th the ccrp values will reset the internal counter . as the ccrp bits are only compared with the highest eight counter bits, the compare values exist in 256 clock cycle multiples. clearing a ll e ight bi ts t o z ero i s i n e ffect a llowing t he c ounter t o ove rflow a t i ts maximum value.
rev. 1.20 134 ?e???a?? 1?? 201? rev. 1.20 135 ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu saa t tm a ms the standard t ype tm can operate in one of fve operating modes, compare match output mode, pwm output mode, single pulse output mode, capture input mode or t imer/counter mode. the operating mode is selected using the stm1 and stm0 bits in the stmc1 register. to select this mode, bits stm1 and stm0 in the stmc1 register , should be set to 00 respectively . in this mode once the counter is enabled and running it can be cleared by three methods. these are a counter overfow , a compare matc h from comparator a and a compare match from comparator p . when the stcclr bit is low , there are two ways in which the counter can be cleared. one is when a compare match from comparator p , the other is when the ccrp bits are all zero which allows the counter t o ov erfow. he re bo th st maf a nd st mpf i nterrupt re quest fa gs fo r co mparator a a nd comparator p respectively, will both be generated. if the stcclr bit in the stmc1 register is high then the counter will be cleared when a compare match oc curs from com parator a. howe ver, he re onl y t he st maf i nterrupt re quest fa g wi ll be generated even if the value of the ccrp bits is less than that of the ccra registers. therefore when stcclr is high no stmpf interru pt request fag will be generated. in the compare match output mode, the ccra cannot be set to "0". if the ccra bits are all zero, the counter will overfow when it reache s its maximum 16-bit, ffff hex, value, however here the stmaf interrupt request fag will not be generated. as the name of the mode suggests, after a comparison is made, the stm output pin, will change state. the stm output pin condition however only changes state when a stmaf interrupt request fag is generated after a compare match occurs from comparator a . the s tmpf interrupt reques t fag, g enerated fr om a c ompare m atch o ccurs fr om c omparator p , wi ll h ave n o e ffect o n t he st m output pin. the way in which the stm output pin changes state are determined by the condition of the stio1 and stio0 bits in the stmc1 register . the stm output pin can be selected using the stio1 and stio0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from comparator a. the initial condition of the stm output pin, which is setup after the st on bit changes from low to high, is setup using the st oc bit. note that if the stio1 and stio0 bits are zero then no pin change will take place.
rev. 1.20 13 ? ? e ??? a ?? 1 ?? 201 ? rev. 1.20 13? ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu co?nte? val?e 0x???? ccrp ccra ston stpau stpol ccrp int. flag stmp? ccra int. flag stma? stm o/p pin time ccrp=0 ccrp > 0 co?nte? ove?flow ccrp > 0 co?nte? clea?ed ?? ccrp val?e pa?se res?me stop co?nte? resta?t stcclr = 0; stm [1:0] = 00 o?tp?t pin set to initial level low if stoc=0 o?tp?t toggle with stma? flag note stio [1:0] = 10 active high o?tp?t select he?e stio [1:0] = 11 toggle o?tp?t select o?tp?t not affected ?? stma? flag. remains high ?ntil ?eset ?? ston ?it o?tp?t pin reset to initial val?e o?tp?t cont?olled ?? othe? pin-sha?ed f?nction o?tp?t inve?ts when stpol is high compa?e match o?tp?t mode C stcclr=0 note: 1. w ith stcclr=0 a comparator p match will clear the counter 2. the stm output pin is controlled only by the stmaf fag 3. the output pin is reset to its initial state by a ston bit rising edge
rev. 1.20 13? ?e???a?? 1?? 201? rev. 1.20 13 ? ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu co?nte? val?e 0x???? ccrp ccra ston stpau stpol ccrp int. flag stmp? ccra int. flag stma? stm o/p pin time ccra=0 ccra = 0 co?nte? ove?flow ccra > 0 co?nte? clea?ed ?? ccra val?e pa?se res?me stop co?nte? resta?t stcclr = 1; stm [1:0] = 00 o?tp?t pin set to initial level low if stoc=0 o?tp?t toggle with stma? flag note stio [1:0] = 10 active high o?tp?t select he?e stio [1:0] = 11 toggle o?tp?t select o?tp?t not affected ?? stma? flag. remains high ?ntil ?eset ?? ston ?it o?tp?t pin reset to initial val?e o?tp?t cont?olled ?? othe? pin-sha?ed f?nction o?tp?t inve?ts when stpol is high stmp? not gene?ated no stma? flag gene?ated on ccra ove?flow o?tp?t does not change compa?e match o?tp?t mode C stcclr=1 note: 1. w ith stcclr=1 a comparator a match will clear the counter 2. the stm output pin is controlled only by the stmaf fag 3. the output pin is reset to its initial state by a ston bit rising edge 4. a stmpf fag is not generated when stcclr=1
rev. 1.20 138 ? e ??? a ?? 1 ?? 201 ? rev. 1.20 139 ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu t/c m to select this mode, bits stm1 and stm0 in the stmc1 register should be set to 1 1 respectively . the t imer/counter m ode operates in an identical w ay to the compare m atch o utput m ode generating the s ame interrupt flags . the exception is that in the t imer/counter m ode the s tm output pin is not used. therefore the above description and t iming diagrams for the compare match out put mod e c an be use d t o un derstand i ts fu nction. as t he st m ou tput pi n i s no t use d i n this mode, the pin can be used as a normal i/o pin or other pin-shared function. to select this mode, bits stm1 and stm0 in the stmc1 register should be set to 10 respectively and als o the stio 1 and stio 0 bits should be set to 10 res pectively. the pwm function w ithin the stm is useful for applications which require functions such as motor control, heating control, illumination control etc. by providing a signal of fxed frequency but of varying duty cycle on the stm output pin, a square wave ac waveform can be generated with varying equivalent dc rms values. as both the period and duty cycle of the pwm waveform can be controlled, the choice of generated waveform i s e xtremely fe xible. i n t he pw m ou tput mo de, t he st cclr b it h as n o e ffect a s t he pwm period. both of the ccra and ccrp registers are used to generate the pwm waveform, one register is used to clear the internal counter and thus control the pwm waveform frequency , while the other one is used to control the duty cycle. which register is used to control either frequency or duty cycle is determined using the stdpx bit in the stmc1 register . the pwm waveform frequency and duty cycle can therefore be controlled by the values in the ccra and ccrp registers. an interrupt fag, one for each of the ccra and ccrp , will be generated when a compare match occurs from either comparator a or comparator p . the st oc bit in the stmc1 register is used to select the required polarity of the pwm waveform while the two stio1 and stio0 bits are used to enable the pwm output or to force the stm output pin to a fxed high or low level. the stpol bit is used to reverse the polarity of the pwm output waveform. ? pe ? iod ccrp25 ? ? 553 ? d ? t ? ccra if f sys = 12mhz, stm clock source is f sys /4, ccrp=2 and ccra=128, the stm pwm output frequency=(f sys /4)/(2256)=f sys /2048=5.859khz, duty=128/(2256)=25%. if the duty value defned by the ccra register is equal to or greater than the period value, then the pwm output duty is 100%. ? pe ? iod ccra d ? t ? ccrp25 ? ? 553 ? the pw m o utput p eriod i s d etermined b y t he c cra r egister v alue t ogether wi th t he t m c lock while t he pw m d uty c ycle i s d efned b y t he c crp r egister v alue e xcept wh en t he c crp v alue i s equal to 0.
rev. 1.20 138 ?e???a?? 1?? 201? rev. 1.20 139 ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu co?nte? val?e ccrp ccra ston stpau stpol ccrp int. flag stmp? ccra int. flag stma? stm o/p pin (stoc=1) time co?nte? clea?ed ?? ccrp pa?se res?me co?nte? stop if ston ?it low co?nte? reset when ston ?et??ns high stdpx = 0; stm [1:0] = 10 pwm d?t? c?cle set ?? ccra pwm ?es?mes ope?ation o?tp?t cont?olled ?? othe? pin-sha?ed f?nction o?tp?t inve?ts when stpol = 1 pwm pe?iod set ?? ccrp stm o/p pin (stoc=0) pwm o?tp?t mode C stdpx=0 note: 1. here stdpx=0 C counter cleared by ccrp 2. a counter clear sets the pwm period 3. the internal pwm function continues running even when stio [1:0] = 00 or 01 4. the stcclr bit has no infuence on pwm operation
rev. 1.20 140 ? e ??? a ?? 1 ?? 201 ? rev. 1.20 141 ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu co?nte? val?e ccrp ccra ston stpau stpol ccrp int. flag stmp? ccra int. flag stma? stm o/p pin (stoc=1) time co?nte? clea?ed ?? ccra pa?se res?me co?nte? stop if ston ?it low co?nte? reset when ston ?et??ns high stdpx = 1; stm [1:0] = 10 pwm d?t? c?cle set ?? ccrp pwm ?es?mes ope?ation o?tp?t cont?olled ?? othe? pin-sha?ed f?nction o?tp?t inve?ts when stpol = 1 pwm pe?iod set ?? ccra stm o/p pin (stoc=0) pwm o?tp?t mode C stdpx=1 note: 1. here stdpx=1 C counter cleared by ccra 2. a counter clear sets the pwm period 3. the internal pwm function continues even when stio [1:0] = 00 or 01 4. the stcclr bit has no infuence on pwm operation
rev. 1.20 140 ?e???a?? 1?? 201? rev. 1.20 141 ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu sl ls m to select this mode, bits stm1 and stm0 in the stmc1 register should be set to 10 respectively and also the stio1 and stio0 bits should be set to 1 1 respectively . the single pulse output mode, as the name suggests, will generate a single shot pulse on the stm output pin. the trigger for the pulse output leading edge is a low to high transition of the st on bit, which can be implement ed using the appli cation program. however in the single pulse output mode, the ston bit can also be made to automatically change from low to high using the external stck pin, which will in turn initiate the single pulse output. when the st on bit transitions to a high level, the counter will start running and the pulse leading edge will be generated. the st on bit should remain high when the pulse is in its active state. the generated pulse trailing edge will be generated when the st on bit is cleared to zero, which can be implemented using the application program or when a compare match occurs from comparator a. however a c ompare m atch f rom c omparator a wi ll a lso a utomatically c lear t he st on b it a nd thus generate the single pulse output trailing edge. in this way the ccra value can be used to control the pulse width. a compare match from comparator a will also generate a stm interrupt. the counter can only be reset back to zero when the st on bit changes from low to high when the counter restarts. in the single pulse output mode ccrp is not used. the stcclr and stdpx bits are not used in this mode. ston ?it 0 1 s/w command set ston o? stck pin t?ansition ston ?it 1 0 ccra t?ailing edge s/w command clr ston o? ccra compa?e match stp o?tp?t pin p?lse width = ccra val?e ccra leading edge single p?lse gene?ation
rev. 1.20 142 ? e ??? a ?? 1 ?? 201 ? rev. 1.20 143 ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu co?nte? val?e ccrp ccra ston stpau stpol ccrp int. ?lag stmp? ccra int. ?lag stma? stm o/p pin (stoc=1) time co?nte? stopped ?? ccra pa?se res?me co?nte? stops ?? softwa?e co?nte? reset when ston ?et??ns high stm [1:0] = 10 ; stio [1:0] = 11 p?lse width set ?? ccra o?tp?t inve?ts when stpol = 1 no ccrp inte???pts gene?ated stm o/p pin (stoc=0) stck pin softwa?e t?igge? clea?ed ?? ccra match stck pin t?igge? a?to. set ?? stck pin softwa?e t?igge? softwa?e clea? softwa?e t?igge? softwa?e t?igge? single p?lse o?tp?t mode note: 1. counter stopped by ccra 2. ccrp is not used 3. the pulse triggered by the stck pin or by setting the ston bit high 4. a stck pin active edge will automatically set the ston bit high. 5. in the single pulse output mode, stio [1:0] must be set to 11 and cannot be changed.
rev. 1.20 142 ?e???a?? 1?? 201? rev. 1.20 143 ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ca m to select this mode bits stm1 and stm0 in the stmc1 register should be set to 01 respectively . this mode enables external s ignals to capture and s tore the pres ent value of the internal counter and c an t herefore be use d fo r a pplications suc h a s pu lse wi dth m easurements. t he e xternal si gnal is suppl ied on t he st pi pi n, whose a ctive e dge c an be a ri sing e dge, a fa lling e dge or bot h ri sing and falling edges; the active edge transition type is selected using the stio1 and stio0 bits in the stmc1 register . the counter is started when the st on bit changes from low to high which is initiated using the application program. when the required edge transition appears on the stpi pin the present value in the counter will be latched into the ccra registers and a stm interrupt generated. irrespective of what events occur on the stpi pin the counter will continue to free run until the st on bit changes from high to low . when a ccrp compare match occurs the counter will reset back to zero; in this way the ccrp value c an be use d t o c ontrol t he m aximum c ounter va lue. w hen a ccrp c ompare m atch oc curs from comparat or p , a stm interrupt will also be generated. counting the number of overfl ow interrupt signals from the ccrp can be a useful method in measuring long pulse widths. the stio1 and stio0 bits can select the active trigger edge on the stpi pin to be a rising edge, falling edge or both edge types. if the stio1 and stio0 bits are both set high, then no capture operation will take place irrespective of what happens on the stpi pin, however it must be noted that the counter will continue to run. the stcclr and stdpx bits are not used in this mode.
rev. 1.20 144 ? e ??? a ?? 1 ?? 201 ? rev. 1.20 145 ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu co?nte? val?e yy ccrp ston stpau ccrp int. ?lag stmp? ccra int. ?lag stma? ccra val?e time co?nte? clea?ed ?? ccrp pa?se res?me co?nte? reset stm [1:0] = 01 stm capt??e pin stpi xx co?nte? stop stio [1:0] val?e xx yy xx yy active edge active edge active edge 00 C rising edge 01 C ?alling edge 10 C both edges 11 C disa?le capt??e capt??e inp?t mode note: 1. stm [1:0] = 01 and active edge set by the stio [1:0] bits 2. a stm capture input pin active edge transfers the counter value to ccra 3. stcclr bit not used 4. no output function C stoc and stpol bits are not used 5. ccrp determin es the counter value and the counter has a maximum count value when ccrp is equal to zero.
rev. 1.20 144 ?e???a?? 1?? 201? rev. 1.20 145 ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu t tm tm the pe riodic t ype t m c ontains fv e o perating m odes, wh ich a re c ompare ma tch ou tput, t imer/ event counter , capture input, single pulse output and pwm output modes. the periodic tm can be controlled with two external input pins and can drive an external output pins. ht ??? b5 ? 2 ht ??? b5 ? 4 ht ??? b5 ?? 10- ? it ptm0 10- ? it ptm1 10- ? it ptm2 ptck0 ? ptp0i ptck1 ? ptp1i ptck2 ? ptp2i ptp0 ptp1 ptp2 n=0~2 10-?it co?nt-?p co?nte? 10-?it compa?ato? p ccrp 10-?it compa?ato? a o?tp?t cont?ol pola?it? cont?ol pin cont?ol ptpn ccra edge detecto? ptpni pin cont?ol ptncclr f sys f sys /4 f h /?4 f h /1? f sub ptnck2~ptnck0 ptnon ptnpau compa?ato? a match compa?ato? p match co?nte? clea? ptnoc ptnm1? ptnm0 ptnio1? ptnio0 ptmna? inte???pt ptmnp? inte???pt ptnpol pxsn ptnio1? ptnio0 f sub ptncapts 000 001 010 011 100 101 110 111 ?0~?9 ?0~?9 0 1 1 0 i?s pxsn ptckn pe?iodic t?pe tm block diag?am (n=0~2) pe?iodic tm ope?ation the periodic t ype tm core is a 10-bit count-up counter which is driven by a user selectable internal or e xternal c lock sourc e. t here a re a lso t wo i nternal c omparators wi th t he na mes, com parator a and comparator p . these comparators will compare the value in the counter with ccrp and ccra registers. the ccrp comparator is 10-bit wide. the onl y way of changing the value of the 10-bit counte r using the appl ication program , is to clear the counter by changing the ptnon bit from low to high. the counter will also be cleared automatically by a counter overfow or a compare match with one of its associated comparators. when these conditions occur , a ptmn interrupt signal will also usually be generated. the periodic type tm can operate in a number of dif ferent operational modes, can be driven by dif ferent clock sources including an input pin and can also control more than one output pin. all operating setup conditions are selected using relevant internal registers. overall operation of the periodic t ype tm is controlled using a series of registers. a read only register pair exists to store the internal counter 10-bit value, while two read/write register pairs exist to store the int ernal 10-bit ccra val ue and ccrp val ue. the rem aining two registers are control registers which setup the different operating and control modes.
rev. 1.20 14 ? ? e ??? a ?? 1 ?? 201 ? rev. 1.20 14? ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu rs a b 7 6 5 4 2 ptmnc0 ptnpau ptnck2 ptnck1 ptnck0 ptnon ptmnc1 ptnm1 ptnm0 ptnio1 ptnio0 ptnoc ptnpol ptncapts ptncclr ptmndl d ? d ? d5 d4 d3 d2 d1 d0 ptmndh d9 d8 ptmnal d ? d ? d5 d4 d3 d2 d1 d0 ptmnah d9 d8 ptmnrpl d ? d ? d5 d4 d3 d2 d1 d0 ptmnrph d9 d8 10-?it pe?iodic tm registe?s list (n=0~2) ptmnc0 registe? bit ? ? 5 4 3 2 1 0 name ptnpau ptnck2 ptnck1 ptnck0 ptnon r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 bit 7 ptnpau : ptmn counter pause control 0: run 1: pause the c ounter c an be pa used by se tting t his bi t hi gh. cl earing t he bi t t o z ero re stores normal counter operation. when in a pause condition the ptmn will remain powered up a nd c ontinue t o c onsume po wer. t he c ounter wi ll re tain i ts re sidual va lue whe n this bit changes from low to high and res ume counting from this value w hen the bit changes to a low value again. bit 6~4 ptnck2~ptnck0 : select ptmn counter clock 000: f /4 001: f 010: f 011: f /64 100: f sub 101: f sub 110: ptckn rising edge clock 111: ptckn falling edge clock these three bits are used to select the clock source for the ptmn. the external pin clock source can be chosen to be active on the rising or falling edge. the clock source is the system clock, while f and f sub are other internal clocks, the details of which can be found in the oscillator section. bit 3 ptnon : ptmn counter on/off control 0: off 1: on this bit controls the overall on/of f function of the ptmn. setting the bit high enables the counter to run, clearing the bit disables the ptmn. clearing this bit to zero will stop the counter from counting and turn of f the ptmn which will reduce its power consumption. when the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low , the internal counter will retain its residual value until the bit returns high again. if the ptmn is in the compare match output mode, pwm output mode or single pulse output mode then the ptmn output pin will be reset to its initial condition, as specifed by the ptnoc bit, when the ptnon bit changes from low to high. bit 2~0 unimplemented, read as 0
rev. 1.20 14? ?e???a?? 1?? 201? rev. 1.20 14 ? ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu tmc rs b 7 6 5 4 2 name ptnm1 ptnm0 ptnio1 ptnio0 ptnoc ptnpol ptncapts ptncclr r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 ptnm1~ptnm0 : select ptmn operating mode 00: compare match output mode 01: capture input mode 10: pwm output mode or single pulse output mode 11: t imer/counter mode these bits setup the required operating mode for the ptmn. t o ensure reliable operation the ptmn should be switched of f before any changes are made to the ptnm1 and ptnm0 bits. in the t imer/counter mode, the ptmn output pin control must be disabled. bit 5~4 ptnio1~ptnio0 : select ptmn external pin (ptpn, ptpni or ptckn) function compare match output mode 00: no change 01: output low 10: output high 11: t oggle output pwm output mode/single pulse output mode 00: pwm output inactive state 01: pwm output active state 10: pwm output 11: single pulse output capture input mode 00: input capture at rising edge of ptpni or ptckn 01: input capture at falling edge of ptpni or ptckn 10: input capture at falling/rising edge of ptpni or ptckn 11: input capture disabled timer/counter mode unused these two bits are used to determine how the ptmn output pin changes state when a certain condition is reached. the function that these bits select depends upon in which mode the ptmn is running. in the compare match output mode, the ptnio1 and ptnio0 bits determine how the ptmn output pin changes state when a compare match occurs from the comparator a. the ptmn output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the comparator a. when the bits are both zero, then no change will take place on the output. the initial value of the ptmn output pin should be setup us ing the ptnoc bit in the ptmnc1 regis ter. note that the output level requested by the ptnio1 and ptnio0 bits must be dif ferent from the initial value setup using the ptnoc bit otherwise no change will occur on the ptmn output pin when a compare match occurs. after the ptmn output pin changes state, it can be reset to its initial level by changing the level of the ptnon bit from low to high. in t he pw m out put mode , t he pt nio1 a nd pt nio0 bi ts de termine how t he pt mn output pin changes state when a certain compare match condition occurs. the pwm output function is modifed by changing these two bits. it is necessary to only change the values of the ptnio1 and ptnio0 bits only after the tm has been switched of f. unpredictable pwm outputs will occur if the ptnio1 and ptnio0 bits are changed when the ptmn is running.
rev. 1.20 148 ? e ??? a ?? 1 ?? 201 ? rev. 1.20 149 ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu bit 3 : ptmn ptpn output control bit compare match output mode 0: initial low 1: initial high pwm output mode/single pulse output mode 0: active low 1: active high this is the output control bit for the ptmn output pin. its operation depends upon whether ptmn is being used in the compare match output mode or in the pwm output mode/single pulse output mode. it has no ef fect if the ptmn is in the t imer/ counter mod e. in t he c ompare ma tch out put mod e i t de termines t he l ogic l evel of the ptmn output pin before a compare match occurs. in the pwm output mode it determines if the pwm signal is active high or active low . in the single pulse output mode it determines the logic level of the ptmn output pin when the ptnon bit changes from low to high. bit 2 : ptmn ptpn output polarity control 0: non-invert 1: invert this bit controls the polarity of the ptpn output pin. when the bit is set high the ptmn output pin will be inverted and not inverted when the bit is zero. it has no ef fect if the ptmn is in the t imer/counter mode. bit 1 : ptmn capture t rigger source selection 0: from ptpni pin 1: from ptckn pin bit 0 : select ptmn counter clear condition 0: ptmn comparator p match 1: ptmn comparator a match this bi t i s use d t o se lect t he m ethod whi ch c lears t he c ounter. re member t hat t he periodic t m c ontains t wo c omparators, com parator a a nd com parator p , e ither of which can be selected to clear the internal counter . w ith the ptncclr bit set high, the counter will be cleared when a compare match occurs from the comparator a. when the bit is low , the counter will be cleared when a compare match occurs from the comparator p or with a counter overfow . a counter overfow clearing method can only be implemented if the ccrp bits are all cleared to zero. the ptncclr bit is not used in the pwm output mode, single pulse or capture input mode. ptmndl register bit 7 6 5 4 3 2 1 0 name d ? d ? d5 d4 d3 d2 d1 d0 r/w r r r r r r r r por 0 0 0 0 0 0 0 0 bit 7~0 : ptmn counter low byte register bit 7 ~ bit 0 ptmn 10-bit counter bit 7 ~ bit 0 ptmndh register bit 7 6 5 4 3 2 1 0 name d9 d8 r/w r r por 0 0 bit 7~2 unimplemented, read as 0 bit 1~0 : ptmn counter high byte register bit 1 ~ bit 0 ptmn 10-bit counter bit 9 ~ bit 8
rev. 1.20 148 ?e???a?? 1?? 201? rev. 1.20 149 ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu tml rs b 7 6 5 4 2 name d ? d ? d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 d7~d0 : ptmn ccra low byte register bit 7 ~ bit 0 ptmn 10-bit ccra bit 7 ~ bit 0 name d9 d8 r/w r/w r/w por 0 0 bit 7~2 unimplemented, read as 0 bit 1~0 d9~d8 : ptmn ccra high byte register bit 1 ~ bit 0 ptmn 10-bit ccra bit 9 ~ bit 8 name d ? d ? d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 d7~d0 : ptmn ccrp low byte register bit 7 ~ bit 0 ptmn 10-bit ccrp bit 7 ~ bit 0 name d9 d8 r/w r/w r/w por 0 0 bit 7~2 unimplemented, read as 0 bit 1~0 d9~d8 : ptmn ccrp high byte register bit 1 ~ bit 0 ptmn 10-bit ccrp bit 9 ~ bit 8
rev. 1.20 150 ? e ??? a ?? 1 ?? 201 ? rev. 1.20 151 ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu t tm a ms the standard t ype tm can operate in one of fve operating modes, compare match output mode, pwm output mode, single pulse output mode, capture input mode or t imer/counter mode. the operating mode is selected using the ptnm1 and ptnm0 bits in the ptmnc1 register. to select this mode, bits ptnm1 and ptnm0 in the ptmnc1 register , should be set to 00 respectively. in this mode once the counter is enabled and running it can be cleared by three methods. these are a counter overfow , a compare match from comparator a and a compare match from comparator p . when the ptncclr bit is low , there are two ways in which the counter can be cleared. one is when a compare match from comparator p , the other is when the ccrp bits are all zero which allows the counter to overfow . here both ptmnaf and ptmnpf interrupt request fags for comparator a and comparator p respectively, will both be generated. if the ptncclr bit in the ptmnc1 register is high then the counter will be cleared when a compare match occurs from comparator a. however , here only the ptmnaf interrupt request flag will be generated even if the value of the ccrp bits is less than that of the ccra registers. therefore when ptncclr is high no ptmnpf interrupt request fag will be generated. in the compare match output mode, the ccra cannot be cleared to zero. if t he c cra b its a re a ll z ero, t he c ounter wi ll o verfow wh en i t r eaches i ts m aximum 1 0-bit, 3 ff hex, value, however here the ptmnaf interrupt request fag will not be generated. as the name of the mode suggests, after a comparison is made, the ptmn output pin, will change state. the ptmn output pin condition however only changes state when a ptmnaf interrupt request fag is generated after a compare match occurs from comparator a. the ptmnpf interrupt request fag, generated from a compare match occurs from comparator p , will have no ef fect on the ptmn output pin. the way in which the ptmn output pin changes state are determined by the condition of the ptnio1 and ptnio0 bits in the ptmnc1 register . the ptmn output pin can be selected using the pt nio1 a nd pt nio0 bi ts t o go hi gh, t o go l ow or t o t oggle fr om i ts pre sent c ondition whe n a compare match occurs from comparator a. the initial condition of the ptmn output pin, which is setup afte r the ptnon bit changes from low to high, is setup using the ptnoc bit. note that if the ptnio1 and ptnio0 bits are zero then no pin change will take place.
rev. 1.20 150 ?e???a?? 1?? 201? rev. 1.20 151 ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu co?nte? val?e 0x3?? ccrp ccra ptnon ptnpau ptnpol ccrp int. ?lag ptmnp? ccra int. ?lag ptmna? ptmn o/p pin time ccrp=0 ccrp > 0 co?nte? ove?flow ccrp > 0 co?nte? clea?ed ?? ccrp val?e pa?se res?me stop co?nte? resta?t o?tp?t pin set to initial level low if ptnoc=0 o?tp?t toggle with ptmna? flag note ptnio [1:0] = 10 active high o?tp?t select he?e ptnio [1:0] = 11 toggle o?tp?t select o?tp?t not affected ?? ptmna? flag. remains high ?ntil ?eset ?? ptnon ?it o?tp?t pin reset to initial val?e o?tp?t cont?olled ?? othe? pin-sha?ed f?nction o?tp?t inve?ts when ptnpol is high ptncclr = 0; ptnm [1:0] = 00 compa?e match o?tp?t mode C ptncclr=0 (n=0~2) note: 1. w ith ptncclr=0 a comparator p match will clear the counter 2. the ptmn output pin is controlled only by the ptmnaf fag 3. the output pin is reset to its initial state by a ptnon bit rising edge
rev. 1.20 152 ? e ??? a ?? 1 ?? 201 ? rev. 1.20 153 ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu co?nte? val?e 0x3?? ccrp ccra ptnon ptnpau ptnpol ccrp int. ?lag ptmnp? ccra int. ?lag ptmna? ptmn o/p pin time ccra=0 ccra = 0 co?nte? ove?flow ccra > 0 co?nte? clea?ed ?? ccra val?e pa?se res?me stop co?nte? resta?t o?tp?t pin set to initial level low if ptnoc=0 o?tp?t toggle with ptmna? flag note ptnio [1:0] = 10 active high o?tp?t select he?e ptnio [1:0] = 11 toggle o?tp?t select o?tp?t not affected ?? ptmna? flag. remains high ?ntil ?eset ?? ptnon ?it o?tp?t pin reset to initial val?e o?tp?t cont?olled ?? othe? pin-sha?ed f?nction o?tp?t inve?ts when ptnpol is high ptmnp? not gene?ated no ptmna? flag gene?ated on ccra ove?flow o?tp?t does not change ptncclr = 1; ptnm [1:0] = 00 compa?e match o?tp?t mode C ptncclr=1 (n=0~2) note: 1. w ith ptncclr=1 a comparator a match will clear the counter 2. the ptmn output pin is controlled only by the ptmnaf fag 3. the output pin is reset to its initial state by a ptnon bit rising edge 4. a ptmnpf fag is not generated when ptncclr=1
rev. 1.20 152 ?e???a?? 1?? 201? rev. 1.20 153 ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu t/c m to se lect t his mode , bi ts pt nm1 and pt nm0 i n t he pt mnc1 regi ster should be se t t o 1 1 respectively. the t imer/counter mode operates in an identical way to the compare match output mode generating the same interrupt flags. the exception is that in the t imer/counter mode the tm output pin is not used. therefore the above description and t iming diagrams for the compare match output mode can be used to understand its function. as the tm output pin is not used in this mode, the pin can be used as a normal i/o pin or other pin-shared function. to select this mode, bits ptnm1 and ptnm0 in the ptmnc1 register should be set to 10 respectively. the pwm function within the ptmn is useful for applica tions which require functions such as motor control, heating control, illumination control etc. by providing a signal of fixed frequency but of varying duty cycle on the ptmn output pin, a square wave ac waveform can be generated with varying equivalent dc rms values. as both the period and duty cycle of the pwm waveform can be controlled, the choice of generated waveform is extre mely fexible. in the pwm output mode, the ptncclr bit has no ef fect on the pwm operation. both of the ccra and ccrp registers are used to generate the pwm waveform, one register is used to clear the internal counter and thus control the pwm waveform frequency , while the other one is used to control the duty cycle. the pwm waveform frequency and duty cycle can therefore be controlled by the values in the ccra and ccrp registers. an interrupt fag, one for each of the ccra and ccrp , will be generated when a compare match occurs from either comparator a or comparator p . the ptnoc bit in the ptmnc1 register is used to select the required polari ty of the pwm waveform whi le the two ptnio1 and ptnio0 bi ts are used to enable the pwm output or to force the ptmn output pin to a fxed high or low level. the ptnpol bit is used to reverse the polarity of the pwm output waveform. ? pe ? iod 1~1023 1024 d ? t ? ccra if f sys = 12mhz, ptmn clock source select f sys /4, ccrp=512 and ccra=128, the ptmn pwm output frequency=(f sys /4)/512=f sys /2048=5.8594khz, duty=128/(2256)=25%. if the duty value defned by the ccra register is equal to or greater than the period value, then the pwm output duty is 100%.
rev. 1.20 154 ? e ??? a ?? 1 ?? 201 ? rev. 1.20 155 ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu co?nte? val?e ccrp ccra ptnon ptnpau ptnpol ccrp int. ?lag ptmnp? ccra int. ?lag ptmna? ptmn o/p pin (ptnoc=1) time co?nte? clea?ed ?? ccrp pa?se res?me co?nte? stop if ptnon ?it low co?nte? reset when ptnon ?et??ns high pwm d?t? c?cle set ?? ccra pwm ?es?mes ope?ation o?tp?t cont?olled ?? othe? pin-sha?ed f?nction o?tp?t inve?ts when ptnpol = 1 pwm pe?iod set ?? ccrp ptmn o/p pin (ptnoc=0) ptnm [1:0] = 10 pwm o?tp?t mode (n=0~2) note: 1. counter cleared by ccrp 2. a counter clear sets the pwm period 3. the internal pwm function continues running even when ptnio[1:0] = 00 or 01 4. the ptncclr bit has no infuence on pwm operation
rev. 1.20 154 ?e???a?? 1?? 201? rev. 1.20 155 ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu sl ls m to select this mode, bits ptnm1 and ptnm0 in the ptmnc1 register should be set to 10 respectively and also the ptnio1 and ptnio0 bits should be set to 1 1 respectively . the single pulse output mode, as the name suggests, will generate a single shot pulse on the ptmn output pin. the t rigger f or t he p ulse o utput l eading e dge i s a l ow t o h igh t ransition o f t he pt non b it, wh ich can be implement ed using the appli cation program. however in the single pulse output mode, the ptnon bit can also be made to automatically change from low to high using the external ptckn pin, whi ch wi ll i n t urn i nitiate t he si ngle pul se output . w hen t he pt non bit t ransitions t o a high level, the counter will start running and the pulse leading edge will be generated. the ptnon bit should r emain h igh wh en t he p ulse i s i n i ts a ctive st ate. t he g enerated p ulse t railing e dge wi ll b e generated when the ptnon bit is cleared to zero, which can be implemented using the application program or when a compare match occurs from comparator a. however a compa re match from comparator a will also automatically clear the ptnon bit and thus generate the single pulse output trailing edge. in this way the ccra value can be used to control the pulse width. a compare match from comparator a will also generate a ptmn interrupt. the counter can only be res et back to zero w hen the ptno n bit changes from low to high w hen the counter restarts. in the single pulse output mode ccrp is not used. the ptncclr bit is not used in this mode. ptnon ?it 0 1 s/w command set ptnon o? ptckn pin t?ansition ptnon ?it 1 0 ccra t?ailing edge s/w command clr ptnon o? ccra compa?e match ptpn o?tp?t pin p?lse width = ccra val?e ccra leading edge single p?lse gene?ation (n=0~2)
rev. 1.20 15 ? ? e ??? a ?? 1 ?? 201 ? rev. 1.20 15? ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu co?nte? val?e ccrp ccra ptnon ptnpau ptnpol ccrp int. ?lag ptmnp? ccra int. ?lag ptmna? ptmn o/p pin (ptnoc=1) time co?nte? stopped ?? ccra pa?se res?me co?nte? stops ?? softwa?e co?nte? reset when ptnon ?et??ns high p?lse width set ?? ccra o?tp?t inve?ts when ptnpol = 1 no ccrp inte???pts gene?ated ptmn o/p pin (ptnoc=0) ptckn pin softwa?e t?igge? clea?ed ?? ccra match ptckn pin t?igge? a?to. set ?? ptckn pin softwa?e t?igge? softwa?e clea? softwa?e t?igge? softwa?e t?igge? ptnm [1:0] = 10 ; ptnio [1:0] = 11 single p?lse o?tp?t mode (n=0~2) note: 1. counter stopped by ccra 2. ccrp is not used 3. the pulse is triggered by the ptckn pin or by setting the ptnon bit high 4. a ptckn pin active edge will automatically set the ptnon bit high 5. in the single pulse output mode, ptnio[1:0] must be set to 11 and cannot be changed.
rev. 1.20 15? ?e???a?? 1?? 201? rev. 1.20 15 ? ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ca m to select this mode bits ptnm1 and ptnm0 in the ptmnc1 register should be set to 01 respectively. this mode enables external signals to capture and store the present value of the internal counter and can therefore be used for applications such as pulse width measurements. the external signal i s sup plied on t he pt pni or pt ckn p in whi ch i s se lected usi ng t he pt ncapts b it i n t he ptmnc1 register . the input pin active edge can be either a rising edge, a falling edge or both rising and fallin g edges; the active edge transition type is selected using the ptnio1 and ptnio0 bits in the ptmnc1 register . the counter is started when the ptnon bit changes from low to high which is initiated using the application program. when the required edge transition appears on the ptpni or ptckn pin the present value in the counter will be latched into the ccra registers and a ptmn interrupt generated. irrespective of what events occur on the ptpni or ptckn pin, the counter will continue to free run until the ptnon bit changes from high to low . when a ccrp compare match occurs the counter will reset back to zero; in this way the ccrp value can be used to control the maximum counter value. when a ccrp compare match occurs from comparator p , a ptmn interrupt will also be generated. counting the number of overfow interrupt signals from the ccrp can be a useful method in measuring long pulse widths. the ptnio1 and ptnio0 bits can select the active trigger edge on the ptpni or ptckn pin to be a rising edge, falling edge or both edge types. if the ptnio1 and ptnio0 bits are both set high, then no capture operation will take place irrespective of what happens on the ptpni or ptckn pin, however it must be noted that the counter will continue to run. as the ptpni or ptckn pin is pin shared with other functions, care must be taken if the ptmn is in the capture input mode. this is because if the pin is setup as an output, then any transitions on this pin may cause an input capture operation to be executed. the ptncclr, ptnoc and ptnpol bits are not used in this mode.
rev. 1.20 158 ? e ??? a ?? 1 ?? 201 ? rev. 1.20 159 ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu co?nte? val?e yy ccrp ptnon ptnpau ccrp int. ?lag ptmnp? ccra int. ?lag ptmna? ccra val?e time co?nte? clea?ed ?? ccrp pa?se res?me co?nte? reset ptnm[1:0] = 01 ptmn capt??e pin ptpni o? ptckn xx co?nte? stop ptnio [1:0] val?e active edge active edge active edge 00 - rising edge 01 - ?alling edge 10 - both edges 11 - disa?le capt??e xx yy xx yy capt??e inp?t mode (n=0~2) note: 1. ptnm[1:0] = 01 and active edge set by the ptnio[1:0] bits 2. a ptmn capture input pin active edge transfers the counter value to ccra 3. ptncclr bit not used 4. no output function C ptnoc and ptnpol bits are not used 5. ccrp determin es the counter value and the counter has a maximum count value when ccrp is equal to zero.
rev. 1.20 158 ?e???a?? 1?? 201? rev. 1.20 159 ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu al dal c the need to interface to real world analog signals is a common requirement for many electronic systems. however , to properly process these signals by a microcontroller , they must first be converted into digital signals by a/d converters. by integrating the a/d conversion electronic circuitry into the microcontroller , the need for external components is reduced signifcantly with the corresponding follow-on benefts of lower costs and reduced component space requirements. these d evices c ontain a m ulti-channel a nalog t o d igital c onverter wh ich c an d irectly i nterface to external analog signals, such as that from sensors or other control signals and convert these signals d irectly i nto a 1 2-bit d igital v alue. t he e xternal o r i nternal a nalog si gnal t o b e c onverted i s determined by the sains3~sains0 bits together with the sacs3~sacs0 bits. when the external analog s ignal is to be converted, the corres ponding pin-s hared control bits s hould first be properly configured and then desired external channel input should be selected using the sains3~sains0 and sacs3~sacs0 bits. note that when the internal analog signal is to be converted, the pin-shared control bits should also be properly confgured except the sains and sacs bit felds. more detailed information about the a/ d input signal is described in the a/d converter control registers and a/d converter input signals sections respectively. ht ??? b5 ? 2 8: an0~an ? ? : av dd ? av dd /2 ? av dd /4 ? v r ? v r /2 ? v r /4 sains3~sains0 ? sacs3~sacs0 ht ??? b5 ? 4 12: an0~an11 ht ??? b5 ?? 1 ? : an0~an15 the accompanying block diagram shows the overall internal structure of the a/d converter , together with its associated registers. pin-sha?ed selection sacs3~sacs0 sains3~sains0 a/d conve?te? start adbz adcen av ss a/d clock 2 n (n=0~?) f sys sacks2~ sacks0 av dd adcen sadol sadoh an0 an1 ann a/d refe?ence voltage a/d data registe?s av dd av dd /2 av dd /4 v r v r /2 v r /4 adr?s pga v ri v bgre? pgags1~pgags0 (gain=1/1.???/2.5/3.333) adpgaen v r av dd vre?i pgais savrs1~savrs0 vre? vr pin-sha?ed selection pin-sha?ed selection pin-sha?ed selection note: n=7 for ht66fb572; n=11 for ht66fb574; n=15 for HT66FB576.
rev. 1.20 1 ? 0 ? e ??? a ?? 1 ?? 201 ? rev. 1.20 1?1 ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu /d c rs ds overall operation of the a/d converter is controlled using six registers. a read only register pair exists to store the a/d converter data 12-bit value. the remaining four registers are control registers which setup the operating and control function of the a/d converter. sadol(adr ? s=0) d3 d2 d1 d0 sadol(adr ? s=1) d ? d ? d5 d4 d3 d2 d1 d0 sadoh(adr ? s=0) d11 d10 d9 d8 d ? d ? d5 d4 sadoh(adr ? s=1) d11 d10 d9 d8 sadc0 start adbz adcen adr ? s sacs3 sacs2 sacs1 sacs0 sadc1 sains3 sains2 sains1 sains0 sacks2 sacks1 sacks0 sadc2 adpgaen pgais savrs1 savrs0 pgags1 pgags0 vbgrc vbgren a/d conve?te? registe?s list a/d conve?te? data registe?s C sadol? sadoh as these devices contain an internal 12-bit a/d converter , it requires two data registers to store the converted value. these are a high byte register , known as sadoh, and a low byte register , known as sadol. after the conversion process takes place, these registers can be directly read by the microcontroller to obtain the digitised conversion value. as only 12 bits of the 16-bit register space is ut ilised, t he form at i n whi ch t he da ta i s st ored i s c ontrolled by t he adrfs bi t i n t he sadc0 register as shown in the accompany ing table. d0~d1 1 are the a/d conversion result data bits. any unused bits will be read as zero. note that a/d data registers contents will be unchanged if the a/d converter is disabled. 0 d11 d10 d9 d8 d ? d ? d5 d4 d3 d2 d1 d0 x x x x 1 x x x x d11 d10 d9 d8 d ? d ? d5 d4 d3 d2 d1 d0 a/d conve?te? data registe?s a/d conve?te? cont?ol registe?s C sadc0? sadc1? sadc2 to c ontrol t he f unction a nd o peration o f t he a/ d c onverter, t hree c ontrol r egisters k nown a s sadc0~sadc2 are provided. these 8-bit registers defne functions such as the selection of which analog channel is connected to the internal a/d converter , the digitise d data format, the a/d clock source as well as controlling the start function and monitoring the a/d converter busy status. as the devices contain only one actual analog to digital converter hardware circuit, each of the external or i nternal a nalog si gnal i nputs m ust be ro uted t o t he c onverter. t he sacs3~ sacs0 bi ts i n t he sadc0 register are used to determine which external channel input is selected to be converted. the sains3~sains0 bits in the sadc1 register are used to determine that the analog signal to be converted comes from the internal analog signal or external analog channel input. the relev ant pin-shared function selection bits determine which pins on i/o ports are used as analog inputs for the a/d converter input and which pins are not to be used as the a/d converter input. when the pin is selected to be an a/d input, its original function whether it is an i/o or other pin- shared function will be removed. in addition, any internal pull-high resistor connected to the pin will be automatically removed if the pin is selected to be an a/d converter input.
rev. 1.20 1?0 ?e???a?? 1?? 201? rev. 1.20 1 ? 1 ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ? name start adbz adcen adr ? s sacs3 sacs2 sacs1 sacs0 r/w r/w r r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 start : start the a/d conversion 010: start this bit is used to initiate an a/ d conversion process. the bit is normally low but if set high and then cleared low again, the a/d converter will initiate a conversion process. bit 6 adbz : a/d converter busy fag 0: no a/d conversion is in progress 1: a/d conversion is in progress this read only fag is us ed to indicate w hether the a /d convers ion is in progress or not. when the st art bit is set from low to high and then to low again, the adbz fag will be set to 1 to indicate that the a/d conversion is initiated. the adbz fag will be cleared to 0 after the a/d conversion is complete. bit 5 adcen : a/d converter function enable control 0: disable 1: enable this bit controls the a/d internal function. this bit should be set to one to enable the a/ d c onverter. i f t he b it i s se t l ow, t hen t he a/ d c onverter wi ll b e swi tched off reducing the devices power consumption. when the a/d converter function is disabled, the contents of the a/d data register pair known as sadoh and sadol will be unchanged. bit 4 adrfs : a/d converter data format select 0: a/d converter data format sadoh = d[11:4]; sadol = d[3:0] 1: a/d converter data format sadoh = d[11:8]; sadol = d[7:0] this bit controls the format of the 12-bit converted a/d value in the two a/d data registers. details are provided in the a/d data register section. bit 3~0 sacs3~sacs0 : a/d converter external analog channel input select ht66fb572 0000: an0 0001: an1 0110: an6 0111: an7 other values: adc input is foating ht66fb574 0000: an0 0001: an1 1010: an10 1011: an1 1 other values: adc input is foating HT66FB576 0000: an0 0001: an1 1110: an14 1111: an15
rev. 1.20 1 ? 2 ? e ??? a ?? 1 ?? 201 ? rev. 1.20 1?3 ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ? name sains3 sains2 sains1 sains0 sacks2 sacks1 sacks0 r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 bit 7~4 sains3~sains0 : a/d converter input signal select 0000: external input C external analog channel input 0001: internal input C internal a/d converter power supply voltage a v 0010: internal input C internal a/d converter power supply voltage a v /2 0011: internal input C internal a/d converter power supply voltage a v /4 0100: external input C external analog channel input 0101: internal input C internal a/d converter pga output voltage v r 0110: internal input C internal a/d converter pga output voltage v r /2 0111: internal input C internal a/d converter pga output voltage v r /4 1000~1011: reserved, connected to ground 1100~1111: external input C external analog channel input when the internal analog signal and the external signal are select ed to be converte d simultaneously, the external channel input signal will automatically be switched of f regardless of the sacs3~sacs0 bit feld value. bit 3 unimplemented, read as 0 bit 2~0 sacks2~sacks0 : a/d conversion clock source select 000: f 001: f /2 010: f /4 011: f /8 100: f 101: f /32 110: f /64 111: f /128 these three bits are used to select the clock source for the a/d converter. ? name adpgaen pgais savrs1 savrs0 pgags1 pgags0 r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7 adpgaen : pga enable/disable control 0: disable 1: enable when the pga output v r is selected as a/d converter input or a/d converter reference voltage, the pga needs to be enabled by setting this bit high. otherwise the pga needs to be disabled by clearing this bit to zero to conserve the power. bit 6~5 unimplemented, read as 0 bit 4 pgais : pga input (v ri ) select 0: external vrefi pin 1: internal independent reference voltage, v bgref when the external voltage on vrefi pin and the internal independent reference voltage v bgref are selected as the pga input simultaneously , the hardware will only choose the internal voltage v bgref as the pga input. bit 3~2 savrs1~savrs0 : a/d converter reference voltage select 00: internal a/d converter power, a v 01: vref pin 1x: internal pga output voltage, v r
rev. 1.20 1?2 ?e???a?? 1?? 201? rev. 1.20 1 ? 3 ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu these bits are used to select the a/d converter reference voltage. when the internal a/d converter power or the internal pga output voltage and the external input voltage on vref pin are selected as the reference voltage simultaneously , the hardware will only choose the internal reference voltage as the a/d converter reference voltage. bit 1~0 : pga gain select 00: gain=1 01: gain=1.667, v r =2v for v ri =v bgref (pgais=1) 10: gain=2.5, v r =3v for v ri =v bgref (pgais=1) 11: gain=3.333, v r =4v for v ri =v bgref (pgais=1) the st art bit in the sadc0 register is used to start the ad conversion. when the microcontroller sets t his b it f rom l ow t o h igh a nd t hen l ow a gain, a n a nalog t o d igital c onversion c ycle wi ll b e initiated. the adbz bi t i n t he sadc0 re gister i s use d t o i ndicate whe ther t he a nalog t o di gital c onversion process is in progress or not. this bit will be automatically set to 1 by the microcontroller after an a/d conversion is successfully initiated. when the a/d conversion is complete, the adbz will be cleared to 0. in addition, the corresponding a/d interrupt request fag will be set in the interrupt control register , and if the interrupts are enabled, an appropriate internal interrupt signal will be generated. this a/d internal interrupt signal will direct the program flow to the associated a/d internal interrupt address for processing. if the a/d internal interrupt is disabled, the microcontroller can poll the adbz bit in the sadc0 register to check whether it has been cleared as an alternative method of detecting the end of an a/d conversion cycle. the clock source for the a/d converter , which originates from the system clock f sys , can be chosen to be either f sys or a subdivided version of f sys . the division ratio value is determined by the sacks2~sacks0 bits in the sadc1 register . although the a/d cloc k source is determined by the system clock f sys and by bits sacks2~sacks0, there are some limitations on the maximum a/d clock source speed that can be selected. as the recommended range of permissible a/d clock period, t adck , is from 0.5s to 10s, care must be taken for system clock frequencies. for example, as the system clock operates at a frequency of 8mhz, the sacks2~sacks0 bits should not be set to 000, 001 or 1 11. doing so will give a/d clock periods that are less than the minimum or lar ger than the maxim um a/d clock period which may result in inaccurate a/d conversion values. refer to the following table for examples, where values marked with an asterisk * show where, depending upon the devices, special care must be taken. 1mhz 1s 2s 4s 8s 16s * 32s * 64s * 128s * 2mhz 500ns 1s 2s 4s 8s 16s * 32s * 64s * 4mhz 250ns * 500ns 1s 2s 4s 8s 16s * 32s * 8mhz 125ns * 250ns * 500ns 1s 2s 4s 8s 16s * 12mhz 83ns * 1 ?? ns * 333ns * ??? ns 1.33s 2.67s 5.33s 10.67s * 1 ? mhz ? 2.5ns * 125ns * 250ns * 500ns 1s 2s 4s 8s controlling t he powe r on/ off func tion of t he a/ d c onverter c ircuitry i s i mplemented usi ng t he adcen bit in the sadc0 register . this bit must be set high to power on the a/d converter . when the adcen bit is set high to power on the a/d converter internal circuitry a certain delay , as indicated in the timing diagram, must be allowed before an a/d conversion is initiated. even if no pins are selected for use as a/d inputs, if the adcen bit is high, then some power will still be
rev. 1.20 1 ? 4 ? e ??? a ?? 1 ?? 201 ? rev. 1.20 1?5 ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu consumed. in power conscious applications it is therefore recommended that the adcen is set low to reduce power consumption when the a/d converter function is not being used. the reference voltage supply to the a/d converter can be supplied from the positive power supply pin, a vdd, or from an external reference source supplied on pin vref , or from the internal pga output voltage, v r . the desired selection is made using the sa vrs1 and sa vrs0 bits. when the savrs bit feld is set to 00, the a/d converter reference voltage will come from the a vdd pin. if the sa vrs bit feld is set to 01, the a/d converter reference volta ge will come from the vref pin. otherwise, the a/d converter reference voltage will come from the pga output, v r . as the vref p in i s p in-shared wi th o ther f unctions, wh en t he vr ef p in i s se lected a s t he r eference v oltage supply pin, the vref pin-shared function control bits should be properly confgured to disable other pin functions. in addition, if the program selects an external reference voltage on vref pin and the internal reference voltage a v dd or v r as the a/d converter reference voltage, then the hardware will only choose the internal reference voltage as the a/d converter reference voltage input. the analog input values must not be allowed to exceed the value of the selected reference voltage, v ref . the a/ d converter also has a vre fi pin which is one of pga inputs for a/ d converter reference. t o select this pga input signal, the pgais bit in the sadc2 register must be cleared to zero and the revelent pin-shared control bits should be properly confgured. however , the pga input can be aslo supplied from the internal independent reference voltage, v bgref . if the application program selects the external voltag e on the vrefi pin and an internal voltage v bgref as pga input simultaneously , then the hardware will only choose the internal voltage v bgref as pga input. 00 av dd inte ? nal a/d conve ? te ? powe ? s ? ppl ? voltage 01 vre ? pin exte ? nal a/d conve ? te ? ? efe ? ence pin vre ? 1x v r inte ? nal a/d conve ? te ? pga o ? tp ? t voltage a/d conve?te? refe?ence voltage selection vbgrc registe? bit ? ? 5 4 3 2 1 0 name vbgren r/w r/w por 0 bit 7~1 unimplemented, read as 0 bit 0 : independent reference bandgap enable/disable control 0: disable 1: enable when the vbgren bit is cleared to zero, the v bgref is in a high impedance state. all the external a/d analog channel input pins are pin-shared with the i/o pins as well as other functions. the correspondi ng cont rol bit s for ea ch a/ d ext ernal i nput pin in t he pxs0 and pxs1 registers determine whether the input pins are setup as a/d converter analog inputs or whether they have other functions. if the pin is setup to be as an a/d analog channel input, the original pin functions will be disabled. in this way , pins can be changed under program control to change their function bet ween a/ d inputs and other func tions. al l pull high resi stors, whic h are set up through register programm ing, will be autom atically disconnected if the pins are setup as a/d inputs. note that it is not necessary to frst setup the a/d pin as an input in the port control register to enable the
rev. 1.20 1?4 ?e???a?? 1?? 201? rev. 1.20 1 ? 5 ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu a/d input as when the pin-shared function control bits enable an a/d input, the status of the port control register will be overridden. if the sains3~sains0 bits are set to 0000, 0100, or 1 100~1111, the external analog channel input is selected to be converted and the sacs3~sacs0 bits can determine which actual external channel is selecte d to be converted. if the sains3~sains0 bits are set to 0001~001 1, the a v voltage with a specifc ratio of 1, 1/2 or 1/4 is selected to be converted. if the sains3~sains0 bits are set to 0101~01 11, the pga output voltage with a specifc ratio of 1, 1/2 or 1/4 is selected to be converted. note that when the programs select external signal (an0~an15) and internal signal ( av , av /2, a v /4, v r , v r /2 or v r /4) as an a/d converter input signal simultaneously , then the hardware will only choose the inter nal signal as an a/d converter input, the external analog signal will be switched off automatically. sains[3:0] sacs[3:0] input signals description 0000 ? 0100 ? 1 100 ~1111 0000~0111 an0~an ? ( ? o ? ht ??? b5 ? 2) exte ? nal pin analog inp ? t 0000~1011 an0~an 11 ( ? o ? ht ??? b5 ? 4) 0000~1111 an0~an 15 ( ? o ? ht ??? b5 ? ? ) 0001 xxxx av dd inte ? nal a/d conve ? te ? powe ? s ? ppl ? voltage 0010 xxxx av dd /2 inte ? nal a/d conve ? te ? powe ? s ? ppl ? voltage /2 0011 xxxx av dd /4 inte ? nal a/d conve ? te ? powe ? s ? ppl ? voltage /4 0101 xxxx v r inte ? nal a/d conve ? te ? pga o ? tp ? t voltage 0110 xxxx v r /2 inte ? nal a/d conve ? te ? pga o ? tp ? t voltage/2 0111 xxxx v r /4 inte ? nal a/d conve ? te ? pga o ? tp ? t voltage/4 1000~ 1011 xxxx rese ? ved ? connected to g ? o ? nd a/d converter input signal selection conversion rate and timing diagram a com plete a/d conversi on contains two parts, dat a sampli ng and dat a conversi on. the dat a sampling which is defned as t ads takes 4 a/d clock cycles and the data conversion takes 12 a/d clock cycles. therefore a total of 16 a/d clock cycles for an external input a/d conversion which is defned as t adc are necessary. maximum single a/d conversion rate = a/d clock period / 16 the accompanying diagram shows graphically the various stages involved in an analog to digital conversion process and its associated timing. after an a/d conversion process has been initiated by the application program, the microcontroller internal hardware w ill begin to carry out the conversion, d uring wh ich t ime t he p rogram c an c ontinue wi th o ther f unctions. t he t ime t aken f or t he a/d conversion is 16 t adck clock cycles where t adck is equal to the a/d clock period.
rev. 1.20 1 ?? ? e ??? a ?? 1 ?? 201 ? rev. 1.20 1?? ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu adcen start adbz sacs[3:0] (sains[3:0]=0000) off on off on t on2st t ads a/d sampling time t ads a/d sampling time sta?t of a/d conve?sion sta?t of a/d conve?sion sta?t of a/d conve?sion end of a/d conve?sion end of a/d conve?sion t adc a/d conve?sion time t adc a/d conve?sion time t adc a/d conve?sion time 0011b 0010b 0000b 0001b a/d channel switch a/d conve?sion timing C exte?nal channel inp?t s?mma?? of a/d conve?sion steps the following summarises the individual steps that should be executed in order to implement an a/ d conversion process. ? step 1 select the require d a/d conversion clock by correctly programming bits sacks2~sacks0 in the sadc1 register. ? step 2 enable the a/d by setting the adcen bit in the sadc0 register to one. ? step 3 select which signal is to be connec ted to the internal a/d converter by correctly confguring the sains3~sains0 bits in the sadc1 register. select the external channel input to be converted, go to step 4. select the internal analog signal to be converted, go to step 5. ? step 4 if the a/d input signal comes from the external channel input selected by confguring the sains bit fel d, the corresponding pins should be confgured as a/d input functi on by confguring the relevant pin-shared function control bits. the desired analog channel then should be selected by confguring the sacs bit feld. after this step, go to step 6. ? step 5 if the a/d input signal comes from the internal analog signal, the sains bit field should be properly configured and then the external channel input will automatically be disconnected regardless of the sacs bit feld value. after this step, go to step 6. ? step 6 select the reference voltage source by configuring the sa vrs1~savrs0 bits in the sadc2 register. if the pga output voltage is selected, the pga must be enabled and then select the pga input source by confguring the pgais bit in the sadc2 register. ? step 7 select a/d converter output data format by setting the adrfs bit in the sadc0 register. ? step 8 if a/d conversion interrupt is used, the interrupt control registers must be correctly confgured to ensure the a/d interrupt function is active. the master interrupt control bit, emi, and the a/d conversion interrupt control bit, ade, must both be set high in advance.
rev. 1.20 1?? ?e???a?? 1?? 201? rev. 1.20 1 ?? ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ? step 9 the a/d conversion procedure can now be initialized by setting the st art bit from low to high and then low again. ? step 10 if a/ d conversi on i s i n progre ss, t he adbz fla g wi ll be se t high. aft er t he a/ d conversi on process is complete, the a dbz flag w ill go low and then the output data can be read from sadoh and sadol registers. note: when checking for the end of the conversion process, if the met hod of polling the adbz bit in the sadc0 register is used, the interrupt enable step above can be omitted. during m icrocontroller ope rations where t he a/d c onverter i s not be ing use d, t he a/d i nternal circuitry c an be swi tched of f t o re duce powe r c onsumption, by c learing bi t adce n t o 0 i n t he sadc0 regist er. when thi s happens, the int ernal a/ d converter ci rcuits wi ll not consume power irrespective of what analog voltage is applied to their input lines. if the a/d converter input lines are used as normal i/os, then care must be taken as if the input voltage is not at a valid logic level, then this may lead to some increase in power consumption. as the devices contain a 12-bit a/d converter , its full-scale converted digitised value is equal to 0fffh. since the full-scale analog input value is equal to the actual a/d converter reference voltage, v ref , this gives a single bit analog input value of v ref divided by 4096. 1 lsb = v ref 4096 the a/d converter input voltage value can be calculated using the following equation: a/d input voltage = a/d output digital value ( v ref 4096 ) the diagram shows the ideal transfer function between the analog input value and the digitised output val ue for t he a/ d conve rter. e xcept for t he di gitised ze ro val ue, t he subsequent digi tised values will change at a point 0.5 lsb below where they would change without the of fset, and the last full scale digitised value will change at a point 1.5 lsb below the v ref level. note that here the v ref voltage is the actual a/d converter reference voltage determined by the savrs feld. ???h ??eh ??dh 03h 02h 01h 0 1 2 3 4093 4094 4095 409? v re? 409? analog inp?t voltage a/d conve?sion res?lt 1.5 lsb 0.5 lsb ideal a/d t?ansfe? ??nction
rev. 1.20 1 ? 8 ? e ??? a ?? 1 ?? 201 ? rev. 1.20 1?9 ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu /d cs a eals the following two programming examples illustrate how to setup and implement an a/d conversion. in the frst example, the method of polling the adbz bit in the sadc0 register is used to detect when the conversion cycle is complete, whereas in the second example, the a/d interrupt is used to determine when the conversion is complete. clr ade ; disable adc interrupt mov a,03h mov sa dc1,a ; s elect f sys /8 a s a /d cl ock set a dcen mov a ,03h ; s etup p bs0 t o c onfgure p in a n0 mov p bs0,a mov a,20h mov sa dc0,a mov a,00h mov s adc2,a ; e nable an d c onnect a n0 c hannel t o a /d c onverter : : start_conversion: clr st art ; h igh p ulse o n s tart b it t o i nitiate c onversion set s tart ; r eset a /d clr s tart ; s tart a /d polling_eoc: sz a dbz ; p oll t he s adc0 r egister a dbz b it t o d etect e nd o f a /d c onversion jmp p olling_eoc ; c ontinue p olling mov a ,sadol ; re ad l ow b yte c onversion re sult v alue mov s adol_buffer,a ; s ave r esult t o us er d efned r egister mov a ,sadoh ; re ad h igh b yte c onversion re sult v alue mov s adoh_buffer,a ; s ave r esult t o us er d efned r egister : : jmp s tart_conversion ; s tart n ext a/ d c onversion clr ade ; disable adc interrupt mov a,03h mov sa dc1,a ; s elect f sys /8 a s a /d cl ock set a dcen mov a ,03h ; s etup p bs0 t o c onfgure p in a n0 mov p bs0,a mov a,20h mov sa dc0,a mov a,00h mov s adc2,a ; e nable an d c onnect a n0 c hannel t o a /d c onverter : : start_conversion: clr st art ; h igh p ulse o n st art b it t o i nitiate c onversion set s tart ; r eset a /d clr s tart ; s tart a /d clr a df ; c lear a dc i nterrupt re quest f ag set ade ; enable adc interrupt set e mi ; e nable gl obal i nterrupt : :
rev. 1.20 1?8 ?e???a?? 1?? 201? rev. 1.20 1 ? 9 ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu dc s adc_isr: mov ac c_stack,a ; s ave a cc t o u ser d efned m emory mov a ,status mov s tatus_stack,a ; s ave st atus t o us er d efned m emory mov a ,sadol ; re ad l ow b yte c onversion re sult v alue mov s adol_buffer,a ; s ave r esult t o us er d efned r egister mov a ,sadoh ; re ad h igh b yte c onversion re sult v alue mov s adoh_buffer,a ; s ave r esult t o us er d efned r egister exit_int_isr: mov a ,status_stack mov s tatus,a ; restore s tatus f rom u ser d efned m emory mov a ,acc_stack ; r estore a cc fr om u ser d efned m emory comparators two independent analog comparators are contained within the devices. these functions of fer fexibility via their register controlled features such as power -down, polarity select, hysteresis etc. in sharing their pins with normal i/o pins the comparators do not waste precious i/o pins if there functions are otherwise unused. + ? cmpnen cmpnpol cmpno one shot cmp n interrupt cmpnhyen cnx pin pin-shared selection cn+ cn- pin-shared selection comparators (n=0~1) comparator operation the devices conta in two comparato r functions which are used to compare two analog voltages and provide an output based on their difference. any pull-high resistors connected to the shared comparator input pins will be automatically disconnected when the comparator is enabled. as the comparator inputs approach their switching level, some spurious output signals may be generated on the comparator output due to the slow rising or falling nature of the input signals. this can be minimised by selecting the hysteresis function will apply a small amount of positive feedback to the comparator . ideally the comparator should switch at the point where the positive and negative inputs signals are at the same voltage level. however , unavoidable input of fsets introduce some uncertainties here. the hysteresis function, if enabled, also increases the switching offset value.
rev. 1.20 1 ? 0 ? e ??? a ?? 1 ?? 201 ? rev. 1.20 1?1 ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu caa rss full control over each internal comparator is provided via the control register , cmpnc. the comparator output is recorded via a bit in their respective control register , but can also be transferred out o nto a sh ared i /o p in. ad ditional c omparator f unctions i nclude o utput p olarity, h ysteresis functions and power down control. name cmpnen cmpnpol cmpno cmpnhyen r/w r/w r/w r r/w por 0 0 0 1 bit 7 unimplemented, read as 0 bit 6 cmpnen : comparator n enable control 0: disable 1: enable this is the comparator n on/of f control bit. if the bit is zero the comparator n will be switched of f and no power consumed even if analog voltages are applied to its inputs. for powe r se nsitive a pplications t his bi t shoul d be c leared t o z ero i f t he c omparator n is not used or before the devices ent er the sleep or idle mode. note that the comparator n output will be set low when this bit is cleared to zero. bit 5 cmpnpol : comparator n output polarity control 0: output is not inverted 1: output is inverted this is the comparator n polarity control bit. if the bit is zero then the comparator n output bit, cmpno, will refect the non-inverted output condition of the comparator n. if the bit is high the comparator n output bit will be inverted. bit 4 cmpno : comparator n output bit if cmpnpol=0, 0: cn+ < cn- 1: cn+ > cn- if cmpnpol=1, 0: cn+ > cn- 1: cn+ < cn- this bit stores the comparator n output bit. the polarity of the bit is determined by the voltages on the comparator n inputs and by the condition of the cmpnpol bit. bit 3~1 unimplemented, read as 0 bit 0 cmpnhyen : comparator n hysteresis enable control 0: disable 1: enable this is the comparator n hysteres is enable control bit and if s et high w ill apply a l imited a mount of hyst eresis t o t he c omparator, a s sp ecified i n t he com parator electrical c haracteristics t able. t he p ositive f eedback i nduced b y hy steresis r educes the effect of spurious switching near the comparator threshold.
rev. 1.20 1?0 ?e???a?? 1?? 201? rev. 1.20 1 ? 1 ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu caa each comparator also possesses its own interrupt function. when any one of the output bits changes state, its relevant interrupt fag will be set, and if the corresponding interrupt enable bit is set, then a jump to its relevant interrupt vector will be executed. note that it is the changing state of the cmpno bit and not the output pin w hich generates an interrupt. if the microcontroller is in the sleep or idle mode and the comparator is enabled, then if the external input lines cause the comparator output bit to change state, the resulting generated interrupt flag will also generate a wake-up. if it is required to disable a wake-up from occurring, then the interrupt fag should be frst set high before entering the sleep or idle mode. if the comparator is enabled, it will remain active when the microcontroller enters the sleep or idle mode, however as it will consume a certain amount of power , the user may wish to consider disabling it before the sleep or idle mode is entered. as comparator pins are shared with normal i/o pins the i/o registers for these pins will be read as zero (port control register is "1") or read as port data register value (port control register is "0") if the comparator function is enabled. the devices conta in a serial interface module, which includes both the four line spi interface and the two line i 2 c interface types, to allow an easy method of communication with external peripheral hardware. ha ving re latively si mple c ommunication prot ocols, t hese se rial i nterface t ypes a llow the microcontroller to interface to external spi or i 2 c based hardware such as sensors, flash or eeprom memory , etc. the sim interface pins are pin-shared with other i/o pins therefore the sim interface functiona l pins must frst be selected using the corresponding pin-shared function selection bits. as both inter face types share the same pins and registers, the choice of whether the spi or i 2 c type is used is made using the sim operating mode control bits, named sim2~sim0, in the simc0 register. these pull-high resistors of the sim pin-shared i/o are selected using pull-high control registers when the sim function is enabled and the corresponding pins are used as sim input pins. this spi i nterface f unction, wh ich i s p art o f t he se rial i nterface mo dule, sh ould n ot b e c onfused with the other independent spi function, which is described in another section of this datasheet. the spi interface is often used to communicate with external peripheral devices such as sensors, flash or eeprom memory devices etc. originally developed by motorola, the four line spi interface is a synchronous serial data interface that has a relatively simple communication protocol simplifying the programming requirements when communicating with external hardware devices. the communication is full duplex and operates as a slave/master type, where the devices can be either mas ter or s lave. a lthough the s pi interface s pecifcation can control multiple s lave devices from a single master , but the devices provide only one scs pin. if the master needs to control multiple slave devices from a single master, the master can use i/o pin to select the slave devices. the spi i nterface i s a f ull d uplex sy nchronous se rial d ata l ink. i t i s a f our l ine i nterface wi th p in names sdi, sdo, sck and scs . pins sdi and sdo are the serial data input and serial data output lines, the sck pin is the serial clock line and scs is the slave select line. as the spi interface pins are pin-shared with normal i/o pins and with the i 2 c function pins, the spi interface pins must frst
rev. 1.20 1 ? 2 ? e ??? a ?? 1 ?? 201 ? rev. 1.20 1?3 ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu be selected by confguring the pin-shared function selection bits and setting the correct bits in the simc0 and simc2 registers. communication between devices connected to the spi interface is carried out in a slave/master mode with all data transfer initiations being implemented by the master . the master also controls the clock signal. as the devices only contain a single pin only one slave device can be utilized. the pin is controlled by software, set csen bit to 1 to enable pin function, set csen bit to 0 the pin will be foating state. sck spi master sdo sdi scs sck spi slave sdi sdo scs spi master/slave connection the spi function in the devices offers the following features: ? full duplex synchronous data transfer ? both master and slave modes ? lsb frst or msb frst data transmission modes ? transmission complete fag ? rising or falling active clock edge the status of the spi interface pins is determined by a number of factors such as whether the devices are in the master or slave mode and upon the condition of certain control bits such as csen and simen. simd tx/rx shift registe? sdi pin clock edge/pola?it? cont?ol ckeg ckpolb clock so??ce select f sys f sub stm ccrp match f?eq?enc?/2 sck pin csen b?s? stat?s sdo pin scs pin data b?s wcol tr? simic? spi block diagram
rev. 1.20 1?2 ?e???a?? 1?? 201? rev. 1.20 1 ? 3 ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu s rss there are three internal registers which control the overall operation of the spi interface. these are the simd data register and two control registers, simc0 and simc2. simc0 sim2 sim1 sim0 simdeb1 simdeb0 simen simic ? simc2 d ? d ? ckpolb ckeg mls csen wcol tr ? simd d ? d ? d5 d4 d3 d2 d1 d0 spi registe?s list spi data registe? the simd register is used to store the data being transmitted and received. the same register is used by both the spi and i 2 c functions. before the devices write data to the spi bus, the actual data to be transmitted must be placed in the simd register . after the data is received from the spi bus, the devices can read it from the simd register . any transmission or reception of data from the spi bus must be made via the simd register. ? name d ? d ? d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por x x x x x x x x x: ? nknown bit 7~0 d7~d0 : sim data register bit 7 ~ bit 0 there are also two control registers for the spi interface, simc0 and simc2. note that the simc2 register also has the name sima which is used by the i 2 c function. the simc0 register is used to control the enable/disable function and to set the data transmission clock frequency . the simc2 register is used for other control functions such as lsb/msb selection, write collision fag etc. ? name sim2 sim1 sim0 simdeb1 simdeb0 simen simic ? r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 0 0 0 0 bit 7~5 sim2~sim0 : sim operating mode control 000: spi master mode; spi clock is f /4 001: spi master mode; spi clock is f 010: spi master mode; spi clock is f /64 011: spi master mode; spi clock is f sub 100: spi master mode; spi clock is stm ccrp match frequency/2 101: spi slave mode 110: i 2 c slave mode 111: unused mode these bits setup the overall operatin g mode of the sim function. as well as selecting if the i 2 c or spi function, they are used to control the spi master/slav e selection and the spi master clock frequency . the spi clock is a function of the system clock but can a lso b e c hosen t o b e so urced f rom st m and f sub . i f t he spi sl ave mo de i s selected then the clock will be supplied by an external master device. bit 4 unimplemented, read as 0
rev. 1.20 1 ? 4 ? e ??? a ?? 1 ?? 201 ? rev. 1.20 1?5 ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu bit 3~2 : i 2 c debounce t ime selection these bits are only used for the i 2 c mode of sim and are described in the i 2 c registers section. bit 1 : sim enable control 0: disable 1: enable the bi t is the overa ll on/of f control for the sim interface. when the simen bi t is cleared to zero to disable the sim interface, the sdi, sdo, sck and scs , or sda and scl lines will lose their spi or i 2 c function and the sim operating current will be reduced to a minim um value. when the bit is high the sim interface is enabled. if the sim is confgured to operate as an spi interface via the sim2~sim0 bits, the contents of the spi control registers will remain at the previous settings when the simen bit changes from low to high and should therefore be frst initialised by the application program. if the sim is confgured to operate as an i 2 c interface via the sim2~sim0 bits and the simen bit changes from low to high, the contents of the i 2 c control bits such as htx and txak will remain at the previous settings and should therefore be frst i nitialised by t he a pplication progra m whi le t he re levant i 2 c fags suc h a s hcf , haas, hbb, srw and rxak will be set to their default states. bit 0 : sim spi incomplete flag 0: sim spi incomplete condition is not occurred 1: sim spi incomplete condition is occurred this bit is only available when the sim is confgured to operate in an spi slave mode. if the spi operate s in the slave mode with the simen and csen bits both being set to 1 but the scs line is pulled high by the external master device before the spi data transfer is completely fnished, the simicf bit will be set to 1 togethe r with the trf bit. when this condition occurs, the corresponding interrupt will occur if the interrupt function is enabled. however , the trf bit will not be set to 1 if the simicf bit is set to 1 by software application program. ? name d ? d ? ckpolb ckeg mls csen wcol tr ? r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 : undefned bits these bits can be read or written by the application program. bit 5 : spi clock line base condition selection 0: the sck line will be high when the clock is inactive 1: the sck line will be low when the clock is inactive the ckpolb bi t de termines the ba se condition of the clock line, if the bi t is hi gh, then t he sck l ine wi ll be l ow whe n t he c lock i s i nactive. w hen t he ckpol b bi t i s low, then the sck line will be high when the clock is inactive. bit 4 : spi sck clock active edge type selection ckpolb=0 0: sck is high base level and data capture at sck rising edge 1: sck is high base level and data capture at sck falling edge ckpolb=1 0: sck is low base level and data capture at sck falling edge 1: sck is low base level and data capture at sck rising edge the ckeg and ckpolb bits are used to setup the way that the clock signal outputs and inputs data on the spi bus. these two bits must be confgured before data transfer is e xecuted ot herwise a n e rroneous c lock e dge m ay be ge nerated. t he ckpol b bi t determines t he ba se c ondition of t he c lock l ine, i f t he bi t i s hi gh, t hen t he sck l ine will be low when the clock is inact ive. when the ckpolb bit is low , then the sck
rev. 1.20 1?4 ?e???a?? 1?? 201? rev. 1.20 1 ? 5 ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu line will be high when the clock is inactive. the ckeg bit determines active clock edge type which depends upon the condition of ckpolb bit. bit 3 : spi data shift order 0: lsb frst 1: msb frst this is the data shift select bit and is used to select how the data is transferred, either msb or lsb frst. setting the bit high will select msb frst and low for lsb frst. bit 2 : spi scs pin control 0: disable 1: enable the csen bit is used as an enable/disable for the scs pin. if this bit is low , then the scs pin will be disabled and placed into a foating condition. if the bit is high the scs pin will be enabled and used as a select pin. bit 1 : spi write collision fag 0: no collision 1: collision the wcol fag is used to detect if a data collision has occurred. if this bit is high it means that data has been attempted to be written to the simd register during a data transfer operation . this writing operation will be ignored if data is being transferred. the bit can be cleared by the application program. bit 0 : spi t ransmit/receive complete fag 0: spi data is being transferred 1: spi data transmission is completed the trf bit is the t ransmit/receive complete fag and is set 1 automatically when an spi data transmission is completed, but must set to 0 by the application program. it can be used to generate an interrupt. after t he spi i nterface i s e nabled by se tting t he sime n bi t hi gh, t hen i n t he ma ster mode , whe n data is written to the simd register , transmission/reception will begin simultaneously . when the data t ransfer i s c omplete, t he t rf fl ag wi ll be se t a utomatically, but m ust be c leared usi ng t he application program. in the slave mode, when the clock signal from the master has been received, any data in the simd register will be transmitted and any data on the sdi pin will be shifted into the simd re gister. t he m aster shoul d out put a n scs si gnal t o e nable t he sl ave de vices be fore a clock signal is provided. the slave data to be transferred should be well prepared at the appropriate moment relative to the scs signal depending upon the confgurations of the ckpolb bit and ckeg bit. the accompanying timing diagram shows the relationship between the slave data and scs signal for various confgurations of the ckpolb and ckeg bits. the spi wil l c ontinue t o funct ion i n spe cial idl e mode s i f t he c lock sourc e use d by t he spi interface is still active.
rev. 1.20 1 ?? ? e ??? a ?? 1 ?? 201 ? rev. 1.20 1?? ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu sck (ckpolb=1? ckeg=0) sck (ckpolb=0? ckeg=0) sck (ckpolb=1? ckeg=1) sck (ckpolb=0? ckeg=1) scs sdo (ckeg=0) sdo (ckeg=1) sdi data capt??e w?ite to simd simen? csen=1 simen=1? csen=0 (exte?nal p?ll-high) d?/d0 d?/d1 d5/d2 d4/d3 d3/d4 d2/d5 d1/d? d0/d? d?/d0 d?/d1 d5/d2 d4/d3 d3/d4 d2/d5 d1/d? d0/d? spi maste? mode timing sck (ckpolb=1) sck (ckpolb=0) scs sdo sdi data capt??e w?ite to simd (sdo does not change ?ntil fi?st sck edge) d?/d0 d?/d1 d5/d2 d4/d3 d3/d4 d2/d5 d1/d? d0/d? spi slave mode timing C ckeg=0 sck (ckpolb=1) sck (ckpolb=0) scs sdo sdi data capt??e d?/d0 d?/d1 d5/d2 d4/d3 d3/d4 d2/d5 d1/d? d0/d? w?ite to simd (sdo changes as soon as w?iting occ??s; sdo is floating if scs=1) note: ?o? spi slave mode? if sime n=1 and csen=0? spi is alwa?s ena?led and igno?es the scs level. spi slave mode timing C ckeg=1
rev. 1.20 1?? ?e???a?? 1?? 201? rev. 1.20 1 ?? ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu clea? sawcol w?ite data into spiad sawcol=1? t?ansmission completed? (satr?=1?) read data f?om spiad clea? satr? end t?ansfe? finished? a spia t?ansfe? maste? o? slave ? spiaen=1 config??e sackpolb? sackeg? sacsen and samls a saspi[2:0]=000? 001? 010? 011 o? 100 saspi[2:0]=101 maste? slave y y n n n y spi t?ansfe? cont?ol ?lowcha?t
rev. 1.20 1 ? 8 ? e ??? a ?? 1 ?? 201 ? rev. 1.20 1?9 ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu s bs eal/dsal to enable the spi bus, set csen=1 and scs =0, then wait for data to be written into the simd (txrx buf fer) re gister. for t he ma ster mode , a fter da ta ha s be en wri tten t o t he simd (t xrx buffer) register , then transmission or reception will start automatically . when all the data has been transferred, the trf bit should be set. for the slave mode, when clock pulses are received on sck, data in the txrx buffer will be shifted out or data on sdi will be shifted in. when the spi bus is disabled, sck, sdi, sdo and scs will become i/o pins or the other functions by confguring the corresponding pin-shared control bits. all communication is carried out using the 4-line interface for either master or slave mode. the csen bit in the simc2 register controls the overall function of the spi interface. setting this bit high will enable the spi interfac e by allowing the scs line to be active, which can then be used to control the spi interface. if the csen bit is low , the spi interface will be disabled and the scs line will be in a foating condition and can therefore not be used for control of the spi interface. if the csen bit and the simen bit in the simc0 are set high, thi s will place the sdi line in a foating condition and the sdo line high. if in master mode the sck line will be either high or low depending upon the clock polarity selection bit ckpolb in the simc2 register . if in slave mode the sck line will be in a foating condition. if the simen bit is low , then the bus will be disabled and scs , sdi, sdo and sck will all become i/o pins or the other functions. in the master mode the master will always generate the clock signal. the clock and data transmission will be initiated after data has been written into the simd register . in the slave mode, the clock signal will be received from an external master device for both data transmission and reception. the following sequences show the order to be followed for data transfer in both master and slave mode. ? step 1 select the spi master mode and clock source using the sim2~sim0 bits in the simc0 control register. ? step 2 setup the csen bit and setup the mls bit to choose if the data is msb or lsb frst, this setting must be the same with the slave devices. ? step 3 setup the simen bit in the simc0 control register to enable the spi interface. ? step 4 for write operations: write the data to the simd register , which will actually place the data into the txrx buffer. then use the sck and scs lines to output the data. after this, go to step5. for r ead o perations: t he d ata t ransferred i n o n t he sdi l ine wi ll b e st ored i n t he t xrx b uffer until all the data has been received at which point it will be latched into the simd register. ? step 5 check the wcol bit if set high then a collision error has occurred so return to step 4. if equal to zero then go to the following step. ? step 6 check the trf bit or wait for a spi serial bus interrupt. ? step 7 read data from the simd register.
rev. 1.20 1?8 ?e???a?? 1?? 201? rev. 1.20 1 ? 9 ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ? step 8 clear trf . ? step 9 go to step 4. ? step 1 select the spi slave mode using the sim2~sim0 bits in the simc0 control register ? step 2 setup the csen bit and setup the mls bit to choose if the data is msb or lsb frst, this setting must be the same with the master devices. ? step 3 setup the simen bit in the simc0 control register to enable the spi interface. ? step 4 for write operations: write the data to the simd register , which will actually place the data into the txrx buffer. then wait for the master clock sck and scs signal. after this, go to step5. for r ead o perations: t he d ata t ransferred i n o n t he sdi l ine wi ll b e st ored i n t he t xrx b uffer until all the data has been received at which point it will be latched into the simd register. ? step 5 check the wcol bit if set high then a collision error has occurred so return to step 4. if equal to zero then go to the following step. ? step 6 check the trf bit or wait for a spi serial bus interrupt. ? step 7 read data from the simd register. ? step 8 clear trf . ? step 9 go to step 4. the wcol bit in the simc2 register is provided to indicate errors during data transfer . the bit is set by the spi serial interface but must be cleared by the application program. this bit indicates a data colli sion has occurred which happens if a write to the simd register takes place during a data transfer operation and will prevent the write operation from continuing.
rev. 1.20 180 ? e ??? a ?? 1 ?? 201 ? rev. 1.20 181 ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu 2 c a the i 2 c interface is used to communicate with external peripheral devices such as sensors, eeprom m emory e tc. or iginally d eveloped b y ph ilips, i t i s a t wo l ine l ow sp eed se rial i nterface for synchronous serial data transfer . the advantage of only two lines for communication, relatively simple communication protocol and the ability to accommodate multiple devices on the same bus has made it an extremely popular interface type for many applications. device slave device maste? device slave vdd sda scl i 2 c maste? slave b?s connection i 2 c inte?face ope?ation the i 2 c serial interface is a two line interf ace, a serial data line, sda, and serial clock line, scl. as many devices may be connected together on the same bus, their outputs are both open drain types. for this reason it is necessary that external pull-high resistors are connected to these outputs. note that no chip select line exists, as each device on the i 2 c bus is identifed by a unique address which will be transmitted and received on the i 2 c bus. when two device s communicate with each other on the bidirectional i 2 c bus, one is known as the master de vice a nd one a s t he sl ave de vice. bot h m aster a nd sl ave c an t ransmit a nd re ceive da ta, however, it is the master device that has overall control of the bus. for the devices, which only operates in slave mode, there are two methods of transferring data on the i 2 c bus, the slave transmit mode and the slave receive mode. shift registe? t?ansmit/ receive cont?ol unit f sys f sub data b?s i 2 c add?ess registe? (sima) i 2 c data registe? (simd) add?ess compa?ato? read/w?ite slave srw detect sta?t o? stop hbb time-o?t cont?ol simto? add?ess match C haas i 2 c inte???pt de?o?nce ci?c?it?? scl pin m u x txak data o?t msb simtoen add?ess match simdeb[1:0] sda pin data in msb di?ection cont?ol htx 8-?it data t?ansfe? complete C hc? i 2 c block diag?am
rev. 1.20 180 ?e???a?? 1?? 201? rev. 1.20 181 ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu start signal f?om maste? send slave add?ess and r/w ?it f?om maste? acknowledge f?om slave send data ??te f?om maste? acknowledge f?om slave stop signal f?om maste? the simdeb1 and simdeb0 bits determine the debounce time of the i 2 c interface. this uses the internal clock to in ef fect add a debounce time to the external clock to reduce the possibility of gl itches on t he c lock l ine c ausing e rroneous ope ration. t he de bounce t ime, i f se lected, c an be chosen to be either 2 or 4 sys tem clocks. t o achieve the required i 2 c data trans fer speed, there exists a relationship between the system clock, f , and the i 2 c debounce time. for either the i 2 c standard or fast mode operation, users must take care of the selected system clock frequency and the confgured debounce time to match the criterion shown in the following table. i 2 c debounce time selection i 2 c standard mode (100khz) i 2 c fast mode (400khz) no de ? o ? nce f sys > 2 mhz f sys > 5 mhz 2 s ? stem clock de ? o ? nce f sys > 4 mhz f sys > 10 mhz 4 s ? stem clock de ? o ? nce f sys > 8 mhz f sys > 20 mhz i 2 c minimum f sys frequency i 2 c registers there a re t hree c ontrol re gisters a ssociated wi th t he i 2 c bus, simc0, simc1 a nd simt oc, one address register sima and one data register, simd. register name bit 7 6 5 4 3 2 1 0 simc0 sim2 sim1 sim0 simdeb1 simdeb0 simen simic ? simc1 hc ? haas hbb htx txak srw iamwu rxak simd d ? d ? d5 d4 d3 d2 d1 d0 sima a ? a5 a4 a3 a2 a1 a0 d0 simtoc simtoen simto ? simtos5 simtos4 simtos3 simtos2 simtos1 simtos0 i 2 c registers list i 2 c data register the simd register is used to store the data being transmitted and received. the same register is used by bot h t he spi a nd i 2 c fun ctions. be fore t he de vices wr ite da ta t o t he i 2 c bus, t he a ctual da ta t o be transmitted must be placed in the simd register . after the data is received from the i 2 c bus, the devices can read it from the simd register . any transmission or reception of data from the i 2 c bus must be made via the simd register.
rev. 1.20 182 ? e ??? a ?? 1 ?? 201 ? rev. 1.20 183 ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ? name d ? d ? d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por x x x x x x x x x: ? nknown bit 7~0 d7~d0 : sim data register bit 7 ~ bit 0 the sima registe r is also used by the spi interface but has the name simc2. the sima register is the location where the 7-bit slave address of the slave device is stored. bits 7~1 of the sima register defne the device slave address. bit 0 is not defned. when a master device, which is connected to the i 2 c bus, sends out an address, which matches the slave address in the sima register , the slave device will be selected. note that the sima register is the same register address as simc2 which is used by the spi interface. ? name a ? a5 a4 a3 a2 a1 a0 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~1 a6~a0 : i 2 c slave address a6~a0 is the i 2 c slave address bit 6~bit 0. bit 0 d0 : reserved bit, can be read or written there are three control registers for the i 2 c interface, simc0, simc1 and simt oc. the simc0 register is used to control the enable/disable function and to set the data transmission clock frequency. the simc1 register contains the relevant flags which are used to indicate the i 2 c communication status. another register , simt oc, is used to control the i 2 c time-out function and described in the corresponding section. ? name sim2 sim1 sim0 simdeb1 simdeb0 simen simic ? r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 0 0 0 0 bit 7~5 sim2~sim0 : sim operating mode control 000: spi master mode; spi clock is f /4 001: spi master mode; spi clock is f 010: spi master mode; spi clock is f /64 011: spi master mode; spi clock is f sub 100: spi master mode; spi clock is stm ccrp match frequency/2 101: spi slave mode 110: i 2 c slave mode 111: unused mode these bits setup the overall operatin g mode of the sim function. as well as selecting if the i 2 c or spi function, they are used to control the spi master/slav e selection and the spi master clock frequency . the spi clock is a function of the system clock but can a lso b e c hosen t o b e so urced f rom st m and f sub . i f t he spi sl ave mo de i s selected then the clock will be supplied by an external master device.
rev. 1.20 182 ?e???a?? 1?? 201? rev. 1.20 183 ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu bit 4 unimplemented, read as 0 bit 3~2 : i 2 c debounce t ime selection 00: no debounce 01: 2 system clock debounce 1x: 4 system clock debounce bit 1 : sim enable control 0: disable 1: enable the bi t is the overa ll on/of f control for the sim interface. when the simen bi t is cleared to zero to disable the sim interface, the sdi, sdo, sck and scs , or sda and scl lines will lose their spi or i 2 c function and the sim operating current will be reduced to a minim um value. when the bit is high the sim interface is enabled. if the sim is confgured to operate as an spi interface via the sim2~sim0 bits, the contents of the spi control registers will remain at the previous settings when the simen bit changes from low to high and should therefore be frst initialised by the application program. if the sim is confgured to operate as an i 2 c interface via the sim2~sim0 bits and the simen bit changes from low to high, the contents of the i 2 c control bits such as htx and txak will remain at the previous settings and should therefore be frst i nitialised by t he a pplication progra m whi le t he re levant i 2 c fags suc h a s hcf , haas, hbb, srw and rxak will be set to their default states. bit 0 : sim spi incomplete flag this bit is only us ed for the s pi mode of s im and is des cribed in the s pi regis ters section. ? name hc ? haas hbb htx txak srw iamwu rxak r/w r r r r/w r/w r r/w r por 1 0 0 0 0 0 0 1 bit 7 : i 2 c bus data transfer completion fag 0: data is being transferred 1: completion of an 8-bit data transfer the hcf flag is the data transfer flag. this flag will be zero when data is being transferred. upon completion of an 8-bit data transfer the flag will go high and an interrupt will be generated. bit 6 : i 2 c bus address match fag 0: not address match 1: address match the haas fa g i s t he a ddress m atch fa g. t his fa g i s use d t o de termine i f t he sl ave device address is the same as the master transmit address. if the addresses match then this bit will be high, if there is no match then the fag will be low. bit 5 : i 2 c bus busy fag 0: i 2 c bus is not busy 1: i 2 c bus is busy the hbb flag is the i 2 c busy flag. this flag will be 1 when the i 2 c bus is busy which will occur when a st art signal is detected. the fag will be set to 0 when the bus is free which will occur when a stop signal is detected. bit 4 : i 2 c slave device is transmitter or receiver selection 0: slave device is the receiver 1: slave device is the transmitter bit 3 : i 2 c bus transmit acknowledge fag 0: slave send acknowledge fag 1: slave do not send acknowledge fag
rev. 1.20 184 ? e ??? a ?? 1 ?? 201 ? rev. 1.20 185 ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu the txak bit is the transmit acknowledge fag. after the slave device receipt of 8 bits of data, this bit will be transmitted to the bus on the 9th clock from the slave device. the slave device must always set txak bit to 0 before further data is received. bit 2 : i 2 c slave read/write fag 0: slave device should be in receive mode 1: slave device should be in transmit mode the sr w f lag i s t he i 2 c sl ave r ead/write f lag. t his f lag d etermines wh ether the master device wishes to transmit or receive data from the i 2 c bus. when the transmitted address and slave address is match, that is when the haas fag is set high, the slave device will check the sr w fag to determine whether it should be in transmit mode or receive mode. if the sr w fag is high, the master is requesting to read data from the bus, so the slave device should be in transmit mode. when the sr w flag is zero, the master will write data to the bus, therefore the slave device should be in receive mode to read this data. bit 1 : i 2 c address match w ake-up control 0: disable 1: enable this bit should be set to 1 to enabl e the i 2 c address match wake up from the sleep or idle mode. if the iamwu bit has been set before entering either the sleep or idle mode to enable the i 2 c address match wake up, then this bit must be cleared by the application program after wake-up to ensure correction device operation. bit 0 : i 2 c bus receive acknowledge fag 0: slave receive acknowledge fag 1: slave does not receive acknowledge fag the r xak fl ag i s t he r eceiver a cknowledge f lag. w hen t he r xak f lag i s 0, i t means that a acknowledge signal has been received at the 9th clock, after 8 bits of data have been transmitted. when the slave device in the transmit mode, the slave device checks the rxak fag to determine if the master receiver wishes to receive the next byte. t he sl ave t ransmitter wi ll t herefore c ontinue se nding out da ta unt il t he rxak fag is 1. when this occurs, the slave transmitter will release the sda line to allow the master to send a stop signal to release the i 2 c bus. i 2 c bus communication communication on the i 2 c bus requires four separate steps, a st art signal, a slave device address transmission, a data transmission and finally a st op signal. when a st art signal is placed on the i 2 c bus, all devices on the bus will receive this signal and be notifed of the imminent arrival of data on the bus. the frst seven bits of the data will be the slave address with the frst bit being the msb. if the address of the slave device matches that of the transmitted address, the haas bit in the simc1 register will be set and an i 2 c interrupt will be generated. after entering the interrupt service routine, the slave device must frst check the condition of the haas and simt of bits to determine whether the interrupt source originates from an address match or from the completion of an 8-bit data t ransfer c ompletion o r i 2 c b us t ime-out o ccurrence. du ring a d ata t ransfer, n ote t hat a fter t he 7-bit slave address has been transmitted, the following bit, which is the 8th bit, is the read/write bit whose value will be placed in the sr w bit. this bit will be checked by the slave device to determine whether to go into transmit or recei ve mode. before any transfer of data to or from the i 2 c bus, the microcontroller must initialise the bus, the following are steps to achieve this: ? step 1 set the sim2~sim0 and sime n bits in the simc0 register to 1 10 and 1 respectively to enable the i 2 c bus. ? step 2 write the slave address of the devices to the i 2 c bus address register sima.
rev. 1.20 184 ?e???a?? 1?? 201? rev. 1.20 185 ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ? step 3 set the sime interrupt enable bit of the interrupt control register to enable the sim interrupt. set sim[2:0]=110 set simen w?ite slave add?ess to sima i 2 c b?s inte???pt=? clr sime poll sim? to decide when to go to i 2 c b?s isr no yes set sime wait fo? inte???pt goto main p?og?am goto main p?og?am sta?t i 2 c b?s initialisation ?low cha?t i 2 c b?s sta?t signal the st art signal can only be generated by the master device connec ted to the i 2 c bus and not by the slave device. this st art signal will be detected by all devices connected to the i 2 c bus. when detected, this indicates that the i 2 c bus is busy and therefore the hbb bit will be set. a st art condition occurs when a high to low transition on the sda line takes place when the scl line remains high. the t ransmission o f a st art si gnal b y t he m aster wi ll b e d etected b y a ll d evices o n t he i 2 c b us. to determine which slave device the master wishes to communicate with, the address of the slave device will be sent out immediately following the st art signal. all slave devices, after receiving this 7-bit address data, will compare it with their own 7-bit slave address. if the address sent out by the maste r matche s the internal address of the microcontroller slave device, then an internal i 2 c bus interrupt signal wil l be generat ed. the next bit fol lowing the address, which is the 8th bit, defnes the read/write status and will be saved to the sr w bit of the simc1 register . the slave device will then transmit an acknowledge bit, which is a low level, as the 9th bit. the slave device will also set the status fag haas when the addresses match. as a n i 2 c bus i nterrupt c an c ome fro m t hree sourc es, whe n t he progra m e nters t he i nterrupt subroutine, the haas and simt of bits should be examined to see whether the interrupt source has c ome from a m atching sl ave a ddress or from t he c ompletion of a dat a byt e t ransfer or t he i 2 c bus time-out occurrence. when a slave address is matched, the devices must be placed in either the transmit mode and then write data to the simd register , or in the receive mode where it must implement a dummy read from the simd register to release the scl line.
rev. 1.20 18 ? ? e ??? a ?? 1 ?? 201 ? rev. 1.20 18? ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu 2 c bs ra/ sal the sr w bit in the simc1 register defnes whether the master device wishes to read data from the i 2 c bus or write data to the i 2 c bus. the slave device should examine this bit to determine if it is to be a transmitter or a receiver . if the sr w fag is 1 then this indicates that the master device wishes to read data from the i 2 c bus, therefore the slave device must be setup to send data to the i 2 c bus as a transmitter . if the sr w fag is 0 then this indicates that the master wishes to send data to the i 2 c bus, therefore the slave device must be setup to read data from the i 2 c bus as a receiver. after the mas ter has trans mitted a calling addres s, any s lave device on the i 2 c bus , w hose own internal address matches the calling address, must generate an acknowledge signal. the acknowledge signal will inform the master that a slave device has accepted its calling address. if no acknowledge signal is received by the master then a st op signal must be transmitted by the master to end the communication. when the haas fag is high, the addresses have matched and the slave device must check the sr w fag to determine if it is to be a transmitter or a receiver . if the sr w fag is high, the slave device should be setup to be a transmitter so the htx bit in the simc1 register should be set to 1. if the sr w fag is low , then the microcontroller slave device should be setup as a receiver and the htx bit in the simc1 register should be set to 0. the transmitted data is 8-bit wide and is transmitted after the slave device has acknowledged receipt of its slave address. the order of serial bit transmission is the msb frst and the lsb last. after receipt of 8 bits of data, the receiver must transmit an acknowledge signal, level 0, before it can receive the next data byte. if the slave transmitter does not receive an acknowledge bit signal from the master receive r, then the slave transmitter will release the sda line to allow the master to send a st op signal to release the i 2 c bus. the corresponding data will be stored in the simd register . if setup as a transmitter , the slave device must frst write the data to be transmitted into the simd register. if setup as a receiver , the slave device must read the transmitted data from the simd register. when the slave receiver receives the data byte, it must generate an acknowledge bit, known as txak, on the 9th clock. the slave device, which is setup as a transmi tter will check the rxak bit in the simc1 register to determine if it is to send another data byte, if not then it will release the sda line and await the receipt of a stop signal from the master.
rev. 1.20 18? ?e???a?? 1?? 201? rev. 1.20 18 ? ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu sta?t scl sda scl sda 1 s=sta?t (1 ?it) sa=slave add?ess (? ?its) sr=srw ?it (1 ?it) m=slave device send acknowledge ?it (1 ?it) d=data (8 ?its) a=ack (rxak ?it fo? t?ansmitte?? txak ?it fo? ?eceive?? 1 ?it) p=stop (1 ?it) 0 ack slave add?ess srw stop data ack 1101010 10010100 s sa sr m d a d a s sa sr m d a d a p i 2 c comm?nication timing diag?am note: *when a slave address is matched, the device s must be placed in either the transmit mode and then write data to the simd register , or in the receive mode where it must implement a dummy read from the simd register to release the scl line. sta?t simto?=1? set simtoen clr simto? reti haas=1? htx=1? srw=1? read f?om simd to ?elease scl line reti rxak=1? w?ite data to simd to ?elease scl line clr htx clr txak d?mm? ?ead f?om simd to ?elease scl line reti reti set htx w?ite data to simd to ?elease scl line reti clr htx clr txak d?mm? ?ead f?om simd to ?elease scl line reti yes no no yes yes no yes no no yes i 2 c b?s isr ?low cha?t
rev. 1.20 188 ? e ??? a ?? 1 ?? 201 ? rev. 1.20 189 ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu 2 c t cl in order to reduce the problem of i 2 c lockup due to reception of erroneous clock sources, a time-out function is provided. if the clock source to the i 2 c is not received for a while, then the i 2 c circuitry and registers will be reset after a certain time-out period. the time-out counter starts counting on an i 2 c bus st art & address match condition, and is cleared by an scl falling edge. before the next scl falling edge arrives, if the time elapsed is greater than the tim e-out setup by the simt oc register, then a tim e-out condition will occur . the time-out function will stop when an i 2 c st op condition occurs. sta?t scl sda scl sda 1 0 ack slave add?ess srw stop 1101010 10010100 i 2 c time-o?t co?nte? sta?t i 2 c time-o?t co?nte? ?eset on scl negative t?ansition i 2 c time-o?t when an i 2 c time-out counter overfow occurs, the counter will stop and the simt oen bit will be c leared t o z ero a nd t he simt of bi t wi ll be se t hi gh t o i ndicate t hat a t ime-out c ondition ha s occurred. the time-out condition will also generate an interrupt which uses the i 2 c interrupt vector . when an i 2 c time-out occurs, the i 2 c internal circuitry will be reset and the registers will be reset into the following condition: simd ? sima ? simc0 no change simc1 reset to por condition i 2 c registe?s afte? time-o?t the simt of fag can be cleared by the application program. there are 64 time-out periods which can be selected using simt os bit feld in the simt oc register . the time-out time is given by the formula: ((1~64) 32) / f sub . this gives a time-out period which ranges from about 1ms to 64ms. ? name simtoen simto ? simtos5 simtos4 simtos3 simtos2 simtos1 simtos0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 : sim i 2 c t ime-out control 0: disable 1: enable bit 6 : sim i 2 c t ime-out fag 0: no time-out occurred 1: t ime-out occurred
rev. 1.20 188 ?e???a?? 1?? 201? rev. 1.20 189 ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu bit 5~0 : sim i 2 c t ime-out period selection i 2 c time-out clock source is f sub /32. i 2 c time-out time is equal to (simtos[5:0]+1) (32/f sub ). the devices contain an independent spi function. it is important not to confuse this independent spi function with the additional one contained within the combined sim function, which is described in another section of this datasheet. this independent spi function will carry the name spia to distinguish it from the other one in the sim. the spia interface is often used to communicate with external peripheral devices such as sensors, flash or eeprom memory devices etc. originally developed by motorola, the four line spia interface is a synchronous serial data interface that has a relatively simple communication protocol simplifying the programming requirements when communicating with external hardware devices. the communication is full duplex and operates as a slave/master type, where the devices can be either master or slave. although the spia interface specifcation can control multiple slave devices from a single master , however the devices provide only one scsa pin. if the master needs to control multiple slave devices from a single master, the master can use i/o pins to select the slave devices. the spia interfac e is a full duplex synchronous serial data link. it is a four line interface with pin names sdia, sdoa, scka and scsa . pins sdia and sdoa are the serial data input and serial data output lines, the scka pin is the serial clock line and scsa is the slave select line. as the spia inte rface pins are pin-shared with normal i/o pins, the spia interface must frst be enabled by confguring the corresponding selec tion bits in the pin-shared function selection registers. the spia can be disabled or enabled using the spiaen bit in the spiac0 register . communication between devices connected to the spia interface is carried out in a slave/master mode with all data transfer initiations being implemented by the master . the master also controls the clock signal. as the devices only contain a single scsa pin only one slave device can be utilized. the scsa pin is controlled by the application program, set the sacsen bit to 1 to enable the scsa pin function and clear the sacsen bit to 0 to place the scsa pin into a foating state. scka spia maste? sdoa sdia scsa scka spia slave sdoa sdia scsa spia maste?/slave connection the spia function in the devices offers the following features: ? full duplex synchronous data transfer ? both master and slave modes ? lsb frst or msb frst data transmission modes ? transmission complete fag ? rising or falling active clock edge
rev. 1.20 190 ? e ??? a ?? 1 ?? 201 ? rev. 1.20 191 ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu the status of the spia interface pins is determined by a number of factors such as whether the devices are in the master or slave mode and upon the condition of certain control bits such as sacsen and spiaen. spiad tx/rx shift registe? sdia pin clock edge/pola?it? cont?ol sackeg sackpolb clock so??ce select f sys f sub ptm0 ccrp match f?eq?enc?/2 scka pin sacsen b?s? stat?s sdoa pin sawcol satr? scsa pin data b?s spiaic? spia block diag?am spia registe?s there are three internal registers which control the overall operation of the spia interface. these are the spiad data register and two registers, spiac0 and spiac1. spiac0 saspi2 saspi1 saspi0 spiaen spiaic ? spiac1 sackpolb sackeg samls sacsen sawcol satr ? spiad d ? d ? d5 d4 d3 d2 d1 d0 spia registe?s list spia data registe? the spiad re gister i s use d t o st ore t he da ta be ing t ransmitted a nd re ceived. be fore t he de vices write data to the spia bus, the actual data to be transmitted must be placed in the spiad register . after the data is received from the spia bus, the devices can read it from the spiad register . any transmission or reception of data from the spia bus must be made via the spiad register. ? name d ? d ? d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por x x x x x x x x x: ? nknown bit 7~0 d7~d0 : spia data register bit 7 ~ bit 0
rev. 1.20 190 ?e???a?? 1?? 201? rev. 1.20 191 ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu s cl rss there are also two control registers for the spia interface, spiac0 and spiac1. the spiac0 register is used to control the enable/disable function and to set the data transmission clock frequency. the spiac1 register is used for other control functions such as lsb/msb selection, write collision fag etc. ? name saspi2 saspi1 saspi0 spiaen spiaic ? r/w r/w r/w r/w r/w r/w por 1 1 1 0 0 bit 7~5 saspi2~saspi0 : spia operating mode control 000: spia master mode; spia clock is f /4 001: spia master mode; spia clock is f 010: spia master mode; spia clock is f /64 011: spia master mode; spia clock is f sub 100: spia master mode; spia clock is ptm0 ccrp match frequency/2 101: spia slave mode 110: unimplemented 111: unimplemented these bits are used to control the spia master/slave selection and the sp ia master clock f requency. t he spi a c lock i s a f unction o f t he sy stem c lock b ut c an a lso b e chosen to be sourced from ptm0 and f sub . if the spia slave mode is selected then the clock will be supplied by an external master device. bit 4~2 unimplemented, read as 0 bit 1 spiaen : spia enable control 0: disable 1: enable the bit is the overall on/of f control for the spia interface. when the spiaen bit is c leared t o z ero t o di sable t he spia i nterface, t he sdia, sdoa, scka a nd scsa lines will lose thei r spia function and the spia operating current will be reduced to a minimum value. when the bit is high the spia interface is enabled. bit 0 spiaicf : spia incomplete flag 0: spia incomplete condition is not occurred 1: spia incomplete condition is occured this bit is only available when the spia is configured to operate in an spia slave mode. if the spia operates in the slave mode with the spiaen and sacsen bits both being set to 1 but the scsa line is pulled high by the external master device before the spia data transfer is completely fnished, the spiaicf bit will be set to 1 together with the sa trf bit. when this condition occurs, the corresponding interrupt will occur if the interrupt function is enabled. however , the sa trf bit will not be set to 1 if the spiaicf bit is set to 1 by software application program.
rev. 1.20 192 ? e ??? a ?? 1 ?? 201 ? rev. 1.20 193 ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ? name sackpolb sackeg samls sacsen sawcol satr ? r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7~6 unimplemented, read as 0 bit 5 sackpolb : spia clock line base condition selection 0: the scka line will be high when the clock is inactive 1: the scka line will be low when the clock is inactive the sackpolb bit determines the base condition of the clock line, if the bit is high, then the scka line will be low when the clock is inactive. when the sackpolb bit is low, then the scka line will be high when the clock is inactive. bit 4 sackeg : spia scka clock active edge type selection sackpolb=0 0: scka has high base level with data capture on scka rising edge 1: scka has high base level with data capture on scka falling edge sackpolb=1 0: scka has low base level with data capture on scka falling edge 1: scka has low base level with data capture on scka rising edge the sackeg and sackpolb bits are used to setup the way that the clock signal outputs and inputs data on the spia bus. these two bits must be confgured before a data transfer is executed otherwise an erroneous clock edge may be generated. the sackpolb b it d etermines t he b ase c ondition o f t he c lock l ine, i f t he b it i s h igh, then t he scka l ine wi ll be l ow whe n t he c lock i s i nactive. w hen t he sackpol b bit is low , then the scka line will be high when the clock is inactive. the sackeg bit determines active clock edge type which depends upon the condition of the sackpolb bit. bit 3 samls : spia data shift order 0: lsb frst 1: msb frst this is the data shift select bit and is used to select how the data is transferred, either msb or lsb frst. setting the bit high will select msb frst and low for lsb frst. bit 2 sacsen : spia scsa pin control 0: disable 1: enable the sacsen bit is used as an enable/disable for the scsa pin. if this bit is low , then the scsa pin will be disabled and placed into a foating condition. if the bit is high the scsa pin will be enabled and used as a select pin. bit 1 sawcol : spia write collision fag 0: no collision 1: collision the sa wcol fag is used to detec t if a data collision has occurred. if this bit is high it means that data has been attempte d to be written to the spiad register during a data transfer operation . this writing operation will be ignored if data is being transferred. the bit can be cleared by the application program. bit 0 satrf : spia t ransmit/receive complete fag 0: spia data is being transferred 1: spia data transmission is completed the sa trf bit is the t ransmit/receive com plete flag and is set 1 automa tically when an spia data transmission is completed, but must set to zero by the application program. it can be used to generate an interrupt.
rev. 1.20 192 ?e???a?? 1?? 201? rev. 1.20 193 ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu s ca after the spia interface is enabled by setting the spiaen bit high, then in the master mode, when data is written to the spiad register , transmission/reception will begin simultaneously . when the data t ransfer i s c omplete, t he sa trf fag wi ll be se t a utomatically, but m ust be c leared usi ng t he application program. in the slave mode, when the clock signal from the master has been received, any data in the spiad register will be transmitted and any data on the sdia pin will be shifted into the spiad register. the master should output an scsa signal to enable the slave device before a clock signal is provided. the slave data to be transferred should be well prepared at the appropriate moment relative to the scsa si gnal d epending u pon t he c onfigurations o f t he sac kpolb b it a nd sac keg b it. t he accompanying timing diagram shows the relationship between the slave data and scsa signal for various confgurations of the sackpolb and sackeg bits. the spia wil l continue to funct ion in spec ial idle modes if the cl ock source used by the spia interface is still active. scka (sackpolb=1? sackeg=0) scka (sackpolb=0? sackeg=0) scka (sackpolb=1? sackeg=1) scka (sackpolb=0? sackeg=1) scsa sdoa (sackeg=0) sdoa (sackeg=1) sdia data capt??e w?ite to spiad spiaen? sacsen=1 spiaen=1? sacsen=0 (exte?nal p?ll-high) d?/d0 d?/d1 d5/d2 d4/d3 d3/d4 d2/d5 d1/d? d0/d? d?/d0 d?/d1 d5/d2 d4/d3 d3/d4 d2/d5 d1/d? d0/d? spia maste? mode timing scka (sackpolb=1) scka (sackpolb=0) scsa sdoa sdia data capt??e w?ite to spiad (sdoa does not change ?ntil fi?st scka edge) d?/d0 d?/d1 d5/d2 d4/d3 d3/d4 d2/d5 d1/d? d0/d? spia slave mode timing C sackeg=0
rev. 1.20 194 ? e ??? a ?? 1 ?? 201 ? rev. 1.20 195 ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu scka (sackpolb=1) scka (sackpolb=0) scsa sdoa sdia data capt??e d?/d0 d?/d1 d5/d2 d4/d3 d3/d4 d2/d5 d1/d? d0/d? w?ite to spiad (sdoa changes as soon as w?iting oc c??s; sdoa is floating if scsa=1) note: ?o? spia slave mode? if spiaen=1 and sacsen=0? spia is alwa?s ena?led and igno?es the scsa level. spia slave mode timing C sackeg=1 clea? sawcol w?ite data into spiad sawcol=1? t?ansmission completed? (satr?=1?) read data f?om spiad clea? satr? end t?ansfe? finished? a spia t?ansfe? maste? o? slave ? spiaen=1 config??e sackpolb? sackeg? sacsen and samls a saspi[2:0]=000? 001? 010? 011 o? 100 saspi[2:0]=101 maste? slave y y n n n y spia t?ansfe? cont?ol ?lowcha?t
rev. 1.20 194 ?e???a?? 1?? 201? rev. 1.20 195 ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu s bs eal/dsal to enable the spia bus, set sacsen=1 and scsa =0, then wait for data to be written into the spiad (txrx buf fer) register . for the master mode, after data has been written to the spiad (txrx buffer) register, then transmission or reception will start automatically. when all the data has been transferred the sa trf bit should be set. for the slave mode, when clock pulses are received on scka, data in the txrx buffer will be shifted out or data on sdia will be shifted in. when the spia bus is diabled, scka, sdia, sdoa, scsa will become i/o pins or the other functions by confguring the corresponding pin-shared control bits. all communication is carried out using the 4-line interface for either master or slave mode. the sacsen bit in the spiac1 register controls the overall function of the spia interface. setting this bit high will enable the spia interface by allowing the scsa line to be active, which can then be used to control the spia interface. if the sacsen bit is low , the spia interface will be disabled and the scsa line will be in a foating condition and can therefore not be used for control of the spia interface. if the sacsen bit and the spiaen bit in the spiac0 register are set high, this will place the sdia line in a foating condition and the sdoa line high. if in master mode the scka line will be e ither h igh o r l ow d epending u pon t he c lock p olarity se lection b it sac kpolb i n t he spi ac1 register. if in slave mode the scka line will be in a floating condition. if spiaen is low then the bus will be disabled and scsa , sdia, sdoa and scka will all become i/o pins or the other functions. in the master mode the master will always generate the clock signal. the clock and data transmission will be initiated after data has been written into the spiad register . in the slave mode, the clock signal will be received from an external master device for both data transmission and reception. the following sequences show the order to be followed for data transfer in both master and slave mode. master mode: ? step 1 select the clock source and master mode using the saspi2~saspi0 bits in the spiac0 control register. ? step 2 setup the sacsen bit and setup the samls bit to choose if the data is msb or lsb frst, this must be same as the slave device. ? step 3 setup the spiaen bit in the spiac0 control register to enable the spia interface. ? step 4 for write operations: write the data to the spiad register , which will actually place the data into the txrx buffer. then use the scka and scsa lines to output the data. after this go to step 5. for read operations: the data transferred in on the sdia line will be stored in the txrx buf fer until all the data has been received at which point it will be latched into the spiad register. ? step 5 check the sa wcol bit if set high then a collision error has occurred so return to step 4. if equal to zero then go to the following step. ? step 6 check the satrf bit or wait for a spia serial bus interrupt. ? step 7 read data from the spiad register.
rev. 1.20 19 ? ? e ??? a ?? 1 ?? 201 ? rev. 1.20 19? ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ? step 8 clear satrf. ? step 9 go to step 4. ? step 1 select the spia slave mode using the saspi2~saspi0 bits in the spiac0 control register. ? step 2 setup the sacsen bit and setup the samls bit to choose if the data is msb or lsb frst, this setting must be the same with the master device. ? step 3 setup the spiaen bit in the spiac0 control register to enable the spia interface. ? step 4 for write operations: write the data to the spiad register , which will actually place the data into the txrx buffer. then wait for the master clock scka and scsa signal. after this, go to step 5. for read operations: the data transferred in on the sdia line will be stored in the txrx buf fer until all the data has been received at which point it will be latched into the spiad register. ? step 5 check the sa wcol bit if set high then a collision error has occurred so return to step 4. if equal to zero then go to the following step. ? step 6 check the satrf bit or wait for a spia serial bus interrupt. ? step 7 read data from the spiad register. ? step 8 clear satrf. ? step 9 go to step 4. error detection the sa wcol bit in the spiac1 register is provided to indicate errors during data transfer . the bit is set by the spia serial interface but must be cleared by the applicatio n program. this bit indicates a data collision has occurred which happens if a write to the spiad register takes place during a data transfer operation and will prevent the write operation from continuing.
rev. 1.20 19? ?e???a?? 1?? 201? rev. 1.20 19 ? ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu urt a the devices conta in an integrated full-duplex asynchronous serial communications uar t interface that enables communication with external devices that contain a serial interface. the uart function has many features and can transmit and receive data serially by transferring a frame of data with eight or nine data bits per transmission as well as being able to detect errors when the data is overwritten or incorrectly framed. the uar t function possesses its own internal interrupt which can be used to indicate when a reception occurs or when a transmission terminates. the integrated uart function contains the following features: ? full-duplex, asynchronous communication ? 8 or 9 bits character length ? even, odd or no parity options ? one or two stop bits ? baud rate generator with 8-bit prescaler ? parity, framing, noise and overrun error detection ? support for interrupt on address detect (last character bit=1) ? separately enabled transmitter and receiver ? 2-byte deep fifo receive data buffer ? rx pin wake-up function ? transmit and receive interrupts ? interrupts can be initialized by the following conditions: ? transmitter empty ? transmitter idle ? receiver full ? receiver overrun ? address mode detect msb lsb t?ansmitte? shift registe? (tsr) msb lsb receive? shift registe? (rsr) tx pin rx pin ba?d rate gene?ato? txr_rxr registe? txr_rxr registe? data to ?e t?ansmitted data ?eceived b?ffe? f h mcu data b?s uart data t?ansfe? block diag?am
rev. 1.20 198 ? e ??? a ?? 1 ?? 201 ? rev. 1.20 199 ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu urt eal s to communicate with an external serial interface, the internal uar t has two external pins known as tx and rx. the tx and rx pins are the uar t transmitter and receiver pins respectively . the tx and rx pin function should frst be selected by the corresponding pin-shared function selection register before the uar t function is used. along with the uar ten bit, the txen and rxen bits, if set, will setup these pins to their respective tx output and rx input conditions and disable any pull-high resistor option which may exist on the tx and rx pins. when the tx or rx pin function is disabled by clea ring the uar ten, txen or rxen bit, the tx or rx pin will be set to a foating state. at this time whether the inter nal pull-high resistor is connected to the tx or rx pin or not is determined by the corresponding i/o pull-high function control bit. the above block diagram shows the overall data transfer structure arrangement for the uar t. the actual d ata t o b e t ransmitted f rom t he mc u i s f irst t ransferred t o t he t xr_rxr r egister b y t he application program. the data will then be transferred to the t ransmit shift register from where it will be shifted out, lsb frst, onto the tx pin at a rate controlled by the baud rate generator . only the txr_rxr register is mapped onto the mcu data memory , the t ransmit shift register is not mapped and is therefore inaccessible to the application program. data to be received by the uar t is accepted on the external rx pin, from where it is shifted in, lsb frst, to the receiver shift register at a rate controlled by the baud rate generator . when the shift register is full, the data will then be transferred from the shift register to the internal txr_rxr register, wh ere i t i s b uffered a nd c an b e m anipulated b y t he a pplication p rogram. on ly t he t xr_ rxr register is mapped onto the mcu data memory, the receiver shift register is not mapped and is therefore inaccessible to the application program. it should be noted that the actual register for data transmission and reception only exists as a single shared register, txr_rxr, in the data memory. there are fve control registers associated with the uar t function. the usr, ucr1 and ucr2 registers c ontrol t he o verall f unction o f t he uar t, wh ile t he b rg r egister c ontrols t he b aud r ate. the actua l data to be transmitted and received on the serial interface is managed through the txr_ rxr data register. usr perr n ? ? err oerr ridle rxi ? tidle txi ? ucr1 uarten bno pren prt stops txbrk rx8 tx8 ucr2 txen rxen brgh adden wake rie tiie teie txr_ rxr d ? d ? d5 d4 d3 d2 d1 d0 brg d ? d ? d5 d4 d3 d2 d1 d0 uart registe?s list
rev. 1.20 198 ?e???a?? 1?? 201? rev. 1.20 199 ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu usr s the usr register is the status register for the uart, which can be read by the program to determine the present status of the uar t. all fags within the usr register are read only . further explanation on each of the fags is given below: name perr n ? ? err oerr ridle rxi ? tidle txi ? r/w r r r r r r r r por 0 0 0 0 1 0 1 1 bit 7 perr : parity error fag 0: no parity error is detected 1: parity error is detected the perr fag is the parity error fag. when this read only fag is "0", it indicates a parity error has not been detected. when the fag is "1", it indicates that the parity of the received word is incorrect. this error fag is applicable only if parity mode (odd or even) is selected. the fag can also be cleared by a software sequence which involves a read to the status register usr followed by an access to the txr_rxr data register. bit 6 nf : noise fag 0: no noise is detected 1: noise is detected the nf fla g is the noise fla g. whe n thi s read only fla g is "0", it indi cates no noise condition. when the fag is "1", it indicates that the uar t has detected noise on the receiver input. the nf fag is set during the same cycle as the rxif fag but will not be set in the case of as overrun. the n f fag can be cleared by a softw are sequence which will involve a read to the status register usr followed by an access to the txr_rxr data register. bit 5 ferr : framing error fag 0: no framing error is detected 1: framing error is detected the ferr fag is the framing error fag. when this read only fag is "0", it indicates that there is no framing error . when the fag is " 1", it indicates that a framing error has been detected for the current character . the fag can also be cleared by a software sequence which will involve a read to the status register usr followed by an access to the txr_rxr data register. bit 4 oerr : overrun error fag 0: no overrun error is detected 1: overrun error is detected the oerr fag is the overrun error fag which indicates when the rece iver buf fer has overfowed. when this read only fag is "0", it indicates that there is no overrun error . when the fag is "1", it indicates that an overrun error occurs which will inhibit further transfers to the tx r_rxr receive data regis ter. the flag is cleared by a softw are sequence, which is a read to the status register usr followed by an access to the txr_rxr data register. bit 3 ridle : receiver status 0: data reception is in progress (data being received) 1: no data reception is in progress (receiver is idle) the ridle fag is the receiver status fag. when this read only fag is "0", it indicates that the receiver is between the init ial detection of the start bit and the completion of the stop bit. when the fag is "1", it indicates that the receiver is idle. between the completion of the stop bit and the detection of the next start bit, the ridle bit is "1" indicating that the uart receiver is idle and the rx pin stays in logic high condition.
rev. 1.20 200 ? e ??? a ?? 1 ?? 201 ? rev. 1.20 201 ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu bit 2 : receive txr_rxr data register status 0: txr_rxr data register is empty 1: txr_rxr data register has available data the rxif fag is the receive data register status fag. when this read only fag is "0", it i ndicates t hat t he t xr_rxr re ad da ta re gister i s e mpty. w hen t he fl ag i s "1 ", i t indicates that the txr_rxr read data register contains new data. when the contents of the shift registe r are transferred to the txr_rxr register , an interru pt is generated if rie=1 in the ucr2 register . if one or more errors are detected in the received word, the appropriate receive-related fags nf , ferr, and/or perr are set within the same clock c ycle. t he rxif fa g i s c leared whe n t he usr re gister i s re ad wi th rxif se t, followed by a read from the txr_rxr register , and if the txr_rxr register has no data available. bit 1 : t ransmission idle 0: data transmission is in progress (data being transmitted) 1: no data transmission is in progress (transmitter is idle) the tidle flag is known as the transmission complete flag. when this read only flag is " 0", it indicates that a transmiss ion is in progress. this flag will be set high when the txif fag is "1" and when there is no transmit data or break character being transmitted. when tidle is equal to "1", the tx pin becomes idle with the pin state in logic high condition. the tidle fag is cleared by reading the usr register with tidle set and then writing to the txr_rxr register . the fag is not generated when a data character or a break is queued and ready to be sent. bit 0 : t ransmit txr_rxr data register status 0: character is not transferred to the transmit shift register 1: character has transferred to the transmit shift register (txr_rxr data register is empty) the txif fag is the transmit data register empty fag. when this read only fag is "0", it indicat es that the character is not transferred to the transmitter shift register . when the fag is "1", it indicates that the transmitter shift register has received a character from the txr_rxr data register . the txif flag is cleared by reading the uar t status register (usr) with txif set and then writing to the txr_rxr data register . note that when the txen bit is set, the txif fag bit will also be set since the transmit data register is not yet full. ucr1 register the ucr1 register together with the ucr2 register are the two uart control registers that are used to set the various options for the uar t function, such as overall on/of f control, parity control, data transfer bit length etc. further explanation on each of the bits is given below: bit 7 6 5 4 3 2 1 0 name uarten bno pren prt stops txbrk rx8 tx8 r/w r/w r/w r/w r/w r/w r/w r w por 0 0 0 0 0 0 x 0 x: ? nknown bit 7 : uart function enable control 0: disable uart. tx and rx pins are in a foating state 1: enable uart. tx and rx pins function as uart pins the uar ten b it i s t he uar t e nable b it. w hen t his b it i s e qual t o "0 ", t he uar t wi ll be disabled and the rx pin as well as the tx pin will be set in a foating state. when the bit is equal to "1", the uart will be enabled and the tx and rx pins will function as defned by the txen and rxen enable control bits. when the uar t is disabled, it will empty the buf fer so any character remaining in the buf fer will be discarded. in addition, the value of the baud rate counter will be reset. if the uar t is disabled, all error and status fags will be reset. also the txen, rxen, txbrk, rxif , oerr, ferr, perr and nf bits will be cle ared, while the
rev. 1.20 200 ?e???a?? 1?? 201? rev. 1.20 201 ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu tidle, txif and ridle bits will be set. other control bits in ucr1, ucr2 and brg registers will remain unaf fected. if the uar t is active and the uar ten bit is cleared, all pending transmis sions and receptions will be terminated and the module will be reset as defined above. when the uar t is re-enabled, it will restart in the same confguration. bit 6 : number of data transfer bits selection 0: 8-bit data transfer 1: 9-bit data transfer this bit is used to select the data length format, which can have a choice of either 8-bit or 9-bit format. when this bit is equal to "1", a 9-bit data length format will be selected. if the bit is equal to "0", then an 8-bit data length format will be selected. if 9-bit data length format is selected, then bits rx8 and tx8 will be used to store the 9th bit of the received and transmitted data respectively. bit 5 : parity function enable control 0: parity function is disabled 1: parity function is enabled this is the parity enable bit. when this bit is equal to "1", the parity function will be enabled. if the bit is equal to "0", then the parity function will be disabled. replace the most signifcant bit position with a parity bit. bit 4 : parity type selection bit 0: even parity for parity generator 1: odd parity for parity generator this bit is the parity type selection bit. when this bit is equal to "1", odd parity type will be selected. if the bit is equal to "0", then even parity type will be selected. bit 3 : number of stop bits selection 0: one stop bit format is used 1: t wo stop bits format is used this bit determines if one or two stop bits are to be used. when this bit is equal to "1", two stop bits are used. if this bit is equal to "0", then only one stop bit is used. bit 2 : t ransmit break character 0: no break character is transmitted 1: break characters transmit the txbrk bit is the t ransmit break character bit. when this bit is "0", there are no break characte rs and the tx pin operates normally . when the bit is "1", there are transmit break characters and the transmitter will send logic zeros. when this bit is equal to "1", after the buf fered data has been transmitted, the transmitter output is held low for a minimum of a 13-bit length and until the txbrk bit is reset. bit 1 : receive data bit 8 for 9-bit data transfer format (read only) this bit is only used if 9-bit data transfers are used, in which case this bit location will store the 9th bit of the received data known as rx8. the bno bit is used to determine whether data transfers are in 8-bit or 9-bit format. bit 0 : t ransmit data bit 8 for 9-bit data transfer format (write only) this bit is only us ed if 9-bit data transfers are us ed, in w hich cas e this bit location will st ore t he 9 th b it o f t he t ransmitted d ata k nown a s t x8. t he b no b it i s u sed t o determine whether data transfers are in 8-bit or 9-bit format.
rev. 1.20 202 ? e ??? a ?? 1 ?? 201 ? rev. 1.20 203 ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ucr2 s the ucr2 register is the second of the two uart control registers and serves several purposes. one of its main functio ns is to control the basic enable/disable operation of the uar t t ransmitter and receiver as well as enabling the various uar t interrupt sources. the register also serves to control the baud rate speed, receiver wake-up enable and the address detect enable. further explanation on each of the bits is given below: name txen rxen brgh adden wake rie tiie teie r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 txen : uart t ransmitter enabled control 0: uart transmitter is disabled 1: uart transmitter is enabled the bit named txen is the t ransmitter enable bit. when this bit is equal to "0", the transmitter will be disabled with any pending data transmissions being aborted. in addition the buf fers will be reset. in this situation the tx pin will be set in a foating state. if the txen bit is equal to "1" and the uar ten bit is also equal to "1", the transmitter will be enabled and the tx pin will be controlled by the uar t. clearing the txen bit during a transmission will cause the data transmission to be aborted and will reset the transmitter . if this situation occurs, the tx pin will be set in a foating state. bit 6 rxen : uart receiver enabled control 0: uart receiver is disabled 1: uart receiver is enabled the bi t na med rxe n i s t he re ceiver e nable bi t. w hen t his bi t i s e qual t o "0", t he receiver will be disabled with any pending data receptions being aborted. in addition the receive buf fers will be reset. in this situation the rx pin will be set in a foating state. if the rxen bit is equal to "1" and the uar ten bit is also equal to "1", the receiver will be enabled and the rx pin will be controlled by the uar t. clearing the rxen bit during a reception will cause the data reception to be aborted and will reset the receiver. if this situation occurs, the rx pin will be set in a foating state. bit 5 brgh : baud rate speed selection 0: low speed baud rate 1: high speed baud rate the bit named brgh selects the high or low speed mode of the baud rate generator . this bit, together with the value placed in the baud rate register brg, controls the baud rate of the uar t. if this bit is equal to "1", the high speed mode is selected. if the bit is equal to "0", the low speed mode is selected. bit 4 adden : address detect function enable control 0: address detect function is disabled 1: address detect function is enabled the bi t na med adde n i s t he a ddress de tect fu nction e nable c ontrol bi t. w hen t his bit i s e qual t o "1", t he a ddress de tect func tion i s e nabled. w hen i t oc curs, i f t he 8t h bit, which corresponds to rx7 if bno=0 or the 9th bit, which corresponds to rx8 if bno=1, ha s a va lue of "1 ", t hen t he re ceived word wi ll be i dentifed a s a n a ddress, rather than data. if the corresponding interrupt is enabled, an interrupt request will be generated each time the received word has the address bit set, which is the 8th or 9th bit d epending o n t he v alue o f b no. i f t he a ddress b it k nown a s t he 8 th o r 9 th b it o f t he received word is "0" with the address detect function being enabled, an interrupt will not be generated and the received data will be discarded.
rev. 1.20 202 ?e???a?? 1?? 201? rev. 1.20 203 ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu bit 3 : rx pin wake-up uart function enable control 0: rx pin wake-up uart function is disabled 1: rx pin wake-up uart function is enabled this bit is used to control the wake-up uar t function when a falling edge on the rx pin occurs. note that this bit is only available when the uar t clock (f h ) is switched off. there will be no rx pin wake-up uar t function if the uar t clock (f h ) exists. if t he w ake b it i s se t t o 1 a s t he uar t c lock ( f h ) i s swi tched o ff, a uar t wa ke- up request will be initiated when a falling edge on the rx pin occurs. when this request happens and the corresponding interrupt is enabled, an rx pin wake-up uar t interrupt will be generated to inform the mcu to wake up the uar t function by switching on the uar t clock (f h ) via the application program. otherwise, the uar t function cannot resume even if there is a falling edge on the rx pin when the w ake bit is cleared to 0. bit 2 : receiver interrupt enable control 0: receiver related interrupt is disabled 1: receiver related interrupt is enabled this bit enables or disables the rece iver interrupt. if this bit is equal to "1" and when the receiver overrun fag oerr or receive data available fag rxif is set, the uar t interrupt request fag will be set. if this bit is equal to "0", the uar t interrupt request fag will not be infuenced by the condition of the oerr or rxif fags. bit 1 : t ransmitter idle interrupt enable control 0: t ransmitter idle interrupt is disabled 1: t ransmitter idle interrupt is enabled this bit enables or disables the transmitter idle interrupt. if this bit is equal to "1" and when t he t ransmitter i dle fa g t idle i s se t, due t o a t ransmitter i dle c ondition, t he uart interrupt request fag will be set. if this bit is equal to "0", the uar t interrupt request fag will not be infuenced by the condition of the tidle fag. bit 0 : t ransmitter empty interrupt enable control 0: t ransmitter empty interrupt is disabled 1: t ransmitter empty interrupt is enabled this bit enables or disables the transmitter empty interrupt. if this bit is equal to "1" and when the transmitter empty fag txif is set, due to a transmitter empty condition, the uar t i nterrupt re quest fl ag wi ll be se t. if t his bi t i s e qual t o "0", t he uar t interrupt request fag will not be infuenced by the condition of the txif fag.
rev. 1.20 204 ? e ??? a ?? 1 ?? 201 ? rev. 1.20 205 ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu trrr s b 7 6 5 4 2 name d ? d ? d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por x x x x x x x x x ? nknown bit 7~0 d7~d0 : uart t ransmit/receive data bit 7 ~ bit 0 name d ? d ? d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por x x x x x x x x x ? nknown bit 7~0 d7~d0 : baud rate values by programming the brgh bit in ucr2 register which allows selection of the related formula described above and programming the required value in the brg register, the required baud rate can be setup. note: baud rate=f / [64 (n+1)] if brgh=0. baud rate=f / [16 (n+1)] if brgh=1. to setup the speed of the serial data communication, the uar t function contains its own dedicated baud ra te ge nerator. t he ba ud ra te i s c ontrolled by i ts own i nternal fre e runni ng 8-bi t t imer, t he period of which is determined by two factors. the frst of these is the value placed in the baud rate register brg and the second is the value of the brgh bit with the control register ucr2. the brgh bit decides if the baud rate generator is to be used in a high speed mode or low speed mode, which in turn determines the formula that is used to calculate the baud rate. the value n in the brg register which is used in the following baud rate calculation formula determines the division factor . note that n is the decimal value placed in the brg register and has a range of between 0 and 255. ba ? d rate (br) f h / [ ? 4 (n+1)] f h / [1 ? (n+1)] by programming the brgh bit which allows selection of the related formula and programming the required value in the brg register , the required baud rate can be setup. note that because the actual baud rate is determ ined using a discrete value, n, placed in the brg register , there will be an error associated between the actual and requested value. the following example shows how the brg register value n and the error value can be calculated. for a clock frequency of 4mhz, and with brgh cleared to zero determine the brg register value n, the actual baud rate and the error value for a desired baud rate of 4800. from the above table the desired baud rate br = f / [64 (n+1)] re-arranging this equation gives n = [f / (br64)] - 1 giving a value for n = [4000000 / (480064)] - 1 = 12.0208 to obtain the closest value, a decim al value of 12 should be placed into the brg register . this gives an actual or calculated baud rate value of br = 4000000 / [64 (12+1)] = 4808 therefore the error is equal to (4808 - 4800) / 4800 = 0.16%
rev. 1.20 204 ?e???a?? 1?? 201? rev. 1.20 205 ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu urt s a cl for data transfer , the uar t functio n utilizes a non-return-to-zero, more commonly known as nrz, format. this is composed of one start bit, eight or nine data bits, and one or two stop bits. parity is supported by the uar t hardware, and can be setup to be even, odd or no parity . for the most common data format, 8 data bits along with no parity and one stop bit, denoted as 8, n, 1, is used as the default setti ng, which is the setting at power -on. the number of data bits and stop bits, along with t he pa rity, a re se tup by pr ogramming t he c orresponding b no, pr t, pr en, a nd st ops b its in the ucr1 register . the baud rate used to transmit and receive data is setup using the internal 8-bit baud rate generator , while the data is transmitted and received lsb frst. although the uar t transmitter and receiver are functionally independent, they both use the same data format and baud rate. in all cases stop bits will be used for data transmission. the basic on/of f function of the internal uar t function is controlled using the uar ten bit in the ucr1 register . if the uar ten, txen and rxen bits are set, then these two uar t pins will act as n ormal t x o utput p in a nd r x i nput p in r espectively. i f n o d ata i s b eing t ransmitted o n t he t x pin, then it will default to a logic high value. clearing the uar ten bit will disable the tx and rx pins and allow these two pins to be used as normal i/o or other pin-shared functional pins by confguring the corresponding pin-shared control bits. when the uar t function is disabled the buf fer will be reset to an empty condition, at the same time discarding any remaining residual data. disabling the uar t will also reset the error and status fags with bits txen, rx en, txbrk, rx if, oerr, ferr, perr and nf being cleared while bits tidle, txif and ridle will be set. the remaining control bits in the ucr1, ucr2 and brg registers will remain unaffected. if the uarten bit in the ucr1 register is cleared while the uart is active, then all pending transmissions and receptions will be immediately suspended and the uart will be reset to a condition as defned above. if the uar t is then subsequently re-enabled, it will restart again in the same confguration. the f ormat o f t he d ata t o b e t ransferred i s c omposed o f v arious f actors su ch a s d ata b it l ength, parity on/of f, parity type, address bits and the number of stop bits. these factors are determined by the setup of various bits within the ucr1 register . the bno bit controls the number of data bits which can be set to either 8 or 9, the pr t bit controls the choice of odd or even parity , the pren bit controls the parity on/of f function and the st ops bit decides whether one or two stop bits are to be used. the following table shows various formats for data transmission. the address bit, which is the msb of the data byte, identife s the frame as an address character or data if the address detect function is enable d. the number of stop bits, which can be either one or two, is independent of the data length and only to be used for the transmitter. there is only one stop bit for the receiver. 1 8 0 0 1 1 ? 0 1 1 1 ? 1 0 1 example of 9-?it data ?o?mats 1 9 0 0 1 1 8 0 1 1 1 8 1 0 1 t?ansmitte? receive? data ?o?mat
rev. 1.20 20 ? ? e ??? a ?? 1 ?? 201 ? rev. 1.20 20? ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu the following diagram shows the transmit and receive waveforms for both 8-bit and 9-bit data formats. bit 0 8-?it data fo?mat bit 1 stop bit next sta?t bit sta?t bit pa?it? bit bit 2 bit 3 bit 4 bit 5 bit ? bit ? bit 0 9-?it data fo?mat bit 1 sta?t bit bit 2 bit 3 bit 4 bit 5 bit ? stop bit next sta?t bit pa?it? bit bit 8 bit ? uart t?ansmitte? data word lengths of either 8 or 9 bits can be selected by programming the bno bit in the ucr1 register. when bno bit is set, the word length will be set to 9 bits. in this case the 9th bit, which is the msb, needs to be stored in the tx8 bit in the ucr1 register . at the transmitter core lies the t ransmitter sh ift r egister, m ore c ommonly k nown a s t he t sr, wh ose d ata i s o btained f rom the t ransmit d ata r egister, wh ich i s k nown a s t he t xr_rxr r egister. t he d ata t o b e t ransmitted is loaded into this txr_rxr register by the application program. the tsr register is not written to with new data unt il the stop bit from the previous transmission ha s been sent out. as soon as this stop bit has been transmitted, the tsr can then be loaded with new data from the txr_rxr register, if it is available. it should be noted that the tsr register , unlike many other registers, is not directly mapped into the data memory area and as such is not available to the application program for direct read/write operations. an actual transmission of data will normally be enabled when the txen bit is set, but the data will not be transmitted until the txr_rxr register has been loaded with data and the baud rate generator has defned a shift clock source. however , the transmission can also be initiated by frst loading data into the txr_rxr register , after which the txen bit can be set. when a transmission of data begins, the tsr is normally empt y, in which case a transfer to the txr_rxr register will result in an immediate transfer to the tsr. if during a transmission the txen bit is cleared, the transmission will immediately cease and the transmitter will be reset. the tx o utput p in c an t hen b e c onfgured a s t he i /o o r o ther p in-shared f unctions b y c onfguring t he corresponding pin-shared control bits. when the uar t is transmitting data, the data is shifted on the tx pin from the shift register , with the least signifcant bit frst. in the transmit mode, the txr_rxr register forms a buf fer between the internal bus and the transmitter shift register . it should be noted that if 9-bit data format has been selected, then the msb will be take n from the tx8 bit in the ucr1 register . the steps to initiate a data transfer can be summarized as follows: ? make the correct selection of the bno, pr t, pren and st ops bits to defne the required word length, parity type and the number of stop bits. ? setup the brg register to select the desired baud rate. ? set the txen bit to ensure that the tx pin is used as a uart transmitter pin. ? access the usr register and write the data that is to be transmitted into the txr_rxr register . note that this step will clear the txif bit. this sequence of events can now be repeated to send additional data. it should be noted that when txif=0, data will be inhibited from being written to the txr_rxr register. clearing the txif fag is always achieved using the following software sequence:
rev. 1.20 20? ?e???a?? 1?? 201? rev. 1.20 20 ? ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu 1. a usr register access 2. a txr_rxr register write execution the read-only txif flag is set by the uar t hardware and if set indicates that the txr_rxr register is empty and that other data can now be written into the txr_rxr register without overwriting the previous data. if the teie bit is set then the txif fag will generate an interrupt. during a data transmission, a write instruction to the txr_rxr register will place the data into the txr_rxr registe r, which will be copied to the shift register at the end of the present transmission. when t here i s n o d ata t ransmission i n p rogress, a wr ite i nstruction t o t he t xr_rxr r egister wi ll place the data directly into the shift register , resulting in the commencement of data transmission, and the txif bit being immediately set. when a frame transmission is complete, which happens after stop bits are sent or after the break frame, the tidle bit will be set. t o clear the tidle bit the following software sequence is used: 1. a usr register access 2. a txr_rxr register write execution note that both the txif and tidle bits are cleared by the same software sequence. if the txbrk bit is set then break characters will be sent on the next transmission. break character transmission consists of a start bit, followed by 13n 0 bits and stop bits, where n=1, 2, etc. if a break character is to be transmitted then the txbrk bit must be frst set by the application program, and then cleared to generate the stop bits. t ransmitting a break character will not generate a transmit interrupt. note that a break condition length is at least 13 bits long. if the txbrk bit is continually kept at a logic high level then the transmitter circuitry will transmit continuous break characters. after the application program has cleared the txbrk bit, the transmitter will fnish transmitting the last break character and subsequently send out one or two stop bits. the automatic logic highs at the end of the last break character will ensure that the start bit of the next frame is recognized. the uar t is capable of receiving word lengths of either 8 or 9 bits. if the bno bit is set, the word length will be set to 9 bits with the msb being stored in the rx8 bit of the ucr1 register . at the receiver core lies the receive serial shift register , commonly known as the rsr. the data which is receive d on the rx external input pin is sent to the data recovery block. the data recovery block operating speed is 16 times that of the baud rate, while the main receiv e serial shifter operates at the baud rate. after the rx pin is sampled for the stop bit, the received data in rsr is transferred to the receive data register, if the register is empty. the data which is received on the external rx input pin is sample d three times by a majority detect circuit to determine the logic level that has been placed onto the rx pin. it should be noted that the rsr register , unlike many other registers, is not directly mapped into the data memory area and as such is not available to the application program for direct read/write operations. when the uar t receiver is receiv ing data, the data is serially shifted in on the external rx input pin, ls b f rst. in the read mode, the tx r_rxr regis ter forms a buf fer betw een the internal bus and the receiver shift register . the txr_rxr register is a two byte deep fifo data buf fer, where two byt es c an be he ld i n t he fifo whil e a t hird byt e c an c ontinue t o be re ceived. note t hat t he application program must ensure that the data is read from txr_rxr before the third byte has been completely shifted in, otherwise this third byte will be discarded and an overrun error oerr will be subsequently indicated. the steps to initiate a data transfer can be summarized as follows:
rev. 1.20 208 ? e ??? a ?? 1 ?? 201 ? rev. 1.20 209 ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ? make the correct selection of bno, prt and pren bits to defne the word length and parity type. ? setup the brg register to select the desired baud rate. ? set the rxen bit to ensure that the rx pin is used as a uart receiver pin. at this point the receiver will be enabled which will begin to look for a start bit. when a character is received the following sequence of events will occur: ? the rxif bit in the u sr regis ter w ill be set w hen the tx r_rxr regis ter has data available. there will be at most one more character available before an overrun error occurs. ? when the contents of the shift register have been transferred to the txr_rxr register , then if the rie bit is set, an interrupt will be generated. ? if during reception, a frame error , noise error , parity error , or an overrun error has been detected, then the error fags can be set. the rxif bit can be cleared using the following software sequence: 1. a usr register access 2. a txr_rxr register read execution any break character received by the uar t will be managed as a framing error . the receiver will count and expect a certain number of bit times as specifed by the value s programmed into the bno plus one stop bit. if the break is much longer than 13 bit times, the reception will be considered as complete after the number of bit times specifed by bno plus one stop bit. the rxif bit is set, ferr is set, zeros are loaded into the receive data register , interrupts are generated if appropriate and the ridle bit is set. a break is regarded as a character that contains only zeros with the ferr fag set. if a long break signal has been detected, the receiver will regard it as a data frame including a start bit, data bits and the invalid stop bit and the ferr fag will be set. the receiver must wait for a valid stop bit before looking for the next start bit. the receiver will not make the assumption that the break conditio n on the line is the next start bit. the break character will be loaded into the buf fer and no further data will be received until stop bits are received. it should be noted that the ridle read only fag will go high when the stop bits have not yet been received. the reception of a break character on the uart registers will result in the following: ? the framing error fag, ferr, will be set. ? the receive data register, txr_rxr, will be cleared. ? the oerr, nf, perr, ridle or rxif fags will possibly be set. when the receiver is reading data, which means it will be in between the detection of a start bit and the readin g of a stop bit, the receiver status fag in the usr register , otherwise known as the ridle fag, will have a zero value. in between the reception of a stop bit and the detection of the next start bit, the ridle fag will have a high value, which indicates the receiver is in an idle condition. the read only receive interrupt fag rxif in the usr register is set by an edge generated by the receiver. an i nterrupt i s ge nerated i f rie =1, whe n a word i s t ransferred from t he re ceive shi ft register, rsr, t o t he rec eive da ta regi ster, t xr_rxr. an ove rrun e rror c an a lso ge nerate a n interrupt if rie=1.
rev. 1.20 208 ?e???a?? 1?? 201? rev. 1.20 209 ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu maa r es several types of reception errors can occur within the uart module, the following section describes the various types and how they are managed by the uart. the txr_rxr register is composed of a two byte deep fifo data buf fer, where two bytes can be held in the fifo register , while a third byte can continue to be receive d. before this third byte has been enti rely shifted in, the data should be read from the txr_rxr register . if this is not done, the overrun error fag oerr will be consequently indicated. in the event of an overrun error occurring, the following will happen: ? the oerr fag in the usr register will be set. ? the txr_rxr contents will not be lost. ? the shift register will be overwritten. ? an interrupt will be generated if the rie bit is set. the oerr fag can be cleared by an access to the usr register followed by a read to the txr_ rxr register. over-sampling i s u sed f or d ata r ecovery t o i dentify v alid i ncoming d ata a nd n oise. i f n oise i s detected within a frame the following will occur: ? the read only noise fag, nf, in the usr register will be set on the rising edge of the rxif bit. ? data will be transferred from the shift register to the txr_rxr register. ? no interrupt will be generated. however this bit rises at the same time as the rxif bit which itself generates an interrupt. note that the nf fag is reset by a usr register read operation followed by a txr_rxr register read operation. the read only framing error fag, ferr, in the usr register , is set if a zero is detected instead of stop bits. if two stop bits are selected, both stop bits must be high; otherwise the ferr fag will be set. the ferr fag and the rece ived data will be recorded in the usr and txr_rxr registers respectively, and the fag is cleared in any reset. the read only parity error fag, perr, in the usr register , is set if the parity of the received word is incorrect. this error fag is only applicable if the parity is enabled, pren = 1, and if the parity type, odd or even is selected. the read only perr fag and the received data will be recorded in the usr and txr_rxr registers respectively . it is cleared on any reset, it should be noted that the fags, ferr and perr, in the usr register should frst be read by the applic ation program before reading the data word. several i ndividual uar t c onditions c an ge nerate a uar t i nterrupt. w hen t hese c onditions e xist, a low pulse will be generated to get the attention of the microcontroller . these conditions are a transmitter data register empty , trans mitter idle, receiver data available, receiver overrun, addres s detect and an rx pin wake-up. when any of these conditions are created, if the global interrupt enable bit, multi-f unction interrupt enable bit and its corresponding interrupt control bit are enabled
rev. 1.20 210 ? e ??? a ?? 1 ?? 201 ? rev. 1.20 211 ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu and the s tack is not full, the program w ill jump to its corresponding interrupt vector w here it can be serviced before returning to the main program. four of these conditions have the corresponding usr register fags which will generate a uar t interrupt if its associate d interrupt enable control bit in the ucr2 register is set. the two transmitter interrupt conditions have their own corresponding enable c ontrol bi ts, whi le t he t wo re ceiver i nterrupt c onditions ha ve a sha red e nable c ontrol bi t. these enable bits can be used to mask out individual uart interrupt sources. the address det ect condit ion, whi ch i s al so a uar t i nterrupt source, does not have an associa ted fag, but will generate a uar t interrupt when an address detect condition occurs if its function is enabled by setting the adden bit in the ucr2 register . an rx pin wake-up, which is also a uar t interrupt source, does not have an associated fag, but will generate a uar t interrupt if the uar t clock (f ) source is switched of f and the w ake and rie bits in the ucr2 register are set when a falling edge on the rx pin occurs. note t hat t he usr r egister f lags a re r ead o nly a nd c annot b e c leared o r se t b y t he a pplication program, neither will they be cleared when the program jumps to the corresponding interrupt servicing routine, as is the cas e for some of the other interrupts. the flags will be cleared automatically whe n c ertain a ctions a re t aken by t he uar t, t he de tails of whi ch a re gi ven i n t he uart regi ster se ction. the overal l uar t i nterrupt ca n be disable d or ena bled by t he rel ated interrupt enable control bits in the interrupt control registers of the microcontroller to decide whether the interrupt requested by the uart module is masked out or allowed. t?ansmitte? empt? ?lag txi? usr registe? t?ansmitte? idle ?lag tidle receive? ove???n ?lag oerr receive? data availa?le rxi? adden rx pin wake-?p wake 0 1 0 1 rx? if bno=0 rx8 if bno=1 ucr2 registe? rie 0 1 tiie 0 1 teie 0 1 uart inte???pt req?est ?lag ur? ucr2 registe? ure m?ne emi 0 1 inte???pt signal to mcu uart interrupt structure address detect mode setting the address detect mode bit, adden, in the ucr2 register , enables this special mode. if this bit is enabled then an additional qualifer will be placed on the generation of a receiver data available interrup t, which is requested by the rxif fag. if the adden bit is enabled, then when data is available, an interrupt will only be generated, if the highest received bit has a high value. note that the mfne, ure and emi interrupt enable bits must also be enabled for correct interrupt generation. this highes t addres s bit is the 9th bit if bn o=1 or the 8th bit if bn o=0. if this bit is high, then the received word will be defined as an address rather than data. a data a vailable interrupt will be generated every time the last bit of the received word is set. if the adden bit is not enabled, then a receiver data a vailable interrupt will be generated each time the rx if flag i s se t, i rrespective o f t he d ata l ast b it st atus. t he a ddress d etect m ode a nd p arity e nable a re mutually exclusive functions. therefore if the address detect mode is enabled, then to ensure correct operation, the parity function should be disabled by resetting the parity enable bit pren to zero.
rev. 1.20 210 ?e???a?? 1?? 201? rev. 1.20 211 ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu dde b b b b urt ga 0 0 1 1 0 1 when the u art clock (f h ) is of f, the u art w ill ceas e to function, all clock sources to the module are shutdown. if the uar t clock (f h ) is of f while a transmission is still in progress, then the transmission will be paused until the uar t clock source derived from the microcontroller is activated. in a similar way , if the mcu enters the power down mode while receiving data, then the reception of data will likewise be paused. when the mcu enters the power down mode, note that the usr, ucr1, ucr2, transmit and receive registers, as well as the brg register will not be affected. it is recommended to make sure frst that the uar t data transmission or reception has been fnished before the microcontroller enters the power down mode. the u art function contains a receiver rx pin wake-up function, which is enabled or disabled by the w ake bit in the ucr2 register . if this bit, along with the uar t enable bit, uar ten, the receiver enable bit, rxen and the receiver interrupt bit, rie, are all set when the uar t clock (f h ) is of f, then a fallin g edge on the rx pin will trigger an rx pin wake-up uar t interrupt. note that as i t t akes c ertain syst em c lock c ycles a fter a wa ke-up, be fore nor mal m icrocontroller ope ration resumes, any data received during this time on the rx pin will be ignored. for a uar t wake-up interrupt to occur , in addition to the bits for the wake-up being set, the global interrupt e nable bi t, e mi, t he mu lti-function int errupt e nable bi t, mfne , a nd t he uar t i nterrupt enable bit, ure, must be set. if the emi, mfne and ure bits are not set then only a wake up event will occur and no interrupt will be generated. note also that as it takes certain system clock cycles after a wa ke-up b efore n ormal m icrocontroller r esumes, t he uar t i nterrupt wi ll n ot b e g enerated until after this time has elapsed.
rev. 1.20 212 ? e ??? a ?? 1 ?? 201 ? rev. 1.20 213 ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu l la d ld the devic es have a low v oltage detector function, also known as l vd. this enabled the devices to monitor the power supply voltage, v dd , and provide a warning signal should it fall below a certain level. this function may be especially useful in battery applications where the supply voltage will gradually reduce as the battery ages, as it allows an early warning battery low signal to be generated. the low v oltage detector also has the capability of generating an interrupt signal. the low voltage detector function is controlled using a single register with the name l vdc. three bits in this register , v lvd2 ~v lvd0 , are us ed to select one of eight fxed voltages below which a low voltage condition will be determined. a low voltage condition is indicated when the l vdo bit is set. if the l vdo bit is low , this indicates that the v dd voltage is above the preset low voltage value. the l vden bit is used to control the overall on/of f function of the low voltage detector . setting the bit high will enabl e the low voltage detector . clearing the bit to zero will switch of f the internal low voltage detector circuits. as the low voltage detector will consume a certain amount of power, it may be desirable to switch of f the circuit when not in use, an important consideration in power sensitive battery powered applications. name lvdo lvden vbgen vlvd2 vlvd1 vlvd0 r/w r r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7~6 unimplemented, read as 0 bit 5 : lvd output fag 0: no low v oltage detected 1: low v oltage detected bit 4 : low v oltage detector enable control 0: disable 1: enable bit 3 : bandgap v oltage output enable control 0: disable 1: enable note that the bandgap circuit is enabled when the l vd or l vr functio n is enabled or when the vbgen bit is set to 1. bit 2~0 : lvd v oltage selection 000: 2.0v 001: 2.2v 010: 2.4v 011: 2.7v 100: 3.0v 101: 3.3v 110: 3.6v 111: 4.0v
rev. 1.20 212 ?e???a?? 1?? 201? rev. 1.20 213 ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ld a the low v oltage detector function operates by comparing the pow er supply voltage, v dd , with a pre-specifed volta ge level stored in the l vdc register . this has a range of between 2.0v and 4.0v . when the power supply voltage, v dd , falls below this pre-determined value, the l vdo bit will be set high indicating a low power supply voltage condition. the low v oltage detector function is su pplied b y a r eference v oltage wh ich wi ll b e a utomatically e nabled. w hen t he d evices a re i n the sleep mode, the low voltage detector will be disabled even if the l vden bit is high. after enabling the low v oltage detector , a time delay t lvds should be allowed for the circuitry to stabilise before reading the l vdo bit. note also that as the v dd voltage may rise and fall rather slowly , at the voltage nears that of v lvd , there may be multiple bit lvdo transitions. vdd lvden lvdo v lvd t lvds lvd ope?ation the low v oltage detector also has its own interrupt which is contained within one of the multi- function interrupts, providing an alternative means of low voltage detection, in addition to polling the l vdo bit. the interrupt will only be generated after a delay of t lvd after the l vdo bit has been set high by a low voltage condition . in this case, the l vf interrupt request fag will be set, causing an interrupt to be generated if v dd falls below the preset l vd voltage. this will cause the devices to wa ke-up f rom t he idl e mod e, h owever i f t he l ow v oltage de tector wa ke u p fu nction i s no t required then the lvf fag should be frst set high before the devices enter the idle mode.
rev. 1.20 214 ? e ??? a ?? 1 ?? 201 ? rev. 1.20 215 ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu usb a the usb interfac e is a 4-wire serial bus that allows communication between a host device and up to 127 max peripheral devices on the same bus. a token based protocol method is used by the host device for communication control. other advantages of the usb bus include live plugging and unplugging and dynamic device confguration. as the complexity of usb data protocol does not permit comprehen sive usb operation information to be provided in this datasheet, the reader should therefore consult other external information for a detailed usb understanding. the devic es includ e a usb interfac e function allowing for the conveni ent design of usb peripheral products. there are three power planes for the devices and they are usb sie vdd, vddio and the mcu vdd. for the usb sie vdd it will supply power for all circuits related to usb sie and is sourced from ubus pi n. once t he usb i s re moved from t he usb i nterface a nd t here i s no powe r i n t he usb bus, the usb sie circuit is no longer operational. for the p a port, the power can be supplied by the vdd, v33o or vddio pin selected using the pmps register. the vddio is pin-shared with pe0 and vref pins .the vddio function can be selected by the corresponding pin-shared function selection bits. for the mcu vdd, it supplies power for all the device circuits except the usb sie which is supplied by ubus. to communicate with an external usb host, the internal usb module has the external pins known as udp and udn along with the 3.3v regulator output v33o. a serial interface engine (sie) decodes the incom ing usb data stream and transfers it to the correct endpoint buf fer memory known as the fifo. t he usb m odule ha s 8 e ndpoints, e p0 ~ e p7, a nd t he fifo si ze fo r e ach e ndpoint e xcept endpoint 0 can respectively be confgured using the ufc0~ufc2 registers by application programs. all endpoints except endpoint 0 can be confgured to have 8, 16, 32 or 64 bytes together with the fifon registers as the fifo size. the endpoint 0 has 8-byte fifo size. the endpoint 0 supports the control transfer while the endpoint 1 ~ endpoint 7 support the interrupt or bulk transfer. as t he usb fi fo i s a ssigned f rom t he l ast se ctor o f t he ge neral pu rpose da ta me mory a nd h as a start address to the upper address, dependent on the fifo size, if the corresponding data ram sector is used for both general purpose ram and the usb fifo, special care should be taken that the ram equ defnition should not overlap with the usb fifo ram address. the usb fifo size and defnition for in/out control depends upon the ufc0~ufc2, ufien and ufoen registers.
rev. 1.20 214 ?e???a?? 1?? 201? rev. 1.20 215 ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu out 3 (8 ??tes) in 3 (8 ??tes) out 2 (1? ??tes) in 2 (1? ??tes) out 1 (8 ??tes) nc8h n?8h n??h n?0h ne?h ne0h nd?h nd0h nc?h nc0h nc?h n sho?ld sta?t f?om ?~0. in 1 (8 ??tes) n??h : : gene?al p??pose data memo?? n80h usb fifo size confguration example the u sb function control is implemented us ing a s eries of registers . a s eries of s tatus registers provide the user with the usb data transfer situation as well as any error conditions. the usb contains i ts o wn i ndependent i nterrupt wh ich c an b e u sed t o i ndicate wh en t he usb fi fos a re accessed by the host device or a change of the usb operating conditions including the usb suspend mode, resume event or usb reset occurs. sysc usbdis rubus ubus ? d1 esd ? usb_stat od1o od0o od1i od0i se1 se0 pu uint ep ? en ep ? en ep5en ep4en ep3en ep2en ep1en ep0en usc urd ums2 ums1 ums0 resume urst rmwk susp uesr ep ?? ep ?? ep5 ? ep4 ? ep3 ? ep2 ? ep1 ? ep0 ? ucc rctrl jsusp susp2 usbcken eps2 eps1 eps0 awr ad ? ad5 ad4 ad3 ad2 ad1 ad0 wken stli stli ? stli ? stli5 stli4 stli3 stli2 stli1 stli0 stlo stlo ? stlo ? stlo5 stlo4 stlo3 stlo2 stlo1 sies nmi uerr2 uerr1 uerr0 in out u ? err aset misc len0 ready setcmd v33os clear tx request u ? ien seti ? seti ? seti5 seti4 seti3 seti2 seti1 ? i ? o_de ? u ? oen seto ? seto ? seto5 seto4 seto3 seto2 seto1 datatg u ? c0 e3 ? s1 e3 ? s0 e2 ? s1 e2 ? s0 e1 ? s1 e1 ? s0 u ? c1 e ?? s1 e ?? s0 e ?? s1 e ?? s0 e5 ? s1 e5 ? s0 e4 ? s1 e4 ? s0 u ? c2 e3odb e3idb e2odb e2idb ? i ? o0 d ? d ? d5 d4 d3 d2 d1 d0 ? i ? o1 d ? d ? d5 d4 d3 d2 d1 d0 ? i ? o2 d ? d ? d5 d4 d3 d2 d1 d0 ? i ? o3 d ? d ? d5 d4 d3 d2 d1 d0
rev. 1.20 21 ? ? e ??? a ?? 1 ?? 201 ? rev. 1.20 21? ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu rs a b 7 6 5 4 2 ? i ? o4 d ? d ? d5 d4 d3 d2 d1 d0 ? i ? o5 d ? d ? d5 d4 d3 d2 d1 d0 ? i ? o ? d ? d ? d5 d4 d3 d2 d1 d0 ? i ? o ? d ? d ? d5 d4 d3 d2 d1 d0 usb inte?face registe?s list sysc registe? bit ? ? 5 4 3 2 1 0 name usbdis rubus ubus ? d1 esd ? r/w r/w r/w r r/w r/w por 0 0 0 0 x x: ? nknown bit 7 unimplemented, read as 0 bit 6 usbdis : usb sie function control 0: enable 1: disable this bit is used to control the usb sie function. when this bit is set to 1, the usb sie function will be disabled. bit 5 rubus : ubus pin pull low function control 0: enable 1: disable bit 4 ubusf : ubus pin input status 0: low level 1: high level bit 3~2 unimplemented, read as 0 bit 1 d1 : reserved bit, cannot be used and must be fxed at 0 bit 0 esdf : esd issue fag this bi t wil l be set t o 1 whe n t here i s a n e sd i ssue. it i s set by sie a nd c leared by software. name od1o od0o od1i od0i se1 se0 pu r/w r/w r/w r r r/w r/w r/w por 1 1 x x 0 0 0 x: ? nknown bit 7 od1o : output data on od1 pin, open drain nmos output bit 6 od0o : output data on od0 pin, open drain nmos output bit 5 od1i : od1 pin input status bit 4 od0i : od0 pin input status bit 3 se1 : usb bus se1 noise indication this bit is used to indicate that the sie has detected a se1 noise on the usb bus. this bit is set by sie and cleared by software. bit 2 se0 : usb bus se0 noise indication this bit is used to indicate that the sie has detected a se0 noise on the usb bus. this bit is set by sie and cleared by software.
rev. 1.20 21? ?e???a?? 1?? 201? rev. 1.20 21 ? ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu bit 1 : udp/udn pins pull-high function control 0: disable C no internal pull-high resistor 1: enable C internal 600k pull-high resistor on udp/udn pins bit 0 unimplemented, read as 0 uint register bit 7 6 5 4 3 2 1 0 name ep ? en ep ? en ep5en ep4en ep3en ep2en ep1en ep0en r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 : usb endpoint 7 interrupt enable control 0: disable 1: enable bit 6 : usb endpoint 6 interrupt enable control 0: disable 1: enable bit 5 : usb endpoint 5 interrupt enable control 0: disable 1: enable bit 4 : usb endpoint 4 interrupt enable control 0: disable 1: enable bit 3 : usb endpoint 3 interrupt enable control 0: disable 1: enable bit 2 : usb endpoint 2 interrupt enable control 0: disable 1: enable bit 1 : usb endpoint 1 interrupt enable control 0: disable 1: enable bit 0 : usb endpoint 0 interrupt enable control 0: disable 1: enable usc register bit 7 6 5 4 3 2 1 0 name urd ums2 ums1 ums0 resume urst rmwk susp r/w r/w r/w r/w r/w r r/w r/w r por 1 0 0 0 x x x x x: ? nknown bit 7 : usb reset signal reset function control 0: usb reset signal cannot reset mcu 1: usb reset signal will reset mcu bit 6~4 : usb and od mode select 000: no mode available C the v33o output will be foating. the relevant external pins will be in an input foating state. 001: open drain output mode C the v33o output will be pulled high to vdd. the relevant external pins will become od0/od1 pins with a pull-high resistor respectively connected to vdd. 01x: usb mode C the v33o function will be enabled. the relevant external pins will be used as the udp and udn pins. 100~111: undefned, the od0/od1 will be in a foating state.
rev. 1.20 218 ? e ??? a ?? 1 ?? 201 ? rev. 1.20 219 ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu bit 3 : usb resume indication 0: resume signal is not asserted or usb device has left the suspend mode 1: resume signal is asserted and usb device is going to leave the suspend mode this bit is read only . when the resume event occurs, this bit will be set high by sie and then an interrupt w ill also be generated to w ake up the m cu. in order to detect the suspend state, the mcu should set the usbcken bit to 1 and clear the susp2 bit to 0. when the usb device leaves the suspend mode, the susp bit will be cleared to 0 and then the resume bit will also be cleared to 0. the resume signal which causes the mcu to wake up should be noted and taken into consideration when the mcu is detecting the suspend mode. bit 2 : usb reset indication 0: no usb reset event occurs 1: usb reset event occurs this bit is set and cleared by the sie. when the urst bit is set high, it indicates that a usb reset event has occurred and a usb interrupt will be generated. bit 1 : usb remote wake-up command 0: no usb remote wake-up command initiated 1: initiate usb remote wake-up command the rmwk bit is set to 1 by the mcu to force the u sb host leaving the sus pend mode. se tting t he rmw k bi t t o 1 wi ll i nitiate a re mote wa ke-up c ommand. t he rmwk bit should be kept high for at least 1 usb clock to make sure that the remote wake-up command is accepted by the sie. bit 0 : usb suspend indication 0: usb leaves the suspend mode 1: usb enters the suspend mode this bit is read only and set to 1 by the sie to indicate that the usb has entered the suspend mode. the corresponding interrupt will also be generated when the susp bit changes from low to high. uesr register the ue sr re gister i s t he usb e ndpoint i nterrupt st atus re gister a nd i s use d t o i ndicate wh ich endpoint is accessed and to select the usb bus. the endpoint request flags, epnf , are used to indicate which endpoints are accessed. if an endpoint is accessed, the related endpoint request fag will be set to 1 and the usb interrupt will occur if the usb interrupt is enabled and the stack is not f ull. w hen t he a ctive e ndpoint r equest fa g i s se rviced, t he e ndpoint r equest fa g h as t o b e c leared to 0 by software. bit 7 6 5 4 3 2 1 0 name ep ?? ep ?? ep5 ? ep4 ? ep3 ? ep2 ? ep1 ? ep0 ? r/w r/w r/w r/w r/w r/w r/w r/w r/w por x x x x x x x x x: ? nknown bit 7 : endpoint 7 access interrupt request fag 0: not accessed 1: accessed bit 6 : endpoint 6 access interrupt request fag 0: not accessed 1: accessed bit 5 : endpoint 5 access interrupt request fag 0: not accessed 1: accessed
rev. 1.20 218 ?e???a?? 1?? 201? rev. 1.20 219 ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu bit 4 : endpoint 4 access interrupt request fag 0: not accessed 1: accessed bit 3 : endpoint 3 access interrupt request fag 0: not accessed 1: accessed bit 2 : endpoint 2 access interrupt request fag 0: not accessed 1: accessed bit 1 : endpoint 1 access interrupt request fag 0: not accessed 1: accessed bit 0 : endpoint 0 access interrupt request fag 0: not accessed 1: accessed ucc register bit 7 6 5 4 3 2 1 0 name rctrl jsusp susp2 usbcken eps2 eps1 eps0 r/w r/w r r/w r/w r/w r/w r/w por 0 0 x 0 x x x x: ? nknown bit 7 : 7.5k resistor between udp and ubus connection control 0: disable C no 7.5k resistor is connected between udp and ubus lines 1: enable C 7.5k resistor is connected between udp and ubus lines bit 6 unimplemented, read as 0 bit 5 : usb j-state suspend mode indication 0: usb interface is not in the j-state suspend mode 1: usb interface is in the j-state suspend mode this bit indicates whether the usb interface is in the j-state suspend mode or not. bit 4 : usb suspend mode current reduction control 0: current reduction is disabled in suspend mode 1: current reduction is enabled in suspend mode the current can be reduced to meet the usb standard specifcation if this bit is set to 1 when entering the suspend mode. bit 3 : usb clock enable control 0: disable 1: enable bit 2~0 : endpoint fifo access selection 000: endpoint 0 fifo is selected 001: endpoint 1 fifo is selected 010: endpoint 2 fifo is selected 011: endpoint 3 fifo is selected 100: endpoint 4 fifo is selected 101: endpoint 5 fifo is selected 110: endpoint 6 fifo is selected 111: endpoint 7 fifo is selected
rev. 1.20 220 ? e ??? a ?? 1 ?? 201 ? rev. 1.20 221 ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu r rs the a wr register contains the current address and a remote wake up function control bit. the initial value of a wr is 00h. the address value extracted from the usb host command is immediately loaded into this register or not is determined by the aset bit in the sies register. name ad ? ad5 ad4 ad3 ad2 ad1 ad0 wken r/w r/w r/w r/w r/w r/w r/w r/w r/w por x x x x x x x x x: ? nknown bit 7~1 ad6~ad0 : usb device address bit 6 ~ bit 0 bit 0 wken : usb remote wake-up enable control 0: disable 1: enable the stli/stlo registers show whether the corresponding endpoint has worked properly or not. as soon as an endpoint improper in/out operation occurs, the related bit in the stli/stlo registers has to be set high by applicat ion program. the stli/stlo regi sters content will be cleared by a usb reset signal and a setup token event. ? name stli ? stli ? stli5 stli4 stli3 stli2 stli1 stli0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por x x x x x x x x x: ? nknown bit 7~0 stli7~stli0 : usb endpoint n fifo in operation stall indication 0: endpoint n fifo in operation is not stalled 1: endpoint n fifo in operation is stalled the st lin b it i s se t b y u ser wh en t he usb e ndpoint n i s st alled. t he st lin b it i s cleared by a usb reset signal. for endpoint 0 the stli0 bit can also be cleared by a setup token event. ? name stlo ? stlo ? stlo5 stlo4 stlo3 stlo2 stlo1 r/w r/w r/w r/w r/w r/w r/w r/w por x x x x x x x x: ? nknown bit 7~1 stlo7~stlo1 : usb endpoint n fifo out operation stall indication 0: endpoint n fifo out operation is not stalled 1: endpoint n fifo out operation is stalled the stlon bit is set by user when the usb endpoint n is stalled. the stlon bit is cleared by a usb reset signal. bit 0 unimplemented, read as 0
rev. 1.20 220 ?e???a?? 1?? 201? rev. 1.20 221 ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ses rs the sies register is used to indicate the present signal state which the sie receives and also controls whether the sie changes the device address automatically or not. name nmi uerr2 uerr1 uerr0 in out u ? err aset r/w r/w r/w r/w r/w r r/w r/w r/w por x x x x x x x x x: ? nknown bit 7 nmi : nak token interrupt mask control 0: nak token interrupt is not masked 1: nak token interrupt is masked if t his b it i s se t t o 1 , t he i nterrupt wi ll n ot b e g enerated wh en t he d evices se nd a nak token to the usb host. otherwise, the endpoint n nak token interrupt will be generated if the corresponding endpoint interrupt control is enabled when this bit is set to 0 and the devices send a nak token to the usb host. bit 6~4 uerr2~uerr0 : usb sie error status 0xx: no error 100: usb pid error 101: bit stuffng error 110: crc error 111: host no response to sie these bits indicate which kind of error is detected by the usb sie. these bits are set by the usb sie and cleared by the application program. bit 3 in : in token indication 0: the received token packet is not in token 1: the received token packet is in token the in bit is used to indicate whether the current token packet received from the usb host is in token or not. bit 2 out : out token indication 0: the received token packet is not out token 1: the received token packet is out token the out bit is used to indicate whether the token received from the usb host is out token or not e xcept t he out z ero l ength t oken. t his bi t shoul d be c leared t o 0 by application program after an out data has been read. note that this bit will also be cleared when the next valid setup token is received. bit 1 uferr : fifo access error indication 0: no error occurs 1: error occurs this bit is used to indicate whether the usb bus errors, such as crc error , pid error or bit stuffng error , etc., has occurred or not when the fifo is accessed. this bit is set by sie and cleared by application program. bit 0 aset : device address update method control 0: device address is immediately updated when an address is written into the a wr register 1: device address is updated after the devices in token data have completely been read by the usb host this bit is used to confgure the sie to automatically change the device address by the value stored in the a wr register . when this bit is set to 1 by frmware, the sie will update the device address by the value stored in the a wr register after the usb host has succe ssfully read the data from the devices by an in operation. otherwise, when this bit is cleared to 0, the sie will update the device address immediately after an address is written to the a wr regis ter. therefore, in order to operate properly , the frmware has to clear this bit after a next valid setup token is received.
rev. 1.20 222 ? e ??? a ?? 1 ?? 201 ? rev. 1.20 223 ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu msc rs b 7 6 5 4 2 name len0 ready setcmd v33os clear tx request r/w r r r/w r/w r/w r/w r/w por x x x 0 x x x x: ? nknown bit 7 len0 : zero-length packet indication 0: the received packet is not zero-length packet 1: the received packet is zero-length packet this bit is used to show whether the usb host sends a zero-length packet or not. it is set by hardware and cleared by firmware. it will also be cleared by hardware after the mcu receives a valid usb setup token. bit 6 ready : endpoint fifo ready indication 0: the desired endpoint fifo is not ready 1: the desired endpoint fifo is ready bit 5 setcmd : setup command indication 0: the data in the fifo is not setup token 1: the data in the fifo is setup token this bit is set by hardware and cleared by application program. bit 4 v33os : v oltage select 0: internal v33o voltage 1: external 3.3v ldo bit 3 unimplemented, read as 0 bit 2 clear : fifo clear function enable control 0: no operation 1: clear the requested endpoint fifo this bit is used to clear the requested fifo even if the corresponding fifo is not ready. t he c lear b it sh ould b e se t t o 1 t o g enerate a p ositive p ulse wi th a p ulse width to clear the requested fifo and then clear this bit to zero. after clearing the fifo, the usb interface out pipe endpoint can receive new data from the host and in pipe endpoint can transfer new data to the host. bit 1 tx : data transfer direction indication 0: mcu read data from the usb fifo 1: mcu wirte data to the usb fifo this bit defi nes the data transfe r directi on betwee n the mcu and usb endpoint fifo. when the tx bit is set to 1, it means that the mcu wants to write data to the usb endpoint fifo. after the mcu write operation has completed, this bit has to be c leared t o 0 be fore t erminating t he fifo re quest t o i ndicate t he e nd of t he da ta transfer. for a mcu read operation this bit has to be cleared to 0 to indicate that the mcu wants to read data from the usb endpoint fifo. then this bit has to be set to 1 before terminating the fifo request to indicate the end of the data transfer after an mcu read operation completion. bit 0 request : fifo request control 0: no reqeust or request completion 1: request desired fifo this bit is used to request an operation of the desired endpoint fifo. after selecting the desired endpoint fifo, the fifo can be requested by setting this bit high. then this bit should be cleared to zero after the operation completion.
rev. 1.20 222 ?e???a?? 1?? 201? rev. 1.20 223 ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ufe rs b 7 6 5 4 2 name seti ? seti ? seti5 seti4 seti3 seti2 seti1 ? i ? o_de ? r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 seti7 : endpoint 7 input fifo enable control 0: disable 1: enable bit 6 seti6 : endpoint 6 input fifo enable control 0: disable 1: enable bit 5 seti5 : endpoint 5 input fifo enable control 0: disable 1: enable bit 4 seti4 : endpoint 4 input fifo enable control 0: disable 1: enable bit 3 seti3 : endpoint 3 input fifo enable control 0: disable 1: enable bit 2 seti2 : endpoint 2 input fifo enable control 0: disable 1: enable bit 1 seti1 : endpoint 1 input fifo enable control 0: disable 1: enable bit 0 fifo_def : fifo confguration redefne enable control 0: disable 1: enable if this bit is set to 1, the sie will redefne the fifo confguration. then this bit will be automatically cleared to 0 by the sie. name seto ? seto ? seto5 seto4 seto3 seto2 seto1 datatg r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 seto7 : endpoint 7 output fifo enable control 0: disable 1: enable bit 6 seto6 : endpoint 6 output fifo enable control 0: disable 1: enable bit 5 seto5 : endpoint 5 output fifo enable control 0: disable 1: enable bit 4 seto4 : endpoint 4 output fifo enable control 0: disable 1: enable
rev. 1.20 224 ? e ??? a ?? 1 ?? 201 ? rev. 1.20 225 ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu bit 3 : endpoint 3 output fifo enable control 0: disable 1: enable bit 2 : endpoint 2 output fifo enable control 0: disable 1: enable bit 1 : endpoint 1 output fifo enable control 0: disable 1: enable bit 0 : data token toggle control 0: data0 will be sent frst 1: data1 will be sent frst this bit is used to sel ect the dat a token toggle bit . when thi s bit is cl eared to 0, a data0 wi ll fi rst be se nt i n t he fol lowing in or out da ta pi pe for t he re quested endpoint fifo. otherwise, a da ta1 will be sent frst followed by the successive in or out data transfer. ufc0 register bit 7 6 5 4 3 2 1 0 name e3 ? s1 e3 ? s0 e2 ? s1 e2 ? s0 e1 ? s1 e1 ? s0 r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7~6 : endpoint 3 fifo size selection 00: 8 bytes 01: 16 bytes 10: 32 bytes 11: 64 bytes bit 5~4 : endpoint 2 fifo size selection 00: 8 bytes 01: 16 bytes 10: 32 bytes 11: 64 bytes bit 3~2 : endpoint 1 fifo size selection 00: 8 bytes 01: 16 bytes 10: 32 bytes 11: 64 bytes bit 1~0 unimplemented, read as 0 ufc1 register bit 7 6 5 4 3 2 1 0 name e ?? s1 e ?? s0 e ?? s1 e ?? s0 e5 ? s1 e5 ? s0 e4 ? s1 e4 ? s0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 : endpoint 7 fifo size selection 00: 8 bytes 01: 16 bytes 10: 32 bytes 11: 64 bytes
rev. 1.20 224 ?e???a?? 1?? 201? rev. 1.20 225 ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu bit 5~4 : endpoint 6 fifo size selection 00: 8 bytes 01: 16 bytes 10: 32 bytes 11: 64 bytes bit 3~2 : endpoint 5 fifo size selection 00: 8 bytes 01: 16 bytes 10: 32 bytes 11: 64 bytes bit 1~0 : endpoint 4 fifo size selection 00: 8 bytes 01: 16 bytes 10: 32 bytes 11: 64 bytes ufc2 register bit 7 6 5 4 3 2 1 0 name e3odb e3idb e2odb e2idb r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~4 unimplemented, read as 0 bit 3 : endpoint 3 output fifo size for single or double buffer selection 0: single buffer 1: double buffer bit 2 : endpoint 3 input fifo size for single or double buffer selection 0: single buffer 1: double buffer bit 1 : endpoint 2 output fifo size for single or double buffer selection 0: single buffer 1: double buffer bit 0 : endpoint 2 input fifo size for single or double buffer selection 0: single buffer 1: double buffer fifon registers the fifon register is used for data transactions storages between the usb device and the usb host. t he mc u r eads d ata f rom o r wr ites d ata t o t he fi fon v ia t he sp ecific c ombination o f t he corresponding control and selection bits. name type por descriptions ? i ? o0 r/w xxxx xxxx endpoint 0 data pipe ? i ? o1 r/w xxxx xxxx endpoint 1 data pipe ? i ? o2 r/w xxxx xxxx endpoint 2 data pipe ? i ? o3 r/w xxxx xxxx endpoint 3 data pipe ? i ? o4 r/w xxxx xxxx endpoint 4 data pipe ? i ? o5 r/w xxxx xxxx endpoint 5 data pipe ? i ? o ? r/w xxxx xxxx endpoint ? data pipe ? i ? o ? r/w xxxx xxxx endpoint ? data pipe x: ? nknown usb suspend mode and wake-up
rev. 1.20 22 ? ? e ??? a ?? 1 ?? 201 ? rev. 1.20 22? ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu usb ss m if there is no signal on the usb bus for over 3ms, the usb device will enter the suspend mode. the suspend fag, susp, in the usc register will then be set high and an usb interrupt will be generated to indicate that the devices should jump to the suspend state to meet the requirements of the usb suspend current specifcation. in order to meet the requirements of the suspend current; the frmware should disable the usb clock by clearing the usbcken bit to 0. the suspend mode current can be further decreased by setting the susp2 bit in the ucc register. when the resume signal is asserted by the usb host, the devices will be woken up by the usb interrupt and the resume bit in the usc register will be set. t o ensure correct device operation, the application program should set the usbcken bit high and the usb host will start to communicate with the usb device. then the susp2 bit will be cleared low together with the resume bit when the usb device actually leaves the suspend mode. therefore, when the devices detect the suspend bit, susp2, the resume bit, resume, should be monitored and taken into consideration. susp resume usb_int s?spend and host wake-?p usb remote wake-?p as the usb devic e has a remote wake-up function, the usb device can wake up the usb host by sending a remote wake-up pulse which is generated by setting the rmwk bit high. once the usb host receives a remote wake-up signal from the usb device, the host will send a resume signal to devices. susp resume usb_int rmwk 2.5ms (min.) 1usb clock (min.) s?spend and remote wake-?p usb inte???pts several usb conditions can generate an usb interrupt. when one of these conditions exists, an interrupt pulse will be generated to get the attention of the microcontroller . these conditions are the usb suspended, usb resumed, usb reset and usb endpoint fifo access events. when the usb interrupt caused by any of these conditions occurs, if the corresponding interrupt control is enabled and the stack is not full, the program will jump to the corresponding interrupt vector where it can be serviced before returning to the main program. for the usb endpoint fifo access event, there are the corresponding indication fags to indicate which endpoint fifo is accessed. as the endpoint fifo access fag is set, it will generate a usb interrupt if the associated endpoint fifo pipe and interrupt control are both enabled. the endpoint fifo access fags should be cleared by the application program. as the usb suspended or usb resume condition occurs, the corresponding indication fag, known as susp and resume bits, will
rev. 1.20 22? ?e???a?? 1?? 201? rev. 1.20 22 ? ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu be set and a usb interrupt will directly generate without enabling the associated interrupt control bit. the susp and resume bits are read only and set or cleared by the usb sie. for a usb interrupt occurred to be serviced, in addition to the bits for the corresponding interrupt enable control in usb module being set, the global interru pt enable control and the related interrupt enable control bits in the host mcu must also be set. if these bits are not set, then no interrupt will be serviced. the devic es includ e a pwm fuction for rgb led application, which is composed of n led pwm modules, led page ram & register transfer unit and a led com output unit. module 0 module n 6-bit pwm intensity /64 led ram_a led ram_b mncce led color and intensity pwm transfer unit hlmos & lcio & lfcr register uds & comdir & ldcome & ccolpo & ldcom[2:0] mncbe mncae lmncar [5:0] mnie led com output pwmn[1:0] 6-bit pwm color c pwm control 6-bit pwm color b pwm control 6-bit pwm color a pwm control rgb3n pwmilm & pwmalm & pwmblm & pwmclm & llmd register pwmihm & pwma hm & pwmbhm & pwmchm & hlmd register lmncbr [5:0] lmnccr [5:0] pwmn[1:0] pwmn[1:0] lmnir [5:0] rgb3n+1 rgb3n+2 pwmck[1:0] ledcom m led register a ledcom 0 ledcom m led register b ledcom 0 comm ledint (to led pwm interrupt) udint (to led up/down interrupt) led ram sfr f pwm _16m f pwm _12m note: n=0~4 for ht66fb572; n=0~7 for ht66fb574; n=0~f for HT66FB576, while m=0~7 for the series devices.
rev. 1.20 228 ? e ??? a ?? 1 ?? 201 ? rev. 1.20 229 ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu m rss overall operation of the pwm function for rgb led is controlled using a series of registers. lcio0 cbpwm3 cbpwm2 cbpwm1 cbpwm0 capwm3 capwm2 capwm1 capwm0 lcio1 ipwm3 ipwm2 ipwm1 ipwm0 ccpwm3 ccpwm2 ccpwm1 ccpwm0 l ? cr l ? cr ? l ? cr ? l ? cr5 l ? cr4 l ? cr3 l ? cr2 l ? cr1 l ? cr0 racme0 (ht ??? b5 ? 2) racm4 racm3 racm2 racm1 racm0 racme0 (ht ??? b5 ? 4/ ht ??? b5 ?? ) racm ? racm ? racm5 racm4 racm3 racm2 racm1 racm0 racme1 (ht ??? b5 ?? ) racm ? racme racmd racmc racmb racma racm9 racm8 rbcme0(ht ??? b5 ? 2) rbcm4 rbcm3 rbcm2 rbcm1 rbcm0 rbcme0 (ht ??? b5 ? 4/ ht ??? b5 ?? ) rbcm ? rbcm ? rbcm5 rbcm4 rbcm3 rbcm2 rbcm1 rbcm0 rbcme1 (ht ??? b5 ?? ) rbcm ? rbcme rbcmd rbcmc rbcmb rbcma rbcm9 rbcm8 lmnir mnie mnid5 mnid4 mnid3 mnid2 mnid1 mnid0 lmncar mncae mncad5 mncad4 mncad3 mncad2 mncad1 mncad0 lmncbr mncbe mncbd5 mncbd4 mncbd3 mncbd2 mncbd1 mncbd0 lmnccr mncce mnccd5 mnccd4 mnccd3 mnccd2 mnccd1 mnccd0 pwmctl0 pwmn1 pwmn0 pwmck1 pwmck0 ldcome ldcom2 ldcom1 ldcom0 pwmctl1 uclpd ccolpo comdir uds d3 d2 pwmge psel pwmilm ilm5 ilm4 ilm3 ilm2 ilm1 ilm0 pwmalm calm5 calm4 calm3 calm2 calm1 calm0 pwmblm cblm5 cblm4 cblm3 cblm2 cblm1 cblm0 pwmclm cclm5 cclm4 cclm3 cclm2 cclm1 cclm0 pwmihm ihm5 ihm4 ihm3 ihm2 ihm1 ihm0 pwmahm cahm5 cahm4 cahm3 cahm2 cahm1 cahm0 pwmbhm cbhm5 cbhm4 cbhm3 cbhm2 cbhm1 cbhm0 pwmchm cchm5 cchm4 cchm3 cchm2 cchm1 cchm0 hlmos hmos3 hmos2 hmos1 hmos0 lmos3 lmos2 lmos1 lmos0 hlmd hlmd5 hlmd4 hlmd3 hlmd2 hlmd1 hlmd0 llmd llmd5 llmd4 llmd3 llmd2 llmd1 llmd0 pwm registe?s list note: n=0~4 for ht66fb572; n=0~7 for ht66fb574; n=0~f for HT66FB576, while m=0~7 for the series devices. name cbpwm3 cbpwm2 cbpwm1 cbpwm0 capwm3 capwm2 capwm1 capwm0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~4 cbpwm3~cbpwm0 : offset value for led module color b pwm bit 3~0 capwm3~capwm0 : offset value for led module color a pwm note: 1. this register will be updated every column application program. 2. this register is only available in auto mode.
rev. 1.20 228 ?e???a?? 1?? 201? rev. 1.20 229 ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu lc rs b 7 6 5 4 2 name ipwm3 ipwm2 ipwm1 ipwm0 ccpwm3 ccpwm2 ccpwm1 ccpwm0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~4 ipwm3~ipwm0 : offset value for led module intensity pwm bit 3~0 ccpwm3~ccpwm0 : offset value for led module color c pwm note: 1. this register will be updated every column application program. 2. this register is only available in auto mode. name l ? cr ? l ? cr ? l ? cr5 l ? cr4 l ? cr3 l ? cr2 l ? cr1 l ? cr0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 lfcr7~lfcr0 : these b its d etermine t he t ime i nterval, ( lfcr+1) l ed f rames, t o c heck wh ether t o modify the corresponding pwm duty data in the led ram or not according to the current pwm mode. note: 1. this register will be updated every (lfcr+1) led frames. 2. this register is only available in auto mode. name racm4 racm3 racm2 racm1 racm0 r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 bit 7~5 unimplemented, read as 0 bit 4 racm4 : t o store led page a com_m and module 4 pwm function output enable or disable control 0: disable 1: enable bit 3 racm3 : t o store led page a com_m and module 3 pwm function output enable or disable control 0: disable 1: enable bit 2 racm2 : t o store led page a com_m and module 2 pwm function output enable or disable control 0: disable 1: enable bit 1 racm1 : t o store led page a com_m and module 1 pwm function output enable or disable control 0: disable 1: enable bit 0 racm0 : t o store led page a com_m and module 0 pwm function output enable or disable control 0: disable 1: enable note: 1. if the p wm function output bit is dis abled, the hardw are w ill not plus or minus the corresponding offset value and also not restore to the led ram. 2. this register is only available in auto mode.
rev. 1.20 230 ? e ??? a ?? 1 ?? 201 ? rev. 1.20 231 ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu rce rs ht66fb574/HT66FB576 b 7 6 5 4 2 name racm ? racm ? racm5 racm4 racm3 racm2 racm1 racm0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 racm7 : t o store led page a com_m and module 7 pwm function output enable or disable control 0: disable 1: enable bit 6 racm6 : t o store led page a com_m and module 6 pwm function output enable or disable control 0: disable 1: enable bit 5 racm5 : t o store led page a com_m and module 5 pwm function output enable or disable control 0: disable 1: enable bit 4 racm4 : t o store led page a com_m and module 4 pwm function output enable or disable control 0: disable 1: enable bit 3 racm3 : t o store led page a com_m and module 3 pwm function output enable or disable control 0: disable 1: enable bit 2 racm2 : t o store led page a com_m and module 2 pwm function output enable or disable control 0: disable 1: enable bit 1 racm1 : t o store led page a com_m and module 1 pwm function output enable or disable control 0: disable 1: enable bit 0 racm0 : t o store led page a com_m and module 0 pwm function output enable or disable control 0: disable 1: enable note: 1. if the pwm function output bit is disabled, the hardware will not plus or minus the corresponding offset value and also not restore to the led ram. 2. this register is only available in auto mode.
rev. 1.20 230 ?e???a?? 1?? 201? rev. 1.20 231 ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu rce rs HT66FB576 b 7 6 5 4 2 name racm ? racme racmd racmc racmb racma racm9 racm8 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 racmf : t o store led page a com_m and module f pwm function output enable or disable control 0: disable 1: enable bit 6 racme : t o store led page a com_m and module e pwm function output enable or disable control 0: disable 1: enable bit 5 racmd : t o store led page a com_m and module d pwm function output enable or disable control 0: disable 1: enable bit 4 racmc : t o store led page a com_m and module c pwm function output enable or disable control 0: disable 1: enable bit 3 racmb : t o store led page a com_m and module b pwm function output enable or disable control 0: disable 1: enable bit 2 racma : t o store led page a com_m and module a pwm function output enable or disable control 0: disable 1: enable bit 1 racm9 : t o store led page a com_m and module 9 pwm function output enable or disable control 0: disable 1: enable bit 0 racm8 : t o store led page a com_m and module 8 pwm function output enable or disable control 0: disable 1: enable note: 1. if the pwm function output bit is disabled, the hardware will not plus or minus the corresponding offset value and also not restore to the led ram. 2. this register is only available in auto mode.
rev. 1.20 232 ? e ??? a ?? 1 ?? 201 ? rev. 1.20 233 ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu rbce rs ht66fb572 b 7 6 5 4 2 name rbcm4 rbcm3 rbcm2 rbcm1 rbcm0 r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 bit 7~5 unimplemented, read as 0 bit 4 rbcm4 : t o store led page b com_m and module 4 pwm function output enable or disable control 0: disable 1: enable bit 3 rbcm3 : t o store led page b com_m and module 3 pwm function output enable or disable control 0: disable 1: enable bit 2 rbcm2 : t o store led page b com_m and module 2 pwm function output enable or disable control 0: disable 1: enable bit 1 rbcm1 : t o store led page b com_m and module 1 pwm function output enable or disable control 0: disable 1: enable bit 0 rbcm0 : t o store led page b com_m and module 0 pwm function output enable or disable control 0: disable 1: enable note: 1. if the pwm function output bit is disabled, the hardware will not plus or minus the corresponding offset value and also not restore to the led ram. 2. this register is only available in auto mode. name rbcm ? rbcm ? rbcm5 rbcm4 rbcm3 rbcm2 rbcm1 rbcm0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 rbcm7 : t o store led page b com_m and module 7 pwm function output enable or disable control 0: disable 1: enable bit 6 rbcm6 : t o store led page b com_m and module 6 pwm function output enable or disable control 0: disable 1: enable bit 5 rbcm5 : t o store led page b com_m and module 5 pwm function output enable or disable control 0: disable 1: enable bit 4 rbcm4 : t o store led page b com_m and module 4 pwm function output enable or disable control 0: disable 1: enable
rev. 1.20 232 ?e???a?? 1?? 201? rev. 1.20 233 ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu bit 3 : t o store led page b com_m and module 3 pwm function output enable or disable control 0: disable 1: enable bit 2 : t o store led page b com_m and module 2 pwm function output enable or disable control 0: disable 1: enable bit 1 : t o store led page b com_m and module 1 pwm function output enable or disable control 0: disable 1: enable bit 0 : t o store led page b com_m and module 0 pwm function output enable or disable control 0: disable 1: enable note: 1. if the pwm function output bit is disabled, the hardware will not plus or minus the corresponding offset value and also not restore to the led ram. 2. this register is only available in auto mode. rbcme1 register C HT66FB576 bit 7 6 5 4 3 2 1 0 name rbcm ? rbcme rbcmd rbcmc rbcmb rbcma rbcm9 rbcm8 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 : t o store led page b com_m and module f pwm function output enable or disable control 0: disable 1: enable bit 6 : t o store led page b com_m and module e pwm function output enable or disable control 0: disable 1: enable bit 5 : t o store led page b com_m and module d pwm function output enable or disable control 0: disable 1: enable bit 4 : t o store led page b com_m and module c pwm function output enable or disable control 0: disable 1: enable bit 3 : t o store led page b com_m and module b pwm function output enable or disable control 0: disable 1: enable bit 2 : t o store led page b com_m and module a pwm function output enable or disable control 0: disable 1: enable bit 1 : t o store led page b com_m and module 9 pwm function output enable or disable control 0: disable 1: enable
rev. 1.20 234 ? e ??? a ?? 1 ?? 201 ? rev. 1.20 235 ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu bit 0 : t o store led page b com_m and module 8 pwm function output enable or disable control 0: disable 1: enable note: 1. if the pwm function output bit is disabled, the hardware will not plus or minus the corresponding offset value and also not restore to the led ram. 2. this register is only available in auto mode. lmnir register bit 7 6 5 4 3 2 1 0 name mnie mnid5 mnid4 mnid3 mnid2 mnid1 mnid0 r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 bit 7 : module n intensity pwm function enable or disable control 0: disable, intensity pwm counter = 0 1: enable bit 6 unimplemented, read as 0 bit 5~0 : duty data for module n 6-bit intensity pwm lmncar register bit 7 6 5 4 3 2 1 0 name mncae mncad5 mncad4 mncad3 mncad2 mncad1 mncad0 r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 bit 7 : module n color a pwm function enable or disable control 0: disable, color a pwm counter = 0 1: enable bit 6 unimplemented, read as 0 bit 5~0 : duty data for module n 6-bit color a pwm lmncbr register bit 7 6 5 4 3 2 1 0 name mncbe mncbd5 mncbd4 mncbd3 mncbd2 mncbd1 mncbd0 r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 bit 7 : module n color b pwm function enable or disable control 0: disable, color b pwm counter = 0 1: enable bit 6 unimplemented, read as 0 bit 5~0 : duty data for module n 6-bit color b pwm lmnccr register bit 7 6 5 4 3 2 1 0 name mncce mnccd5 mnccd4 mnccd3 mnccd2 mnccd1 mnccd0 r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 bit 7 : module n color c pwm function enable or disable control 0: disable, color c pwm counter = 0 1: enable
rev. 1.20 234 ?e???a?? 1?? 201? rev. 1.20 235 ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu bit 6 unimplemented, read as 0 bit 5~0 : duty data for module n 6-bit color c pwm pwmctl0 register bit 7 6 5 4 3 2 1 0 name pwmn1 pwmn0 pwmck1 pwmck0 ldcome ldcom2 ldcom1 ldcom0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 : number of pwm output each com 00: 3 times pwm waveform output 01: 2 times pwm waveform output 10: 1 time pwm waveform output 11: 4 times pwm waveform output these bits can be changed when the pwm for rgb led function is confgured in manual mode or the pwmge bit is disabled. bit 5~4 : led pwm modul e s clock source selection ( f pwm ) 00: 16mhz 01: reserved 10: reserved 11: 12mhz these bits can be changed when the pwm for rgb led function is confgured in manual mode or the pwmge bit is disabled. bit 3 : led hardware com function enable or disable control 0: disable, manual mode, users should fll the related registers by the application program. 1: enable, auto mode, the led hardware automatically completes the related duty, mode operation and com output. bit 2~0 : hardware com output selection 000: com 0 output 001: com 0~1 output 010: com 0~2 output 011: com 0~3 output 100: com 0~4 output 101: com 0~5 output 110: com 0~6 output 111: com 0~7 output note: t he hardwa re a lways c hooses t he se lected com(s) t o out put a ccording t he data in ldcom2~ldcm0. but in the condition of m < hardware com output selection value, the hardware wil l keep the correspondi ng pwm waveform output disabled in the extra com . these bits can be changed when the pwm for rgb led function is confgured in manual mode or the pwmge bit is disabled. pwmctl1 register bit 7 6 5 4 3 2 1 0 name uclpd ccolpo comdir uds d3 d2 pwmge psel r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 1 0 0 0 0 0 0 bit 7 : mcu update led ram pwm data control 0: disable ? do not writing to led ram 1: enable ? can writing to led ram the a pplication progra m m ust t ake c are t o pre vent ha rdware dma a nd mcu from writing to the same address ram simultaneously which will result in data error.
rev. 1.20 23 ? ? e ??? a ?? 1 ?? 201 ? rev. 1.20 23? ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu bit 6 : output cco low pulse between two consecutive coms output 0: disable 1: enable the low pulse is between two consecutive coms. bit 5 : com output polarity 0: low active 1: high active bit 4 : pwm mode up/down selection 0: pwm mode=01 indicates down 1: pwm mode=01 indicates up bit 3~2 : reserved; must be set 01 bit 1 : global led hardware function enable or disable control 0: disable 1: enable bit 0 : t o defne which led ram and pwm enable register is in action 0: led page a ram and register 1: led page b ram and register note: led hardware unit should monitor this bit after one frame pwm is completed. pwmilm register bit 7 6 5 4 3 2 1 0 name ilm5 ilm4 ilm3 ilm2 ilm1 ilm0 r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7~6 unimplemented, read as 0 bit 5~0 : these bits are used in pwm mode, up/down mode and breathing modes, for intensity pwm. if the pwm duty is less than this value, the pwm of fset value will change to lmos[3:0]. note: the pwm ihm value must be greater than the pwm ilm value since the hardware has no mistake-proof fuction. pwmalm register bit 7 6 5 4 3 2 1 0 name calm5 calm4 calm3 calm2 calm1 calm0 r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7~6 unimplemented, read as 0 bit 5~0 : these bi ts a re use d i n pw m m ode, up/ down m ode a nd br eathing m odes, fo r c olor a p wm. if the p wm duty is les s than this value, the p wm of fset value changes to lmos[3:0]. note: the pwmahm value must be greater than the pwmalm value since the hardware has no mistake-proof fuction.
rev. 1.20 23? ?e???a?? 1?? 201? rev. 1.20 23 ? ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu mblm rs b 7 6 5 4 2 name cblm5 cblm4 cblm3 cblm2 cblm1 cblm0 r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7~6 unimplemented, read as 0 bit 5~0 cblm5~cblm0 : these bi ts a re use d i n pw m m ode, up/ down m ode a nd br eathing m odes, fo r c olor b p wm. if the p wm duty is les s than this value, the p wm of fset value changes to lmos[3:0]. note: t he pwmbhm va lue m ust be gre ater t han t he pwmblm va lue si nce t he hardware has no mistake-proof fuction. name cclm5 cclm4 cclm3 cclm2 cclm1 cclm0 r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7~6 unimplemented, read as 0 bit 5~0 cclm5~cclm0 : these bi ts a re use d i n pw m m ode, up/ down m ode a nd br eathing m odes, fo r c olor c p wm. if the p wm duty is les s than this value, the p wm of fset value changes to lmos[3:0]. note: t he pwmchm va lue m ust be gre ater t han t he pwmclm va lue si nce t he hardware has no mistake-proof fuction. name ihm5 ihm4 ihm3 ihm2 ihm1 ihm0 r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 bit 7~6 unimplemented, read as 0 bit 5~0 ihm5~ihm0 : these bits are used in pwm mode, up/down mode and breathing modes, for intensity pwm. if the pwm duty is greater than this value, the pwm of fset value will change to hmos[3:0]. note: the pwm ihm value must be greater than the pwm ilm value since the hardware has no mistake-proof fuction.
rev. 1.20 238 ? e ??? a ?? 1 ?? 201 ? rev. 1.20 239 ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu mhm rs b 7 6 5 4 2 name cahm5 cahm4 cahm3 cahm2 cahm1 cahm0 r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 bit 7~6 unimplemented, read as 0 bit 5~0 cahm5~cahm0 : these bits are used in pwm mode, up/down mode and breathing modes, for color a pwm. if the pwm duty is greater than this value, the pwm of fset value changes to hmos[3:0]. note: the pwmahm value must be greater than the pwmalm value since the hardware has no mistake-proof fuction. name cbhm5 cbhm4 cbhm3 cbhm2 cbhm1 cbhm0 r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 bit 7~6 unimplemented, read as 0 bit 5~0 cbhm5~cbhm0 : these bits are used in pwm mode, up/down mode and breathing modes, for color b pwm. if the pwm duty is greater than this value, the pwm of fset value changes to hmos[3:0]. note: t he pwmbhm va lue m ust be gre ater t han t he pwmblm va lue si nce t he hardware has no mistake-proof fuction. name cchm5 cchm4 cchm3 cchm2 cchm1 cchm0 r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 bit 7~6 unimplemented, read as 0 bit 5~0 cchm5~cchm0 : these bits are used in pwm mode, up/down mode and breathing modes, for color c pwm. if the pwm duty is greater than this value, the pwm of fset value changes to hmos[3:0]. note: t he pwmchm va lue m ust be gre ater t han t he pwmclm va lue si nce t he hardware has no mistake-proof fuction. name hmos3 hmos2 hmos1 hmos0 lmos3 lmos2 lmos1 lmos0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~4 hmos3~hmos0 : defne pwm offset value when pwm duty is greater than high limit when the pwm duty is greater than the high limit, pwmihm, pwmahm, pwmbhm or pwmchm, the pwm offset value will change to hmos[3:0].
rev. 1.20 238 ?e???a?? 1?? 201? rev. 1.20 239 ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu bit 3~0 : defne pwm offset value when pwm duty is less than low limit when the pwm duty is less than the low limit, pwmilm, pwmalm, pwmblm or pwmclm, the pwm offset value will change to lmos[3:0]. note: 1. this register is only available in auto mode. 2. the intensity , color a, color b or color c of fset value will change from their origianl value defned in the lcio0 or lcio1 register to hmos[3:0] or lmos[3:0] when t he pwm duty is greater than the high limit, pwmihm, pwmahm, pwmbhm or pwmchm, or less than the low limit, pwmilm, pwmalm, pwmblm or pwmclm. hlmd register bit 7 6 5 4 3 2 1 0 name hlmd5 hlmd4 hlmd3 hlmd2 hlmd1 hlmd0 r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 bit 7~6 unimplemented, read as 0 bit 5~0 : defne pwm duty high limit data for intensity, color a, color b and color c duty pwm note: 1. this register is only available in auto mode. 2. t he hlmd value must be greater than the llmd value since the hardware has no mistake- proof fuction. 3. the initial pwm duty should be between llmd and hlmd, otherwise the situation where the duty value is beyond the range of llmd to hlmd will occur at frst. llmd register bit 7 6 5 4 3 2 1 0 name llmd5 llmd4 llmd3 llmd2 llmd1 llmd0 r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7~6 unimplemented, read as 0 bit 5~0 : defne pwm duty low limit data for intensity, color a, color b and color c duty pwm note: 1. this register is only available in auto mode. 2. t he hlmd value must be greater than the llmd value since the hardware has no mistake- proof fuction. 3. the initial pwm duty should be between llmd and hlmd, otherwise the situation where the duty value is beyond the range of llmd to hlmd will occur at frst. led pwm modules the devices provide n led pwm modules, each module contains four pwms, they are three 6-bit color pwms, namely capwm, cbpwm and ccpwm, and one 6-bit intensity pwm, namely ipwm. each led pwm module has the same architecture, the number of pwm segment outputs is 3(n+1) decided by the selected module number n. device total pwm module 4(n+1) color pwm 3(n+1) intensity pwm (n+1) ht ??? b5 ? 2 20 15 5 ht ??? b5 ? 4 32 24 8 ht ??? b5 ?? ? 4 48 1 ? note: n=0~4 for ht66fb572; n=0~7 for ht66fb574; n=0~f for HT66FB576.
rev. 1.20 240 ? e ??? a ?? 1 ?? 201 ? rev. 1.20 241 ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu led cm u the devices provide a led com output unit used to output external enable m com control signal. by using the t ime shared method combined with led pwm modules, 3(n+1)(m+1) led segment pwm outputs can be generated, it can implement a up to (m+1)(n+1) groups of rg b led application. the number of led com outputs is determined by the ldcom[2:0] bits and m, 1 to (m+1) com outputs can be selected. there are two pages of led ram, led page a ram and led page b ram, each of which is used to respective ly record pwm duty data, mode state and whether the pwm signal is enabled or not for (m+1)(n+1) rgb led. each page is compose of 4(n+1)(m+1) bytes ram and (m+1) bytes pwm module enable led registers. users can determine which led page ram is in action by the psel bit. switching to the next page should not be performed until the last page has been completed. the l ed r am & r egister t ransfer u nit i s u sed t o c hange t he l ed p age r am d ata t o t he l ed pwm module related registers data, and generate (m+1)3(n+1) led segment pwm signals. in addition, the unit is also used for the addition or subtraction operation on led ram according to the dif ferent pwm modes, and then the results will be written back to the corresponding led page ram address. for the of fset data added to or subtracted from and the time interval of addition or substraction, refer to the lcio0, lcio1 and lfcr register data. whether t he a bove l ed a uto m ode ope ration i s e nabled or not i s de termined by t he l dcome bit. if the ldcome bit is cleared to zero, users can also control the pwm output in manual mode through led pwm modules, pwm register enable signals and duty data. the devices provide an area of embedded data memory for the rgb led. this data area is known as the led memory .more the data memory . for more detailed led memory information, refer to the data memory section. the led memory is subdivided into two pages, each size of which is 512 bytes. the led ram i s subdi vided i nto 8 c olumns, na mely col umn 0~col umn 7, c orresponding re spectively t o com0~com7. the led ram data can be allocated as follows:
rev. 1.20 240 ?e???a?? 1?? 201? rev. 1.20 241 ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu col?mn 0 col?mn 1 col?mn m col?mn ? col?mn ? col?mn 0 col?mn 1 col?mn m col?mn ? col?mn ? pwmi_cmm0 pwmca_cmm0 pwmcb_cmm0 pwmcc_cmm0 pwmi_cmmn pwmca_cmmn pwmcb_cmmn pwmcc_cmmn bit ?~?: define pwm mode 00: ?ixed pwm val?e 01: pwm val?e up o? down defined ?? the uds ?it 10: pwm val?e up in ??eathing mode 11: pwm val?e down in ??eathing mode if these ?its a?e 10 o? 11? the state is ?pdated ?? the ci?c?it in ??eathing mode. bit 5~0: define pwm val?e ? ? 5 4 3 2 1 0 led ram_a led ram_b led memo?? allocation note: n=0~4 for ht66fb572; n=0~7 for ht66fb574; n=0~f for HT66FB576, while m=0~7 for the series devices. led ram_a: secto ? 8 led ram_b: secto ? 12 col ? mn0 80h~b ? h led ram_a: secto ? 8 led ram_b: secto ? 10 col ? mn0 80h~9 ? h led ram_a: secto ? 8 led ram_b: secto ? 10 col ? mn0 80h~93h col ? mn1 c0h~ ?? h col ? mn1 a0h~b ? h col ? mn1 a0h~b3h led ram_a: secto ? 9 led ram_b: secto ? 12 col ? mn2 80h~b ? h col ? mn2 c0h~d ? h col ? mn2 c0h~d3h col ? mn3 c0h~ ?? h col ? mn3 e0h~ ?? h col ? mn3 e0h~ ? 3h led ram_a: secto ? 10 led ram_b: secto ? 12 col ? mn4 80h~b ? h led ram_a: secto ? 9 led ram_b: secto ? 11 col ? mn4 80h~9 ? h led ram_a: secto ? 9 led ram_b: secto ? 11 col ? mn4 80h~93h col ? mn5 c0h~ ?? h col ? mn5 a0h~b ? h col ? mn5 a0h~b3h led ram_a: secto ? 11 led ram_b: secto ? 12 col ? mn ? 80h~b ? h col ? mn ? c0h~d ? h col ? mn ? c0h~d3h col ? mn ? c0h~ ?? h col ? mn ? e0h~ ?? h col ? mn ? e0h~ ? 3h each column has 4(n+1) bytes data, the data is recorded as follows: pwm m odule 0 d ata pwmi_c0m0 ----- 1 byte pwmca_c0m0 ----- 1 byte pwmcb_c0m0 ----- 1 byte pwmcc_c0m0 ----- 1 byte pwm m odule 1 d ata pwmi_c1m1 pwmca_c1m1 pwmcb_c1m1 pwmcc_c1m1 : :
rev. 1.20 242 ? e ??? a ?? 1 ?? 201 ? rev. 1.20 243 ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu pwm mo dule n d ata pwmi_cmmn pwmca_cmmn pwmcb_cmmn pwmcc_cmmn the format of each byte data is as follows: bit 7~6 defne pwm mode 00: output a fxed pwm value 01: after the pwm vaule output, plus or minus the corresponding offset value, and store back to led ram, the addition or subtraction operation is determined by the uds bit. 10: in breathing mode up state, plus the corresponding offset value, and store back to led ram 11: in breathing mode down state, minus the corresponding offset value, and store back to led ram in bre athing m ode, i f t he l ed ram dut y da ta i s i ncreased t o t he m aximum va lue, the h ardware wi ll a utomatically c hange t he pw m m ode t o 11, t he b reathing m ode down state. simil arly, if the led ram duty data is decreased to the minimum value in b reathing m ode, t he h ardware wi ll a utomatically c hange t he pw m m ode t o 10, the breathing mode up state. bit 5~0 pwm duty data the rgb led has two interrupt output signals, ledint and udint . after one frame, i.e. (m+1)3(n+1) led segment pwm cco signals, is completed by the hardware, a ledint signal will b e g enerated t o i nform t he mc u. i n pw m up o r do wn m ode, wh ich i s d ecided b y t he uds b it, if the pwm duty in led ram is increased or decreased by the of fset value, and reaches the hlmd or llmd register value, the hardware will inform the mcu using the udint signal. the t iming of ha rdware l ed pwm, t hat i s 3(n+1) l ed segme nt pw m a nd (m +1) com, i s a s follows: com0 led com time slot led f?ame inte???pt ?eq?est flag ena?le the co??esponding pwm ?egiste? and o?tp?t pwm c?cle com 1 com m com m-1 com 1 com m com m-1 com 0 cco[2:0] cco[5:3] cco[4?:45] a?o?t 10?s ?etween com m-1 and com m fo? non-ove?lap t t led com c?cle com m led pwm timing diag?am note: n=0~4 for ht66fb572; n=0~7 for ht66fb574; n=0~f for HT66FB576, while m=0~7 for the series devices.
rev. 1.20 242 ?e???a?? 1?? 201? rev. 1.20 243 ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu the pwm module rgbn pwm output waveform is as follows: mod?le ?-?it intensit? pwm pe?iod mod?le ?-?it colo? pwm (d?t? val?e = 2) mod?le ?-?it intensit? pwm mod?le rgb pwm o?tp?t wavefo?m mod?le ?-?it colo? pwm pe?iod 1 ?4 1 ?4 mod?le ?-?it intensit? pwm pe?iod colo? pwm d?t? c?cles intensit? pwm d?t? c?cles intensit? pwm d?t? c?cles com o?tp?t wavefo?m (each com = 2 pwm pe?od) mod?le rgb pwm o?tp?t wavefo?m sta?t end config??e pwm o?tp?t n?m?e? each com ?? pwmn[1:0] config??e how man? led f?ames to ?pdate led ram data ?? l?cr ?egiste? config??e the co??esponding colo? pwm and intensit? pwm offset data ?? lcio0? lico1 & hlmos registe? config??e the limit ?egiste? hlmd? llmd config??e the co??esponding limit ?egiste? pwmxhm? pwmxlm whe?e x= i? a? b & c in o?de? to decide which offset ?egiste? lcio0 & lico1 o? hlmos is in ope?ation. ena?le led ha?dwa?e unit ?? set ldcome ?it and pwmge ?it config??e pwm clock so??ce f?eq?enc? ?? pwmck[1:0] config??e how man? led com o?tp?t ?? ldcom[2:0] pwm o?tp?t cont?ol ?low cha?t
rev. 1.20 244 ? e ??? a ?? 1 ?? 201 ? rev. 1.20 245 ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu csa c led d there is an accurate constant current driver which is specifically designed for led display applications. the devices provide n-channel stable and constant current outputs for driving leds. the output constant current is deter mined by the current gain selection bits, ccg[1:0], rgbn pwm input a nd a n e xternal re sistor, r ext , whi ch i s c onnected be tween t he re xt pi n a nd ground. t he current level is set according to the r ext value. the current variation between channels is less than 3% while the current variation between dif ferent devices is less than 6%. the characteristic curve in the saturation region is fat. the output current remains constant regardless of the led forward voltage value. the constant current can be calculated using the following formula: i ccon = 25ma / (r rext /1800) gain if the ccen bi t is set hi gh and the rgbn signal is in a logic low level, the ccon is driven by a constant current. otherwise the ccon is in a foating status. reg?lato? and dac ccon mod?le 0 mod?le n i out rgbn rext ccen ledvssn/4 ccvdd ccvss ccg[1:0] note: 1. n=0~14 for ht66fb572, n=0~23 for ht66fb574, n=0~47 for HT66FB576. 2. module n stands for module 0 ~ module 4 for ht66fb572; module n stands for module 0 ~ module 7 for ht66fb574; module n stands for module 0 ~ module f for HT66FB576. 3. ledvssn/4 stands for every 4 cco outputs sharing one ledvss. name ccen d ? d5 d4 ccg1 ccg0 r/w r/w r/w r/w r/w r/w r/w por 0 0 1 0 0 1 bit 7 ccen : constant current function enable or disable control 0: disable 1: enable if the ccen bit is set high and the rgbn signal is in a logic low level, the ccon is driven by a constant current. otherwise the ccon is in a foating status. bit 6~4 d6~d4 : reserved bits. these bits cannot be used and must be fxed as 010. bit 3~2 unimplemented, read as 0
rev. 1.20 244 ?e???a?? 1?? 201? rev. 1.20 245 ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu bit 1~0 : constant current gain selection 00: gain=1.0, i ccon =20ma @ r ext =1800 01: gain=1.4, i ccon =30ma @ r ext =1800 10: gain=1.8, i ccon =40ma @ r ext =1800 11: gain=2.4, i ccon =50ma @ r ext =1800 interrupts interrupts are an important part of any microcontroller s ystem. when an external event or an internal function such as a t imer module or an a/d converter requires microcontroller attention, their corresponding interrupt will enforce a temporary suspension of the main program allowing the microcontroller to direct attention to their respective needs. the devices contain several external interrupt and internal interrupts functions. the external interrupts are generated by the action of the external int0~int1 pins, while the internal interrupts are generated by various internal functions such as the tms, comparators, lvd and the a/d converter. interrupt registers overall interrupt control, w hich bas ically means the s etting of reques t flags w hen certain microcontroller conditions occur and the setting of interrupt enable bits by the application program, is controlled by a series of registers, located in the special purpose data memory , as shown in the accompanying table. the number of regis ters falls into three categories. the firs t is the intc0~intc3 registers which setup the primary interrupts, the second is the mfi0~mfi5 registers which setup the multi-function interrupts. finally there is an integ register to setup the external interrupt trigger edge type. each regist er contai ns a number of enable bit s to enable or disa ble indivi dual regist ers as wel l as interrupt flags to indicate the presence of an interrupt request. the naming convention of these follows a specifc pattern. first is listed an abbreviated interrupt type, then the (optional) number of that interrupt followed by either an e for enable/disable bit or f for request fag. function enable bit request flag notes glo ? al emi intn pin intne intn ? n=0 o ? 1 usb usbe usb ? compa ? ato ? cpne cpn ? n=0 o ? 1 led f ? ame lede led ? led up/down ude ud ? sim sime sim ? spia spiae spia ? time base tbne tbn ? n=0 o ? 1 m ? lti-f ? nction m ? ne m ? n ? n=0~5 a/d conve ? te ? ade ad ? uart ure ur ? eeprom dee de ? lvd lve lv ? stm stmpe stmp ? stmae stma ? ptm ptmnpe ptmnp ? n=0~2 ptmnae ptmna ? interrupt register bit naming conventions
rev. 1.20 24 ? ? e ??? a ?? 1 ?? 201 ? rev. 1.20 24? ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu rs a b 7 6 5 4 2 integ int1s1 int1s0 int0s1 int0s0 intc0 usb ? int1 ? int0 ? usbe int1e int0e emi intc1 m ? 1 ? m ? 0 ? cp1 ? cp0 ? m ? 1e m ? 0e cp1e cp0e intc2 sim ? m ? 4 ? m ? 3 ? m ? 2 ? sime m ? 4e m ? 3e m ? 2e intc3 m ? 5 ? tb1 ? tb0 ? spia ? m ? 5e tb1e tb0e spiae m ? i0 stma ? stmp ? stmae stmpe m ? i1 ptm0a ? ptm0p ? ptm0ae ptm0pe m ? i2 ptm1a ? ptm1p ? ptm1ae ptm1pe m ? i3 ptm2a ? ptm2p ? ptm2ae ptm2pe m ? i4 ud ? led ? ude lede m ? i5 de ? ad ? ur ? lv ? dee ade ure lve inte???pt registe?s list integ registe? bit ? ? 5 4 3 2 1 0 name int1s1 int1s0 int0s1 int0s0 r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~4 unimplemented, read as 0 bit 3~2 int1s1~int1s0 : interrupt edge control for int1 pin 00: disable 01: rising edge 10: falling edge 11: rising and falling edges bit 1~0 int0s1~int0s0 : interrupt edge control for int0 pin 00: disable 01: rising edge 10: falling edge 11: rising and falling edges name usb ? int1 ? int0 ? usbe int1e int0e emi r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 bit 7 unimplemented, read as 0 bit 6 usbf : usb interrupt request fag 0: no request 1: interrupt request bit 5 int1f : int1 interrupt request fag 0: no request 1: interrupt request bit 4 int0f : int0 interrupt request fag 0: no request 1: interrupt request bit 3 usbe : usb interrupt control 0: disable 1: enable
rev. 1.20 24? ?e???a?? 1?? 201? rev. 1.20 24 ? ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu bit 2 : int1 interrupt control 0: disable 1: enable bit 1 : int0 interrupt control 0: disable 1: enable bit 0 : global interrupt control 0: disable 1: enable intc1 register bit 7 6 5 4 3 2 1 0 name m ? 1 ? m ? 0 ? cp1 ? cp0 ? m ? 1e m ? 0e cp1e cp0e r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 : multi-function interrupt 1 request fag 0: no request 1: interrupt request bit 6 : multi-function interrupt 0 request fag 0: no request 1: interrupt request bit 5 : comparator 1 interrupt request fag 0: no request 1: interrupt request bit 4 : comparator 0 interrupt request fag 0: no request 1: interrupt request bit 3 : multi-function interrupt 1 interrupt control 0: disable 1: enable bit 2 : multi-function interrupt 0 interrupt control 0: disable 1: enable bit 1 : comparator 1 interrupt control 0: disable 1: enable bit 0 : comparator 0 interrupt control 0: disable 1: enable
rev. 1.20 248 ? e ??? a ?? 1 ?? 201 ? rev. 1.20 249 ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu tc2 rs b 7 6 5 4 2 name sim ? m ? 4 ? m ? 3 ? m ? 2 ? sime m ? 4e m ? 3e m ? 2e r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 simf : sim interrupt request fag 0: no request 1: interrupt request bit 6 mf4f : multi-function interrupt 4 request fag 0: no request 1: interrupt request bit 5 mf3f : multi-function interrupt 3 request fag 0: no request 1: interrupt request bit 4 mf2f : multi-function interrupt 2 request fag 0: no request 1: interrupt request bit 3 sime : sim interrupt control 0: disable 1: enable bit 2 mf4e : multi-function interrupt 4 control 0: disable 1: enable bit 1 mf3e : multi-function interrupt 3 control 0: disable 1: enable bit 0 mf2e : multi-function interrupt 2 control 0: disable 1: enable
rev. 1.20 248 ?e???a?? 1?? 201? rev. 1.20 249 ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu tc rs b 7 6 5 4 2 name m ? 5 ? tb1 ? tb0 ? spia ? m ? 5e tb1e tb0e spiae r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 mf5f : multi-function interrupt 5 request fag 0: no request 1: interrupt request bit 6 tb1f : t ime base1 interrupt request fag 0: no request 1: interrupt request bit 5 tb0f : t ime base 0 interrupt request fag 0: no request 1: interrupt request bit 4 spiaf : spia interrupt request fag 0: no request 1: interrupt request bit 3 mf5e : multi-function interrupt 5 control 0: no request 1: interrupt request bit 2 tb1e : t ime base1 interrupt control 0: disable 1: enable bit 1 tb0e : t ime base 0 interrupt control 0: disable 1: enable bit 0 spiae : spia interrupt control 0: disable 1: enable name stma ? stmp ? stmae stmpe r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~6 unimplemented, read as 0 bit 5 stmaf : stm comparator a match interrupt request fag 0: no request 1: interrupt request bit 4 stmpf : stm comparator p match interrupt request fag 0: no request 1: interrupt request bit 3~2 unimplemented, read as 0 bit 1 stmae : stm comparator a match interrupt control 0: disable 1: enable bit 0 stmpe : stm comparator p match interrupt control 0: disable 1: enable
rev. 1.20 250 ? e ??? a ?? 1 ?? 201 ? rev. 1.20 251 ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu mf rs b 7 6 5 4 2 name ptm0a ? ptm0p ? ptm0ae ptm0pe r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~6 unimplemented, read as 0 bit 5 ptm0af : ptm0 comparator a match interrupt request fag 0: no request 1: interrupt request bit 4 ptm0pf : ptm0 comparator p match interrupt request fag 0: no request 1: interrupt request bit 3~2 unimplemented, read as 0 bit 1 ptm0ae : ptm0 comparator a match interrupt control 0: disable 1: enable bit 0 ptm0pe : ptm0 comparator p match interrupt control 0: disable 1: enable name ptm1a ? ptm1p ? ptm1ae ptm1pe r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~6 unimplemented, read as 0 bit 5 ptm1af : ptm1 comparator a match interrupt request fag 0: no request 1: interrupt request bit 4 ptm1pf : ptm1 comparator p match interrupt request fag 0: no request 1: interrupt request bit 3~2 unimplemented, read as 0 bit 1 ptm1ae : ptm1 comparator a match interrupt control 0: disable 1: enable bit 0 ptm1pe : ptm1 comparator p match interrupt control 0: disable 1: enable
rev. 1.20 250 ?e???a?? 1?? 201? rev. 1.20 251 ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu mf rs b 7 6 5 4 2 name ptm2a ? ptm2p ? ptm2ae ptm2pe r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~6 unimplemented, read as 0 bit 5 ptm2af : ptm2 comparator a match interrupt request fag 0: no request 1: interrupt request bit 4 ptm2pf : ptm2 comparator p match interrupt request fag 0: no request 1: interrupt request bit 3~2 unimplemented, read as 0 bit 1 ptm2ae : ptm2 comparator a match interrupt control 0: disable 1: enable bit 0 ptm2pe : ptm2 comparator p match interrupt control 0: disable 1: enable name ud ? led ? ude lede r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~6 unimplemented, read as 0 bit 5 udf : led up/down interrupt request fag 0: no request 1: interrupt request bit 4 ledf : led frame interrupt request fag 0: no request 1: interrupt request bit 3~2 unimplemented, read as 0 bit 1 ude : led up/down interrupt control 0: disable 1: enable bit 0 lede : led frame interrupt control 0: disable 1: enable
rev. 1.20 252 ? e ??? a ?? 1 ?? 201 ? rev. 1.20 253 ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu mf5 rs b 7 6 5 4 2 name de ? ad ? ur ? lv ? dee ade ure lve r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 def : data eeprom interrupt request fag 0: no request 1: interrupt request bit 6 adf : a/d converter interrupt request fag 0: no request 1: interrupt request bit 5 urf : uart interrupt request fag 0: no request 1: interrupt request bit 4 lvf : lvd interrupt request fag 0: no request 1: interrupt request bit 3 dee : data eeprom interrupt control 0: disable 1: enable bit 2 ade : a/d converter interrupt control 0: disable 1: enable bit 1 ure : uart interrupt control 0: disable 1: enable bit 0 lve : lvd interrupt control 0: disable 1: enable when the conditions for an interrupt event occur , such as a tm comparator p or comparator a match or a/d conversion completion etc., the relevant interrupt request fag will be set. whether the request fag actually generates a program jump to the relevant interrupt vector is determined by the condition of the interrupt enabl e bit. if the enable bit is set high then the program will jump to its relevant vector; if the enable bit is zero then although the interrupt request fag is set an actual interrupt will not be generated and the program will not jump to the relevant interrupt vector . the global interrupt enable bit, if cleared to zero, will disable all interrupts. when an interrupt is generated, the program counter, which stores the address of the next instruction to be executed, will be transferred onto the stack. the program counter will then be loaded with a new address which will be the value of the corresponding interrupt vector . the microcontroller will then fetch its next instruction from this interrupt vector . the instruction at this vector will usually be a jmp which will jump to another section of program which is known as the interrupt service routine. here is located the code to control the appropriate interrupt. the interrupt service routine must be terminated w ith a reti, w hich retrieves the original p rogram counter address from the st ack a nd a llows t he m icrocontroller t o c ontinue wi th n ormal e xecution a t t he p oint wh ere t he interrupt occurred. the various interrupt enable bits, together with their associated request flags, are shown in the accompanying diagrams with their order of priority . some interrupt sources have their own individual vector w hile others s hare the s ame multi-function interrupt vector . o nce an interrupt
rev. 1.20 252 ?e???a?? 1?? 201? rev. 1.20 253 ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu subroutine is serviced, all the other interrupts will be blocked, as the global interrupt enable bit, emi bit will be cleared automatically . this will prevent any further interrupt nesting from occurring. however, i f ot her i nterrupt re quests oc cur duri ng t his i nterval, a lthough t he i nterrupt wi ll not be immediately serviced, the request fag will still be recorded. if an interrupt requires immediate servicing while the program is alread y in another interrupt service routine, the emi bit should be set after entering the routine, to allow interrupt nesting. if the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the stack pointer is decremented. if immediate service is desired, the stack must be prevented from becoming full. in case of simultaneous requests, the accompanying diagram shows the priority that is applied . all of the interrupt request fags when set will wake-up the devices if it is in sleep or idle mode, however to prevent a wake-up from occurring the corresponding fag should be set before the devices are in sleep or idle mode. inte???pt name req?est ?lags ena?le bits maste? ena?le vecto? emi a?to disa?led in isr p?io?it? high low inte???pts contained within m?lti-??nction inte???pts 10h 14h 04h 0ch 08h 18h 1ch 20h 24h 2ch inte???pt name req?est ?lags ena?le bits int0 pin int0? int0e emi int1 pin int1? int1e emi emi usb usb? usbe m. ??nct. 0 m?0? m?0e emi comp.0 cp0? cp0e emi 30h 34h 3ch sim sim? sime emi spia spia? spiae emi emi m. ??nct. 1 m?1? m?1e ptm0 p ptm0p? ptm0pe ptm0 a ptm0a? ptm0ae emi m. ??nct. 2 m?2? m?2e ptm1 p ptm1p? ptm1pe ptm1 a ptm1a? ptm1ae emi m. ??nct. 3 m?3? m?3e ptm2 p ptm2p? ptm2pe ptm2 a ptm2a? ptm2ae stm p stmp? stmpe stm a stma? stmae emi m. ??nct. 5 m?5? m?5e uart ur? ure a/d ad? ade xxe ena?le bits xx? req?est ?lag? a?to ?eset in isr legend xx? req?est ?lag? no a?to ?eset in isr comp.1 cp1? cp1e emi time base 0 tb0? tb0e emi 38h time base 1 tb1? tb1e emi lvd lv? lve eeprom de? dee 28h emi m. ??nct. 4 m?4? m?4e led ??ame led? lede led up/down ud? ude inte???pt st??ct??e
rev. 1.20 254 ? e ??? a ?? 1 ?? 201 ? rev. 1.20 255 ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu eal s the external interrupts are controlled by signal transitions on the pins int0 and int1. an external interrupt request will take place when the external interrupt request fags, int0f~int1f , are set, which will occur when a transition, whose type is chosen by the edge select bits, appears on the external interrupt pins . t o allow the program to branch to its res pective interrupt vector addres s, the g lobal i nterrupt e nable b it, e mi, a nd r espective e xternal i nterrupt e nable b it, i nt0e~int1e, must first be set. additionally the correct interrupt edge type mus t be selected using the integ register to enable the external interrupt function and to choose the trigger edge type. as the external interrupt pins are pin-shared with i/o pins, they can only be confgured as external interrupt pins if their external interrupt enable bit in the corresponding interrupt register has been set and the external interrupt pin is selected by the corresponding pin-shared function selection bits. the pin must also be setup as an input by setting the corresponding bit in the port control register . when the interrupt is enabled, the stack is not full and the correct transition type appears on the external interrupt pin, a subroutine call to the external interrupt vector , will take place. when the interrupt is serviced, the external interrupt request fags, int0f~int1f , will be automatically reset and the emi bit will be automatically cleared to disable other interrupts. note that any pull-high resistor selections on the external interrupt pins will remain valid even if the pin is used as an external interrupt input. the integ register is used to select the type of active edge that will trigger the external interrupt. a choice of either rising or falling or both edge types can be chosen to trigger an external interrupt. note that the integ register can also be used to disable the external interrupt function. several usb conditions can generate a usb interrupt. when one of these conditions occurs, an interrupt pu lse wi ll be ge nerated t o ge t t he a ttention of t he m icrocontroller. t hese c onditions a re the usb suspended, usb resumed, usb reset and usb endpoint fifo access events. t o allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and usb inte rrupt enable bit, usbe, must frst be set. when the interrupt is enabled, the stack is not full and a ny o f t hese c onditions a re c reated, a su broutine c all t o t he usb i nterrupt v ector, wi ll t ake p lace. when the interrupt is serviced, the usb interrupt request fag, usbf , will be automatically reset and the emi bit will be automatically cleared to disable other interrupts. the comparator interrupts are controlled by the two internal comparators. a comparator interrupt request will take place when the comparator interrupt request fag, cpnf , is set, a situation that will occur when the comparator output bit changes state. t o allow the program to branch to its respective interrupt v ector a ddress, t he g lobal i nterrupt e nable b it, e mi, a nd c omparator i nterrupt e nable b it, cpne, must frst be set. when the interrupt is enabled, the stack is not full and the comparator inputs generate a c omparator out put bi t t ransition, a subrout ine c all t o t he c omparator i nterrupt ve ctor, will take place. when the interrupt is serviced, the comparator interrup t request fag, cpnf , will be automatically reset and the emi bit will be automatically cleared to disable other interrupts. the seri al int erface modul e int errupt, a lso known a s t he sim i nterrupt, wi ll t ake pl ace when the sim interrupt request fag, simf , is set, which occurs when a byte of data has been received or transm itted by t he sim i nterface, or an i 2 c sl ave address ma tch occurs, or an i 2 c bus t ime- out oc curs. t o a llow t he progra m t o bra nch t o i ts re spective i nterrupt ve ctor a ddress, t he gl obal interrupt enable bit, emi, and the serial interface interrupt enable bit, sime, must first be set. when the interrup t is enabled, the stack is not full and any of the above described situations occurs,
rev. 1.20 254 ?e???a?? 1?? 201? rev. 1.20 255 ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu a subrout ine c all t o t he re spective int errupt ve ctor, wi ll t ake pl ace. w hen t he i nterrupt i s se rviced, the se rial in terface in terrupt fa g, simf , wi ll be a utomatically c leared. t he e mi bi t wi ll a lso be automatically cleared to disable other interrupts. the serial peripheral interface interrupt, also known as the spia interr upt, will take place when the spia interrupt reques t f ag, s piaf, is s et, w hich occurs w hen a byte of data has been received or transmitted by the spia interface or an spia incomplete transfer occurs. t o allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and the serial interface int errupt e nable bi t, spiae , m ust frst be se t. w hen t he i nterrupt i s e nabled, t he st ack i s not full and any of the above described situations occurs, a subroutine call to the respective interrupt vector, will take place. when the interrupt is serviced, the serial interface interrupt fag, spiaf , will be automatically cleared. the emi bit will also be automatically cleared to disable other interrupts. the function of the t ime base interrupts is to provide regular time signal in the form of an internal interrupt. they are controlled by the overfow signals from their respective timer functions. when these happens their respective interrupt request flags, tb0f or tb1f will be set. t o allow the program to branch to their respective interrupt vector addresses, the global interrupt enable bit, emi and t ime base enable bits, tb0e or tb1e, must frst be set. when the interrupt is enabled, the stack is not full and the t ime base overfow s, a subroutine call to their res pective vector locations will take place. when the interrupt is serviced, the respective interrupt request fag, tb0f or tb1f , will be automatically reset and the emi bit will be cleared to disable other interrupts. the purpose of the t ime base interrupt is to provide an interrupt signal at fxed time periods. its clock source, f psc , originates from the internal clock source f sys , f sys /4 or f sub and then passes through a divider , the division ratio of which is selected by programming the appropriate bits in the tb0c and tb1c registers to obtain longer interrupt periods whose value ranges. the clock source which i n t urn c ontrols t he t ime b ase i nterrupt p eriod i s se lected u sing t he c lksel1~clksel0 bits in the pscr register. m u x f sys /4 f sys f sub p?escale? clksel[1:0] f psc f psc /2 8 ~ f psc /2 15 m u x m u x tb0[2:0] tb1[2:0] time base 0 inte???pt time base 1 inte???pt tb0on tb1on f psc /2 8 ~ f psc /2 15 time base inte???pts
rev. 1.20 25 ? ? e ??? a ?? 1 ?? 201 ? rev. 1.20 25? ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu scr rs b 7 6 5 4 2 name clksel1 clksel0 r/w r/w r/w por 0 0 bit 7~2 unimplemented, read as 0 bit 1~0 clksel1~clksel0 : prescaler clock source selection 00: f sys 01: f sys /4 1x: f sub name tb0on tb02 tb01 tb00 r/w r/w r/w r/w r/w por 0 0 0 0 bit 7 tb0on : t ime base 0 control 0: disable 1: enable bit 6~3 unimplemented, read as 0 bit 2~0 tb02~tb00 : select t ime base 0 t ime-out period 000: 2 8 /f psc 001: 2 9 /f psc 010: 2 10 /f psc 011: 2 11 /f psc 100: 2 12 /f psc 101: 2 13 /f psc 110: 2 14 /f psc 111: 2 15 /f psc 1c ete t 6 1 name tb1on tb12 tb11 tb10 r/w r/w r/w r/w r/w por 0 0 0 0 bit 7 tb1on : t ime base 1 control 0: disable 1: enable bit 6~3 unimplemented, read as 0 bit 2~0 tb12~tb10 : select t ime base 1 t ime-out period 000: 2 8 /f psc 001: 2 9 /f psc 010: 2 10 /f psc 011: 2 11 /f psc 100: 2 12 /f psc 101: 2 13 /f psc 110: 2 14 /f psc 111: 2 15 /f psc
rev. 1.20 25? ?e???a?? 1?? 201? rev. 1.20 25 ? ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ml s within the devices there are up to six multi-function interrupts. unlike the other independent interrupts, these interrupts have no independent source, but rather are formed from other existing interrupt sources, namely the led frame, led up/down, tm interrupts, a/d converter interrupt, uart interrupt, eeprom interrupt and lvd interrupt. a multi-function interrupt request will take place when any of the multi-function interrupt request flags, mfnf are set. the multi-function interrupt flags will be set when any of their included functions generate an interrupt request fag. t o allow the program to branch to its respective interrupt vector address, when the multi-func tion interrupt is enabled and the stack is not full, and either one of the interrupts contained within each of multi-function interrupt occurs, a subroutine call to one of the multi-function interrupt vectors will take place. when the interrupt is serviced, the related multi- function request fag will be automatically reset and the emi bit will be automatically cleared to disable other interrupts. however, i t m ust be not ed t hat, a lthough t he mul ti-function int errupt fa gs wi ll be a utomatically reset when the interrupt is serviced, the request fags from the original source of the multi-function interrupts will not be automatically reset and must be manually reset by the application program. the led frame interrupt is contained within the multi-function interrupt. an led frame interrupt request will take place when the led frame interrupt request fag, ledf , is set, which occurs when one frame led pwm is completed. t o allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, led frame interrupt enable bit, lede, and associated multi-function interrupt enable bit, must frst be set. when the interrupt is enabled, the stack is not full and one frame led pwm is completed, a subroutine call to the multi-function interrupt vector , will take place. when the led frame interrupt is serviced, the emi bit will be automatically cleared to disable other interrupts, however only the multi-function interrupt request flag will be also automatically clea red. as the ledf fag will not be automatically clear ed, it has to be cleared by the application program. the l ed up/ down int errupt i s c ontained wi thin t he mult i-function int errupt. an l ed up/ down interrupt request will take place when the led up/down interrupt request fag, udf , is set, which occurs when the pwm duty reaches the hlmd or llmd register value in pwm up or down mode respectively. t o allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, em i, led frame interrupt enable bit, u de, and as sociated m ulti-function interrupt enable bit, must frst be set. when the interrupt is enabled, the stack is not full and the pwm duty reaches the hlmd or llmd regist er value in pwm up or down mode re spectively, a subroutine call to the multi-function interrupt vector , will take place. when the led up/down interrupt is serviced, the emi bit will be automatically cleared to disable other interrupts, however only t he mul ti-function i nterrupt re quest fa g wi ll be a lso a utomatically c leared. as t he udf fa g will not be automatically cleared, it has to be cleared by the application program. the a/d converter interrupt is contained within the multi-function interrupt. an a/d converter interrupt request will take place when the a/d converter interrupt request fag, adf , is set, which occurs when the a/d conversion process fnishes. t o allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and a/ d interrupt enable bit, ade , and associated multi-function interrupt enable bit, must frst be set. when the interrupt is enabled, the
rev. 1.20 258 ? e ??? a ?? 1 ?? 201 ? rev. 1.20 259 ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu stack is not full and the a/d conversion process has ended, a subroutine call to the multi-function interrupt vector , will take place. when the a/d converter interrupt is serviced, the emi bit will be automatically clea red to disable other interrupts, however only the multi-function interrupt request fag will be also automatically clea red. as the adf fag will not be automatically cleared, it has to be cleared by the application program. the uar t i nterrupt i s c ontained wi thin t he mu lti-function i nterrupt. se veral i ndividual uar t conditions can generate a uar t interrupt. when one of these conditio ns occurs, an interrupt pulse will be generated to get the attention of the microcontroller . these conditions are a transmitter data register empty , transmitter idle, receiver data available, receiver overrun, address detect and an rx pin wake-up. t o allow the program to branch to the respective interrupt vector addresses, the global interrupt enable bit, emi, multi-function enable bit, mfne and uar t interrupt enable bit, ure, must firs t be s et. when the interrupt is enabled, the s tack is not full and any of thes e conditions are created, a subroutine call to the respective multi-function interrupt vector , will take place. when the uar t interrupt is serviced, the emi bit will be automatically cleared to disable other interrupts, however only the multi-function interrupt request fag will be also automatically cleared. as the urf fag will not be automatically cleared, it has to be cleared by the application program. however, the usr register fags will be cleared automatically when certain actions are taken by the uart, the details of which are given in the uart section. the eeprom interrupt is contained within the multi-function interrupt. an eeprom interrupt request will take place when the eeprom interrupt request flag, def , is set, which occurs when an eeprom w rite cycl e ends. t o allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and eeprom interrupt enable bit, dee, and associated multi-function interrupt enable bit, must frst be set. when the interrupt is enabled, the stack i s n ot f ull a nd a n e eprom w rite c ycle e nds, a su broutine c all t o t he r espective e eprom interrupt vector will take place. when the eeprom interrupt is serviced, the emi bit will be automatically clea red to disable other interrupts, however only the multi-function interrupt request fag will be also automatically cleared. as the def fag will not be automatically cleared, it has to be cleared by the application program. the l ow v oltage de tector i nterrupt i s c ontained wi thin t he mu lti-function i nterrupt. an l vd interrupt reques t w ill take place w hen the l vd interrupt request flag, l vf, is s et, w hich occurs when the low v oltage detector function detects a low power supply voltage. t o allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, low v oltage interrupt enable bit, l ve, and associated multi-function interrupt enable bit, must frst be set. when the interrupt is enabled, the stack is not full and a low voltage conditio n occurs, a subroutine call to the multi-function interrupt vector , will take place. when the low v oltage interrupt is serviced, the emi bit wi ll be aut omatically cl eared t o disable othe r i nterrupts, however only t he mul ti-function interrupt request fag will be also automatically cleared. as the l vf fag will not be automatically cleared, it has to be cleared by the application program. the standard and periodic t ype tms have two interrupts, one comes from the comparator a match situation a nd t he o ther c omes f rom t he c omparator p m atch si tuation. al l o f t he t m i nterrupts are contained within the multi-function interrupts. for all of the tm types there are two interrupt
rev. 1.20 258 ?e???a?? 1?? 201? rev. 1.20 259 ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu request fa gs and two enable control bit s. a tm int errupt reque st wi ll ta ke plac e when any of the tm re quest fa gs a re se t, a si tuation whi ch oc curs whe n a t m c omparator p or a m atch si tuation happens. to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, respective tm interrupt enable bit, and relevant multi-function interrupt enable bit, mfne, must frst be set. when the interrupt is enabled, the stack is not full and a tm comparator match situation occurs, a subroutine call to the relevant multi-function interrupt vector locations, will take place. when the tm interrupt is serviced, the emi bit will be automatically cleared to disable other interrupts, however only the related mfnf fag will be automatically cleared. as the tm interrupt request fags will not be automatically cleared, they have to be cleared by the application program. each of the int errupt funct ions has the capa bility of waki ng up the mi crocontroller when in the sleep o r i dle mo de. a wa ke-up i s g enerated wh en a n i nterrupt r equest fa g c hanges f rom l ow to high and is independent of whether the interrupt is enabled or not. therefore, even though the devices are in the sleep or idle mode and its system oscillator stopped, situations such as external edge transitions on the external interrupt pins, a low power supply voltage or comparator output bit change may cause their respective interrupt fag to be set high and consequently generate an i nterrupt. c are m ust t herefore b e t aken i f sp urious wa ke-up si tuations a re t o b e a voided. i f a n interrupt wake-up function is to be disabled then the corresponding interrupt request fag should be set high before the devices enter the sleep or idle mode. the interr upt enable bits have no ef fect on the interrupt wake-up function. by di sabling t he re levant i nterrupt e nable bi ts, a re quested i nterrupt c an be pre vented from be ing serviced, however , once an interrupt request flag is set, it will remain in this condition in the interrupt register until the corresponding interrupt is serviced or until the request fag is cleared by the application program. where a certain interrupt is contained w ithin a m ulti-function interrupt, then w hen the interrupt service routine is executed, as only the multi-function interrupt request flags, mfnf , will be automatically cleared, the individual request flag for the function needs to be cleared by the application program. it is recommended that programs do not use the call instruction within the interrupt service subroutine. interrupts often occur in an unpredictable manner or need to be serviced immediately . if only one stack is left and the inte rrupt is not well controlled, the original control sequence will be damaged once a call subroutine is executed in the interrupt subroutine. every interrupt has the capability of waking up the microcontroller when it is in the sleep or idle mode, the wake up being generated when the interrupt request fag changes from low to high. if it is required to prevent a certain interru pt from waking up the microcontrol ler then its respective request fag should be frst set high before enter sleep or idle mode. as only the program counter is pushed onto the stack, then when the interrupt is serviced, if the contents of the accumulator , status register or other registers are altered by the interrupt service program, t heir c ontents shoul d be sa ved t o t he m emory a t t he be ginning of t he i nterrupt se rvice routine.
rev. 1.20 2 ? 0 ? e ??? a ?? 1 ?? 201 ? rev. 1.20 2?1 ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu to return from an interrupt subroutine, either a ret or reti instruction may be executed. the reti instruction in addition to executing a return to the main program also automatically sets the emi bit high to allow further interrupts. the ret instruction however only executes a return to the main program leaving the emi bit in its present zero state and therefore disabling the execution of further interrupts. confguration options confguration options refer to certain options within the mcu that are programmed into the devices during the programming process. during the development process, these options are selected using the ht -ide software development tools. as these options are programmed into the devices using the hardwa re programm ing tools, once they are sel ected they cannot be changed la ter using the application program. all options must be defned for proper system function, the details of which are shown in the table. 1 clock mode ?? eq ? enc ? : 1. 12mhz 2. ? mhz application ci?c?its com0 comm com? vdd/avdd/ubus vss 100k res vdd v33o udn udp 300 0.1? com?~com0 ht???b5?2/ht???b5?4/ht???b5?? vbus d- d+ vss 0.1? 0.1? 10? 4?p? 4?p? 33 33 ccon~cco0 vdd vdd vdd i/o ke? mat?ix * ht???b5?2/ht???b5?4/ht???b5?? application ci?c?it fo? rgb gamming ke??oa?d * change r fo? ccon = 1v *n=0~14 fo? ht???b5?2? n=0~23 fo? ht???b5?4? n=0~4? fo? ht???b5??. rgb led ledvss/ccvss cco4? cco45 cco4? ccon+1 ccon ccon+2 cco1 cco0 cco2 r3 r3 r3 vdd ccvdd rext r ext
rev. 1.20 2?0 ?e???a?? 1?? 201? rev. 1.20 2 ? 1 ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu s s central to the successful operation of any microcontroller is its instruction set, which is a set of program instruction codes that direc ts the microcontroller to perform certain operations. in the case of holtek microcontroller , a comprehensive and fexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of programming overheads. for easier understanding of the various instruction codes, they have been subdivided into several functional groupings. most instructions are implemented within one instruction cycle. the exceptions to this are branch, call, or table read instructions where two ins truction cycles are required. one instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8mhz system oscillator , most instructions would be i mplemented wi thin 0.5 s a nd bra nch or c all i nstructions woul d be i mplemented wi thin 1s. although instructions which require one more cycle to implement are generally limited to the jmp , call, ret , reti and table read instructions, it is important to realize that any other instructions which involve manipulation of the program counter low register or pcl will also take one more cycle to implement. as instructions which change the contents of the pcl will imply a direct j ump t o t hat ne w a ddress, one m ore c ycle wi ll be re quired. e xamples of suc h i nstructions would be clr pcl or mov pcl, a. for the case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. the t ransfer of da ta wi thin t he m icrocontroller progra m i s one of t he m ost fre quently use d operations. making use of several kinds of mov instructions, data can be transferred from registers to the accumulator and vice-versa as well as being able to move specifc immediate data directly into the accumulator . one of the most important data transfer applications is to receive data from the input ports and transfer data to the output ports. the ability to perform certain arithm etic operations and data manipula tion is a necessary feature of most m icrocontroller a pplications. w ithin t he hol tek m icrocontroller i nstruction se t a re a ra nge of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. care must be taken to ens ure correct handling of carry and borrow data w hen res ults exceed 255 for addition and less than 0 for subtraction. the increment and decrement instructions such as inc, inca, dec and deca provide a simple means of increasing or decreasing by a value of one of the values in the destination specifed.
rev. 1.20 2 ? 2 ? e ??? a ?? 1 ?? 201 ? rev. 1.20 2?3 ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu lal a ra a the standard logical operations such as and, or, xor and cpl all have their own instruction within t he hol tek m icrocontroller i nstruction se t. as wi th t he c ase of m ost i nstructions i nvolving data m anipulation, d ata m ust p ass t hrough t he ac cumulator wh ich m ay i nvolve a dditional programming steps. in all logical data operations, the zero flag may be set if the result of the operation is zero. another form of logical data manipulation comes from the rotate instructions such as rr, rl, rrc and rlc which provide a simple means of rotating one bit right or left. dif ferent rotate instructions exist depending on program requirements. rotate instructions are useful for serial port progra mming a pplications whe re da ta c an be rot ated from a n i nternal re gister i nto t he ca rry bit from where it can be examined and the necessary serial bit set high or low . another application which rotate data operations are used is to implement multiplication and division calculations. program branching takes the form of either jumps to specifed locations using the jmp instruction or t o a su broutine usi ng t he cal l i nstruction. t hey di ffer i n t he se nse t hat i n t he c ase of a subroutine call, the program mus t return to the ins truction immediately w hen the s ubroutine has been c arried out. t his i s done by pl acing a re turn i nstruction ret i n t he subrout ine whi ch wi ll cause the program to jump back to the address right after the call instruction. in the case of a jmp instruction, the program simply jumps to the desired location. there is no requirement to jump back to the original jumping of f point as in the case of the call instruction. one special and extremely useful set of branch instructions are the conditional branches. here a decision is frst made regarding the c ondition of a c ertain da ta m emory or i ndividual bi ts. de pending upon t he c onditions, t he program will continue with the next instruction or skip over it and jump to the following instruction. these i nstructions a re t he ke y t o de cision m aking a nd bra nching wi thin t he progra m pe rhaps determined by the condition of certain input switches or by the condition of internal data bits. the abili ty to provide single bit operations on data memory is an extremely fexible feature of all holtek microcontrollers . this feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the set [m].i or clr [m].i instructions respectively . the feature removes the need for programmers to frst read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. this read-modify-write process is taken care of automatically when these bit operation instructions are used. data st orage i s norm ally i mplemented by usi ng re gisters. however , whe n worki ng wi th l arge amounts of fxed data, the volume involved often makes it inconvenient to store the fxed data in the data memory . t o overcome this problem, holtek microcontrollers allow an area of program memory to be setup as a table where data can be directly stored. a set of easy to use instructions provides the means by w hich this fixed data can be referenced and retrieved from the program memory. in addition to the above functional instructions, a range of other instructions also exist such as the hal t instruction for power -down operations and instructions to control the operation of the w atchdog t imer for reliable program operations under extreme electric or electromagnetic environments. for their relevant operations, refer to the functional related sections.
rev. 1.20 2?2 ?e???a?? 1?? 201? rev. 1.20 2 ? 3 ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu s s sa the i nstructions re lated t o t he da ta m emory a ccess i n t he fol lowing t able c an be used whe n t he desired data memory is located in data memory sector 0. x: bits immediate data m: data memory address a: accumulator i: 0~7 number of bits addr: program memory address add a ? [m] add data memo ?? to acc 1 z ? c ? ac ? ov ? sc addm a ? [m] add acc to data memo ?? 1 note z ? c ? ac ? ov ? sc add a ? x add immediate data to acc 1 z ? c ? ac ? ov ? sc adc a ? [m] add data memo ?? to acc with ca ??? 1 z ? c ? ac ? ov ? sc adcm a ? [m] add acc to data memo ?? with ca ??? 1 note z ? c ? ac ? ov ? sc sub a ? x s ?? t ? act immediate data f ? om the acc 1 z ? c ? ac ? ov ? sc ? cz sub a ? [m] s ?? t ? act data memo ?? f ? om acc 1 z ? c ? ac ? ov ? sc ? cz subm a ? [m] s ?? t ? act data memo ?? f ? om acc with ? es ? lt in data memo ?? 1 note z ? c ? ac ? ov ? sc ? cz sbc a ? x s ?? t ? act immediate data f ? om acc with ca ??? 1 z ? c ? ac ? ov ? sc ? cz sbc a ? [m] s ?? t ? act data memo ?? f ? om acc with ca ??? 1 z ? c ? ac ? ov ? sc ? cz sbcm a ? [m] s ?? t ? act data memo ?? f ? om acc with ca ???? ? es ? lt in data memo ?? 1 note z ? c ? ac ? ov ? sc ? cz daa [m] decimal adj ? st acc fo ? addition with ? es ? lt in data memo ?? 1 note c logic ope?ation and a ? [m] logical and data memo ?? to acc 1 z or a ? [m] logical or data memo ?? to acc 1 z xor a ? [m] logical xor data memo ?? to acc 1 z andm a ? [m] logical and acc to data memo ?? 1 note z orm a ? [m] logical or acc to data memo ?? 1 note z xorm a ? [m] logical xor acc to data memo ?? 1 note z and a ? x logical and immediate data to acc 1 z or a ? x logical or immediate data to acc 1 z xor a ? x logical xor immediate data to acc 1 z cpl [m] complement data memo ?? 1 note z cpla [m] complement data memo ?? with ? es ? lt in acc 1 z inc?ement & dec?ement inca [m] inc ? ement data memo ?? with ? es ? lt in acc 1 z inc [m] inc ? ement data memo ?? 1 note z deca [m] dec ? ement data memo ?? with ? es ? lt in acc 1 z dec [m] dec ? ement data memo ?? 1 note z rotate rra [m] rotate data memo ?? ? ight with ? es ? lt in acc 1 none rr [m] rotate data memo ?? ? ight 1 note none rrca [m] rotate data memo ?? ? ight th ? o ? gh ca ??? with ? es ? lt in acc 1 c rrc [m] rotate data memo ?? ? ight th ? o ? gh ca ??? 1 note c rla [m] rotate data memo ?? left with ? es ? lt in acc 1 none rl [m] rotate data memo ?? left 1 note none rlca [m] rotate data memo ?? left th ? o ? gh ca ??? with ? es ? lt in acc 1 c rlc [m] rotate data memo ?? left th ? o ? gh ca ??? 1 note c
rev. 1.20 2 ? 4 ? e ??? a ?? 1 ?? 201 ? rev. 1.20 2?5 ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu m ds cls fla daa m mov a ? [m] move data memo ?? to acc 1 none mov [m] ? a move acc to data memo ?? 1 note none mov a ? x move immediate data to acc 1 none bit ope?ation clr [m].i clea ? ? it of data memo ?? 1 note none set [m].i set ? it of data memo ?? 1 note none b?anch ope?ation jmp add ? j ? mp ? nconditionall ? 2 none sz [m] skip if data memo ?? is ze ? o 1 note none sza [m] skip if data memo ?? is ze ? o with data movement to acc 1 note none sz [m].i skip if ? it i of data memo ?? is ze ? o 1 note none snz [m] skip if data memo ?? is not ze ? o 1 note none snz [m].i skip if ? it i of data memo ?? is not ze ? o 1 note none siz [m] skip if inc ? ement data memo ?? is ze ? o 1 note none sdz [m] skip if dec ? ement data memo ?? is ze ? o 1 note none siza [m] skip if inc ? ement data memo ?? is ze ? o with ? es ? lt in acc 1 note none sdza [m] skip if dec ? ement data memo ?? is ze ? o with ? es ? lt in acc 1 note none call add ? s ??? o ? tine call 2 none ret ret ?? n f ? om s ??? o ? tine 2 none ret a ? x ret ?? n f ? om s ??? o ? tine and load immediate data to acc 2 none reti ret ?? n f ? om inte ??? pt 2 none ta?le read ope?ation tabrd [m] read table (specifc page) to tblh and data memory 2 note none tabrdl [m] read ta ? le (last page) to tblh and data memo ?? 2 note none itabrd [m] increment table pointer tblp frst and read table to tblh and data memory 2 note none itabrdl [m] increment table pointer tblp frst and read table (last page) to tblh and data memo ?? 2 note none miscellaneo?s nop no ope ? ation 1 none clr [m] clea ? data memo ?? 1 note none set [m] set data memo ?? 1 note none clr wdt clea ? watchdog time ? 1 to ? pd ? swap [m] swap ni ?? les of data memo ?? 1 note none swapa [m] swap ni ?? les of data memo ?? with ? es ? lt in acc 1 none halt ente ? powe ? down mode 1 to ? pd ? note: 1. for skip instructions, if the result of the comparison involves a skip then up to three cycles are required, if no skip takes place only one cycle is required. 2. any instruction which changes the contents of the pcl will also require 2 cycles for execution. 3. for the clr wdt instruction the t o and pdf fags may be af fected by the execution status. the t o and pdf fags are cleared after the clr wdt instructions is executed. otherwise the t o and pdf fags remain unchanged.
rev. 1.20 2?4 ?e???a?? 1?? 201? rev. 1.20 2 ? 5 ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu e s s the extended instructions are used to support the full range address access for the data memory . when the accessed data memory is located in any data memory sections except sector 0, the extended instructi on can be used to access the data memory instead of using the indirect addressing access to improve the cpu frmware performance. ladd a ? [m] add data memo ?? to acc 2 z ? c ? ac ? ov ? sc laddm a ? [m] add acc to data memo ?? 2 note z ? c ? ac ? ov ? sc ladc a ? [m] add data memo ?? to acc with ca ??? 2 z ? c ? ac ? ov ? sc ladcm a ? [m] add acc to data memo ?? with ca ??? 2 note z ? c ? ac ? ov ? sc lsub a ? [m] s ?? t ? act data memo ?? f ? om acc 2 z ? c ? ac ? ov ? sc ? cz lsubm a ? [m] s ?? t ? act data memo ?? f ? om acc with ? es ? lt in data memo ?? 2 note z ? c ? ac ? ov ? sc ? cz lsbc a ? [m] s ?? t ? act data memo ?? f ? om acc with ca ??? 2 z ? c ? ac ? ov ? sc ? cz lsbcm a ? [m] s ?? t ? act data memo ?? f ? om acc with ca ???? ? es ? lt in data memo ?? 2 note z ? c ? ac ? ov ? sc ? cz ldaa [m] decimal adj ? st acc fo ? addition with ? es ? lt in data memo ?? 2 note c logic ope?ation land a ? [m] logical and data memo ?? to acc 2 z lor a ? [m] logical or data memo ?? to acc 2 z lxor a ? [m] logical xor data memo ?? to acc 2 z landm a ? [m] logical and acc to data memo ?? 2 note z lorm a ? [m] logical or acc to data memo ?? 2 note z lxorm a ? [m] logical xor acc to data memo ?? 2 note z lcpl [m] complement data memo ?? 2 note z lcpla [m] complement data memo ?? with ? es ? lt in acc 2 z inc?ement & dec?ement linca [m] inc ? ement data memo ?? with ? es ? lt in acc 2 z linc [m] inc ? ement data memo ?? 2 note z ldeca [m] dec ? ement data memo ?? with ? es ? lt in acc 2 z ldec [m] dec ? ement data memo ?? 2 note z rotate lrra [m] rotate data memo ?? ? ight with ? es ? lt in acc 2 none lrr [m] rotate data memo ?? ? ight 2 note none lrrca [m] rotate data memo ?? ? ight th ? o ? gh ca ??? with ? es ? lt in acc 2 c lrrc [m] rotate data memo ?? ? ight th ? o ? gh ca ??? 2 note c lrla [m] rotate data memo ?? left with ? es ? lt in acc 2 none lrl [m] rotate data memo ?? left 2 note none lrlca [m] rotate data memo ?? left th ? o ? gh ca ??? with ? es ? lt in acc 2 c lrlc [m] rotate data memo ?? left th ? o ? gh ca ??? 2 note c data move lmov a ? [m] move data memo ?? to acc 2 none lmov [m] ? a move acc to data memo ?? 2 note none bit ope?ation lclr [m].i clea ? ? it of data memo ?? 2 note none lset [m].i set ? it of data memo ?? 2 note none
rev. 1.20 2 ?? ? e ??? a ?? 1 ?? 201 ? rev. 1.20 2?? ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu m ds cls fla bah lsz [m] skip if data memo ?? is ze ? o 2 note none lsza [m] skip if data memo ?? is ze ? o with data movement to acc 2 note none lsnz [m] skip if data memo ?? is not ze ? o 2 note none lsz [m].i skip if ? it i of data memo ?? is ze ? o 2 note none lsnz [m].i skip if ? it i of data memo ?? is not ze ? o 2 note none lsiz [m] skip if inc ? ement data memo ?? is ze ? o 2 note none lsdz [m] skip if dec ? ement data memo ?? is ze ? o 2 note none lsiza [m] skip if inc ? ement data memo ?? is ze ? o with ? es ? lt in acc 2 note none lsdza [m] skip if dec ? ement data memo ?? is ze ? o with ? es ? lt in acc 2 note none ta?le read ltabrd [m] read ta ? le to tblh and data memo ?? 3 note none ltabrdl [m] read ta ? le (last page) to tblh and data memo ?? 3 note none litabrd [m] increment table pointer tblp frst and read table to tblh and data memory 3 note none litabrdl [m] increment table pointer tblp frst and read table (last page) to tblh and data memo ?? 3 note none miscellaneo?s lclr [m] clea ? data memo ?? 2 note none lset [m] set data memo ?? 2 note none lswap [m] swap ni ?? les of data memo ?? 2 note none lswapa [m] swap ni ?? les of data memo ?? with ? es ? lt in acc 2 none note: 1. for these extended skip instructions, if the result of the comparison involves a skip then up to four cycles are required, if no skip takes place two cycles is required. 2. any extended instruction which changes the contents of the pcl register will also require three cycles for execution.
rev. 1.20 2?? ?e???a?? 1?? 201? rev. 1.20 2 ?? ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu instruction defnition add d ata m emory to a cc w ith carry description the c ontents o f t he s pecifed d ata m emory, a ccumulator a nd t he c arry f ag a re a dded. the re sult is s tored in t he a ccumulator. operation acc a cc + [ m] + c affected f ag(s) ov, z , a c, c , s c add a cc to d ata m emory w ith carry description the c ontents o f t he s pecifed d ata m emory, a ccumulator a nd t he c arry f ag a re a dded. the re sult is s tored in t he sp ecifed d ata m emory. operation [m] a cc + [ m] + c affected f ag(s) ov, z , a c, c , s c add d ata m emory t o a cc description the c ontents o f t he s pecifed d ata m emory a nd t he a ccumulator a re a dded. the re sult is s tored in t he a ccumulator. operation acc a cc + [ m] affected f ag(s) ov, z , a c, c , s c add im mediate data to a cc description the c ontents o f t he a ccumulator a nd t he s pecifed im mediate data a re a dded. the re sult is s tored in t he a ccumulator. operation acc a cc + x affected f ag(s) ov, z , a c, c , s c add a cc to d ata m emory description the c ontents o f t he s pecifed d ata m emory a nd t he a ccumulator a re a dded. the re sult is s tored in t he sp ecifed d ata m emory. operation [m] a cc + [ m] affected f ag(s) ov, z , a c, c , s c logical a nd d ata m emory t o a cc description data i n t he a ccumulator a nd t he s pecifed d ata m emory p erform a b itwise l ogical a nd operation. t he re sult is s tored in t he a ccumulator. operation acc a cc a nd [ m] affected f ag(s) z logical a nd im mediate data to a cc description data i n t he a ccumulator a nd t he s pecifed im mediate data p erform a b it w ise l ogical a nd operation. t he re sult is s tored in t he a ccumulator. operation acc a cc a nd x affected f ag(s) z logical a nd a cc to d ata m emory description data i n t he s pecifed d ata m emory a nd t he a ccumulator p erform a b itwise l ogical a nd operation. t he re sult is s tored in t he d ata m emory. operation [m] a cc and [ m] affected f ag(s) z
rev. 1.20 2 ? 8 ? e ??? a ?? 1 ?? 201 ? rev. 1.20 2?9 ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu cll a subroutine c all description unconditionally c alls a s ubroutine a t t he s pecifed a ddress. th e p rogram c ounter t hen increments b y 1 to o btain t he a ddress o f t he n ext i nstruction w hich i s t hen p ushed o nto t he stack. t he sp ecifed a ddress is t hen loaded a nd t he p rogram c ontinues e xecution f rom t his new a ddress. a s t his instruction re quires a n a dditional op eration, it is a t wo c ycle instruction. operation stack p rogram counter + 1 program c ounter a ddr affected f ag(s) none clear d ata m emory description each b it o f t he s pecifed d ata m emory i s cl eared t o 0 . operation [m] 00h affected f ag(s) none clear bi t o f d ata m emory description bit i o f t he s pecifed d ata m emory i s cl eared t o 0 . operation [m].i 0 affected f ag(s) none clear w atchdog t imer description the t o, p df f ags a nd t he w dt a re al l c leared. operation wdt cl eared to 0 pdf 0 affected f ag(s) to, p df complement d ata m emory description each b it of t he s pecifed d ata m emory i s l ogically complemented ( 1s complement). b its w hich previously c ontained a 1 a re c hanged to 0 a nd v ice v ersa. operation [m] [m] affected f ag(s) z complement d ata m emory w ith r esult i n a cc description each b it of t he s pecifed d ata m emory i s l ogically complemented ( 1s complement). b its w hich previously c ontained a 1 a re c hanged to 0 a nd v ice v ersa. th e c omplemented r esult i s s tored i n the a ccumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc [ m] affected f ag(s) z decimal-adjust a cc f or addition w ith r esult i n d ata m emory description convert t he c ontents o f t he a ccumulator v alue to a b cd ( binary c oded d ecimal) v alue resulting f rom t he p revious a ddition o f t wo b cd v ariables. i f t he low n ibble is greater t han 9 or i f a c f ag i s s et, t hen a v alue o f 6 w ill b e a dded to t he l ow n ibble. o therwise t he l ow n ibble remains u nchanged. i f t he h igh n ibble i s g reater t han 9 o r i f t he c f ag i s s et, t hen a v alue o f 6 will b e a dded to t he h igh n ibble. e ssentially, t he decimal c onversion i s p erformed b y a dding 00h, 0 6h, 6 0h o r 6 6h depending o n t he a ccumulator a nd f ag c onditions. o nly t he c f ag may b e a ffected b y t his instruction w hich indicates t hat if t he o riginal b cd s um is greater t han 100, it al lows m ultiple p recision decimal a ddition. operation [m] a cc + 00h or [m] a cc + 06 h o r [m] a cc + 60h o r [m] a cc + 66h affected f ag(s) c
rev. 1.20 2?8 ?e???a?? 1?? 201? rev. 1.20 2 ? 9 ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu dec decrement d ata m emory description data i n t he s pecifed d ata m emory i s d ecremented b y 1 . operation [m] [ m] ? 1 affected f ag(s) z decrement d ata m emory wi th r esult i n a cc description data in t he sp ecifed d ata m emory is d ecremented b y 1 . t he re sult is s tored in t he accumulator. th e c ontents o f t he d ata m emory r emain u nchanged. operation acc [ m] ? 1 affected f ag(s) z enter p ower down m ode description this i nstruction s tops t he p rogram e xecution a nd t urns o ff t he s ystem c lock. th e c ontents o f the d ata m emory a nd r egisters a re r etained. th e w dt a nd p rescaler a re c leared. th e p ower down f ag p df i s s et a nd t he w dt t ime-out f ag t o i s c leared. operation to 0 pdf 1 affected f ag(s) to, p df increment d ata m emory description data in t he sp ecifed d ata m emory is incremented b y 1 . operation [m] [ m] + 1 affected f ag(s) z increment d ata m emory wi th r esult i n a cc description data i n t he sp ecifed d ata m emory i s i ncremented b y 1 . th e re sult i s s tored i n t he a ccumulator. the c ontents o f t he d ata m emory r emain u nchanged. operation acc [ m] + 1 affected f ag(s) z jump u nconditionally description the c ontents o f t he p rogram c ounter a re re placed w ith t he sp ecifed a ddress. p rogram execution t hen c ontinues f rom t his n ew a ddress. a s t his re quires t he insertion o f a d ummy instruction w hile t he n ew a ddress is loaded, it is a t wo c ycle instruction. operation program counter addr affected f ag(s) none move d ata m emory t o a cc description the c ontents o f t he s pecifed d ata m emory a re c opied to t he a ccumulator. operation acc [ m] affected f ag(s) none move im mediate data to a cc description the im mediate data s pecifed i s l oaded i nto t he a ccumulator. operation acc x affected f ag(s) none move a cc to d ata m emory description the c ontents o f t he a ccumulator a re c opied to t he s pecifed d ata m emory. operation [m] a cc affected f ag(s) none
rev. 1.20 2 ? 0 ? e ??? a ?? 1 ?? 201 ? rev. 1.20 2?1 ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu no o peration description no o peration i s p erformed. e xecution c ontinues w ith t he n ext i nstruction. operation no operation affected f ag(s) none logical o r d ata m emory to a cc description data i n t he a ccumulator a nd t he s pecifed d ata m emory p erform a b itwise logical o r op eration. t he re sult is s tored in t he a ccumulator. operation acc a cc or [ m] affected f ag(s) z logical or im mediate data to a cc description data i n t he a ccumulator a nd t he s pecifed im mediate data p erform a b itwise l ogical o r operation. t he re sult is s tored in t he a ccumulator. operation acc a cc or x affected f ag(s) z logical or a cc to d ata m emory description data i n t he s pecifed d ata m emory a nd t he a ccumulator p erform a b itwise l ogical o r operation. t he re sult is s tored in t he d ata m emory. operation [m] a cc or [ m] affected f ag(s) z return from s ubroutine description the p rogram c ounter is re stored f rom t he s tack. p rogram e xecution c ontinues a t t he re stored a ddress. operation program counter s tack affected f ag(s) none return f rom su broutine and l oad im mediate data to a cc description the p rogram c ounter i s r estored f rom t he s tack a nd t he a ccumulator l oaded w ith t he s pecifed immediate data. p rogram e xecution c ontinues a t t he r estored a ddress. operation program counter s tack acc x affected f ag(s) none return from i nterrupt description the p rogram c ounter is re stored f rom t he s tack a nd t he interrupts a re re -enabled b y s etting t he emi b it. e mi i s t he m aster i nterrupt g lobal e nable b it. i f a n i nterrupt w as p ending w hen t he reti instruction is e xecuted, t he p ending in terrupt ro utine w ill b e p rocessed b efore re turning to t he m ain p rogram. operation program counter s tack emi 1 affected f ag(s) none rotate d ata m emory l eft description the c ontents o f t he s pecifed d ata m emory a re r otated l eft b y 1 b it w ith b it 7 r otated i nto b it 0 . operation [m].(i+1) [ m].i; (i=0~6) [m].0 [ m].7 affected f ag(s) none
rev. 1.20 2?0 ?e???a?? 1?? 201? rev. 1.20 2 ? 1 ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu rl rotate d ata m emory left w ith re sult in a cc description the c ontents o f t he s pecifed d ata m emory a re r otated l eft b y 1 b it w ith b it 7 r otated i nto b it 0 . the r otated r esult i s s tored i n t he a ccumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc.(i+1) [ m].i; (i=0~6) acc.0 [ m].7 affected f ag(s) none rotate d ata m emory l eft t hrough carry description the c ontents o f t he s pecifed d ata m emory a nd t he c arry f ag a re r otated l eft b y 1 b it. b it 7 replaces t he c arry b it a nd t he o riginal c arry f ag i s r otated i nto b it 0 . operation [m].(i+1) [ m].i; (i=0~6) [m].0 c c [ m].7 affected f ag(s) c rotate d ata m emory left t hrough c arry w ith re sult in a cc description data i n t he s pecifed d ata m emory and t he carry f ag are r otated l eft b y 1 b it. b it 7 r eplaces t he carry b it a nd t he o riginal c arry f ag i s r otated i nto t he b it 0 . th e r otated r esult i s s tored i n t he accumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc.(i+1) [ m].i; (i=0~6) acc.0 c c [ m].7 affected f ag(s) c rotate d ata m emory r ight description the contents of t he s pecifed d ata m emory are r otated r ight b y 1 b it w ith b it 0 r otated i nto b it 7 . operation [m].i [ m].(i+1); (i=0~6) [m].7 [ m].0 affected f ag(s) none rotate d ata m emory right with result i n a cc description data i n t he s pecifed d ata m emory i s r otated r ight by 1 bit w ith bit 0 rotated i nto b it 7 . th e r otated r esult i s s tored i n t he a ccumulator a nd t he c ontents o f t he data m emory r emain u nchanged. operation acc.i [ m].(i+1); (i=0~6) acc.7 [ m].0 affected f ag(s) none rotate d ata m emory r ight t hrough carry description the c ontents o f t he s pecifed d ata m emory a nd t he c arry f ag a re r otated r ight b y 1 b it. b it 0 replaces t he c arry b it a nd t he o riginal c arry f ag i s r otated i nto b it 7 . operation [m].i [ m].(i+1); (i=0~6) [m].7 c c [ m].0 affected f ag(s) c
rev. 1.20 2 ? 2 ? e ??? a ?? 1 ?? 201 ? rev. 1.20 2?3 ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu rrc rotate d ata m emory right th rough c arry with result i n a cc description data i n t he s pecifed d ata m emory a nd t he c arry f ag a re r otated r ight b y 1 b it. b it 0 r eplaces the c arry b it a nd t he o riginal c arry f ag i s r otated i nto b it 7 . th e r otated r esult i s s tored i n t he accumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc.i [ m].(i+1); (i=0~6) acc.7 c c [ m].0 affected f ag(s) c subtract d ata m emory from a cc wi th c arry description the c ontents o f t he s pecifed d ata m emory a nd t he c omplement o f t he c arry f ag a re subtracted f rom t he a ccumulator. t he re sult is s tored in t he a ccumulator. n ote t hat if t he result o f s ubtraction is n egative, t he c f ag w ill b e c leared t o 0 , o therwise if t he re sult is positive o r z ero, t he c f ag w ill b e s et to 1 . operation acc a cc ? [ m] ? c affected f ag(s) ov, z , a c, c , s c, c z subtract im mediate data f rom a cc w ith carry description the immediate da ta a nd t he c omplement o f t he c arry f ag a re s ubtracted f rom t he accumulator. t he re sult is s tored in t he a ccumulator. n ote t hat if t he re sult o f s ubtraction is negative, t he c f ag w ill b e c leared t o 0 , o therwise if t he re sult is p ositive o r z ero, t he c f ag will be se t t o 1 . operation acc a cc - [ m] - c affected f ag(s) ov, z , ac , c , s c, cz subtract d ata m emory from a cc wi th c arry a nd r esult i n d ata m emory description the c ontents o f t he s pecifed d ata m emory a nd t he c omplement o f t he c arry f ag a re subtracted f rom t he a ccumulator. t he re sult is s tored in t he d ata m emory. n ote t hat if t he result o f s ubtraction is n egative, t he c f ag w ill b e c leared t o 0 , o therwise if t he re sult is positive o r z ero, t he c f ag w ill b e s et to 1 . operation [m] a cc ? [ m] ? c affected f ag(s) ov, z , a c, c , s c, c z skip i f decrement d ata m emory i s 0 description the c ontents o f t he s pecifed d ata m emory a re fr st decremented b y 1 . i f t he r esult i s 0 t he following instruction is s kipped. a s t his re quires t he insertion o f a d ummy instruction w hile the n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he p rogram proceeds w ith t he f ollowing i nstruction. operation [m] [ m] ? 1 skip if [ m]=0 affected f ag(s) none skip i f decrement d ata m emory i s z ero w ith r esult i n a cc description the c ontents o f t he s pecifed d ata m emory a re fr st decremented b y 1 . i f t he r esult i s 0 , t he following instruction is s kipped. t he re sult is s tored in t he a ccumulator b ut t he sp ecifed data m emory c ontents r emain u nchanged. a s t his r equires t he i nsertion o f a dummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he r esult is n ot 0 , the p rogram p roceeds w ith t he f ollowing instruction. operation acc [ m] ? 1 skip if a cc=0 affected f ag(s) none
rev. 1.20 2?2 ?e???a?? 1?? 201? rev. 1.20 2 ? 3 ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu set [m] set d ata m emory description each b it o f t he s pecifed d ata m emory i s s et t o 1 . operation [m] f fh affected f ag(s) none set [m].i set b it o f d ata m emory description bit i o f t he s pecifed d ata m emory i s s et t o 1 . operation [m].i 1 affected f ag(s) none siz [m] skip i f i ncrement d ata m emory i s 0 description the c ontents o f t he sp ecifed d ata m emory a re f rst incremented b y 1 . i f t he re sult is 0 , t he following instruction is s kipped. a s t his re quires t he insertion o f a d ummy instruction w hile the n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he p rogram proceeds w ith t he f ollowing i nstruction. operation [m] [ m] + 1 skip if [ m]=0 affected f ag(s) none siza [m] skip if increment d ata m emory is z ero w ith re sult in a cc description the c ontents o f t he sp ecifed d ata m emory a re f rst incremented b y 1 . i f t he re sult is 0 , t he following instruction is s kipped. t he re sult is s tored in t he a ccumulator b ut t he sp ecifed data m emory c ontents r emain u nchanged. a s t his r equires t he i nsertion o f a dummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he p rogram p roceeds w ith t he f ollowing instruction. operation acc [ m] + 1 skip if a cc=0 affected f ag(s) none snz [m].i skip i f d ata m emory i s no t 0 description if t he sp ecifed d ata m emory is n ot 0 , t he f ollowing instruction is s kipped. a s t his re quires t he insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is 0 t he p rogram p roceeds w ith t he f ollowing instruction. operation skip i f [ m].i 0 affected f ag(s) none snz [m] skip i f d ata m emory i s no t 0 description if t he sp ecifed d ata m emory is n ot 0 , t he f ollowing instruction is s kipped. a s t his re quires t he insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is 0 t he p rogram p roceeds w ith t he f ollowing instruction. operation skip i f [ m] 0 affected f ag(s) none sub a,[m] subtract d ata m emory from a cc description the s pecifed d ata m emory i s s ubtracted f rom t he c ontents o f t he a ccumulator. th e r esult i s stored in t he a ccumulator. n ote t hat if t he re sult o f s ubtraction is n egative, t he c f ag w ill b e cleared to 0 , o therwise i f t he r esult i s p ositive o r z ero, t he c f ag w ill b e s et to 1 . operation acc a cc ? [ m] affected f ag(s) ov, z , a c, c , s c, c z
rev. 1.20 2 ? 4 ? e ??? a ?? 1 ?? 201 ? rev. 1.20 2?5 ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu subm a,[m] subtract d ata m emory from a cc wi th r esult i n d ata m emory description the s pecifed d ata m emory i s s ubtracted f rom t he c ontents o f t he a ccumulator. th e r esult i s stored in t he d ata m emory. n ote t hat if t he re sult o f s ubtraction is n egative, t he c f ag w ill b e cleared to 0 , o therwise i f t he r esult i s p ositive o r z ero, t he c f ag w ill b e s et to 1 . operation [m] a cc ? [ m] affected f ag(s) ov, z , a c, c , s c, c z sub a,x subtract im mediate data f rom a cc description the im mediate data s pecifed b y t he c ode i s s ubtracted f rom t he c ontents o f t he a ccumulator. the re sult is s tored in t he a ccumulator. n ote t hat if t he re sult o f s ubtraction is n egative, t he c fag w ill b e c leared to 0 , o therwise i f t he r esult i s p ositive o r z ero, t he c f ag w ill b e s et to 1 . operation acc a cc ? x affected f ag(s) ov, z , a c, c , s c, c z swap [m] swap ni bbles of d ata m emory description the l ow-order a nd h igh-order n ibbles o f t he s pecifed d ata m emory a re i nterchanged. operation [m].3~[m].0 ? [ m].7~[m].4 affected f ag(s) none swapa [m] swap ni bbles of d ata m emory w ith r esult i n a cc description the l ow-order a nd h igh-order n ibbles o f t he s pecifed d ata m emory a re i nterchanged. th e result i s s tored i n t he a ccumulator. th e c ontents o f t he d ata m emory r emain u nchanged. operation acc.3~acc.0 [ m].7~[m].4 acc.7~acc.4 [ m].3~[m].0 affected f ag(s) none sz [m] skip i f d ata m emory i s 0 description if t he contents of t he s pecifed d ata m emory i s 0, t he following i nstruction i s s kipped. a s t his requires t he insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a t wo cycle instruction. i f t he re sult is n ot 0 t he p rogram p roceeds w ith t he f ollowing instruction. operation skip if [ m]=0 affected f ag(s) none sza [m] skip i f d ata m emory i s 0 w ith data m ovement to a cc description the c ontents o f t he s pecifed d ata m emory a re c opied to t he a ccumulator. i f t he v alue i s z ero, the f ollowing instruction is s kipped. a s t his re quires t he insertion o f a d ummy instruction while t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he program p roceeds w ith t he f ollowing instruction. operation acc [ m] skip if [ m]=0 affected f ag(s) none sz [m].i skip i f b it i of d ata m emory i s 0 description if b it i o f t he sp ecifed d ata m emory is 0 , t he f ollowing instruction is s kipped. a s t his re quires the insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 , t he p rogram p roceeds w ith t he f ollowing instruction. operation skip if [ m].i=0 affected f ag(s) none
rev. 1.20 2?4 ?e???a?? 1?? 201? rev. 1.20 2 ? 5 ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu tabrd [m] read ta ble ( specifc p age) to t blh a nd d ata m emory description the low b yte o f t he p rogram c ode ( specifc p age) a ddressed b y t he t able p ointer p air (tblp a nd t bhp) i s mo ved t o t he s pecifed d ata m emory a nd t he h igh by te mo ved t o t blh. operation [m] pr ogram c ode (low by te) tblh pr ogram c ode (high by te) affected f ag(s) none tabrdl [m] read t able (last p age) t o t blh a nd d ata m emory description the l ow by te o f t he pr ogram c ode (last p age) a ddressed by t he t able p ointer (tblp) i s mo ved to t he s pecifed d ata m emory a nd t he h igh b yte m oved to t blh. operation [m] pr ogram c ode (low by te) tblh pr ogram c ode (high by te) affected f ag(s) none itabrd [m] increment ta ble p ointer l ow b yte fr st and r ead ta ble to t blh and d ata m emory description increment ta ble p ointer l ow b yte, t blp, fr st and t hen t he p rogram code addressed b y t he table p ointer ( tbhp and t blp) i s m oved to t he s pecifed d ata m emory and t he hi gh b yte moved t o t blh. operation [m] pr ogram c ode (low by te) tblh pr ogram c ode (high by te) affected f ag(s) none itabrdl [m] increment t able p ointer l ow by te f rst a nd r ead t able (last p age) t o t blh a nd d ata m emory description increment ta ble p ointer l ow b yte, t blp, fr st and t hen t he l ow b yte of t he p rogram code (last p age) addressed b y t he ta ble p ointer ( tblp) i s m oved to t he s pecifed d ata m emory and the h igh by te mov ed t o t blh. operation [m] pr ogram c ode (low by te) tblh pr ogram c ode (high by te) affected f ag(s) none xor a,[m] logical x or d ata m emory to a cc description data i n t he a ccumulator a nd t he s pecifed d ata m emory p erform a b itwise l ogical x or operation. t he re sult is s tored in t he a ccumulator. operation acc a cc x or [ m] affected f ag(s) z xorm a,[m] logical x or a cc to d ata m emory description data i n t he s pecifed d ata m emory a nd t he a ccumulator p erform a b itwise l ogical x or operation. t he re sult is s tored in t he d ata m emory. operation [m] a cc xor [ m] affected f ag(s) z xor a,x logical x or im mediate data to a cc description data i n t he a ccumulator a nd t he s pecifed im mediate data p erform a b itwise l ogical x or operation. t he re sult is s tored in t he a ccumulator. operation acc a cc x or x affected f ag(s) z
rev. 1.20 2 ?? ? e ??? a ?? 1 ?? 201 ? rev. 1.20 2?? ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu extended instruction defnition the extended instructions are used to directly access the data stored in any data memory sections. ladc a,[m] add d ata m emory to a cc w ith carry description the c ontents o f t he s pecifed d ata m emory, a ccumulator a nd t he c arry f ag a re a dded. the re sult is s tored in t he a ccumulator. operation acc a cc + [ m] + c affected f ag(s) ov, z , a c, c , s c ladcm a,[m] add a cc to d ata m emory w ith carry description the c ontents o f t he s pecifed d ata m emory, a ccumulator a nd t he c arry f ag a re a dded. the re sult is s tored in t he sp ecifed d ata m emory. operation [m] a cc + [ m] + c affected f ag(s) ov, z , a c, c , s c ladd a,[m] add d ata m emory t o a cc description the c ontents o f t he s pecifed d ata m emory a nd t he a ccumulator a re a dded. the re sult is s tored in t he a ccumulator. operation acc a cc + [ m] affected f ag(s) ov, z , a c, c , s c laddm a,[m] add a cc to d ata m emory description the c ontents o f t he s pecifed d ata m emory a nd t he a ccumulator a re a dded. the re sult is s tored in t he sp ecifed d ata m emory. operation [m] a cc + [ m] affected f ag(s) ov, z , a c, c , s c land a,[m] logical a nd d ata m emory t o a cc description data i n t he a ccumulator a nd t he s pecifed d ata m emory p erform a b itwise l ogical a nd operation. t he re sult is s tored in t he a ccumulator. operation acc a cc a nd [ m] affected f ag(s) z landm a,[m] logical a nd a cc to d ata m emory description data i n t he s pecifed d ata m emory a nd t he a ccumulator p erform a b itwise l ogical a nd operation. t he re sult is s tored in t he d ata m emory. operation [m] a cc and [ m] affected f ag(s) z lclr [m] clear d ata m emory description each b it o f t he s pecifed d ata m emory i s cl eared t o 0 . operation [m] 00h affected f ag(s) none lclr [m].i clear bi t o f d ata m emory description bit i o f t he s pecifed d ata m emory i s cl eared t o 0 . operation [m].i 0 affected f ag(s) none
rev. 1.20 2?? ?e???a?? 1?? 201? rev. 1.20 2 ?? ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu lcpl [m] complement d ata m emory description each b it of t he s pecifed d ata m emory i s l ogically complemented ( 1s complement). b its w hich previously c ontained a 1 a re c hanged to 0 a nd v ice v ersa. operation [m] [m] affected f ag(s) z lcpla [m] complement d ata m emory w ith r esult i n a cc description each b it of t he s pecifed d ata m emory i s l ogically complemented ( 1s complement). b its w hich previously c ontained a 1 a re c hanged to 0 a nd v ice v ersa. th e c omplemented r esult i s s tored i n the a ccumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc [ m] affected f ag(s) z ldaa [m] decimal-adjust a cc f or addition w ith r esult i n d ata m emory description convert t he c ontents o f t he a ccumulator v alue to a b cd ( binary c oded d ecimal) v alue resulting f rom t he p revious a ddition o f t wo b cd v ariables. i f t he low n ibble is greater t han 9 or i f a c f ag i s s et, t hen a v alue o f 6 w ill b e a dded to t he l ow n ibble. o therwise t he l ow n ibble remains u nchanged. i f t he h igh n ibble i s g reater t han 9 o r i f t he c f ag i s s et, t hen a v alue o f 6 will b e a dded to t he h igh n ibble. e ssentially, t he decimal c onversion i s p erformed b y a dding 00h, 0 6h, 6 0h o r 6 6h depending o n t he a ccumulator a nd f ag c onditions. o nly t he c f ag may b e a ffected b y t his instruction w hich indicates t hat if t he o riginal b cd s um is greater t han 100, it al lows m ultiple p recision decimal a ddition. operation [m] a cc + 00h or [m] a cc + 06 h o r [m] a cc + 60h o r [m] a cc + 66h affected f ag(s) c ldec [m] decrement d ata m emory description data i n t he s pecifed d ata m emory i s d ecremented b y 1 . operation [m] [ m] ? 1 affected f ag(s) z ldeca [m] decrement d ata m emory wi th r esult i n a cc description data in t he sp ecifed d ata m emory is d ecremented b y 1 . t he re sult is s tored in t he accumulator. th e c ontents o f t he d ata m emory r emain u nchanged. operation acc [ m] ? 1 affected f ag(s) z linc [m] increment d ata m emory description data in t he sp ecifed d ata m emory is incremented b y 1 . operation [m] [ m] + 1 affected f ag(s) z linca [m] increment d ata m emory wi th r esult i n a cc description data i n t he sp ecifed d ata m emory i s i ncremented b y 1 . th e re sult i s s tored i n t he a ccumulator. the c ontents o f t he d ata m emory r emain u nchanged. operation acc [ m] + 1 affected f ag(s) z
rev. 1.20 2 ? 8 ? e ??? a ?? 1 ?? 201 ? rev. 1.20 2?9 ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu lmov a,[m] move d ata m emory t o a cc description the c ontents o f t he s pecifed d ata m emory a re c opied to t he a ccumulator. operation acc [ m] affected f ag(s) none lmov [m],a move a cc to d ata m emory description the c ontents o f t he a ccumulator a re c opied to t he s pecifed d ata m emory. operation [m] a cc affected f ag(s) none lor a,[m] logical o r d ata m emory to a cc description data i n t he a ccumulator a nd t he s pecifed d ata m emory p erform a b itwise logical o r op eration. t he re sult is s tored in t he a ccumulator. operation acc a cc or [ m] affected f ag(s) z lorm a,[m] logical or a cc to d ata m emory description data i n t he s pecifed d ata m emory a nd t he a ccumulator p erform a b itwise l ogical o r operation. t he re sult is s tored in t he d ata m emory. operation [m] a cc or [ m] affected f ag(s) z lrl [m] rotate d ata m emory l eft description the c ontents o f t he s pecifed d ata m emory a re r otated l eft b y 1 b it w ith b it 7 r otated i nto b it 0 . operation [m].(i+1) [ m].i; (i=0~6) [m].0 [ m].7 affected f ag(s) none lrla [m] rotate d ata m emory left w ith re sult in a cc description the c ontents o f t he s pecifed d ata m emory a re r otated l eft b y 1 b it w ith b it 7 r otated i nto b it 0 . the r otated r esult i s s tored i n t he a ccumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc.(i+1) [ m].i; (i=0~6) acc.0 [ m].7 affected f ag(s) none lrlc [m] rotate d ata m emory l eft t hrough carry description the c ontents o f t he s pecifed d ata m emory a nd t he c arry f ag a re r otated l eft b y 1 b it. b it 7 replaces t he c arry b it a nd t he o riginal c arry f ag i s r otated i nto b it 0 . operation [m].(i+1) [ m].i; (i=0~6) [m].0 c c [ m].7 affected f ag(s) c lrlca [m] rotate d ata m emory left t hrough c arry w ith re sult in a cc description data i n t he s pecifed d ata m emory and t he carry f ag are r otated l eft b y 1 b it. b it 7 r eplaces t he carry b it a nd t he o riginal c arry f ag i s r otated i nto t he b it 0 . th e r otated r esult i s s tored i n t he accumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc.(i+1) [ m].i; (i=0~6) acc.0 c c [ m].7 affected f ag(s) c
rev. 1.20 2?8 ?e???a?? 1?? 201? rev. 1.20 2 ? 9 ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu lrr [m] rotate d ata m emory r ight description the contents of t he s pecifed d ata m emory are r otated r ight b y 1 b it w ith b it 0 r otated i nto b it 7 . operation [m].i [ m].(i+1); (i=0~6) [m].7 [ m].0 affected f ag(s) none lrra [m] rotate d ata m emory right with result i n a cc description data i n t he s pecifed d ata m emory i s r otated r ight by 1 bit w ith bit 0 rotated i nto b it 7 . th e r otated r esult i s s tored i n t he a ccumulator a nd t he c ontents o f t he data m emory r emain u nchanged. operation acc.i [ m].(i+1); (i=0~6) acc.7 [ m].0 affected f ag(s) none lrrc [m] rotate d ata m emory r ight t hrough carry description the c ontents o f t he s pecifed d ata m emory a nd t he c arry f ag a re r otated r ight b y 1 b it. b it 0 replaces t he c arry b it a nd t he o riginal c arry f ag i s r otated i nto b it 7 . operation [m].i [ m].(i+1); (i=0~6) [m].7 c c [ m].0 affected f ag(s) c lrrca [m] rotate d ata m emory right th rough c arry with result i n a cc description data i n t he s pecifed d ata m emory a nd t he c arry f ag a re r otated r ight b y 1 b it. b it 0 r eplaces the c arry b it a nd t he o riginal c arry f ag i s r otated i nto b it 7 . th e r otated r esult i s s tored i n t he accumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc.i [ m].(i+1); (i=0~6) acc.7 c c [ m].0 affected f ag(s) c lsbc a,[m] subtract d ata m emory from a cc wi th c arry description the c ontents o f t he s pecifed d ata m emory a nd t he c omplement o f t he c arry f ag a re subtracted f rom t he a ccumulator. t he re sult is s tored in t he a ccumulator. n ote t hat if t he result o f s ubtraction is n egative, t he c f ag w ill b e c leared t o 0 , o therwise if t he re sult is positive o r z ero, t he c f ag w ill b e s et to 1 . operation acc a cc ? [ m] ? c affected f ag(s) ov, z , a c, c , s c, c z lsbcm a,[m] subtract d ata m emory from a cc wi th c arry a nd r esult i n d ata m emory description the c ontents o f t he s pecifed d ata m emory a nd t he c omplement o f t he c arry f ag a re subtracted f rom t he a ccumulator. t he re sult is s tored in t he d ata m emory. n ote t hat if t he result o f s ubtraction is n egative, t he c f ag w ill b e c leared t o 0 , o therwise if t he re sult is positive o r z ero, t he c f ag w ill b e s et to 1 . operation [m] a cc ? [ m] ? c affected f ag(s) ov, z , a c, c , s c, c z
rev. 1.20 280 ? e ??? a ?? 1 ?? 201 ? rev. 1.20 281 ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu lsdz [m] skip i f decrement d ata m emory i s 0 description the c ontents o f t he s pecifed d ata m emory a re fr st decremented b y 1 . i f t he r esult i s 0 t he following instruction is s kipped. a s t his re quires t he insertion o f a d ummy instruction w hile the n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he p rogram proceeds w ith t he f ollowing i nstruction. operation [m] [ m] ? 1 skip if [ m]=0 affected f ag(s) none lsdza [m] skip i f decrement d ata m emory i s z ero w ith r esult i n a cc description the c ontents o f t he s pecifed d ata m emory a re fr st decremented b y 1 . i f t he r esult i s 0 , t he following instruction is s kipped. t he re sult is s tored in t he a ccumulator b ut t he sp ecifed data m emory c ontents r emain u nchanged. a s t his r equires t he i nsertion o f a dummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he r esult is n ot 0 , the p rogram p roceeds w ith t he f ollowing instruction. operation acc [ m] ? 1 skip if a cc=0 affected f ag(s) none lset [m] set d ata m emory description each b it o f t he s pecifed d ata m emory i s s et t o 1 . operation [m] f fh affected f ag(s) none lset [m].i set b it o f d ata m emory description bit i o f t he s pecifed d ata m emory i s s et t o 1 . operation [m].i 1 affected f ag(s) none lsiz [m] skip i f i ncrement d ata m emory i s 0 description the c ontents o f t he sp ecifed d ata m emory a re f rst incremented b y 1 . i f t he re sult is 0 , t he following instruction is s kipped. a s t his re quires t he insertion o f a d ummy instruction w hile the n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he p rogram proceeds w ith t he f ollowing i nstruction. operation [m] [ m] + 1 skip if [ m]=0 affected f ag(s) none lsiza [m] skip if increment d ata m emory is z ero w ith re sult in a cc description the c ontents o f t he sp ecifed d ata m emory a re f rst incremented b y 1 . i f t he re sult is 0 , t he following instruction is s kipped. t he re sult is s tored in t he a ccumulator b ut t he sp ecifed data m emory c ontents r emain u nchanged. a s t his r equires t he i nsertion o f a dummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he p rogram p roceeds w ith t he f ollowing instruction. operation acc [ m] + 1 skip if a cc=0 affected f ag(s) none lsnz [m].i skip i f d ata m emory i s no t 0 description if t he sp ecifed d ata m emory is n ot 0 , t he f ollowing instruction is s kipped. a s t his re quires t he insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is 0 t he p rogram p roceeds w ith t he f ollowing instruction. operation skip i f [ m].i 0 affected f ag(s) none
rev. 1.20 280 ?e???a?? 1?? 201? rev. 1.20 281 ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu lsnz [m] skip i f d ata m emory i s no t 0 description if t he c ontent o f t he sp ecifed d ata m emory is n ot 0 , t he f ollowing instruction is s kipped. a s this re quires t he insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a two c ycle instruction. i f t he re sult is 0 t he p rogram p roceeds w ith t he f ollowing instruction. operation skip i f [ m] 0 affected f ag(s) none lsub a,[m] subtract d ata m emory from a cc description the s pecifed d ata m emory i s s ubtracted f rom t he c ontents o f t he a ccumulator. th e r esult i s stored in t he a ccumulator. n ote t hat if t he re sult o f s ubtraction is n egative, t he c f ag w ill b e cleared to 0 , o therwise i f t he r esult i s p ositive o r z ero, t he c f ag w ill b e s et to 1 . operation acc a cc ? [ m] affected f ag(s) ov, z , a c, c , s c, c z lsubm a,[m] subtract d ata m emory from a cc wi th r esult i n d ata m emory description the s pecifed d ata m emory i s s ubtracted f rom t he c ontents o f t he a ccumulator. th e r esult i s stored in t he d ata m emory. n ote t hat if t he re sult o f s ubtraction is n egative, t he c f ag w ill b e cleared to 0 , o therwise i f t he r esult i s p ositive o r z ero, t he c f ag w ill b e s et to 1 . operation [m] a cc ? [ m] affected f ag(s) ov, z , a c, c , s c, c z lswap [m] swap ni bbles of d ata m emory description the l ow-order a nd h igh-order n ibbles o f t he s pecifed d ata m emory a re i nterchanged. operation [m].3~[m].0 ? [ m].7~[m].4 affected f ag(s) none lswapa [m] swap ni bbles of d ata m emory w ith r esult i n a cc description the l ow-order a nd h igh-order n ibbles o f t he s pecifed d ata m emory a re i nterchanged. th e result i s s tored i n t he a ccumulator. th e c ontents o f t he d ata m emory r emain u nchanged. operation acc.3~acc.0 [ m].7~[m].4 acc.7~acc.4 [ m].3~[m].0 affected f ag(s) none lsz [m] skip i f d ata m emory i s 0 description if t he contents of t he s pecifed d ata m emory i s 0, t he following i nstruction i s s kipped. a s t his requires t he insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a t wo cycle instruction. i f t he re sult is n ot 0 t he p rogram p roceeds w ith t he f ollowing instruction. operation skip if [ m]=0 affected f ag(s) none lsza [m] skip i f d ata m emory i s 0 w ith data m ovement to a cc description the c ontents o f t he s pecifed d ata m emory a re c opied to t he a ccumulator. i f t he v alue i s z ero, the f ollowing instruction is s kipped. a s t his re quires t he insertion o f a d ummy instruction while t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he program p roceeds w ith t he f ollowing instruction. operation acc [ m] skip if [ m]=0 affected f ag(s) none
rev. 1.20 282 ? e ??? a ?? 1 ?? 201 ? rev. 1.20 283 ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu lsz [m].i skip i f b it i of d ata m emory i s 0 description if b it i o f t he sp ecifed d ata m emory is 0 , t he f ollowing instruction is s kipped. a s t his re quires the insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 , t he p rogram p roceeds w ith t he f ollowing instruction. operation skip if [ m].i=0 affected f ag(s) none ltabrd [m] read ta ble ( current p age) to t blh a nd d ata m emory description the low b yte o f t he p rogram c ode ( current p age) a ddressed b y t he t able p ointer ( tblp) is moved t o t he s pecifed d ata m emory a nd t he h igh by te mo ved t o t blh. operation [m] pr ogram c ode (low by te) tblh pr ogram c ode (high by te) affected f ag(s) none ltabrdl [m] read t able (last p age) t o t blh a nd d ata m emory description the l ow by te o f t he pr ogram c ode (last p age) a ddressed by t he t able p ointer (tblp) i s mo ved to t he s pecifed d ata m emory a nd t he h igh b yte m oved to t blh. operation [m] pr ogram c ode (low by te) tblh pr ogram c ode (high by te) affected f ag(s) none litabrd [m] increment ta ble p ointer l ow b yte fr st and r ead ta ble to t blh and d ata m emory description increment ta ble p ointer l ow b yte, t blp, fr st and t hen t he p rogram code addressed b y t he table p ointer ( tbhp and t blp) i s m oved to t he s pecifed d ata m emory and t he hi gh b yte moved t o t blh. operation [m] pr ogram c ode (low by te) tblh pr ogram c ode (high by te) affected f ag(s) none litabrdl [m] increment t able p ointer l ow by te f rst a nd r ead t able (last p age) t o t blh a nd d ata m emory description increment ta ble p ointer l ow b yte, t blp, fr st and t hen t he l ow b yte of t he p rogram code (last p age) addressed b y t he ta ble p ointer ( tblp) i s m oved to t he s pecifed d ata m emory and the h igh by te mov ed t o t blh. operation [m] pr ogram c ode (low by te) tblh pr ogram c ode (high by te) affected f ag(s) none lxor a,[m] logical x or d ata m emory to a cc description data i n t he a ccumulator a nd t he s pecifed d ata m emory p erform a b itwise l ogical x or operation. t he re sult is s tored in t he a ccumulator. operation acc a cc x or [ m] affected f ag(s) z lxorm a,[m] logical x or a cc to d ata m emory description data i n t he s pecifed d ata m emory a nd t he a ccumulator p erform a b itwise l ogical x or operation. t he re sult is s tored in t he d ata m emory. operation [m] a cc xor [ m] affected f ag(s) z
rev. 1.20 282 ?e???a?? 1?? 201? rev. 1.20 283 ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu package information note that the package information provided here is for consultation purposes only . as this information may be updated at regular intervals users are reminded to consult the holtek website for the latest version of the package/carton information . additional supplementary information with regard to pa ckaging is listed below. click on the relevant section to be transferred to the relevant website page. ? package information (include outline dimensions, product t ape and reel specifcations) ? the operation instruction of packing materials ? carton information
rev. 1.20 284 ? e ??? a ?? 1 ?? 201 ? rev. 1.20 285 ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu 48-pin lqfp (7mm 7mm) outline dimensions symbol dimensions in inch min. nom. max. a 0.354 bsc b 0.2 ?? bsc c 0.354 bsc d 0.2 ?? bsc e 0.020 bsc ? 0.00 ? 0.009 0.011 g 0.053 0.055 0.05 ? h 0.0 ? 3 i 0.002 0.00 ? j 0.018 0.024 0.030 k 0.004 0.008 0 ? symbol dimensions in mm min. nom. max. a 9.00 bsc b ? .00 bsc c 9.00 bsc d ? .00 bsc e 0.50 bsc ? 0.1 ? 0.22 0.2 ? g 1.35 1.40 1.45 h 1. ? 0 i 0.05 0.15 j 0.45 0. ? 0 0. ? 5 k 0.09 0.20 0 ?
rev. 1.20 284 ?e???a?? 1?? 201? rev. 1.20 285 ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu 64-pin lqfp (7mm 7mm) outline dimensions symbol dimensions in inch min. nom. max. a 0.354 bsc b 0.2 ?? bsc c 0.354 bsc d 0.2 ?? bsc e 0.01 ? bsc ? 0.005 0.00 ? 0.009 g 0.053 0.055 0.05 ? h 0.0 ? 3 i 0.002 0.00 ? j 0.018 0.024 0.030 k 0.004 0.008 0 ? symbol dimensions in mm min. nom. max. a 9.00 bsc b ? .00 bsc c 9.00 bsc d ? .00 bsc e 0.40 bsc ? 0.13 0.18 0.23 g 1.35 1.40 1.45 h 1. ? 0 i 0.05 0.15 j 0.45 0. ? 0 0. ? 5 k 0.09 0.20 0 ?
rev. 1.20 28 ? ? e ??? a ?? 1 ?? 201 ? rev. 1.20 28? ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu 80-pin lqfp (10mm 10mm) outline dimensions symbol dimensions in inch min. nom. max. a D 0.4 ? 2 bsc D b D 0.394 bsc D c D 0.4 ? 2 bsc D d D 0.394 bsc D e D 0.015 bsc D ? 0.00 ? 0.009 0.011 g 0.053 0.055 0.05 ? h D D 0.0 ? 3 i 0.002 D 0.00 ? j 0.018 0.024 0.030 k 0.004 D 0.008 0 D ? symbol dimensions in mm min. nom. max. a 12.00 bsc b 10.00 bsc c 12.00 bsc d 10.00 bsc e D 0.40 bsc D ? 0.13 0.18 0.23 g 1.35 1.40 1.45 h D D 1. ? 0 i 0.05 0.15 j 0.45 0. ? 0 0. ? 5 k 0.09 D 0.20 0 D ?
rev. 1.20 28? ?e???a?? 1?? 201? rev. 1.20 28 ? ? e ??? a ?? 1 ?? 201 ? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu 128-pin lqfp (14mm 14mm) outline dimensions (exposed pad) b a c d e f g h j k i symbol dimensions in inch min. nom. max. a 0. ? 30 bsc b 0.551 bsc c 0. ? 30 bsc d 0.551 bsc d2 0.228 0.23 ? e 0.01 ? bsc e2 0.228 0.23 ? ? 0.005 0.00 ? 0.009 g 0.053 0.055 0.05 ? h 0.0 ? 3 i 0.002 0.00 ? j 0.018 0.024 0.030 k 0.004 0.008 0 D ? symbol dimensions in mm min. nom. max. a 1 ? .00 bsc b 14.00 bsc c 1 ? .00 bsc d 14.00 bsc d2 5. ? 9 5.99 e 0.40 bsc e2 5. ? 9 5.99 ? 0.13 0.1 ? 0.23 g 1.35 1.40 1.45 h 1. ? 0 i 0.05 0.15 j 0.45 0. ? 0 0. ? 5 k 0.09 0.20 0 D ?
rev. 1.20 288 ? e ??? a ?? 1 ?? 201 ? rev. 1.20 pb ?e???a?? 1?? 201? ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu ht66fb572/ht66fb574/HT66FB576 usb rgb led flash mcu cop ?? ight ? 201 ? ?? holtek semiconductor inc. the info ? mation appea ? ing in this data sheet is ? elieved to ? e acc ?? ate at the time of p ?? lication. howeve ?? holtek ass ? mes no ? esponsi ? ilit ? a ? ising f ? om the ? se of the specifcations described. the applications mentioned herein are used solely fo ? the p ?? pose of ill ? st ? ation and holtek makes no wa ?? ant ? o ? ? ep ? esentation that s ? ch applications will ? e s ? ita ? le witho ? t f ?? the ? modification ? no ? ? ecommends the ? se of its p ? od ? cts fo ? application that ma ? p ? esent a ? isk to h ? man life d ? e to malf ? nction o ? othe ? wise. holtek's p ? od ? cts a ? e not a ? tho ? ized fo ? ? se as c ? itical components in life s ? ppo ? t devices o ? s ? stems. holtek ? ese ? ves the ? ight to alte ? its products without prior notifcation. for the most up-to-date information, please visit o ?? we ? site at http://www.holtek.com/en/.

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