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datasheet very low power cl ock for 2011 netbooks 9VRS4339B idt? very low power clock for 2011 netbooks 1 9VRS4339B rev a 010312 general description the 9VRS4339B is a intel ck-n et compatible main clock for intel netbooks, conforming to the ck-net specification. it is driven with a 25mhz crystal and generates a variety of clocks, including an lcd clock. an smbus interface allows full control of the device. output features ? 2 ? 0.8v push-pull differential cpu pairs ? 5 ? 0.8v push-pull differential src pairs ? 1 ? 0.8v push-pull differential sata pair ? 1 ? 0.8v push-pull differential dot96/src pair ? 1 ? 0.8v push-pull differential lcd100 pair ? 1 ? 0.8v push-pull differential cpu_itp/src pair ? 2 ? pci (33mhz) ? 1 ? pci_f, (33mhz) free-running ? 1 ? usb_48mhz ? 1 ? 48mhz ? 1 ? 25mhz ? 1 ? 27mhz/pci ? 1 ? 14.318mhz features/benefits ? supports wake_on_lan (see pin55 pin description) ? selectable spread % on cpu, src, pci; supports margining ? uses external 25mhz crystal, external crystal load caps are required for frequency tuning ? clkreq# pins; support src power management ? low power differential clock outputs driving 100 ohm differential traces; reduced powe ? integrated 33 ohm series resistors on all differential outputs; reduced board space key specifications ? cpu outputs cycle-to-cycle jitter <85ps ? src cycle-to-cycle jitter <85ps ? src meets pciex gen2 specifications ? sata outputs cycle-to-cycle jitter <125ps ? pci outputs cycle-to-cycle jitter <500ps ? 100ppm frequency accuracy on all clocks pin configuration gnd25 clkpwrgd/pd#_3.3 cpu0_lprs cpu0#_lprs gndcpu cpu1_lprs cpu1#_lprs vddcpu_lvio vdd_core_1.5 cpu_itp/src1_lprs cpu_itp#/src1#_lprs cpu_stop#_3.3 src7_lprs src#7_lprs 56 55 54 53 52 51 50 49 48 47 46 45 44 43 x2 142 src2_lprs x1 241 src2#_lprs vdd25_3.3 340 gndsrc 25m 4 39 src6_lprs sdata_3.3 5 38 src6#_lprs sclk_3.3 6 37 src3_lprs vddpci_3.3 7 36 src3#_lprs vitp_en/pci_f1_2x 8 35 pci_stop#_3.3 fslb/pci2_2x 9 34 vddsrc_lvio clkreqa#/pci3_2x 10 33 src4_lprs gndpci 11 32 src4#_lprs gnd14m 12 31 sata_lprs 14m_2x/fslc 13 30 sata#_lprs vdd14_3.3 14 29 gndsata 15 16 17 18 19 20 21 22 23 24 25 26 27 28 v dd48_3.3 ^dot96_sel/usb48m clkreqc#/48m gnd48 clkreqb# vdd27 vsel_pci/27m_pci4_2x gnd27 dot96_lprs/src5_lprs dot96#_lprs/src5#_lprs vdd_core_1.5 lcd100_lprs lcd100#_lprs gndlcd v p refix indicates internal p ull-down resistor ^ prefix indicates internal pull-up resistor 9VRS4339B
9VRS4339B very low power clock for 2011 netbooks idt? very low power clock for 2011 netbooks 2 9VRS4339B rev a 010312 pin descriptions pin # pin name type description 1 x2 out cr y stal out p ut, nominall y 25mhz 2x1 in cr y stal in p ut, nominall y 25mhz 3 vdd25_3.3 pwr power p in for cr y stal and 25mhz out p ut, nominal 3.3v 4 25m out 3.3v 25mhz clock out p ut 5 sdata_3.3 i/o data p in for smbus circuitr y , 3.3v tolerant. 6 sclk_3.3 out clock p in of smbus circuitr y , 3.3v tolerant. 7 vddpci_3.3 pwr power su pp l y for pci clocks, nominal 3.3v 8 vitp_en/pci_f1_2x i/o itp enable latched input itp_enable selects the functionality of the cpu_itp/src output as follows: 1 = cpu_itp output 0 = src1 output / free-runnin g 3.3v pci clock out p ut, default to drive 2 loads. 9 fslb/pci2_2x i/o 3.3v tolerant input for cpu frequency selection. low voltage threshold inputs, see input electrical characteristics for vil_fs and vih_fs values / 3.3v pci clock output, default to drive 2 loads. 10 clkreqa#/pci3_2x i/o 3.3v real-time output enable for pci express (src) outputs. smbus selects which outputs are controlled. pin function is programmable through smbus. see clkreq# control table and src power management table for details 0 = controlled outputs are enabled 1 = controlled outputs are low/low / 3.3v pci clock out p ut, default to drive 2 loads. . 11 gndpci pwr ground p in for the pci out p uts 12 gnd14m pwr ground p in for the 14.318mhz out p ut 13 14m_2x/fslc i/o 3.3v 14.318 mhz clock output, default to drive 2 loads / 3.3v tolerant input for cpu frequency selection. refer to input electrical characteristics for vil_fs and vih_fs values. 14 vdd14_3.3 pwr power p in for 14.318mhz out p ut, nominal 3.3v 15 vdd48_3.3 pwr power p in for 48mhz out p uts, nominal 3.3v 16 ^dot96_sel/usb48m i/o input latched pin to select pin23/24 as dot 96mhz clock or src clock 1 = dot96 output 0 = src5 output / 3.3v 48mhz usb clock out p ut. 17 clkreqc#/48m i/o 3.3v real-time output enable for pci express (src) outputs. smbus selects which outputs are controlled. pin function is programmable through smbus. see clkreq# control table and src power management table for details 0 = controlled outputs are enabled 1 = controlled outputs are low/low / 3.3v 48mhz clock out p ut 18 gnd48 pwr ground p in for 48mhz out p uts 19 clkreqb# in 3.3v real-time output enable for pci express (src) outputs. smbus selects which outputs are controlled. 0 = controlled outputs are enabled 1 = controlled out p uts are low/low 20 vdd27 pwr power p in for 27mhz out p ut , nominal 3.3v 21 vsel_pci/27m_pci4_2x i/o 3.3v input latch pin to select this pin as 27m output or pci4 clock output. this pin has an internal pulldown resistor. latch functionality is as follows: 0 = 27mhz output 1 = 33.33mhz pci out p ut 22 gnd27 pwr ground p in for the 27mhz out p ut 23 dot96_lprs/src5_lprs out true clock of push-pull dot96 or src clock with integrated series resistor. no 50 ohm p ull down needed. default is p endin g on pin16 dot96_sel. 24 dot96#_lprs/src5#_lprs out complement clock of push-pull dot96 or src clock with integrated series resistor. no 50 ohm p ull down needed. default is p endin g on pin16 dot96_sel. 25 vdd_core_1.5 pwr power p in for core pll's, nominal 1.5v. 26 lcd100_lprs out true clock of differential push-pull lcd100 output with integrated 33ohm series resistor. no 50ohm resistor to gnd needed. 27 lcd100#_lprs out complementary clock of differential push-pull lcd100 output with integrated 33ohm series resistor. no 50ohm resistor to gnd needed. 28 gndlcd pwr ground p in for lcd clock out p ut
9VRS4339B very low power clock for 2011 netbooks idt? very low power clock for 2011 netbooks 3 9VRS4339B rev a 010312 pin descriptions (cont.) 29 gndsata pwr ground p in for the sata out p uts 30 sata#_lprs out complementary clock of low power differential push-pull sata clock pair with inte g rated 33ohm series resistor. no 50 ohm resistor to gnd needed. 31 sata_lprs out true clock of low power differential push-pull sata clock pair with integrated 33ohm series resistor. no 50 ohm resistor to gnd needed. 32 src4#_lprs out complementary clock of differential 0.8v push-pull src output with integrated 33ohm series resistor. no 50ohm resistor to gnd needed. 33 src4_lprs out true clock of differential 0.8v push-pull src output with integrated 33ohm series resistor. no 50ohm resistor to gnd needed. 34 vddsrc_lvio pwr power p in for src i/o, nominall y 1.05v to 1.5v from external p ower su pp l y 35 pci_stop#_3.3 in stops all stoppable pci, sata and src clocks when low. free-running pci, sata and src clocks are not effected b y this in p ut. this in p ut is 3.3v tolerant. 36 src3#_lprs out complementary clock of differential 0.8v push-pull src output with integrated 33ohm series resistor. no 50ohm resistor to gnd needed. 37 src3_lprs out true clock of differential 0.8v push-pull src output with integrated 33ohm series resistor. no 50ohm resistor to gnd needed. 38 src6#_lprs out complementary clock of differential 0.8v push-pull src output with integrated 33ohm series resistor. no 50ohm resistor to gnd needed. 39 src6_lprs out true clock of differential 0.8v push-pull src output with integrated 33ohm series resistor. no 50ohm resistor to gnd needed. 40 gndsrc pwr ground p in for the src out p uts 41 src2#_lprs out complementary clock of differential 0.8v push-pull src output with integrated 33ohm series resistor. no 50ohm resistor to gnd needed. 42 src2_lprs out true clock of differential 0.8v push-pull src output with integrated 33ohm series resistor. no 50ohm resistor to gnd needed. 43 src#7_lprs out complementary clock of differential 0.8v push-pull src output with integrated 33ohm series resistor. no 50ohm resistor to gnd needed. 44 src7_lprs out true clock of differential 0.8v push-pull src output with integrated 33ohm series resistor. no 50ohm resistor to gnd needed. 45 cpu_stop#_3.3 in sto p s all sto pp able cpu clocks when enabled. this is a 3.3v tolerant in p ut. 46 cpu_itp#/src1#_lprs out complementary clock of low power differential cpu_itp/src pair with integrated 33ohm series resistor. no 50ohm resistor to gnd needed. the pin function is determined by the latched value on itp_en: 0 = src1# 1 = cpu_itp# 47 cpu_itp/src1_lprs out true clock of low power differential cpu_itp/src pair with integrated 33ohm series resistor. no 50ohm resistor to gnd needed. the pin function is determined by the latched value on itp_en: 0 = src1 1 = cpu_itp 48 vdd_core_1.5 pwr power p in for core pll, nominal 1.5v 49 vddcpu_lvio pwr power p in for cpu i/o, nominall y 1.05v to 1.5v from external p ower su pp l y 50 cpu1#_lprs out complementary clock of differential pair 0.8v push-pull cpu output with integrated 33ohm series resistor. no 50 ohm resistor to gnd needed. 51 cpu1_lprs out true clock of differential pair 0.8v push-pull cpu output with integrated 33ohm series resistor. no 50 ohm resistor to gnd needed. 52 gndcpu pwr ground p in for the cpu out p uts 53 cpu0#_lprs out complementary clock of differential pair 0.8v push-pull cpu output with integrated 33ohm series resistor. no 50 ohm resistor to gnd needed. 54 cpu0_lprs out true clock of differential pair 0.8v push-pull cpu output with integrated 33ohm series resistor. no 50 ohm resistor to gnd needed. 55 clkpwrgd/pd#_3.3 in this 3.3v lvttl input notifies device to sample latched inputs and start up on first high assertion or exit power down mode on subsequent assertions. when wlan enable in byte13 bit 5 =1, device will enter wake-on-lan mode with 25mhz being free-running. 1 = normal operation 0 = power down mode or wake-on-lan mode note: for lowest power saving during wol mode, it is mandatory to connect 3.3v and 1.5v core vdd p ins to standb y p ower and sus p end/remove vddio p ins. 56 gnd25 pwr ground p in for 25mhz
9VRS4339B very low power clock for 2011 netbooks idt? very low power clock for 2011 netbooks 4 9VRS4339B rev a 010312 block diagram programmable ss lcd pll cpuclk programmable ss cpu/src pll fix pll2 fix pll1 25mhz sataclk 27fix 14.318m srcclk pciclk 25mhz lcdclk usb48, 48m /2 dot96 series r esistors for single ended outputs 1 load rs = 2 loads rs= 3 loads rs = 1 0.56 / 33 (17 ? )33 ? [39 ? ] - - 2 0.92 / 66 (14 ? )39 ? [43 ? ]22 ? [27 ? ]- notes: 2. desktop/mobile platforms with zo = 50/55 ohms use the first resistor value. 3. systems w ith zo = 60 ohms use the resistor values in brackets [ ]. match point for n & p voltage / current (ma) 1. preferred drive strengths using ck505 clock sources. transmission lines to load do not share series re sistors. number of loads to drive number of loads actually driven. d.c.drive strength
9VRS4339B very low power clock for 2011 netbooks idt? very low power clock for 2011 netbooks 5 9VRS4339B rev a 010312 table 1: cpu/src pll spread frequency selection table 2: lcd spread selection table cpu/src ss select (b1b6) ss1 (b1b5) ss0 (b1b4) fslc (b0b7) fslb (b0b6) spread % cpu mhz src mhz sata mhz pci mhz 00000 -0.50% 133.33 100.00 100.00 33.33 0 0 00 1 -0.50% 166.6 7 100.0 0 100.00 33.33 0 0 01 0 -0.50% 100.0 0 100.0 0 100.00 33.33 0 0 01 1 - 0 .5 0% 200.0 0 100.0 0 100.00 33.33 00100 -0.40% 133.3 3 100.00 100.00 33.33 00101 -0.40% 166.6 7 100.00 100.00 33.33 00110 -0.40% 100.00 100.00 100.00 33.33 00111 -0.40% 200.00 100.00 100.00 33.33 01000 -0.30% 133.3 3 100.00 100.00 33.33 01001 -0.30% 166.67 100.00 100.00 33.33 01010 -0.30% 100.00 100.00 100.00 33.33 01011 -0.30% 200.00 100.00 100.00 33.33 01100 off 133.3 3 100.00 100.00 33.33 01101 off 166.6 7 100.00 100.00 33.33 01110 off 100.00 100.00 100.00 33.33 01111 off 200.00 100.00 100.00 33.33 10000 +/-0.25% 133.3 3 100.00 100.00 33.33 10001 +/-0.25% 166.6 7 100.00 100.00 33.33 10010 +/-0.25% 100.00 100.00 100.00 33.33 10011 +/-0.25% 200.00 100.00 100.00 33.33 10100 +/-0.20% 133.3 3 100.00 100.00 33.33 10101 +/-0.20% 166.6 7 100.00 100.00 33.33 10110 +/-0.20% 100.00 100.00 100.00 33.33 10111 +/-0.20% 200.00 100.00 100.00 33.33 11000 +/-0.15% 133.3 3 100.00 100.00 33.33 11001 +/-0.15% 166.6 7 100.00 100.00 33.33 11010 +/-0.15% 100.00 100.00 100.00 33.33 11011 +/-0.15% 200.00 100.00 100.00 33.33 11100 off 133.3 3 100.00 100.00 33.33 11101 off 166.67 100.00 100.00 33.33 11110 off 100.00 100.00 100.00 33.33 11111 off 200.00 100.00 100.00 33.33 * bold is defaul t fs2 fs1 fs0 lcd ss spread lcd10 0 010 0 -0.50% 100.00 011 0 -1.0% 100.00 100 0 -1.5% 100.00 101 0 -2.0% 100.00 110 0 -2.50% 100.00 010 1 +/-0.25% 100.00 011 1 +/-0.5% 100.00 100 1 +/-0.75% 100.00 101 1 +/-1.0% 100.00 110 1 +/-1.25% 100.00 * bold is default
9VRS4339B very low power clock for 2011 netbooks idt? very low power clock for 2011 netbooks 6 9VRS4339B rev a 010312 power distribution table cpu power management table dot96 and sata power management table src power management table single-ended power management table clkreq# control table 3.3v vdd 1.5v vdd 1.05-1.5v vdd gnd 3 - - 56 25mhz crystal i/o; internal control logic; 25mhz output 7 - - 11 pciclk outputs 14 - - 12 14.318mhz & 27mhz outputs, 14/27mhz pll digital 15 - - 18 48mhz output 20 - - 22 27mhz output, 14/27mhz pll analog - 25 - 28, 29 dot96 fix pll analog & digital, lcd100 pll analog & digital - - 34 40 src outputs - 48 - 52 cpu/src pll analog & digital - - 49 52 cpu outputs pin number description true o/p comp. o/p 1 enable 1 r unning running 1enable0 highlow 0 x x low/20k low x disable x low/20k low clkpwrgd/p d#_3.3 sm bus register oe cpu_stop# cpu (0, 1, itp) true o/p comp. o/p true o/p comp. o/p true o/p comp. o/p 1 enable 1 0 running r unning running r unning running r unning 1 enable 1 1 low/20k low running r unning running r unning 0 x x x low/20k low low/20k low low/20k low xdisablex x low/20k low low/20k low low/20k low clkpwrgd/p d #_3.3 sm bus register oe pci_ stop# clkr eqc# sata dot96 pereqc# controlled pereqc# not-controlled sata tr ue o /p c omp. o/ p tr ue o /p c omp. o/ p tr ue o /p c omp. o/ p true o/p c om p. o/ p 1 enable 1 0 running r unning running r unning running r unning running r unning 1 enable 1 1 low/20k low runnin g r unnin g low/20k low runnin g r unnin g 1 enable 0 0 running r unning runnin g r unnin g hi g h low hi g h low 1 enable 0 1 low/20k low runnin g r unnin g low/20k low hi g h low 0 enable x x low/20k low low/20k low low/20k low low/20k low x disable x x low/20k low low/20k low low/20k low low/20k low clkpwrgd/p d #_3.3 sm bus register oe pci_stop# clkreqx# src controlled by clkreqx# src not controlled by clkreqx# src controlled by clkreqx# src not controlled by clkreqx# free-running stoppable free-run stoppable free-run stoppable wol enabled wol disabled 1 enable 1 r unning running r unning running r unning running r unning running r unning r unning 1 enable 0 r unning low r unning low r unning running r unning running r unning r unning 0 enable x hi-z hi-z low low r unning low hi-z hi-z low hi-z 0 disable x hi-z hi-z low low low low hi-z hi-z low hi-z 1 disable x low low low low low low low low low low pc i3 2 5m clkpwrgd/p d#_3.3 sm bus register oe pci_ stop# pci_f1, pci2, pci4 14.318m usb48 48m 27mhz a src1, 2, 3 bsrc4, 6 c src5, 7, sata clkreq# src /sata controlled
9VRS4339B very low power clock for 2011 netbooks idt? very low power clock for 2011 netbooks 7 9VRS4339B rev a 010312 general smbus serial interf ace information for 9vrs4339 how to write ? controller (host) sends a start bit ? controller (host) sends the write address ? idt clock will acknowledge ? controller (host) sends the beginning byte location = n ? idt clock will acknowledge ? controller (host) sends the byte count = x ? idt clock will acknowledge ? controller (host) starts sending byte n through byte n+x-1 ? idt clock will acknowledg e each byte one at a time ? controller (host) sends a stop bit how to read ? controller (host) will send a start bit ? controller (host) sends the write address ? idt clock will acknowledge ? controller (host) sends the beginning byte location = n ? idt clock will acknowledge ? controller (host) will send a separate start bit ? controller (host) sends the read address ? idt clock will acknowledge ? idt clock will send the data byte count = x ? idt clock sends byte n+x-1 ? idt clock sends byte 0 through byte x (if x (h) was written to byte 8) ? controller (host) will need to acknowledge each byte ? controller (host) will send a not acknowledge bit ? controller (host) will send a stop bit index block write operation controller (host) idt (slave/receiver) tstart bit slave address wr write ack beginning byte = n ack data byte count = x ack beginning byte n x byte ack o o o o o o byte n + x - 1 ack pstop bit read address write address d3 (h) d2 (h) index block read operation controller (host) idt (slave/receiver) tstart bit slave address wr write ack beginning byte = n ack rt repeat start slave address rd read ack data byte count=x ack x byte beginning byte n ack o o o o o o byte n + x - 1 n not acknowledge pstop bit
9VRS4339B very low power clock for 2011 netbooks idt? very low power clock for 2011 netbooks 8 9VRS4339B rev a 010312 smbus table: frequency select, pd config source select register byte 0 name control function type 0 1 default bit 7 fslc freq select bit 1 rw latch bit 6 fslb freq select bit 0 rw latch bit 5 cpu1 stop en enables control of cpu1 with cpu_stop rw free-running stoppable 0 bit 4 cpu0 stop en enables control of cpu0 with cpu_stop rw free-running stoppable 0 bit 3 pci_ssel pci source select rw cpu/src ss pll fix pll 0 bit 2 src_ssel src source select rw cpu/src ss pll fix pll 0 bit 1 sata_ssel sata source select rw cpu/src ss pll fix pll 0 bit 0 pd config forces "cold" start during pd rw reset and relatch normal pd# mode 1 smbus table: cpu, lcd ss and dot96/src5 control register byte 1 name control function type 0 1 default bit 7 dot96_sel selects dot96 or src5 r src5 dot96 latch bit 6 cpu/src ss select selects center or down spread for cpu & src rw down spread center spread 0 bit 5 cpu ss1 cpu ss magnitude msb rw 0 bit 4 cpu ss0 cpu ss magnitude lsb rw 0 bit 3 lcd ss2 lcd ss magnitude msb rw 1 bit 2 lcd ss1 lcd ss magnitude rw 1 bit 1 lcd ss0 lcd ss magnitude lsb rw 0 bit 0 lcd ss select selects center or down spread for lcdclk rw down spread center spread 0 smbus table: output enable control register byte 2 name control function type 0 1 default bit 7 ref oe output enable rw disable enable 1 bit 6 48m oe (pin17) output enable rw disable enable 1 bit 5 usb48m oe (pin16) output enable rw disable enable 1 bit 4 25m oe output enable rw disable enable 1 bit 3 pci3 oe output enable rw disable enable 1 bit 2 pci2 oe output enable rw disable enable 1 bit 1 pci_f1 oe output enable rw disable enable 1 bit 0 cpu_itp stop en enables control of cpu_itp with cpu_stop rw free-running stoppable 0 smbus table: output enable control register byte 3 name control function type 0 1 default bit 7 src7 oe output enable rw disable enable 1 bit 6 src6 oe output enable rw disable enable 1 bit 5 clkreqc# control src5 is controlled rw not controlled controlled 0 bit 4 clkreqc# control src7 is controlled rw not controlled controlled 0 bit 3 pci4/27m oe output enable rw disable enable 1 bit 2 lcdclk oe lcdpll & output enable rw disable enable 1 bit 1 src4 oe output enable rw disable enable 1 bit 0 sata oe output enable rw disable enable 1 smbus table: output enable and ss enable control register byte 4 name control function type 0 1 default bit 7 src3 oe output enable rw disable enable 1 bit 6 src2 oe output enable rw disable enable 1 bit 5 cpu_itp/src1 oe output enable rw disable enable 1 bit 4 dot96/src5 oe output enable rw disable enable 1 bit 3 cpu1 oe output enable rw disable enable 1 bit 2 cpu0 oe output enable rw disable enable 1 bit 1 cpu/src pll ss en output enable rw ss off ss on 1 bit 0 clkreqc# control sata is controlled rw not controlled controlled 0 see table 1: cpu/src pll frequency & spread selection table see table 1: cpu/src pll frequency & spread selection table see table 2: lcdclk spread spectrum table
9VRS4339B very low power clock for 2011 netbooks idt? very low power clock for 2011 netbooks 9 9VRS4339B rev a 010312 smbus table: clkreq control register byte 5 name control function type 0 1 default bit 7 clkreqa# en clkreqa# enable rw disable enable 0 bit 6 clkreqa# control src1 is controlled rw not controlled controlled 0 bit 5 clkreqa# control src2 is controlled rw not controlled controlled 0 bit 4 clkreqa# control src3 is controlled rw not controlled controlled 0 bit 3 clkreqb# en clkreqb# enable rw disable enable 0 bit 2 clkreqb# control src4 is controlled rw not controlled controlled 0 bit 1 clkreqb# control src6 is controlled rw not controlled controlled 0 bit 0 clkreqc# en clkreqc# enable rw disable enable 0 byte 6 reserved register smbus table: revision and vendor id register byte 7 name control function type 0 1 default bit 7 rid3 r 0 bit 6 rid2 r 0 bit 5 rid1 r 0 bit 4 rid0 r 1 bit 3 vid3 r 0 bit 2 vid2 r 0 bit 1 vid1 r 0 bit 0 vid0 r 1 smbus table: output control register byte 8 name control function type 0 1 default bit 7 rw 00 = 1.5v/ns 01 = 2.0v/ns 0 bit 6 rw 10 = 2.6v/ns 11 = 3.3v/ns 0 bit 5 rw 00 = 1.5v/ns 01 = 2.0v/ns 0 bit 4 rw 10 = 2.6v/ns 11 = 3.3v/ns 0 bit 3 reserved reserved rw - - 0 bit 2 pci_skew_mode pciclk skew mode control rw pci aligned pci delayed 0 bit 1 lcd_amp<1> lcd amplitude control bit1 rw 00 = 700mv 01 = 800mv 0 bit 0 lcd_amp<0> lcd amplitude control bit0 rw 10 = 900mv 11 = 1000mv 1 note: a ssystem reset maybe required when switching between pciclk aligned and skew mode smbus table: byte count register byte 9 name control function type 0 1 default bit 7 48m_sel selects 48m or clkreqc rw clkreqc 48m 1 bit 6 reserved reserved rw - - 0 bit 5 reserved reserved rw - - 0 bit 4 bc4 rw 0 bit 3 bc3 rw 1 bit 2 bc2 rw 1 bit 1 bc1 rw 1 bit 0 bc0 rw 1 smbus table: output control register byte 10 name control function type 0 1 default bit 7 rw 00 = 1.5v/ns 01 = 2.0v/ns 0 bit 6 rw 10 = 2.6v/ns 11 = 3.3v/ns 0 bit 5 rw 00 = 1.5v/ns 01 = 2.0v/ns 0 bit 4 rw 10 = 2.6v/ns 11 = 3.3v/ns 0 bit 3 rw 00 = 1.5v/ns 01 = 2.0v/ns 0 bit 2 rw 10 = 2.6v/ns 11 = 3.3v/ns 0 bit 1 rw 00 = 1.5v/ns 01 = 2.0v/ns 0 bit 0 rw 10 = 2.6v/ns 11 = 3.3v/ns 0 25m sr slew rate control ref sr slew rate control pci3 sr slew rate control note: to enable clkreqc function, please write "0" to byte 9 bit 7 and "1" to byte 5 bit 0. to select which output to control, please make necessay selection in bytes 3 & 4. writing to this register will configure how many bytes will be read back, default is 0f or 1f = 15 bytes. note: to enable clkreqc function, please write "0" to byte 9 bit 7 and "1" to byte 5 bit 0. to select which output to control, please make necessay selection in bytes 3 & 4. byte count programming usb48m (pin16) sr slew rate control 27m / pci4 sr slew rate control 48m (pin17) sr slew rate control vendor id 0001 = ics/idt revision id b rev = 0001
9VRS4339B very low power clock for 2011 netbooks idt? very low power clock for 2011 netbooks 10 9VRS4339B rev a 010312 smbus table: output control register byte 11 name control function type 0 1 default bit 7 cpu differential slew rate rw 0=2.5v/ns 1=4v/ns 1 bit 6 src differential slew rate rw 0=2.5v/ns 1=4v/ns 1 bit 5 sata differential slew rate rw 0=2.5v/ns 1=4v/ns 1 bit 4 dot96 differential slew rate rw 0=2.5v/ns 1=4v/ns 1 bit 3 rw 00 = 1.5v/ns 01 = 2.0v/ns 0 bit 2 rw 10 = 2.6v/ns 11 = 3.3v/ns 0 bit 1 rw 00 = 1.5v/ns 01 = 2.0v/ns 0 bit 0 rw 10 = 2.6v/ns 11 = 3.3v/ns 0 smbus table: m/n enable & output stop control register byte 12 name control function type 0 1 default bit 7 cpu/src pll m/n en enables m/n programming for cpu/src pll rw disable enable 0 bit 6 src1 stop en enables control of src1 with pci_stop rw free-running stoppable 0 bit 5 src2 stop en enables control of src2 with pci_stop rw free-running stoppable 0 bit 4 src3 stop en enables control of src3 with pci_stop rw free-running stoppable 0 bit 3 src4 stop en enables control of src4 with pci_stop rw free-running stoppable 0 bit 2 src5 stop en enables control of src5 with pci_stop rw free-running stoppable 0 bit 1 src6 stop en enables control of src6 with pci_stop rw free-running stoppable 0 bit 0 src7 stop en enables control of src7 with pci_stop rw free-running stoppable 0 smbus table: output control register byte 13 name control function type 0 1 default bit 7 itp_en itp_en readback r src1 cpu_itp latch bit 6 sel_pci select pci readback r 27m pci4 latch bit 5 wol enable wol enable for 25m rw wol disabled wol enabled 1 bit 4 pci_f1 free running with pci_stop# rw free-running stoppable 0 bit 3 pci2 free running with pci_stop# rw free-running stoppable 1 bit 2 pci3 free running with pci_stop# rw free-running stoppable 1 bit 1 pci4 free running with pci_stop# rw free-running stoppable 1 bit 0 sata stop en enables control of sata with pci_stop rw free-running stoppable 0 smbus table: differential output amplitude control register byte 14 name control function type 0 1 default bit 7 pciex_amp<1> pciex amplitude control bit1 rw 00 = 700mv 01 = 800mv 0 bit 6 pciex_amp<0> pciex amplitude control bit0 rw 10 = 900mv 11 = 1000mv 1 bit 5 dot96_amp<1> dot96 amplitude control bit1 rw 00 = 700mv 01 = 800mv 0 bit 4 dot96_amp<0> dot96 amplitude control bit0 rw 10 = 900mv 11 = 1000mv 1 bit 3 sata_amp<1> sata amplitude control bit1 rw 00 = 700mv 01 = 800mv 0 bit 2 sata_amp<0> sata amplitude control bit0 rw 10 = 900mv 11 = 1000mv 1 bit 1 cpu_amp<1> cpuclk amplitude control bit1 rw 00 = 700mv 01 = 800mv 0 bit 0 cpu_amp<0> cpuclk amplitude control bit0 rw 10 = 900mv 11 = 1000mv 1 bytes 15+ reserved registers ******************************************************************************************************************************* ***************************************** all reserved bits and reserved bytes in this smbus table s hould not be overwritten at any instance. writing to th ese reserved bits and bytes may cause unexpected behavior. idt does not warrant any application issue going forward if continuing to overwrite these reserve bits and bytes. pci1 slew rate control pci2 slew rate control * for lowest power saving during wol mode, it is mandatory to connect 3.3v and 1.5v core vdd pins to standby power and sus p end/remove vddio p ins.
9VRS4339B very low power clock for 2011 netbooks idt? very low power clock for 2011 netbooks 11 9VRS4339B rev a 010312 absolute maximum ratings?dc parameters stresses above the ratings listed below can cause permanen t damage to the 9VRS4339B. these ratings, which are standard values for idt commercially rated parts, are stress ra tings only. functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for ex tended periods can affe ct product reliability. electrical parameters are guar anteed only over the recommended operating temperature range. electrical characteristics?pciclk/pciclk_f parameter symbol conditions min max units notes maximum supply voltage vdd27, vdd_3.3 supply voltage 4.6 v 1,4 maximum supply voltage vdd_core_1.5 supply voltage 1.9 v 1,4 maximum supply voltage vdd_lvio supply voltage 1.9 v 1,4 maximum input voltage v ih 3.3v inputs, including smbus 4.6 v 1,2,4 minimum input voltage v il any input gnd - 0.5 v 1,4 storage temperature ts - -65 150 c 4 case temperature tcase - 115 c 1 input esd protection esd prot human body model 2000 v 3,4 1 intentionally blank 4 operation under these conditions is neither implied, nor guaranteed. notes on dc parameters: (unless otherwise noted, guaranteed by design and characterization, not 100% tested in production). 2 maximum vih is not to exceed vdd 3 human body model parameter symbol conditions min max units notes long accuracy ppm see tperiod min-max values -100 100 ppm 1,2 33.33mhz output no spread 29.99700 30.00300 ns 1,2,5 33.33mhz output spread 30.08421 30.23459 ns 1,2,5 33.33mhz output no spread 29.49700 30.50300 ns 1,2 33.33mhz output nominal/spread 29.56617 30.58421 ns 1,2 output high voltage v oh i oh = -1 ma 2.4 v 1 output low voltage v ol i ol = 1 ma 0.4 v 1 v oh @min = 1.0 v -33 ma 1 v oh @max = 3.135 v -33 ma 1 v ol @ min = 1.95 v 30 ma 1 v ol @ max = 0.4 v 38 ma 1 rising edge slew rate t slr measured from 0.8 to 2.0 v 1 4 v/ns 1,3 falling edge slew rate t fl r measured from 2.0 to 0.8 v 1 4 v/ns 1,3 duty cycle d t1 v t = 1.5 v 45 55 % 1,4 adjacent pin to pin skew t sk ew v t = 1.5 v, pci aligned mode (default) 250 ps 1,4,7 adjacent pin to pin intentional delay t skew_delay v t = 1.5 v, pci delayed mode ps 1,4,8 total pci skew window t skew_total v t = 1.5 v , pci delayed mode 800 ps 1,4,9 jitte r, cycle to cycle t jcyc-cyc v t = 1.5 v 500 ps 1,4 *ta = 0 - 70c; supply voltage vdd = 3.3 v +/-5%, rs=39ohm, cl=5p f 1 unless otherwise noted, guaranteed by design and characterization, not 100% tested in production. 2 all long term accuracy and clock period specifications are guaranteed assuming that refout is at 25.000000mhz 3 edge rate in system is measured from 0.8v to 2.0v. 4 duty cycle, peroid, skew and jitter are measured with respect to 1.5v 5 the avera g e p eriod over an y 1us p eriod of time output low current i ol clock period t peri od absolute min/max period t abs output high current i oh 200ps typical 6 using frequency counter with the measurment interval equal or greater that 0.15s. target frequencies are 14.318181 mhz, 25.000 000mhz, 33.333333mhz, 27.000000mhz and 48.000000mhz 7 adjacent pin to pin skew is the pin to pin skew between pci1 and pci2, pci2 and pci3, or pci3 to pci4. 8 adjacent pin to pin intentional delay is the intentional delay between pci1 and pci2, pci2 and pci3, or pci3 to pci4. 9 total pci skew winodw is absolute skew between pci1 and pci4.
9VRS4339B very low power clock for 2011 netbooks idt? very low power clock for 2011 netbooks 12 9VRS4339B rev a 010312 pciclk relationship timing diagram during delayed mode
9VRS4339B very low power clock for 2011 netbooks idt? very low power clock for 2011 netbooks 13 9VRS4339B rev a 010312 electrical characteristics?input/su pply/common output dc parameters parameter symbol conditions min max units notes ambient operating temp tambient - 0 70 c vdd27, vdd_3.3 supply voltage 3.135 3.465 v vdd_core_1.5 supply voltage 1.425 1.575 v vdd_lvio supply voltage 0.9975 1.575 v input high voltage v ihse single-ended 3.3v inputs 2 v dd + 0.3 v 3 input low voltage v ilse single-ended 3.3v inputs v ss - 0.3 0.8 v 3 latched input high voltage v ih_li single-ended 3.3v latched inputs 2 vdd + 0.3 v latched input low voltage v il_li single-ended 3.3v latched inputs v ss - 0.3 0.8 v low threshold latched input- high voltage v ih_fs low threshold inputs fsl[c:b] 0.7 vdd+0.3 v low threshold latched input- low voltage v il_fs low threshold inputs fsl[c:b] v ss - 0.3 0.35 v input leakage current i in v in = v dd , v in = gnd -5 5 ua 2 input leakage current i inres inputs with pull up or pull down resistors v in = v dd , v in = gnd -200 200 ua output high voltage v ohse single-ended outputs, i oh = -1ma 2.4 v 1 output low voltage v olse single-ended outputs, i ol = 1 ma 0.4 v 1 i ddop3.3 full active, c l = full load; idd 3.3v 38 ma i ddop1.5 full active, c l = full load; idd 1.5v 40 ma i ddop1.05 full active, c l = full load; idd lvio 46 ma i ddpd3.3 power down mode, 3.3v rail 1.2 ma 5 i ddpd1.5 power down mode, 1.5v rail 1 ma 5 i ddpdlvio power down mode, 1.05v rail 0 ma 5 i ddwol3.3 wake on lan mode, 3.3v rail 10 ma 6 i ddwol1.5 wake on lan mode, 1.5v rail 1 ma 6 i ddwollvio wake on lan mode, lvio rail 0 ma 6 input frequency f i v dd = 3.3 v mhz 4 pin inductance l pin 7nh c in logic inputs 1.5 5 pf c out output pin capacitance 6 pf c inx x1 & x2 pins 6 pf clk stabilization t stab from vdd power-up or de-assertion of pd to 1st clock 1.8 ms tstop_cr_off t croff output stop after clkreq# deasserted 2 3 clocks trun_cr_on t cron output run after clkreq# asserted 2 3 clocks tstop t stop cpu or pci stop after cpu or pci stop# assertion 2 3 clocks trun t run cpu or pci run after cpu or pci stop# de-assertion 2 3 clocks tfall_se t fall 10 ns trise_se t rise 10 ns smbus voltage v dd 2.7 3.3 v low-level output voltage v olsmb @ i pullup 0.4 v current sinking at v olsmb = 0.4 v i pullup smb data pin 4 ma sclk/sdata clock/data rise time t ri2c (max vil - 0.15) to (min vih + 0.15) 1000 ns sclk/sdata clock/data fall time t fi2c (min vih + 0.15) to (max vil - 0.15) 300 ns maximum smbus operating frequency f smbus 100 khz spread spectrum modulation frequency f ssmod triangular modulation 30 33 khz 1 signal is required to be monotonic in this region. 2 input leakage current does not include inputs with pull-up or pull-down resistors fall/rise time of all 3.3v control inputs from 20- 80% notes on dc parameters: (unless otherwise noted, guaranteed by design and characterization, not 100% tested in production). 5 standard powerdown with wake on lan disabled. 6 powerdown with wake on lan enabled 3 3.3v referenced inputs are: pci_stop#, cpu_stop#, itp_en, sclk, sdata, clkpwrgd/pd#, dot96_sel, sel_pci, 48m_sel and pereq# inp uts if selected. 4 for margining purposes only. normal operation should have fin = 25mhz +/-50ppm wake-on-lan current input capacitance supply voltage operating supply current powerdown current 25mhz typical
9VRS4339B very low power clock for 2011 netbooks idt? very low power clock for 2011 netbooks 14 9VRS4339B rev a 010312 ac electrical characteristic s?cpu, src, sata, dot96mhz electrical characteri stics?usb48mhz/48mhz parameter symbol conditions min max units notes rising edge slew rate tslr differential measurement 2.5 4 v/ns 1,3 falling edge slew rate tflr differential measurement 2.5 4 v/ns 1,3 slew rate variation tslvar single-ended measurement 20 % 1,3 maximum output voltage vhigh includes overshoot 1150 mv 1 minimum output voltage vlow includes undershoot -300 mv 1 differential voltage swing vswing differential measurement 300 mv 1 crossing point voltage vxabs single-ended measurement 300 550 mv 1,3,4 crossing point variation vxabsvar single-ended measurement 140 mv 1,3,5 duty cycle dcyc differential measurement 45 55 % 1 cpu jitter - cycle to cycle cpujc2c differential measurement 85 ps 1 src jitter - cycle to cycle srcjc2c differential measurement 85 ps 1 sata jitter - cycle to cycle satajc2c differential measurement 125 ps 1 dot jitter - cycle to cycle dotjc2c differential measurement 250 ps 1 cpu[1:0] skew cpu10skew differential measurement 100 ps 1,6 cpu[itp:0] skew cpu20skew differential measurement 150 ps 1,6 pciex(6, 4:2) skew pciexskew differential measurement 250 ps 1 pciex(7:1) skew pciexskew differential measurement 500 ps 1 notes: t a = 0 - 7 0c; v dd = 3.3 v +/-5%; c l =2pf, rs=0 ? (unless specified otherwise) 1 guaranteed by design and characterization, not 100% tested in production. 2 all long term accuracy and clock period specifications are guaranteed assuming that refout is at 25.000000mhz 3 slew rate emastu red throu g h v_swin g vo lta g e ran g e centered about differential zero 4 vcross is defined at the volta g e where clock = clock#. 6 cpu group skew is nominally 0ps. 5 only applies to the differential rising edge (clock rising, clock# falling.) parameter symbol conditions min max units notes long accuracy ppm see tperiod min-max values -100 100 ppm 1,2 clock period t period 48.00mhz output nominal 20.83125 20.83542 ns 1,2,5 absolute min/max period t ab s 48.00mhz output nominal 20.48125 21.18542 ns 1,2 output high voltage v oh i oh = -1 ma 2.4 v 1 output low voltage v ol i ol = 1 ma 0.4 v 1 v oh @min = 1.0 v -29 ma 1 v oh @max = 3.135 v -23 ma 1 v ol @ min = 1.95 v 29 ma 1 v ol @ max = 0.4 v 27 ma 1 rising edge slew rate (usb48m) t slr measured from 0.8 to 2.0 v 1 2 v/ns 1,3 falling edge slew rate (usb48m) t fl r measured from 2.0 to 0.8 v 1 2 v/ns 1,3 rising edge slew rate (48m) t slr measured from 0.8 to 2.0 v 1 4 v/ns 1,3 falling edge slew rate (48m) t fl r measured from 2.0 to 0.8 v 1 4 v/ns 1,3 duty cycle d t1 v t = 1.5 v 45 55 % 1,4 jitte r, cycle to cycle t jcyc-cyc v t = 1.5 v 350 ps 1,4 *ta = 0 - 70c; supply voltage vdd = 3.3 v +/-5%, rs=39ohm, cl=5pf 1 unless otherwise noted, guaranteed by design and characterization, not 100% tested in production. 2 all long term accuracy and clock period specifications are guaranteed assuming that refout is at 25.000000mhz 3 edge rate in system is measured from 0.8v to 2.0v. 4 duty cycle, peroid and jitter are measured with respect to 1.5v 5 the average period over any 1us period of time 6 using frequency counter with the measurment interval equal or greater that 0.15s. target frequencies are 14.318181 mhz, 25.000 000mhz, 33.333333mhz, 27.000000mhz and 48.000000mhz output low current i ol output high current i oh
9VRS4339B very low power clock for 2011 netbooks idt? very low power clock for 2011 netbooks 15 9VRS4339B rev a 010312 electrical characteristics?25mhz electrical characte ristics?ref-14.318mhz parameter symbol conditions min max units notes long accuracy ppm see tperiod min-max values -30 30 ppm 1,2 clock period t period 25.00mhz output nominal 39.99880 40.00120 ns 1,2,5 output high voltage v oh i oh = -1 ma 2.4 v 1 output low voltage v ol i ol = 1 ma 0.4 v 1 v oh @min = 1.0 v -29 ma 1 v oh @max = 3.135 v -23 ma 1 v ol @ min = 1.95 v 29 ma 1 v ol @ max = 0.4 v 27 ma 1 rising edge slew rate t slr measured from 0.8 to 2.0 v 0.5 2 v/ns 1,3 falling edge slew rate t fl r measured from 2.0 to 0.8 v 0.5 2 v/ns 1,3 duty cycle d t1 v t = 1.5 v 45 55 %1,4 jitte r, cycle to cycle t jcyc-cyc v t = 1.5 v 200 ps 1,4 *ta = 0 - 70c; supply voltage vdd = 3.3 v +/-5%, rs=39ohm, cl=5pf 1 unless otherwise noted, guaranteed by design and characterization, not 100% tested in production. 2 all long term accuracy and clock period specifications are guaranteed assuming that refout is at 25.000000mhz 3 edge rate in system is measured from 0.8v to 2.0v. 4 duty cycle, peroid and jitter are measured with respect to 1.5v 5 the avera g e p eriod over an y 1us p eriod of time i oh i ol output high current 6 using frequency counter with the measurment interval equal or greater that 0.15s. target frequencies are 14.318181 mhz, 25.000 000mhz, 33.333333mhz, 27.000000mhz and 48.000000mhz output low current parameter symbol conditions min max units notes long accuracy ppm see tperiod min-max values -100 100 ppm 1,2 clock period tperiod 14.318mhz output nominal 69.82033 69.86224 ns 1,2,5 absolute min/max period tabs 14.318mhz output nominal 69.83400 70.84800 ns 1,2 output high voltage v oh ioh = -1 ma 2.4 v 1 output low voltage v ol iol = 1 ma 0.4 v 1 v oh @min = 1.0 v -29 ma 1 v oh @max = 3.135 v -23 ma 1 v ol @ min = 1.95 v 29 ma 1 v ol @ max = 0.4 v 27 ma 1 rising edge slew rate t slr measured from 0.8 to 2.0 v 1 4 v/ns 1,3 falling edge slew rate t fl r measured from 2.0 to 0.8 v 1 4 v/ns 1,3 duty cycle d t1 vt = 1.5 v 45 55 % 1,4 jitte r, cycle to cycle t jcyc-cyc vt = 1.5 v 1000 ps 1,4 *ta = 0 - 70c; supply voltage vdd = 3.3 v +/-5%, rs=39ohm, cl=5pf 1 unless otherwise noted, guaranteed by design and characterization, not 100% tested in production. 2 all long term accuracy and clock period specifications are guaranteed assuming that refout is at 25.000000mhz 3 edge rate in system is measured from 0.8v to 2.0v. 4 duty cycle, peroid and jitter are measured with respect to 1.5v 5 the average period over any 1us period of time output high current i oh output low current i ol 6 using frequency counter with the measurment interval equal or greater that 0.15s. target frequencies are 14.318181 mhz, 25.000 000mhz, 33.333333mhz, 27.000000mhz and 48.000000mhz
9VRS4339B very low power clock for 2011 netbooks idt? very low power clock for 2011 netbooks 16 9VRS4339B rev a 010312 electrical characteristics?27mhz clock jitter specifications - low power differential outputs parameter symbol conditions min max units notes -50 50 ppm 1,2 -15 15 ppm 1,2,7 clock period t period 27.000mhz output nominal 37.0365 37.0376 ns 1,4,5 output high voltage v oh i oh = -1 ma 2.4 v 1 output low voltage v ol i ol = 1 ma 0.4 v 1 v oh @min = 1.0 v -29 ma 1 v oh @max = 3.135 v -23 ma 1 v ol @ min = 1.95 v 29 ma 1 v ol @ max = 0.4 v 27 ma 1 rising edge slew rate t slr measured from 0.8 to 2.0 v 1 4 v/ns 1,3 falling edge slew rate t fl r measured from 2.0 to 0.8 v 1 4 v/ns 1,3 duty cycle d t1 v t = 1.5 v 45 55 % 1,4 t ltj long term (10us), , v t = 1.5 v 400 ps 1,4 t jcyc-cyc cycle to cycle, v t = 1.5 v 200 ps 1,4 *ta = 0 - 70c; supply voltage vdd = 3.3 v +/-5%, rs = 39ohm, cl = 5pf 1 unless otherwise noted, guaranteed by design and characterization, not 100% tested in production. 2 all long term accuracy and clock period specifications are guaranteed assuming that refout is at 25.000000mhz 3 edge rate in system is measured from 0.8v to 2.0v. 4 duty cycle, peroid and jitter are measured with respect to 1.5v 5 the average period over any 1us period of time 7 at nominal voltage and temperature. long accuracy ppm see tperiod min-max values 6 using frequency counter with the measurment interval equal or greater that 0.15s. target frequencies are 14.318181 mhz, 25.000 000mhz, 33.333333mhz, 27.000000mhz and 48.000000mhz jitte r i oh output low current i ol output high current parameter symbol conditions min max units notes t jp ha sepll pcie gen 1 86 ps (p-p) 1,2 t jp ha selo pcie gen 2 10khz < f < 1.5mhz 3.0 ps (rms) 1,3,4 t jp ha seh igh pcie gen 2 1.5mhz < f < nyquist (50mhz) 3.1 ps (rms) 1,3,4 *ta = 0 - 70c; supply voltage vdd = 1.5v +/- 5%, rs=0ohm, cl=2pf 3 phase jitter requirement: the designated gen2 outputs will meet the reference clock jitter requiremernts from the pci express gen2 base spec. the test is performed 2 jitter specs are specified as measured on a clock characterization board. system designers need to take special care not to us e these numbers, as the in-system 4 see http://www.pcisig.com for complete specs pciex phase jitter 1 unless otherwise noted, guaranteed by design and characterization, not 100% tested in production.
9VRS4339B very low power clock for 2011 netbooks idt? very low power clock for 2011 netbooks 17 9VRS4339B rev a 010312 differential clock tolerances clock periods?differential outputs with spread spectrum disabled clock periods?differential outputs with spread spectrum enabled cpu src dot96 sata 100 100 100 100 ppm 85 85 250 125 ps -0.50% -0.50% 0.00% -0.50% % ppm tolera nc e cycle to c ycle jitter spread 1 clock 1us 0.1s 0.1s 0.1s 1us 1 clock -c2c jitter absper min -ssc short-term average min - ppm long-term average mi n 0 ppm period nominal + ppm long-term average max +ssc short-term average max +c2c jitter absper max 100.00 9.91400 9.99900 10.00000 10.00100 10.08600 ns 1,2 133.33 7.41425 7.49925 7.50000 7.50075 7.58575 ns 1,2 166.67 5.91440 5.99940 6.00000 6.00060 6.08560 ns 1,2 200.00 4.91450 4.99950 5.00000 5.00050 5.08550 ns 1,2 src 100.00 9.87400 9.99900 10.00000 10.00100 10.12600 ns 1,2 sata 100.00 9.87400 9.99900 10.00000 10.00100 10.12600 ns 1,2 dot96 96.00 10.16563 10.41563 10.41667 10.41771 10.66771 ns 1,2 cpu measurement window ssc off center freq. mhz notes units 1 clock 1us 0.1s 0.1s 0.1s 1us 1 clock -c2c jitter absper min -ssc short-term average min - ppm long-term average min 0 ppm period nominal + ppm long-term average max +ssc short-term average max +c2c jitter absper max 99.75 9.91406 9.99906 10.02406 10.02506 10.02607 10.05107 10.13607 ns 1,2 133.00 7.41430 7.49930 7.51805 7.51880 7.51955 7.53830 7.62330 ns 1,2 166.25 5.91444 5.99944 6.01444 6.01504 6.01564 6.03064 6.11564 ns 1,2 199.50 4.91453 4.99953 5.01203 5.01253 5.01303 5.02553 5.11053 ns 1,2 src 99.75 9.87406 9.99906 10.02406 10.02506 10.02607 10.05107 10.17607 ns 1,2 sata 99.75 9.87406 9.99906 10.02406 10.02506 10.02607 10.05107 10.17607 ns 1,2 1 guaranteed b y desi g n and characterization, not 100% tested in p ro duc tio n. cpu 2 all long term accuracy specifications are guaranteed with the assumption that the crystal input is tuned to exactly 25.000000mh z. measurement window units ssc on center freq. mhz notes
9VRS4339B very low power clock for 2011 netbooks idt? very low power clock for 2011 netbooks 18 9VRS4339B rev a 010312 power-up sequencing requirements marking diagram notes: 1. ###### is the lot number. 2. yyww is the last two digits of the year and week that the part was assembled. 3. ?l? denotes rohs compliant package. 4. ?origin? is the country of origin. ics 9VRS4339Bl yyww origin ######
9VRS4339B very low power clock for 2011 netbooks idt? very low power clock for 2011 netbooks 19 9VRS4339B rev a 010312 package outline and package dimensions (56-pin mlf) ordering information "lf" suffix to the part numb er are the pb-free configurat ion and are rohs compliant. ?b? is the device revision d esignator (will not correlate with the datasheet revision). while the information presented herein has been checked for both accuracy and reliability, integrated device technology (idt) a ssumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would resul t from its use. no other circuits, patents, or licenses are implied. this product is intended for use in normal commercial applications. any other applications such as those requiring extended temperatur e range, high reliability, or other extr aordinary environmental requirements are not recommended without additional processing by idt. idt reserves the right to change any circuitr y or specifications without noti ce. idt does not authorize or warrant any idt product for use in life support devices or critical medical instruments. part / order number marking shipping packaging package temperature 9VRS4339Bklf see page 18 trays 56-pin mlf 0 to +70 ? c 9VRS4339Bklft tape and reel 56-pin mlf 0 to +70 ? c millimeters symbol min max a0.81.0 a1 0 0.05 a3 0.2 reference b0.150.25 e 0.40 basic d x e basic 7.00 x 7.00 d2 min./max. 5.60 5.80 e2 min./max. 5.60 5.80 l min./max. 0.30 0.50 n56 n d 14 n e 14
9VRS4339B very low power clock for 2011 netbooks idt? very low power clock for 2011 netbooks 20 9VRS4339B rev a 010312 revision history rev. initiator issue date description page # 0.1 dc 4/25/2011 initial release - 0.2 dc 10/11/2011 1. updated "features/benefits" section 2. updated power distribution table 3. updated byte 13 4. updated pin 55 description various a dc 1/3/2012 1. updated "general description" 2. updated "features/benefits" 3. updated pin descriptions 4. updated byte13 5. updated "absolute max ratings" and "electrical characteristics - input/supply/common output dc parameters" tables various
? 2012 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. idt, ic s, and the idt logo are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa corporate headquarters integrated device technology, inc. www.idt.com for sales 800-345-7015 408-284-8200 fax: 408-284-2775 for tech support www.idt.com/go/support innovate with idt and accelerate your future netw orks. contact: www.idt.com 9VRS4339B very low power clock for 2011 netbooks synthesizers

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