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datasheet very low power cl ock for 2011 netbooks 9VRS4338D idt? very low power clock for 2011 netbooks 1 9VRS4338D rev a 022616 general description the 9VRS4338D is a main clock for intel netbooks, conforming to the ck-net specification. it is driven with a 14.31818mhz crystal and generates a variety of clocks, including an lcd clock. an smbus interface allows full control of the device. recommended application ck-net output features ? 2 - 0.8v push-pull differential cpu pairs ? 3 - 0.8v push-pull differential src pairs ? 1 - 0.8v push-pull differential sata/src pair ? 1 - 0.8v push-pull differential dot96/src pair ? 1 - 0.8v push-pull differential lcd100 pair ? 1 - 0.8v push-pull differential cpu_itp/src pair ? 3 - pci (33mhz), 1 free-running ? 1 - 25mhz _pci (33mhz) ? 1 - usb_48mhz ? 1 - ref, 14.318mhz features/benefits ? 25m output can run in power down; supports wake_on_lan ? selectable spread % on cpu, src, pci; supports margining ? external 14.318mhz crystal; supports tight ppm ? clkreq# pins; support src power management ? low power differential clock outputs; reduced power and board space ? integrated 33 ohm series resistors on all differential outputs; reduced board space key specifications ? cpu cycle-to-cycle jitter <85ps ? src/sata cycle-to-cycle jitter <85ps ? src(1:4) are pcie gen2 compliant ? src5 is pcie gen1 compliant ? 100ppm frequency accuracy on all clocks except 25m ? 30ppm frequency accuracy on 25m pin configuration gndref clkpwrgd/pd#_3.3 cpu0_lrs cpu0#_lrs gndcpu cpu1_lrs cpu1#_lrs vddcpu_lvio vdd_core_1.5 cpu_itp/src1_lrs cpu_itp#/src1#_lrs cpu_stop#_3.3 48 47 46 45 44 43 42 41 40 39 38 37 x2 1 36 src2_lrs x1 2 35 src2#_lrs vddr ef 3 34 gndsrc ref0_2x/fslc 4 33 src3_lrs sdata_3 .3 5 32 src3#_lrs scl k_3 .3 6 31 pci_stop#_3.3 vddpci_3 .3 7 3 0 vddsrc_lvio vitp_en/ pci_f1_2x 8 29 src4_lrs fslb/pci2_2x 9 28 src4#_lrs clkreqa# /pci3 _2x 10 2 7 sata_lrs gndpci 11 26 sata#_lrs gnd25 12 25 gndsata 13 14 15 16 17 18 19 20 21 22 23 24 vsel_pci/25m_pci4_2x vdd2 5 vdd48 vusb_48mhz_2x gnd48 clkr eqb# dot96_ lrs/src5_lrs dot96#_l rs/src5#_lrs vdd_core_1.5 lcd100_lrs lcd100#_lrs gnd lcd v prefix indicates internal 120kohm pull down resistor ^ prefix indicates internal 120kohm pull up resistor 48-p in mlf, 6x6 m m, 0.4mm pitch 9VRS4338D
9VRS4338D very low power clock for 2011 netbooks idt? very low power clock for 2011 netbooks 2 9VRS4338D rev a 022616 pin descriptions pin # pin name type description 1x2 outcr y stal out p ut, no mina ll y 14.318mhz 2 x1 in crystal input, nominally 14.318mhz. 3 vdd ref pwr ref, xt al pow er s upply, nominal 3.3v 4 ref0_2x/fslc i/o 2x strength 14.318 mhz reference clock./ 3.3v tolerant input for cpu frequency se le ctio n. refer to i np u t e lectri cal ch ar acte ri stics fo r vil_ fs and vi h_ fs values . 5 sdata_3.3 i/o data p in for smbus circuitr y , 3.3v tolerant. 6sclk_3.3 inclock p in of smbus circuitr y , 3.3v tolerant. 7vddpci_3.3 pwrpower su pp l y for pci clocks, nominal 3.3v 8 vitp_en/pci_f1_2x i/o itp enable latched input/free running pci clock output. itp_enable selects the functionality of the cpu_itp/src output as follows: 1 = cpu_itp output 0 = src output 9 fslb/pci2_2x i/o 3.3v tolerant input for cpu frequency selection. low voltage threshold inputs, see input electrical characteristics for vil_fs and vih_fs values. / 3.3v pci clock output. 10 clkreqa#/pci3_2x i/o active low realtime input pin to enable src outputs / pci clock output. (pin fu ncti on is progr a mmab le th ro ug h smbus). see cl kreq# con trol tabl e a n d src power mana g ement table for details. 11 gndpci pwr ground pin for the pci outputs 12 gnd25 pw r gro u nd p in for the 25mhz out p uts 1 3 vsel_pci/2 5m _pc i4_ 2x i/o sel_pci 3.3v latched input to select pin functionality for 25m_pciclk3 output/25m or pci clock output. this pin has an internal 120kohm pulldown resistor. latch func tionality is as follows: 0 = 25mhz output 1 = 33.3mhz pcicl k 14 vdd25 pwr power pin for the 25mhz output.3.3v 15 vdd48 pw r pow er p in for the 48mhz out p ut.3.3v 16 vusb_48mhz_2x out 3.3v 48mhz usb clock output. this pin has an internal 120kohm pull down resistor. 17 gnd48 pwr ground pin for the 48mhz outputs 18 clkreqb# in output enable for pci express (src) outputs. smbus selects which outputs are controlled. 0 = controlled outputs are enabled 1 = controlled out p uts are low/lo w 19 dot96_lrs/src5_lrs out true clock of push-pull dot96 or src clock with integrated series resistor. no 50 ohm pull down needed. default is dot96. after powerup, this pin function ma y be chan g ed to src via smbus. 20 dot 96#_lrs/src5#_lrs out complementary clock of push-pull dot96 or src clock with integrated series resistor. no 50 ohm pull down needed. default is dot96. after powerup, this pin function ma y be chan g ed to src via smbus. 2 1 vdd _c or e_1.5 pw r pow er for pll c or e compo nen ts requ ir ing 1 .5 v 22 lcd100_lrs out true clock of differential push-pull lcd100 output with integrated 33ohm series resistor. no 50ohm resistor to gnd needed. 23 lcd100#_lrs out complementary clock of differential push-pull lcd100 output with integrated 3 3oh m se ri es r esi stor . n o 50 ohm r esi stor to gnd ne ede d. 24 gndlcd pwr ground pin for lcd clock output
9VRS4338D very low power clock for 2011 netbooks idt? very low power clock for 2011 netbooks 3 9VRS4338D rev a 022616 pin descriptions (cont.) 25 gndsata pw r gro u nd p in for the sata out p uts 26 sata#_lrs out complementary clock of low power differential push-pull sata clock pair with integrated 33ohm series resistor. no 50 ohm resistor to gnd needed. 27 sata_lrs out true clock of low power differential push-pull sata clock pair with integrated 33o hm seri es r esi stor . n o 50 oh m r esi stor to gnd ne ede d. 28 src4#_lrs out complementary clock of differential 0.8v push-pull src output with integrated 33o hm seri es r esi stor . n o 5 0oh m r esi stor to gnd ne ede d. 29 src4_lrs out true clock of differential 0.8v push-pull src output with integrated 33ohm seri es r esi stor . n o 5 0oh m r esi stor to gnd ne ede d. 30 vddsrc_lvio pwr vdd for src i/o. nominally 1.05v to 1.5v from external power supply 31 pci_stop#_3.3 in stops all stoppable pci and src clocks at logic 0 level, when low. free running pci and src clocks are not effected by this input. this input is 3.3v tolerant. 32 src3#_lrs out complementary clock of differential 0.8v push-pull src output with integrated 33o hm seri es r esi stor . n o 5 0oh m r esi stor to gnd ne ede d. 33 src3_lrs out true clock of differential 0.8v push-pull src output with integrated 33ohm seri es r esi stor . n o 5 0oh m r esi stor to gnd ne ede d. 34 gndsrc pwr ground pin for the src outputs 35 src2#_lrs out complementary clock of differential 0.8v push-pull src output with integrated 33o hm seri es r esi stor . n o 5 0oh m r esi stor to gnd ne ede d. 36 src2_lrs out true clock of differential 0.8v push-pull src output with integrated 33ohm seri es r esi stor . n o 5 0oh m r esi stor to gnd ne ede d. 37 cpu_stop#_3.3 in stops stoppable cpu clocks when enabled. this is a 3.3v tolerant input. 38 cpu_itp#/src1#_lrs out complementary clock of low power differential cpu_itp/src pair with integrated 33ohm series resistor. no 50ohm resistor to gnd needed. the pin function is determined by the latched value on itp_en: 0 = src0# 1 = cpu itp# 39 cpu _itp/src1_lr s out true clock of low power differential cpu_itp/src pair with integrated 33ohm seri es r esi stor . n o 50 ohm r es istor to gnd ne ede d. the pi n func ti on is determined by the latched value on itp_en: 0 = src0 1 = cpu_itp 40 vdd_core_1.5 pw r pow er for pl l c or e co m p onents re q uirin g 1.5v 41 vddcpu_lvio pwr vdd for cpu i/o. nominall y 1.05v to 1.5v from external p ow er su pp l y . 42 cpu 1#_lr s out complementary clock of differential pair 0.8v push-pull cpu outputs with integrated 33ohm series resistor. no 50 ohm resistor to gnd needed. 43 cpu 1_lrs out true clock of differential pair 0.8v push-pull cpu outputs with integrated 33ohm seri es r esi stor . n o 50 oh m r esi stor to gnd ne ede d. 44 gndcpu pwr ground pin for the cpu outputs 45 cpu 0#_lr s out complementary clock of differential pair 0.8v push-pull cpu outputs with inte g rated 33ohm series resistor. no 50 ohm resistor to gnd needed. 46 cpu 0_lrs out true clock of differential pair 0.8v push-pull cpu outputs with integrated 33ohm seri es r esi stor . n o 50 oh m r esi stor to gnd ne ede d. 47 clkpwrgd/pd#_3.3 in this 3.3v lvttl input notifies device to sample latched inputs and start up on first high assertion, or exit power down mode on subsequent assertions. low enters power down mode. 48 gndref pw r gro u nd p in for the ref out p uts.
9VRS4338D very low power clock for 2011 netbooks idt? very low power clock for 2011 netbooks 4 9VRS4338D rev a 022616 block diagram nonss pll 14.318m xtal ss pll nonss pll usb48mhz pci(3:1) cpu(1:0) sata lcd100 ss pll 100m 25m_pci4 14.318m src(4:2) dot96/src5 0 1 0 1 dot96 1 0 dot96/src sel sel_pci 1 0 cpuipt/src1 itp_en series resistors for single ended outputs 1 load rs = 2 loads rs= 3 loads rs = 1 0.56 / 33 (17 ? )33 ? [39 ? ] na na 2 0.92 / 66 (14 ? )39 ? [43 ? ]22 ? [27 ? ]na notes: 2. desktop/mobile platforms with zo = 50/55 ohms use the first resistor value. 3. systems w ith zo = 60 ohms use the resistor values in brackets [ ]. mat ch point fo r n & p voltage / current (ma) 1. preferred drive strengths using ck505 clock sources. transmission lines to load do not share series resistors. number of loads to drive number of loads actually driven. d.c.drive strength
9VRS4338D very low power clock for 2011 netbooks idt? very low power clock for 2011 netbooks 5 9VRS4338D rev a 022616 test load cl=5pf rs zo single-ended output rs zo rs zo single-ended output `` cl=5pf cl=5pf the singled-ended outputs of the 9vrs4338 can drive 2 loads. if the output is driving one load, the resistor value is adjusted according to the ?series resistors for single-ended outputs table. when driving two loads, both load traces must be equal in length. 5 inches 5 inches 5 inches zo = 100ohms low-power push-pull buffer 9vrs4338 differential test load 2pf 2pf 5 inches
9VRS4338D very low power clock for 2011 netbooks idt? very low power clock for 2011 netbooks 6 9VRS4338D rev a 022616 driving lvds inputs with the 9vrs4338 receiver has termination receiver does not have termination r7a, r7b 10k ohm 140 ohm r8a, r8b 5.6k ohm 75 ohm cc 0.1 uf 0.1 uf vcm 1.2 volts 1.2 volts component value note lvds clk input l4 l4? r8b r7b r8a r7a 3.3 volts 9vrs4338 cc cc
9VRS4338D very low power clock for 2011 netbooks idt? very low power clock for 2011 netbooks 7 9VRS4338D rev a 022616 table 1: cpu/src/pci pll spread/frequency selection table rev d cpu/src/pci center spread (b1 b6) ss1 (b1b5) ss0 (b1b4) fs l c (b0b7) fs l b (b0b6) spr ead cpu mh z src mhz pci mh z 00000 -0.50% 133.33 100.00 33.33 00001 -0.50% 167.67 100.00 33.33 00010 -0.50% 100.00 100.00 33.33 00011 -0.50% 200.00 100.00 33.33 00100 -0.40% 133.33 100.00 33.33 00101 -0.40% 167.67 100.00 33.33 00110 -0.40% 100.00 100.00 33.33 00111 -0.40% 200.00 100.00 33.33 01000 -0.30% 133.33 100.00 33.33 01001 -0.30% 167.67 100.00 33.33 01010 -0.30% 100.00 100.00 33.33 01011 -0.30% 200.00 100.00 33.33 01100 off 133.33 100.00 33.33 01101 off 167.67 100.00 33.33 01110 off 100.00 100.00 33.33 01111 off 200.00 100.00 33.33 10000 +/ - 0. 2 5% 133.33 100.00 33.33 10001 +/ - 0. 2 5% 167.67 100.00 33.33 10010 +/ - 0. 2 5% 100.00 100.00 33.33 10011 + / - 0 . 25% 200.00 100.00 33.33 10100 +/ - 0. 2 0% 133.33 100.00 33.33 10101 +/ - 0. 2 0% 167.67 100.00 33.33 10110 +/ - 0. 2 0% 100.00 100.00 33.33 10111 + / - 0 . 20% 200.00 100.00 33.33 11000 +/ - 0. 1 5% 133.33 100.00 33.33 11001 +/ - 0. 1 5% 167.67 100.00 33.33 11010 +/ - 0. 1 5% 100.00 100.00 33.33 11011 +/ - 0. 1 5% 200.00 100.00 33.33 11100 off 133.33 100.00 33.33 11101 off 167.67 100.00 33.33 11110 off 100.00 100.00 33.33 11111 off 200.00 100.00 33.33 note: changing default spread amounts or type will impact src clocks, too. the default - 0.5% downspread is recommended for src.
9VRS4338D very low power clock for 2011 netbooks idt? very low power clock for 2011 netbooks 8 9VRS4338D rev a 022616 table 2: lcd spread selection table rev b/c/d fs2 (b1b3) fs1 (b1b2) fs0 (b1b1) lcd center spread (b1b0) spread % lcd100 mhz 000 0 off re ser ved 001 0 off 100.00 010 0 -0.50% 100.00 011 0 -1.0% 100.00 100 0 -1.5% 100.00 101 0 -2.0% 100.00 11 0 0 -2.50% 100.00 111 0 off re ser ved 000 1 off re ser ved 001 1off100.00 010 1 +/-0.25% 100.00 011 1 +/-0.5% 100.00 100 1 +/-0.75% 100.00 101 1 +/-1.0% 100.00 110 1 +/-1.25% 100.00 111 1 off re ser ved
9VRS4338D very low power clock for 2011 netbooks idt? very low power clock for 2011 netbooks 9 9VRS4338D rev a 022616 cpu power management table dot96 and sata power management table src power management table single-ended management table clkreq# control table true o/p comp. o/p 1 enable 1 running r unning 1 enable 0 high low 0 x x low/20k low x disable x low/20k low clkpwrgd/pd#_3.3 sm bus register oe cpu_stop# c pu (0, 1, itp) true o/p comp. o/p true o/p comp. o/p 1 enable running running r unning running 0 enable low/20k low low/20k low x disable low/20k low low/20k low clkpwrgd/pd#_3.3 sm bus register oe dot96 sata true o/p comp. o/p true o/p comp. o/p 1 enable 0 running r unning running running 1 enable 1 low/20k low running running 0 enable x low/20k low low/20k low x disable x low/20k low low/20k low src not controlled by clkreqx# src controlled by clkreqx# clkpwrgd/pd#_3.3 sm bus register oe clkreqx# free-run stoppable free-run stoppable wlan enabled wlan disabled 1 enable 1 running r unning running running running running running running 1 enable 0 running low running low running running running running 0 enable x hi-z hi-z low low running hi-z hi-z hi-z x disable x hi-z hi-z hi-z hi-z hi-z hi-z hi-z hi-z clkpwrgd/pd#_3.3 sm bus register oe clkreqa#/pci3 = pci3 pci_f1, pci2, 25m_pci4 = pci4 usb_48 ref pci_stop# 25m_pci4 = 25mhz asrc1, 2 bsrc3, 4 note: smbus selects configuration clkreq# src controlled
9VRS4338D very low power clock for 2011 netbooks idt? very low power clock for 2011 netbooks 10 9VRS4338D rev a 022616 general smbus serial interface information for 9VRS4338D how to write ? controller (host) sends a start bit ? controller (host) sends the write address ? idt clock will acknowledge ? controller (host) sends the beginning byte location = n ? idt clock will acknowledge ? controller (host) sends the byte count = x ? idt clock will acknowledge ? controller (host) starts sending byte n through byte n+x-1 ? idt clock will acknowledg e each byte one at a time ? controller (host) sends a stop bit how to read ? controller (host) will send a start bit ? controller (host) sends the write address ? idt clock will acknowledge ? controller (host) sends the beginning byte location = n ? idt clock will acknowledge ? controller (host) will send a separate start bit ? controller (host) sends the read address ? idt clock will acknowledge ? idt clock will send the data byte count = x ? idt clock sends byte n+x-1 ? idt clock sends byte 0 through byte x (if x (h) was written to byte 8) ? controller (host) will need to acknowledge each byte ? controller (host) will send a not acknowledge bit ? controller (host) will send a stop bit index block write operation controller (host) idt (slave/receiver) tstart bit slave address wr write ack beginning byte = n ack data byte count = x ack beginning byte n x byte ack o o o o o o byte n + x - 1 ack pstop bit read address write address d3 (h) d2 (h) index block read operation controller (host) idt (slave/receiver) tstart bit slave address wr write ack beginning byte = n ack rt repeat start slave address rd read ack data byte count=x ack x byte beginning byte n ack o o o o o o byte n + x - 1 n not acknowledge pstop bit
9VRS4338D very low power clock for 2011 netbooks idt? very low power clock for 2011 netbooks 11 9VRS4338D rev a 022616 smbus table: frequency select, pd config and sata source select register byte 0 name control function type 0 1 default bit 7 fslc freq select bit 1 r latch bit 6 fslb freq select bit 0 r latch bit 5 0 bit 4 0 bit 3 0 bit 2 0 bit 1 sata _ sel selects sata=src or non-ss rw follows src sata pll ( nonss ) 0 bit 0 pd config forces "cold" start during pd rw r eset and relatch normal pd# mode 1 smbus table: cpu, lcd ss and dot96/src5 control register byte 1 name control function type 0 1 default bit 7 dot96/src5 sel selects dot96 or src5 rw dot96 src5 0 bit 6 cpu/src/pci center ss en enables center spread for rw down spread center spread 0 bit 5 c pu/src/pc i ss1 cpu/src /pci ss mag. msb rw 0 bit 4 c pu/src/pc i ss0 cpu/src/pci ss ma g. lsb rw 0 bit 3 lcd ss2 lcd ss magnitude msb rw 1 bit 2 lcd ss1 lcd ss magnitude rw 1 bit 1 lcd ss0 lcd ss magnitude lsb rw 0 bit 0 lcd center ss en enables center spread for lcd rw down spread center spread 0 smbus table: output enable control register byte 2 name control function type 0 1 default bit 7 ref0 oe output enable rw disable enable 1 bit 6 usb_48mhz oe output enable rw disable enable 1 bit 5 1 bit 4 25m_pci4 oe output enable rw disable enable 1 bit 3 pci3 oe outp ut en able rw disab le ena ble 1 bit 2 pci2 oe outp ut en able rw disab le ena ble 1 bit 1 pci_f1 oe output enable rw disable enable 1 bit 0 1 smbus table: output enable control register byte 3 name control function type 0 1 default bit 7 1 bit 6 1 bit 5 1 bit 4 1 bit 3 1 bit 2 lcd clk oe output enable rw disable enable 1 bit 1 src4 oe output enable rw disable enable 1 bit 0 sata oe out p ut enable rw disable enable 1 smbus table: output enable and ss enable control register byte 4 name control function 0 1 default bit 7 src3 oe out p ut enable rw disable enable 1 bit 6 src2 oe output enable rw disable enable 1 bit 5 cpu_itp/src1 oe output enable rw disable enable 1 bit 4 dot96/src 5 oe output enable rw disable enable 1 bit 3 cpu1 oe output enable rw disable enable 1 bit 2 cpu0 oe output enable rw disable enable 1 bit 1 cpu/src pll ss en output enable rw ss off ss on @ -0.5% 1 bit 0 1 reserved reserved reserved reserved reserved reserved reserved reserved reserved see table 2 for details. reserved see table 1: cpu pll frequency selection table reserved reserved see table 1 for details. d efault is -0.5% down spread when spread is enabled
9VRS4338D very low power clock for 2011 netbooks idt? very low power clock for 2011 netbooks 12 9VRS4338D rev a 022616 smbus table: clkreq_a# and clkreqb# mapping byte 5 name control function 0 1 default bit 7 clkreq_a# en pin 10 configuration rw pin 10 = pci3 pin 10 = c lkreq 0 bit 6 clkreq_a# map map clkreq_a# to src rw src1 controlled src2 controlled 0 bit 5 0 bit 4 clkreq_b# map map clkreq_b# to src rw src3 controlled src4 controlled 0 bit 3 0 bit 2 0 bit 1 0 bit 0 0 smbus table: src stop control register byte 6 name control function type 0 1 default bit 7 0 bit 6 0 bit 5 0 bit 4 0 bit 3 0 bit 2 0 bit 1 0 bit 0 src stop en src stop with pci_stop free-running src stoppable 0 smbus table: revision and vendor id register byte 7 name control function type 0 1 default bit 7 rid3 r 0 bit 6 rid2 r 0 bit 5 rid1 r 1 bit 4 rid0 r 0 bit 3 vid3 r 0 bit 2 vid2 r 0 bit 1 vid1 r 0 bit 0 vid0 r 1 smbus table: reserved byte 8 name control function type 0 1 default bit 7 0 bit 6 0 bit 5 0 bit 4 0 bit 3 0 bit 2 0 bit 1 0 bit 0 0 smbus table: byte count register byte 9 name control function type 0 1 default bit 7 0 bit 6 0 bit 5 0 bit 4 bc4 rw 0 bit 3 bc3 rw 1 bit 2 bc2 rw 0 bit 1 bc1 rw 1 bit 0 bc0 rw 0 reserved writing to this register will configure how many bytes will be read back, default is 0a = 10 bytes. reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved vendor id byte count programming reserved reserved reserved 0001 = ics/idt d rev = 0010 reserved re vision id reserved reserved reserved reserved reserved reserved reserved
9VRS4338D very low power clock for 2011 netbooks idt? very low power clock for 2011 netbooks 13 9VRS4338D rev a 022616 absolute maximum ratings stresses above the ratings listed below can cause perma nent damage to the 9VRS4338D. these ratings, which are standard values for idt commercially rated parts, are stress ra tings only. functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for ex tended periods can affe ct product reliability. electrical parameters are guar anteed only over the recommended operating temperature range. ac electrical characteristic s?cpu, src, sata, dot96mhz electrical characteristics - phase jitter parameter symbol conditions min typ max units notes maximum supply voltage vdd supply voltage 3.9 v 1,4 maximum supply voltage vdd_core_1.5 supply voltage 1.9 v 1,4 maximum supply voltage vdd_lvio supply voltage 1.9 v 1,4 maximum input voltage v ih 3.3v inputs, including smbus 3.9 v 1,2,4 minimum input voltage v il any i nput gnd - 0.5 v 1,4 storage temperature ts - -65 150 c 4 case tem peratu re tca se - 1 15 c 1 input esd protection esd prot human body model 2000 v 3,4 parameter symbol conditions min typ max units notes rising edge slew rate tslr differential measurement 2.5 3.2 4 v/ns 1,2 falling edge slew rate tflr differential measurement 2.5 3.1 4 v/ns 1,2 slew rate variation tslvar single-ended measurement 12.4 20 % 1 maximum output voltage vhigh includes overshoot 869 1150 mv 1 minimum output voltage vlow includes undershoot -300 mv 1 differential voltage swing vswing differential measurement 300 mv 1 crossing point voltage vxabs single-ended measurement 300 364 550 mv 1,3,4 crossing point variation vxabsvar single- ended measurement 32 140 mv 1,3,5 duty cycle dcyc differential measurement 45 49.8 55 % 1 cpu jitter - cycle to cycle cpujc2c differential measurement 46.1 85 ps 1 src jitter - cycle to cycle srcjc2c differential measurement 45.9 85 ps 1 sata jitter - cycle to cycle satajc2c differential measurement 52.1 85 ps 1 dot jitter - cycle to cycle dotjc2c differential measurement 110.7 250 ps 1 cpu[1:0] skew cpu10skew differential measurement 32 100 ps 1,6 cpu[2_itp:0] skew cpu20skew differential measurement 53 150 ps 1,6 src(2:4) skew src24skew differential measurement 53 250 ps 1 src(1:5) skew src15skew differential measurement 142 500 ps 1 notes: notes: t a = 0 - 85c; v dd = 3.3 v +/-5%; c l =2pf, rs=0 ? (unless specified otherwise) 1 guaranteed by design and characterization, not 100% tested in production. 2 all long term accuracy and clock period specifications are guaranteed assuming that refout is at 14.31818mhz 3 slew rate emastured throu g h v _ swin g vol t a g e ran g e centered about differential zero 4 vcross is defined at the volta g e where clock = clock#. 5 only applies to the differential rising edge (clock rising, clock# fa lling.) 6 cpu group skew is nominally 0ps. parameter symbol conditions min typ max units notes t jphpc ie1 pcie gen 1 refclk phase jitter 29 86 ps 1,2,3 t jphpcie 2lo pcie gen 2 refclk phase jitter lo-band content 1. 1 3 ps ( rms ) 1,2,4 t jp hpcie2 hi pcie gen 2 refclk phase jitter hi-band content 1. 9 3.1 ps ( rms ) 1,2,4 notes on phase ji tter: 2 sam p le size of at least 100k c y cles. this fi g ures extra p olates to 108 p s p k- p k @ 1m c y cles for a ber of 1 -1 2 3 a pp lies to all src out p uts. 4 applies to src(1:4) outputs. 1 see http://www.pcisig.com for complete specs. guaranteed by design and characterization, not tested in production. jitter, phase
9VRS4338D very low power clock for 2011 netbooks idt? very low power clock for 2011 netbooks 14 9VRS4338D rev a 022616 electrical characteristics?input/ supply/common output parameters parameter symbol conditions min typ max units notes ambient operating te mp tambient - 0 25 85 c vdd supply voltage 3.135 3.3 3.465 v vdd_core_1.5 supply voltage 1.425 1.5 1.575 v vdd_l vio supply voltage 0.9 975 1.05 1.575 v input high voltage v ih se single-ended 3.3v inputs 2 v dd + 0.3 v7 input low voltage v ilse single-ended 3.3v inputs v ss - 0.3 0.8 v 7 lat ch ed input high voltage v ih_ li single-ended 3.3v latched inputs 2 vdd + 0.3 v latched i nput low voltage v il_li sin gle-ended 3.3v latched inputs v ss - 0.3 0.8 v low threshold latched input- hi g h volta g e v ih _f s low threshold inp uts (fs(c:b)) 0 .7 vdd+0.3 v low threshold latched input- low volta g e v il_f s low threshold inp uts (fs(c:b)) v ss - 0.3 0.35 v input leakage current i in v in = v dd , v in = gnd -5 5 ua 6 input leakage current i in res inputs with pull up or pull down re si st ors v in = v dd , v in = gnd -200 200 ua output high voltage v ohs e single-ended outputs, i oh = -1ma 2.4 v 5 output low voltage v olse single-ended outp uts, i ol = 1 ma 0.4 v 5 i dd op3 .3 fu ll active, c l = full load; idd 3. 3v 17.0 25 ma i dd op1 .5 fu ll active, c l = full load; idd 1.5v 29.5 35 ma i ddop1.0 5 full active, c l = full load; idd lvio 31.4 35 ma i dd pd3.3 power down mode , 3.3v rail 0.3 1 ma 9 i dd pd1.5 power down mode , 1.5v rail 0.4 1 ma 9 i ddpd lvio power down mode, 1.05v rail 0.0 0.01 ma 9 i ddwol3.3 wake on lan mode, 3.3v rail 4.0 5 ma 10 i ddwol1.5 wake on lan mode, 1.5v rail 9.0 12 ma 10 i dd wollvio wake on lan mode, lvio rail 0.0 0.01 ma 10 input frequency f i v dd = 3.3 v 15 mhz 8 pin inductance l pin 7nh c in logic inputs 1 .5 5 pf c out out put pin capacitance 6 pf c in x x1 & x2 pins 6 pf clk stabilizat ion t stab from vdd power-up or de-assertion of pd to 1st clock 1.8 ms tstop_cr _off t cr of f output stop after clkreq# deasserted 23clocks trun_cr_on t cron output run after c lkreq# asserted 2 3 clocks tstop t stop cpu or pci stop after cpu or pci stop# assertion 23clocks trun t run cpu or pci run af ter c pu or pci stop# de-assertion 23clocks tfall_se t fall 10 ns trise_se t rise 10 ns smbus vo ltag e v dd 2.7 3.3 3.6 v lo w-level out put voltage v olsmb @ i pullup 0.4 v current sinking at v olsmb = 0.4 v i pu llup sm b dat a pin 4 m a sclk/sd ata clock/data rise time t ri2c (max vil - 0.15) to (min vih + 0. 15) 1000 ns scl k/sdata clock/data fall time t fi2c (min vih + 0.15) to (max vil - 0.15) 300 ns maximum smbus operating fre q uenc y f sm bus 100 khz sp re ad spectrum modulation fre q uenc y f ssmod triangular modulation 30 31.5 33 kh z 1 int e nti o n a ll y b l a nk 4 operation under these cond itions is neither implied, n or guaran teed. 5 si g nal is re q uired to be monotonic in this re g ion . 6 input leakage current does not include inputs with pull-up or pull-down resistors wake-on-la n current operating sup ply current fall/rise time o f all 3. 3v contro l inputs f rom 2 0-80% notes on dc parameters: (unless otherwise noted, guaranteed by design and characterization, not 100% tested in production). supply voltage 2 maximum vih is not to exceed vdd 3 h uman bo dy model 7 3.3v referenced inputs are: pci_stop#, cpu_stop#, itp_en, sclk, sdata, clkpw rgd/pd#, sel_pci and clkreq# inputs if selected. powerdown current input c apacitance 10 powerdown with wake on lan enabled 8 fo r marginin g purpo ses o nly. normal operation shou ld have fin = 14. 318mhz +/-50ppm 9 standard powerdown with wa ke on l an disabled.
9VRS4338D very low power clock for 2011 netbooks idt? very low power clock for 2011 netbooks 15 9VRS4338D rev a 022616 electrical characteristics?pciclk/pciclk_f electrical characteristics?usb48mhz electrical characteristics?25mhz parameter symbol conditions min typ max units notes out put impedance r dsp v o = v dd *(0.5) 12 55 ? 1 long accuracy ppm see tperiod min-max values -100 0 100 ppm 2 output high voltage v oh i oh = -1 m a 2.4 v 1 output low voltage v ol i ol = 1 ma 0.4 v 1 v oh @min = 1.0 v -33 ma 1 v oh @max = 3. 135 v -3 3 m a 1 v ol @ min = 1.95 v 30 ma 1 v ol @ max = 0.4 v 38 ma 1 r ising edge slew rate t sl r measured from 0.8 to 2.0 v 1 1. 4 4v/ns1 falling edge slew rate t flr measured from 2.0 to 0.8 v 1 1. 5 4v/ns1 duty cycle d t1 v t = 1.5 v 45 47.7 55 % 1 pin to pin skew t skew v t = 1.5 v 206 2 50 p s 1 int entional pci to pc i delay t skew v t = 1.5 v 100 200 2 00 p s 1 jitter, cycle to cycle t jcyc-cyc v t = 1.5 v 139 500 ps 1 output low current i ol i oh output high current parameter symbol conditions min typ max units notes long accuracy ppm see tperiod min-max values -100 0 100 ppm 1,2 output high voltage v oh i oh = -1 m a 2.4 v 1 output low voltage v ol i ol = 1 ma 0.4 v 1 v oh @min = 1.0 v -29 ma 1 v oh @max = 3. 135 v -2 3 m a 1 v ol @ min = 1.95 v 29 ma 1 v ol @ max = 0.4 v 27 ma 1 r ising edge slew rate t sl r measured from 0.8 to 2.0 v 1 1. 4 2 v/ns 1 falling edge slew rate t flr measured from 2.0 to 0.8 v 1 1. 4 2 v/ns 1 duty cycle d t1 v t = 1.5 v 45 47.3 55 % 1 jitter, cycle to cycle t jcyc-cyc v t = 1.5 v 123 3 50 p s 1 output high current i oh output low current i ol parameter symbol conditions min typ max units notes long accuracy ppm see tperiod min-max values -30 0 30 ppm 1,2 output high voltage v oh i oh = -1 m a 2.4 v 1 output low voltage v ol i ol = 1 ma 0.4 v 1 v oh @min = 1.0 v -29 ma 1 v oh @max = 3. 135 v -2 3 m a 1 v ol @ min = 1.95 v 29 ma 1 v ol @ max = 0.4 v 27 ma 1 r ising edge slew rate t sl r measured from 0.8 to 2.0 v 0.5 1. 4 2 v/ns 1 falling edge slew rate t flr measured from 2.0 to 0.8 v 0.5 1. 6 2 v/ns 1 duty cycle d t1 v t = 1.5 v 45 49.3 55 % 1 jitter, cycle to cycle t jcyc-cyc v t = 1.5 v 170 2 00 p s 1 output low current i ol output high current i oh
9VRS4338D very low power clock for 2011 netbooks idt? very low power clock for 2011 netbooks 16 9VRS4338D rev a 022616 electrical characte ristics?ref-14.318mhz parameter symbol conditions min typ max units notes long accuracy ppm see tperiod min-max values -100 0 100 ppm 1,2 output high voltage voh ioh = -1 ma 2.4 v 1 output low voltage vol iol = 1 ma 0.4 v 1 output high current ioh voh @min = 1.0 v, voh@max = 3.135 v -29 -23 ma 1 output low current iol vol @min = 1.95 v, vol @max = 0.4 v 29 27 ma 1 rising edge slew rate tslr measured from 0.8 to 2.0 v 1 1.5 4 v/ns 1 falling e dge slew rate tflr measured from 2.0 to 0.8 v 1 1.6 4 v/ns 1 duty cycle dt1 vt = 1.5 v 45 50.1 55 % 1 jitter, cycle to cycle tjcyc-cyc vt = 1.5 v 138 1000 ps 1 notes for pci, usb48m, 25m and 14.318m outputs t a = 0 - 85c; v dd = 3.3 v +/-5%; c l =5pf, rs is according to data sheet loading table for 1 load (unless specified otherwise) 1 guaranteed by design and characterization, not 100% tested in production. 2 all long term accuracy and clock period specifications are guaranteed assuming that ref is at 14.31818mhz 3 the average period over any 1us period of time
9VRS4338D very low power clock for 2011 netbooks idt? very low power clock for 2011 netbooks 17 9VRS4338D rev a 022616 single-ended clock tolerances no spread- spec clock periods - single-ended outputs wi th spread spectrum disabled - spec single-ended clock tolerances with spread spectrum enabled - spec clock periods - single-ended outputs with spread spectr um enabled - spec ref pc i 48m 25m 100 100 100 30 ppm 1000 500 350 200 ps 0.00% 0.00% 0.00% 0.00% % cycle to c ycle jitter spread ppm tolera nc e 1 clock 1us 0.1s 0.1s 0.1s 1us 1 clock -c2c jitter absper min -ssc short-term average min - ppm long-term average mi n 0 ppm period nominal + ppm long-term average max +ssc short-term average max +c2c jitter absper max ref 14.318 68.83429 69.83429 69.84128 69.84826 70.84826 ns 1,2 pci 33.333 29.49700 29.99700 30.00000 30.00300 30.50300 ns 1,2 48m 48.000 20.48125 20.83125 20.83333 20.83542 21.18542 ns 1,2 25m 25.000 39.79880 39.99880 40.00000 40.00120 40.20120 ns 1,2 notes ssc off center freq. mhz measurement window units ref pc i 48m 25m 100 100 100 30 ppm 1000 500 350 200 ps 0.00% -0.50% 0.00% 0.00% % spread ppm tolera nc e cycle to c ycle jitter 1 clock 1us 0.1s 0.1s 0.1s 1us 1 clock -c2c jitter absper min -ssc short-term average min - ppm long-term average mi n 0 ppm period nominal + ppm long-term average max +ssc short-term average max +c2c jitter absper max ref 14.318 ns 1,2 pci 33.250 29.49718 29.99718 30.07218 30.07519 30.07218 30.14718 30.64718 ns 1,2 48m 48.000 ns 1,2 25m 25.000 ns 1,2 1 guaranteed by design and characterization, not 100% tested in production. 2 all long term accuracy specifications are guaranteed with the assumption that the crystal input is tuned to exactly 14.31818mh z . n/a n/a n/a ssc on center freq. mhz measurement window units notes
9VRS4338D very low power clock for 2011 netbooks idt? very low power clock for 2011 netbooks 18 9VRS4338D rev a 022616 differential clock tolerances clock periods?differential outputs with spread spectrum disabled clock periods?differential outputs with spread spectrum enabled cpu src dot96 sata 100 100 100 100 ppm 85 85 250 85 ps -0.50% -0.50% 0.00% 0.00% % ppm tolera nc e cycle to c ycle jitter spread 1 clock 1us 0.1s 0.1s 0.1s 1us 1 clock -c2c jitter absper min -ssc short-term average min - ppm long-term average min 0 ppm period nominal + ppm long-term average max +ssc short-term average max +c 2c jitter absper max 100.00 9.91400 9.99900 10.00000 10.00100 10.08600 ns 1,2 133.33 7.41425 7.49925 7.50000 7.50075 7.58575 ns 1,2 166.67 5.91440 5.99940 6.00000 6.00060 6.08560 ns 1,2 200.00 4.91450 4.99950 5.00000 5.00050 5.08550 ns 1,2 266.67 3.66462 3.74962 3.75000 3.75037 3.83537 ns 1,2 333.33 2.91470 2.99970 3.00000 3.00030 3.08530 ns 1,2 400.00 2.41475 2.49975 2.50000 2.50025 2.58525 ns 1,2 src 100.00 9.91400 9.99900 10.00000 10.00100 10.08600 ns 1,2 sata 100.00 9.91400 9.99900 10.00000 10.00100 10.08600 ns 1,2 dot96 96.00 10.16563 10.41563 10.41667 10.41771 10.66771 ns 1,2 notes cpu measurement window units ssc off center freq. mhz 1 clock 1us 0.1s 0.1s 0.1s 1us 1 cloc k -c2c jitter absper min -ssc short-term average min - ppm long-term average mi n 0 ppm period nominal + ppm long-term average max +ssc short-term average max +c2c jitter absper max 99.75 9.91406 9. 99906 10.02406 10.02506 10.02607 10.05107 10.13607 ns 1,2 133.00 7.41430 7. 49930 7.51805 7.51880 7.51955 7.53830 7.62330 ns 1,2 166.25 5.91444 5. 99944 6.01444 6.01504 6.01564 6.03064 6.11564 ns 1,2 199.50 4.91453 4. 99953 5.01203 5.01253 5.01303 5.02553 5.11053 ns 1,2 266.00 3.66465 3. 74965 3.75902 3.75940 3.75977 3.76915 3.85415 ns 1,2 332.50 2.91472 2. 99972 3.00722 3.00752 3.00782 3.01532 3.10032 ns 1,2 399.00 2.41477 2. 49977 2.50602 2.50627 2.50652 2.51277 2.59777 ns 1,2 src 99.75 9.91406 9. 99906 10.02406 10.02506 10.02607 10.05107 10.13607 ns 1,2 1 guaranteed by design and characterization, not 100% tested in production. cpu 2 all long term accuracy specifications are guaranteed with the assumption that the crystal input is tuned to exactly 14.31818mh z . measurement window units ssc on center freq. mhz notes
9VRS4338D very low power clock for 2011 netbooks idt? very low power clock for 2011 netbooks 19 9VRS4338D rev a 022616 power-up sequencing requirements marking diagram notes: 1. line 1: company name 2. line 2: truncated part number. 3. ?l? denotes rohs compliant package. 4. line 3: yyww is the last two digits of the year and week that the part was assembled. 5. line 4: country of origin. 6. line 5: lot is the lot number. ics vrs4338dl yyww coo lot
9VRS4338D very low power clock for 2011 netbooks idt? very low power clock for 2011 netbooks 20 9VRS4338D rev a 022616 package outline and dimensions (ndg48)
9VRS4338D very low power clock for 2011 netbooks idt? very low power clock for 2011 netbooks 21 9VRS4338D rev a 022616 package outline and dimensions (ndg48), cont.
9VRS4338D very low power clock for 2011 netbooks idt? very low power clock for 2011 netbooks 22 9VRS4338D rev a 022616 ordering information "lf" suffix to the part numb er are the pb-free configurat ion and are rohs compliant. ?d? is the device revision d esignator (will not correlate with the datasheet revision). while the information presented herein has been checked for both accuracy and reliability, integrated device technology (idt) a ssumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would resul t from its use. no other circuits, patents, or licenses are implied. this product is intended for use in normal commercial applications. any other applications such as those requiring extended temperatur e range, high reliability, or other extr aordinary environmental requirements are not recommended without additional processing by idt. idt reserves the right to change any circuitr y or specifications without noti ce. idt does not authorize or warrant any idt product for use in life support devices or critical medical instruments. revision history part / order number shipping packaging package temperature 9VRS4338Dklf trays 48-pin mlf 0 to +85 c 9VRS4338Dklft tape and reel 48-pin mlf 0 to +85 c rev. issue date intiator description page # a 2/26/2016 rdw updated pod drawings with current ndg48 spec. various
? 2016 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. idt, ic s, and the idt logo are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa corporate headquarters integrated device technology, inc. www.idt.com for sales 800-345-7015 408-284-8200 fax: 408-284-2775 tech support www.idt.com/go/support innovate with idt and accelerate your future netw orks. contact: www.idt.com 9VRS4338D very low power clock for 2011 netbooks synthesizers

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