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akros silicon, inc. 6399 san ignacio avenue, suite 250, san jose, ca 95119 usa 408.746.9000 ? www.akrossilicon.com general description the AS1860 integrates akros greenedge ? isolation technology with next generation power-over-ethernet (poe) pd and integrated isolated high speed digital communicati on to deliver up to 90w to an isolated secondary side comprising of four independent outputs. delivering 90w enables a new range of poe pd capabilities and solutions which greatly expands the markets for poe. the AS1860?s 90w capability is fully backwards compatible with type 1 (ieee ? 802.3af) and type 2 (ieee ? 802.3at) compliant pd. this is integrated with high-v oltage isolation and quad-output digital power dc-dc converters ? resulting in a complete poe & power management solution in a single device with minimal external components. in addition to enabling digital poe power conversion, akros greenedge ? isolation enables direct digital management of both isolated primary power and secondary system power for real time end-to-end green power application capabilities. typical applications ? voice-over-ip (voip) phones ? wireless lan & wimax access points (wap) ? pan, tilt, zoom (ptz) cameras, ip cameras ? thin-client and notebook computers ? fiber-to-the-home (ftth) terminals ? point-of-sale (pos) terminals, rfid readers simplified application diagram features poe ? pd ? controller ? ? fully integrated 60/90w pd controller ? backwards compatible with type 1 and type 2 ieee ? 802.3af/at compliant pd ? 60/90w power up can be controlled by pse or AS1860 ? AS1860 will control safe 60/90w delivery from ?dumb? sources ? 4-pair power detection & sec ondary side logic notification ? automatic type 1, type2 & 60w poe detection in hw & i 2 c modes ? low resistance pd power fet switch (0.5 ? typical) primary \ side ? dc \ dc ? controller ? ? high-efficiency dc-dc controller with digital optimization ? primary-secondary high-voltage integrated digital isolation ? programmable primary clock frequency ? local-power operation down to 9.5v secondary \ side ? power ? outputs ? programmable pwm frequencies synched to external clock ? output #1: sync controller with programmable power-fet timing for high efficiency at both light and full load ? outputs #2 & #3: buck regulators w/2a fets ? output #4: dc-dc controller for buck, boost, or led boost platform applications power management ? hardware programmable start-up power sequencing ? primary-side power monitoring & control from secondary-side ? individual output power-good management ? voltage margining for each output ? primary gpio/adc controlled via secondary gpio or i 2 c ? 5v c-compatible with interrupt on alarm services ? programmable watchdog timer emc compliance and protection ? slew-rate-controlled power drivers ? multi-phased pwm clocking, with external sync clock option ? optional spread-spectrum clocki ng available for all pwms ? over-current, under/over-voltage and short-circuit protection ? high-temperature warning and shutdown ? meets iec 61000-4-2/3/4/5/6, iec60747, iec 60950, din en60747-5-2 (vde0884), & ul1577 requirements for emc compliance and basic isolation to 2120 vdc (1500 vrms) ? 100v process for poe transient voltage robustness AS1860 ? 60w/90w poe pd controllers with hv isolation and quad dc-dc outputs
AS1860 akros silicon, inc. 6399 san ignacio avenue, suite 250, san jose, ca 95119 usa 408.746.9000 ? http://www.akrossilicon.com 2 table of contents general des criptio n ........................................................................................................... ................................................ 1 typical applic ations .......................................................................................................... ................................................. 1 simplified applic ation diagram ................................................................................................ ....................................... 1 features ...................................................................................................................... ............................................................ 1 poe pd co ntrolle r ............................................................................................................. ................................................. 1 primary-side dc- dc contro ller ................................................................................................. ..................................... 1 secondary-side po wer outputs .................................................................................................. ................................... 1 power mana gement .............................................................................................................. ............................................... 1 emc compliance a nd protection ................................................................................................. ................................... 1 figures ....................................................................................................................... .............................................................. 4 tables ........................................................................................................................ ................................................................ 5 pin assignments and descript ions .............................................................................................. .................................. 6 test specific ations ........................................................................................................... ................................................ 11 typical performance characteris tics ........................................................................................... .......................... 18 functional d escript ion ........................................................................................................ ........................................... 19 isolation ..................................................................................................................... ........................................................... 19 pd contro ller ................................................................................................................. .................................................... 20 pd power mosfet ............................................................................................................... ................................................. 20 under-voltage lock out (uvlo) .................................................................................................. ................................... 20 poe current limit/ current sen se ............................................................................................... ................................. 20 over-temperature protection ................................................................................................... .................................. 20 pd operatin g states ........................................................................................................... .............................................. 20 at detection operat ion ........................................................................................................ ........................................... 21 local powe r source ............................................................................................................ ............................................. 21 pwm clock ge nerati on .......................................................................................................... ........................................... 22 pwm clock frequency configuration ............................................................................................. .......................... 22 external clock so urce (clk _in) ................................................................................................ ................................... 22 emi performance cont rol ....................................................................................................... ....................................... 22 power outp ut #1 ............................................................................................................... .................................................. 23 primary-side dc- dc contro ller ................................................................................................. ................................... 23 soft-start inrush current limi t ............................................................................................... ................................... 24 current-limit and current sense ............................................................................................................................... . 24 secondary-side sy nc contro ller ................................................................................................ ............................... 24 compensation and loop f eedback ................................................................................................ ............................... 24 low-load current operation - dcm ............................................................................................................................. 2 4 over-voltage protection ....................................................................................................... ........................................ 24 power outputs #2 and #3 ....................................................................................................... .......................................... 24 loop feedback a nd compen sation ................................................................................................ ............................... 25 current-limit and current sense ............................................................................................................................... . 25 over-voltage protection ....................................................................................................... ........................................ 25 power outp ut #4 ............................................................................................................... .................................................. 25 compensation and loop f eedback ................................................................................................ ............................... 26 current-limit and current sense ............................................................................................................................... . 27 over-voltage protection ....................................................................................................... ........................................ 27 hardware mode operation ....................................................................................................... ...................................... 27 device initialization & hardware mode selection ............................................................................... .................. 27 hw mode power ou tput cont rols ................................................................................................. .............................. 27 hw mode power output sequencing ........................................................................................................................... 27 hw mode power moni toring (pgood) .............................................................................................. ............................ 28 hw mode wat chdog ti mer ........................................................................................................ ....................................... 28 watchdog conf iguration ........................................................................................................ ....................................... 28 watchdog ser vice .............................................................................................................. ............................................... 28 watchdog timeout .............................................................................................................. ............................................... 28 hw mode general-purp ose i/o operation ......................................................................................... ........................ 28 software mode operation ....................................................................................................... ...................................... 28 device initialization and software mode selecti on ............................................................................. ............... 28 sw mode power ou tput cont rols ................................................................................................. .............................. 29 sw mode power ou tput sequencing ............................................................................................... ............................ 29
AS1860 akros silicon, inc. 6399 san ignacio avenue, suite 250, san jose, ca 95119 usa 408.746.9000 ? http://www.akrossilicon.com 3 sw mode power status monitoring (pgood) ....................................................................................... ................... 29 history re gister .............................................................................................................. .................................................. 30 pd voltage and curre nt measure ments ........................................................................................... .............. ?..?30 pd over-current alarm thr eshold ............................................................................................... ............................. 30 sw mode powe r margin ing ....................................................................................................... ....................................... 30 sw mode emi perfo rmance co ntro l ............................................................................................... ............................ 30 pwm clocks - prbs randomization ............................................................................................... ................................ 30 pwm clocks - fr actional-n ..................................................................................................... ........................................ 30 sw mode general-purpose i/o & adc ............................................................................................................................ 30 general-purpose i/o pins ............................................................................................................................... .................. 31 general-purpose a dc (adcin pin) ............................................................................................... ................................... 31 sw mode watchdog timer operation .......................................................................................................................... 31 watchdog time r mode s .......................................................................................................... .......................................... 31 watchdog timer operation ...................................................................................................... ...................................... 31 sw mode interrup t operation ................................................................................................... ................................... 32 interrupt m asking ............................................................................................................. ................................................ 32 interrupt st atus .............................................................................................................. .................................................. 32 i 2 c interf ace ................................................................................................................... ...................................................... 32 start/stop timing ............................................................................................................. .................................................. 32 data timing ................................................................................................................... ......................................................... 32 acknowledg e (ack ) ............................................................................................................. ............................................... 32 device address co nfiguration .................................................................................................. ................................... 33 device address/o peration word ................................................................................................. ................................ 34 register address word ............................................................................................................................... .................... 34 data word ............................................................................................................................... ............................................... 34 write cy cle ................................................................................................................... ........................................................ 34 read cycle ............................................................................................................................... .............................................. 34 register des criptio ns ......................................................................................................... ............................................ 34 power over ethe rnet over view .................................................................................................. ................................ 42 power feed alternatives for 10/100/1000m ethe rnet syste ms ..................................................................... .... 42 802.3at specif icatio n ......................................................................................................... ................................................ 43 60w/90w applic ations .......................................................................................................... ............................................... 43 lldp communi cation ............................................................................................................ .............................................. 44 four pair voltage sense enabl ed ............................................................................................... ................................ 44 switching converter pr imary bias enabled ...................................................................................... ..................... 44 secondary side logic enable ................................................................................................... ..................................... 45 package specif ications ........................................................................................................ ........................................... 48 contact info rmation ........................................................................................................... ............................................. 50 important notices ............................................................................................................. ................................................ 50 legal no tice .................................................................................................................. ....................................................... 50 reference design policy ............................................................................................................................... .................. 50 life support policy ........................................................................................................... ................................................ 50 substance co mpliance .......................................................................................................... ........................................... 51
AS1860 akros silicon, inc. 6399 san ignacio avenue, suite 250, san jose, ca 95119 usa 408.746.9000 ? http://www.akrossilicon.com 4 figures figure 1 - AS1860 pi n assignm ents ............................................................................................. ........................................................ 6 figure 2 - vin=38v 12v 2.5a st art up .......................................................................................... ...................................................... 18 figure 3 - vin=40v_ 12v_2.5a _start up with el load ............................................................................ ............................................. 18 figure 4 - vin=57v_12v_3a _sta rt up with el load .............................................................................. .............................................. 18 figure 5 - vin=48v_12v_3a _sta rt up with el load .............................................................................. .............................................. 18 figure 6 - vin=48v_12v _3a _start up ........................................................................................... .................................................... 18 figure 7 - vin=57v_12v _3a _start up ........................................................................................... .................................................... 18 figure 8 - AS1860 bl ock diagram ............................................................................................... ....................................................... 19 figure 9 - AS1860 pd cont roller block diagram ................................................................................. ............................................... 20 figure 10 - pwm clock generation block diagram ............................................................................................................................ 22 figure 11 - power out put #1 block diagram ..................................................................................... ................................................. 23 figure 12 - power output s #2, #3 blo ck diagram ................................................................................ .............................................. 25 figure 13 - power output #4 block diagram - buck .............................................................................. ........................................... 26 figure 14 - power output #4 block diagram - boost ............................................................................. ......................................... 26 figure 15 - power output #4 blo ck diagram - boos t led dr iver .................................................................. .................................. 26 figure 16 - hw mode output (s) hardware enabled ................................................................................ ........................................... 27 figure 17 - hw mode output (s) hardware disabled ............................................................................... ........................................... 27 figure 18 - hw mode power ou tput sequenci ng exam ple ........................................................................... ..................................... 28 figure 19 - hardware mode pgood g eneratio n .................................................................................... ........................................... 28 figure 20 - hardware mode gpio pin mapping .................................................................................... ............................................. 28 figure 21 - sw mode output (s) hardware enabled ................................................................................ ........................................... 29 figure 22 - sw mode output (s) hardware disabled ............................................................................... ........................................... 29 figure 23 - sw mode power ou tput sequenci ng exam ple ........................................................................... ..................................... 29 figure 24 - software mo de pgood g eneratio n .................................................................................... ............................................ 30 figure 25 - gpio and adc pin m apping .......................................................................................... .................................................. 31 figure 26 - i 2 c interface start/st op and data timing ........................................................................................ ................................. 33 figure 27 - i 2 c acknowled ge timi ng .......................................................................................................... ........................................ 33 figure 28 - device addr ess/operati on word ..................................................................................... ................................................. 34 figure 29 - i 2 c interface write cycle timing ................................................................................................ ...................................... 35 figure 30 - i 2 c interface read cycle timi ng (with repeat ed star t) ........................................................................... ........................ 35 figure 31 - ieee ? std. 802.3af power feeding sc hemes ........................................................................................... ....................... 43 figure 32 ? four pair sensing enabling external mosfet m1 ..................................................................... ..................................... 44 figure 33 ? primary bias enab ling external mosfet m1 .......................................................................... ........................................ 45 figure 34 ? secondary side logic c ontrol of external mosfet m1 ................................................................ .................................... 45 figure 35 - poe power-o n sequence waveform .................................................................................... ........................................... 46 figure 36 - typical isolated sync hronous flyback applicat ion .................................................................. ......................................... 47 figure 37 - 64-pin qfn dimensions ............................................................................................................................... .................... 48
AS1860 akros silicon, inc. 6399 san ignacio avenue, suite 250, san jose, ca 95119 usa 408.746.9000 ? http://www.akrossilicon.com 5 tables table 1 - AS1860 signal desc riptions - pr imary side ........................................................................... ............................................... 6 table 2 - AS1860 signal descriptions - secondary side ...................................................................................................................... 8 table 3 - absolute maximum ratings ............................................................................................ ..................................................... 11 table 4 - normal oper ating cond itions ......................................................................................... ..................................................... 11 table 5 - pd section elec trical charac teristics ............................................................................... ................................................... 11 table 6 - primary side digital, i/o, and a/d electrical characteri stics ....................................................... ........................................ 12 table 7 - primary side dc -dc controller electric al characte ristics ............................................................ ....................................... 13 table 8 - secondary side sync controller (output #1) electrical characteristics ............................................................................... 13 table 9 - secondary side dc-dc regulators (out puts #2, #3) electrical characte ristics ......................................... ........................ 14 table 10 - secondary side dc- dc controller (output #4) el ectrical char acteristics ............................................. ............................ 14 table 11 - secondary side digital i/o and i 2 c electrical char acteristics ........................................................................................... 16 table 12 - thermal protection el ectrical char acteristics ...................................................................... .............................................. 17 table 13 - isolation electr ical charac teristics ............................................................................... ...................................................... 17 table 14 - classif ication map ................................................................................................. ............................................................ 21 table 15 - at_det and ldet oper ation .......................................................................................... ................................................. 22 table 16 - typical ldet external resistor design ............................................................................................................................. 2 2 table 17 - pwm clock ra te confi guration ....................................................................................... .................................................. 23 table 18 - sync & overl ap delay timi ng limi t .................................................................................. ................................................. 24 table 19 - sync_dly & sync_ovl re sistor calculat ion example ................................................................... ............................. 24 table 20 - AS1860 device ad dress confi guratio n ................................................................................ ............................................. 33 table 21 - AS1860 regist er addre ss word ....................................................................................... ................................................. 34 table 22 - AS1860 register and bit summary .................................................................................... ............................................... 35 table 23 - alarms and power status (read-on ly) - 00h .......................................................................... .......................................... 36 table 24 - interrupt mask (r/w ) - 01h ......................................................................................... ....................................................... 36 table 25 - interrupt stat us (read-on ly) - 02h ................................................................................. ................................................... 37 table 26 - pgood volt age masks (r/w ) - 03h .................................................................................... ............................................. 37 table 27 - watchdog enable, mask, service (r/w) - 04h ......................................................................... ......................................... 38 table 28 - pgood & watch dog history (r /w) - 05h ............................................................................... .......................................... 38 table 29 - device control and i/o status (r/w) - 06h ........................................................................................................................ 39 table 30 - watchdog ti meout (r/w ) - 07h ....................................................................................... .................................................. 39 table 31 - adcin voltag e (read-only ) - 08h..................................................................................... ................................................ 39 table 32 - adcin alarm threshold (r/w) - 09h ............................................................................................................................... .. 39 table 33 - pd status and system clock control (r/w) - 0ah ..................................................................... ....................................... 39 table 34 - pd voltage (read-only) - 0bh ....................................................................................... ................................................... 40 table 35 - pd current (read-only ) - 0ch ....................................................................................... ................................................... 40 table 36 - pd over-current al arm threshold (r/w) - 0dh ........................................................................ ........................................ 40 table 37 - outputs 1, 2 disable & margin control (r/w) - 0eh .................................................................. ........................................ 41 table 38 - outputs 3, 4 disable & margin control (r/w) - 0fh .................................................................. ........................................ 41 table 39 - poe design framework summary ....................................................................................... ............................................. 42
AS1860 akros silicon, inc. 6399 san ignacio avenue, suite 250, san jose, ca 95119 usa 408.746.9000 ? http://www.akrossilicon.com 6 pin assignments and desc riptions figure 1 - AS1860 pin assignments table 1 - AS1860 signal descriptions - primary side pin name i/o 1 description primary-side: pd controlle r 15 48vin p AS1860 startup power input. paddle #1 48rtn p input power return. one of three bottom side device connections, 48rtn (paddle #1) is connected to the internal pd power mosfet source. 48rtn is connected to 48n (paddle #2) via this internal inrush current limiting power mosfet. paddle #2 48n p primary-side transformer power return. one of three bottom side device connections, 48n (paddle #2) provides the power return for t he dc-dc controller transformer primary. 48n is connected to the internal pd power mosfet drain. 48n is connected to 48rtn via this internal inrush current limiting power mosfet. 16 ldet d, i local power enable input. enables use of local power for the dc-dc controller and disables pd functions. when activated this disables t he poe pd signature capability that normally uses the rsig signature resistor. refer to figure 3 for a typical ldet circuit conf iguration and table 16 for resistor values. if local power detection is not required, connect ldet to 48vin. note that ldet must not be tied to 48rtn. in software mode, the ldet status can be re ad from the pd status & control register. 19 rclass a poe classification resistor. see table 14 for resistor value. connect the classification resistor between this input and the 48rtn (p addle #1). the resistor is automatically disconnected after a valid pd classification. 17 rsig a, i poe signature resistor. connect a 26.7k ? signature resistor from rsig to 48vin. this resistor is automatically disconnecte d after a valid pd detection. 18 clim i sets internal pd po wer mosfet current limit in poe operation mode; should be pulled either high (vdd5i) or low (48rtn). in local mode (ldet active), clim is not used. high = vdd5i = ilim_at (see elec trical characteristics) low = 48rtn = ilim_af (see electrical characteristics) primary-side: common power pins 12 vbp p internal bias node, decouple with an external capacitor to vbias. 13 vbias p bias voltage input (typically from a power transformer winding).
AS1860 akros silicon, inc. 6399 san ignacio avenue, suite 250, san jose, ca 95119 usa 408.746.9000 ? http://www.akrossilicon.com 7 14 vdd3v_out p primary-side supply voltage source (3.3 volts). this supply can be used for additional external circuits on the primary side that are re ferenced to 48n, see electrical characteristics for supply limits. 64 vdd3v_in p primary-side input supply voltage (3.3 volts) normally connected to vdd3_out. 21 vdd5i p low power node that can be used to supply 48rtn referenced devices, see electrical characteristics for supply limits. must be decoupled with an external capacitor. 23 rb i, pu pd controller state machine power-on-reset, connect to 48rtn with external capacitor. primary-side: dc-dc controlle r 7 css a primary-side pwm soft start input, decouple to 48n with an external capacitor. 11 gate a primary-side external power fet gate drive. 8 isensep a current sense input, also used to set primary pwm current limit (with external resistor). 63 sync_dly a along with sync_ovl this signal sets primary and secondary-side primary sync delay timing for output #1. connecting a resistor to ground (48n) from this input will optimize output efficiency for a given pd power level or sync power-fet choice. see table 19 for resistor value selection and other details. 6 sync_ovl a along with sync_dly this signal sets primary and secondary-side primary sync overlap timing for output #1. connecting a resistor to ground (48n) from this input will optimize output efficiency for a given pd power level or sync power-fet choice. see table for resistor value selection and other details. primary-side: clock dividers 2 pri_div a, i primary pwm frequency divider input. connect an external resistor (5%) from this input to ground to set the primary pwm clock divider. us ed in either internal or external (if the clk_in input is active) clocking operation. note that the primary pwm clo cking rate is a function of both pri_div and sec_div divider ratios. see device description, figure 4 and table 17 for details. 62 sec_div a, i secondary pwm frequency divider input. co nnect an external resistor (5%) from this input to ground to set the secondary pwm clock divider for either internal or external (if the clk_in input is active) pwm clocking operation. note that the secondary pwm clo cking rate is a function of this sec_div divider ratio. see pwm clock generation description for details. primary-side: inputs & outputs 3 gpip i, pu general purpose digital input on primary side, referenced to 48n. see gpio operation. 4 gpop o general purpose digital output on primary side, referenced to 48n. see gpio operation. 20 adcin a, i general purpose adc input, referenced to 48rtn. 1 i2c_adr a, i sets the AS1860 i 2 c device address. one of 8 possible device addresses is configured by connecting a resistor on this input to ground (48n ). as a result of the chosen resistor, 3 bits of available addressing for the device are conf igured. see table 20 for resistor values and other details. 61 wd_mode i watchdog timer mode. enables/disables watchdog timer and sets timer period, operation also varies with mode input setup. for hardware mode operation: wd_mode = low (connect to 48n): watchdog off. wd_mode = capacitor to 48n: a 1 second tim eout generates a pgood output transition. wd_mode = high (connect to vdd3v_out): a 32 second timeout generates a pgood output transition. for software mode operation: wd_mode = low (connect to 48n): watchdog off. wd_mode = capacitor to 48n: power-on enables watchdog usage and counter starts (at max count) after pgood indicates good powe r. use the watchdog timeout register to change timeout count. watchdog servicing is via hardware or i 2 c commands. wd_mode = high (connect to vdd3v_out): power-on enables watchdog usage but waits for software to enable before starting. use watchdog timeout register for timeout length (reset to max). watchdog servicing is via hardware pin or i 2 c commands.
AS1860 akros silicon, inc. 6399 san ignacio avenue, suite 250, san jose, ca 95119 usa 408.746.9000 ? http://www.akrossilicon.com 8 table 2 - AS1860 signal descr iptions - secondary side pin name i/o 1 description secondary-side: common power pins paddle #3 sgnd p secondary-side ground connection. one of three bottom side device connections, sgnd (paddle #3) is the secondary-side ground connection. 37, 38 vp p #2, #3, #4 dc-dc regulators and controller power inputs, internally connected together. must be connected externally to the same source, nominally output #1 46 vdd3v_osec p internal buck power regulator output. must be decoupled and used for the vdd3v_isec (pin 58) power source. vdd3v_osec can also be used for additional 3.3v secondary-side platform power (pull-ups, etc.); see elec trical characteristics for supply limits. 58 vdd3v_isec p secondary-side 3.3v power input. this must be sourced from vdd3v_osec (pin 46). secondary-side: synchronous rectification controller (output #1) 47 vdd_sync a sync fet power decoupling node. decouple with an external capacitor, vdd_sync to sgnd. this node is nominally 5v. 51 fb1 a controller voltage feedback input. 53 isenses a controller secondary-side sync switches node current sense. sensed signal is used to control the external secondary-side power fet, making it an efficient power diode. 50 comp1 a controller compensation network connection. 48 sync_out a controller sync gate drive output. used for se condary-side synchronization in conjunction with the primary-side controller. 52 agnd1 p controller secondary-side sense ground, used for both differential feedback and differential current sensing. should be routed differentiall y, as the pairs of fb1 & agnd1 and isenses & agnd1. secondary-side: regulato r (output #2) 41 agnd2 p sense ground for the output #2, should be routed together with fb2 for differential feedback sensing and then tied to ground at the feedba ck resistor. if output #2 is not used, agnd2 should still be tied to sgnd. 39 lx2 a regulator switches node output. if output #2 is not used, float lx2 (no user connection). 40 fb2 a regulator voltage feedback input, also used to disable output #2 (see en2). 5 mode i the mode pin selects the device operation mode at power-on. for hardware mode operation: ? mode 1 = reset mode o mode 1 is selected by holding the mode pin low (mode to 48n). ? mode 2 = hw operating mode o mode 2 is selected with a pull-up resistor (17.8k ? max) from mode to vdd3v_out plus a required power-on reset capacitor from mode to 48n. for software mode operation: ? mode 1 = reset mode o mode 1 is selected by holding the mode pin low (mode to 48n). ? mode 2 = sw operating mode with i2c device address per i2c_adr pin setting o mode 2 is selected with a required power-on reset capacitor from mode to 48n. primary-side: miscellaneous 22 test1 must be pulled down to 48rtn with a resistor (4.7k ? ? ). 9, 10 nc no user connection. must be floated. 1 i = input, o = output, i/o = bidirectional, pu = internal pull-up, pd = internal pull-down, p = power, a = analog, d = digital, od = open drain
AS1860 akros silicon, inc. 6399 san ignacio avenue, suite 250, san jose, ca 95119 usa 408.746.9000 ? http://www.akrossilicon.com 9 44 en2 d, i, pu hardware enables control for dc-dc regulator #2. a capacitor to ground applied to this input is required for buck reset before start up. this capacitor also sets the regulator delay start time, complimenting the internal fixed soft-start time. if output #2 is not used, apply a low (sgnd) to this input, and connect fb2 to vp to fully disable the regulator. secondary-side: regulato r (output #3) 34 agnd3 p sense ground for the output #3, should be ro uted together with fb3 for differential feedback sensing and then tied to ground at the feedback resistor. if output #3 is not used, agnd3 should still be tied to sgnd. 36 lx3 a regulator switches node output. if output #3 is not used, float lx3 (no user connection). 35 fb3 a regulator voltage feedback input, also used to disable output #3 (see en3). 43 en3 d, i, pu hardware enables control for dc-dc regulator #3. a capacitor to ground applied to this input is required for buck reset before start up. this capacitor also sets the regulator delay start time, complimenting the internal fixed soft-start time. if output #3 is not used, apply a low (sgnd) to this input, and connect fb3 to vp to fully disable the regulator. secondary-side: buck or boost controller (output #4) 45 buck_en d, i selects between buck and bo ost mode of operation for output #4. low = sgnd = boost. high = buck if output #4 is not used, tie buck_en to sgnd. 33 vboost a boost voltage decoupling node. decouple with a capacitor to lx4 when output #4 is in buck mode. when operating output #4 in boos t mode, this input should be connected to output #1. if output #4 is not used, vboost should be tied to vp. 30 hsd4 a high side external power fet gate drive. if output #4 is not used hsd4 should be left floating with no user connection. 29 lsd4 a low side external power fet gate drive. if output #4 is not used lsd4 should be left floating with no user connection. 24 agnd4 p sense ground for controller #4, t ogether with fb4 used for differential feedback sensing at the feedback divider. if output #4 is not used, agnd4 should still be tied to sgnd. 27 isenp4 a positive current sense input. if output #4 is not used, isenp4 should be tied to sgnd. 28 isenn4 a negative current sense input. if ou tput #4 is not used, isenn4 should be tied to sgnd. 25 fb4 a controller voltage feedback input, also used to disable output (see en4). 42 en4 d, i, pu enable control for controller #4. a capacitor to ground applied to this input is required for proper controller #4 power-on reset and start up. this capacitor also sets the controller delay start time, complimenting the internal fixed soft-start time. if output #4 is not used, apply a low (sgnd) to this input, and connect fb4 to vp to fully disable the controller. 26 comp4 a controller compensation network connection . if output #4 is not used comp4 should be left floating with no user connection. 31 lx4 a controller switch sense input. if not us ed (typical for boost and led boost applications) lx4 should be tied to sgnd. 32 lx4_sense a remote sense for lx4, used for differential s ensing. should be routed differentially with lx4 (buck mode). if not used (typical for boost and led boost applications) lx4_sense should be tied to sgnd. secondary-side: i 2 c interface (or i/o in hardware mode) 57 sdio / gpos od sdio in software mode, used for i 2 c bi-directional data input/output. gpos in hardware mode, this output reflec ts the gpip pin stat e (from the primary side). 56 scl / gpis i / i scl in software mode, used as the i 2 c clock input. gpis in hardware mode is an input that drives the gpop pin state (on the primary- side).
AS1860 akros silicon, inc. 6399 san ignacio avenue, suite 250, san jose, ca 95119 usa 408.746.9000 ? http://www.akrossilicon.com 10 59 intb / at_det od intb in software mode. the i 2 c interface interrupts output, active low. the open drain output allows user defined vo ltage output high level. at_det in hardware mode. it is the po e+ (802.3at) pse detect indication output. a high level output indicates connection to either a type 2 pse or to a local power supply. the output is open drain, active hi gh. if a type 1 pse is connected, the output of at_det remains in the inactive state (low). secondary side: inputs & outputs 60 clk_in i, pu dc coupled clock input for timing of primary and secondary dc-dc regulators & controllers if synchronizing to an external time source is desired. nominally sourced from the local ethernet master clock. 54 pgood od logical ?and? of gl obal power good & watchdog status. high = all enabled voltages (#1 with any or all of #2, #3, and #4) are within voltage spec and there is presently no watchdog timeout. low = one or more of enabled voltages out of spec, or, the watchdog has timed out. note that pgood operation is different for hardware and software modes of operation (selected by the mode input). for ha rdware mode pgood oper ation details see hw mode power monitoring (pgood) . for software mode pgood operation details see sw mode power status monitoring (pgood) . 55 wdog i watchdog timer input, used for hardware reset of the watchdog timer (if enabled). serviced with a transition of either polarity. secondary i/o: miscellaneous 49 sec_en i, pu secondary-side enable. a capacitor on this input to sgnd is required. 1 i = input, o = output, i/o = bidirectional, pu = internal pull-up, pd = internal pull-down, p = power, a = analog, d = digital, od = open drain
AS1860 akros silicon, inc. 6399 san ignacio avenue, suite 250, san jose, ca 95119 usa 408.746.9000 ? http://www.akrossilicon.com 11 test specifications table 3 - absolute maximum ratings parameter max unit 48vin, 48n, rsig: to 48rtn 100 1 v 48vin: to 48n 100 1 v 48vin, 48n, rsig: to 48rtn (under steady-state conditions) 60 2 v 48vin: to 48n (under steady-state conditions) 60 2 v gate, vbias, vbp: to 48n 20 v ldet: to 48vin no more than 6v less than 48vin v rclass, clim, rb, vdd5i: to 48rtn 6 v adcin to 48rtn 4 v vdd3v_out, vdd3v_in: to 48n 4 v isensep, css, sync_dly, sync_ovl, mode, gpip, gpop, pri_div, i2c_adr, sec_div, wd_mode: to 48n 4 v vboost: to sgnd 12 v vp, lx2, lx3, lx4, lx4_sense, fb 1, fb2, fb3, fb4: to sgnd 6 v clk_in, isenses, sec_en, comp 1, agnd1, pgood, vdd3v_isec, vdd3v_osec: to sgnd 4 v vdd_sync, sync_out, intb/at_de t, scl/gpis, sdio/gpos, wdog: to sgnd 6 v agnd2, agnd3, agnd4, comp4, isen p4, isenn4, lsd4, hsd4, en2, en3, en4, buck_en: to sgnd 6 v esd rating, human body model (per jesd22-a114) 2 kv esd charged device model 500 v esd machine model 200 v esd system level (contact/air) at rj-45 (per iec61000-4-2) 8/15 kv storage temperature 165 c operating junction temperature 125 c 1 the AS1860 has a fast internal surge clamp for transient conditi ons such as system startup and other noise conditions; the devi ce must not be exposed to sustained over-volt age condition at this level. 2 under steady state conditions; higher voltage le vel is acceptable under transient conditions. unless otherwise noted all test specifications apply ov er the full -40c to 85c operating temperature range . caution: exceeding the maximum ratings specified in this table may cause permanent damage to the device. table 4 - normal operating conditions parameter min typ 1 max unit conditions vin_af 37 48 57 v measured at the network interface vin_at 42.5 48 57 v measured at the network interface vaux (optional local power) 9.5 57 v measured at 48vin for full vldet range (referenced to 48n) thermal resistance, junction to case, jc 5 c/w operating junction temperature 125c, max thermal resistance, junction to ambient, ja 20 c/w operating junction temperature 125c, max operating temperature range -40 85 c 1 typical specifications not 100% tested. performanc e guaranteed by design and/or other correlation methods. table 5 - pd section electrical characteristics symbol parameter min typ 1 max unit conditions 2 iinrush_af inrush current limit - af pd 120 ma 13w iinrush_at inrush current limit - at pd 240 ma 30w ilim_af poe current limit - af pd 350 400 500 ma 13w, clim = 48rtn ilim_at poe current limit - at pd 720 750 1000 ma 30w, clim = vdd5i
AS1860 akros silicon, inc. 6399 san ignacio avenue, suite 250, san jose, ca 95119 usa 408.746.9000 ? http://www.akrossilicon.com 12 rds_on pd power mosfet switch on resistance 0.5 0.9 ? as measured between 48rtn and 48n with source of 48v and 200ma current. vreset_min minimum reset voltage level 2.81 v measured at the network interface 2 . vsigmin minimum signature voltage 2.7 v vsigmax maximum signature voltage 10.1 v vclassmin minimum classification voltage 14.5 v in classification, the AS1860 sinks current as defined in table 14, measured at the network interface 2 . vclassmax maximum classification voltage 20.5 v vmarkmin min mark event voltage 5.2 6.90 v measured at the network interface 2 . vmarkmax max mark event voltage 10 v imark mark event current 0.5 2.1 4 ma vclassrset classification reset threshold 2.81 5.2 6.90 v vact full power activation uvlo threshold, voltage rising 37 42 v vdeact full power de-activation uvlo threshold, voltage falling 30 v 1 typical values at: ta = 25c, vin = 48vdc. typical specificat ions not 100% tested. performance guaranteed by design and/or oth er correlation methods. 2 all measurements at the network interface are before the pd diodes (assuming a 1.2v drop across the pd diodes). table 6 - primary side digital, i/o, and a/d electrical characteristics symbol parameter min typ 1 max unit conditions vdd3v_out voltage from internally generated 3v source. 3.0 3.3 3.6 v external bias-windi ng for vbias must be in use. decouple vdd3v_out with 4.7f cap. referenced to 48n. ivdd3v_out current output from internally generated 3v source. 5 ma vdd3v_in 3v primary side voltage input. 3.0 3.3 3.6 v supplied by vdd3_out, referenced to 48n. vdd5i voltage from internally generated 5v node. 4.0 5 6.0 v decouple with 1.5f cap, referenced to 48rtn. ivdd5i current output from internally generated 5v node. 5 ma vhgpop gpop voltage output ? high 3.0 v current at gpop = 1.0 ma (vdd3v_in=3.3v, re ferenced to 48n). vlgpop gpop voltage output ? low 0.4 v current at gpop = -1.0 ma (vdd3v_in=3.3v, re ferenced to 48n). vhgpip gpip voltage input - high 2.0 v (vdd3v_in=3.3v, re ferenced to 48n). vlgpip gpip voltage input - low 0.8 v (vdd3v_in=3.3v, re ferenced to 48n). tgpio primary side gpio pin latency to register update. 10 2 ms independent of i 2 c clock speed. pin i/o is automatic to and from i 2 c registers. tadcin adcin pin latency to register update. 10 2 ms vadcin adcin voltage range 0 2.5 v referenced to 48rtn. radcin adcin resolution 8 bits adcerror adcin total unadjusted error tbd 3 lsb iladcin adcin input leakage current 100 2 na cadcin adcin input capacitance 0.3 2 pf 1 typical values at: ta = 25c, vin = 48vdc. typical specificat ions not 100% tested. performanc e guaranteed by design and/or oth er correlation methods. 2 guaranteed by design. not tested in production. 3 includes offset, full-scale, and linearity.
AS1860 akros silicon, inc. 6399 san ignacio avenue, suite 250, san jose, ca 95119 usa 408.746.9000 ? http://www.akrossilicon.com 13 table 7 - primary side dc-dc cont roller electrical characteristics symbol parameter min typ 1 max unit conditions vin_af type 1 pd input voltage 37 48 57 v measured at the network interface vin_at type 2 pd input voltage 42.5 48 57 v measured at the network interface vaux input voltage, local power mode 9.5 57 v measured at 48vin (referenced to 48n) over full vldet range vldet_on local input voltage threshold for local power mode - on 48vin -2.4v v see table 3 for absolute maximum rating for ldet (referenced to 48vin). vldet_off local input voltage threshold for local power mode - off 48vin- 1.2v v vbias external bias source voltage 8 2 14 2 v sets voh of gate. fpwm1l low end of primary pwm switching frequency range 104 khz set by external re sistors on pri_div and sec_div pins see table 17. fpwm1h high end of primary pwm switching frequency range 512 khz set by external re sistors on pri_div and sec_div pins see table 17. fosc1 pwm1 clock frequency accuracy -20 +20 % see table 17 for frequency. fpwm1t pwm switching frequency temperature coefficient 0.12 %/c refer to table 17 for pwm frequency. rh_gate gate drive impedance 6 ? high side output drive resistance, source. rl_gate 6 ? low side output drive resistance, sink. vpk1p peak current sense threshold voltage at isensep 395 mv ipeak = vpk1p / risensep. dmax1 primary pwm maximum duty cycle 80 3 % dmin1 primary pwm minimum duty cycle 10 3 % 1 typical values at: ta = 25c, vin = 48vdc. typical specificat ions not 100% tested. performance guaranteed by design and/or othe r correlation methods. 2 guaranteed by characterization. not tested in production. 3 guaranteed by design. not tested in production. table 8 - secondary side sync controller (output #1) electrical characteristics symbol parameter min typ 1 max unit conditions vsync_out sync_out voltage 4.5 5 6 v rh_sync sync_out source impedance vdd_sync = 5v 2.5 ? source rl_sync 2.5 ? sink vmr1 output 1 voltage margining range 5 % software mode, see table 37. vref1 fb1 voltage reference 0.98 1.0 1.02 v ilea1 error amp leakage 1 2 a gm1 feedback transconductance (siemens) 150 225 350 s 1 typical values at: ta = 25c, vin = 48vdc. typical specificat ions not 100% tested. performance guaranteed by design and/or oth er correlation methods. 2 guaranteed by design. not tested in production.
AS1860 akros silicon, inc. 6399 san ignacio avenue, suite 250, san jose, ca 95119 usa 408.746.9000 ? http://www.akrossilicon.com 14 table 9 - secondary side dc-dc regulators (outputs #2, #3) electrical characteristics symbol parameter min typ 1 max unit conditions vp input voltage at both vp pins 2.97 5.5 v nominally from output #1 vout23_min output voltage - min 0.8 v vout23_max output voltage - max vp-0.7 v ten23_dly external en2/3 power-on delay (cap on the en2/3 pin) 8 2 ms sec_en cap = 10nf (typical) ven23_on en2/3 threshold ? on 0.75 0.82 1.0 v low to high transition ven23h en2/3 hysteresis 100 200 mv fpwm23l low end of pwm2 / pwm3 switching frequency range 500 khz set by external re sistors on pri_div and sec_div pins see table 17. fpwm23h high end of pwm2 / pwm3 switching frequency range 2000 khz set by external resistors on pri_div and sec_div pins see table 17. fosc23 pwm2 / pwm3 clock frequency accuracy -20 +20 % see table 17 for frequency. dmax23 pwm2/3 maximum duty cycle 85 2 % dmin23 pwm2/3 minimum duty cycle 10 2 % iout23 output current 0 2 2 a rms rms output current. rpfet23 p-channel rdson, #2 and #3 outputs 180 2 m ? vp = 5.0v rnfet23 n-channel rdson, #2 and #3 outputs 120 2 m ? vp = 5.0v lxli23 lx2, lx3 leakage current 0.1 1 2 a lxim23 output #2, #3 current limit 3 2 a peak peak output current. vmr23 outputs #2, #3 voltage margining range -8 / +6 % software mode, see table 37 and table 38. vref23 fb2 and fb3 reference voltage 784 800 816 mv ilfb23 fb2 and fb3 leakage current 0.2 2 a il_en23 en2/en3 leakage current 9 10 11 a ioff23 #2 and #3 regulator shutdown current 0.1 1.0 2 a en2, en3 in disabeled mode 1 typical values at: ta = 25c, vin = 48vdc. typical specificat ions not 100% tested. performance guaranteed by design and/or oth er correlation methods. 2 guaranteed by design. not tested in production. table 10 - secondary side dc-dc controller (output #4) electrical characteristics symbol parameter min typ 1 max unit conditions vout4_min_buck buck output voltage ? min 0.8 v vout4_max_buck buck output voltage ? max vp-0.7 v vout4_max_boost boost output voltage - max 30v v ten4_dly external en4 power- on delay (cap on the en4 pin) 8 2 ms sec_en cap = 10nf (typical) ven4_on en4 threshold ? on 0.75 0.82 1.0 v low to high transition
AS1860 akros silicon, inc. 6399 san ignacio avenue, suite 250, san jose, ca 95119 usa 408.746.9000 ? http://www.akrossilicon.com 15 ven4_h en4 hysteresis 100 200 v high to low transition vbuck_en_hi buck_en input voltage threshold - high 2.0 v vbuck_en_low buck_en input voltage threshold - low 0.8 v fpwm4l low end of pwm4 switching frequency range 125 khz 1/4 of internal buck frequency. set by external resistors on pri_div and sec_div pins; see table 17. fpwm4h high end of pwm4 switching frequency range 500 khz fosc4 pwm4 clock frequency accuracy -20 +20 % see table 17 for frequency. rh_hsd4 hsd4 drive impedance 4 ? high side output drive resistance, source rl_hsd4 4 ? high side output drive resistance, sink rh_lsd4 lsd4 drive impedance 4 ? low side output drive resistance, source rl_lsd4 4 ? low side output drive resistance, sink vpk4n peak current sense threshold voltage at max load (isenp4 ? insenn4) 60 mv il max vpk4ss peak current sense threshold voltage at short circuit (isenp4 ? isenn4) 90 mv current limit (typically 50% above il max) dmax4 pwm4 maximum duty cycle 85 2 % dmin4 pwm4 minimum duty cycle 10 2 % illx4 lx4 leakage current 0.1 1 2 a vmr4 output #4 voltage margining range -8 / +6 % software mode, see table 37 and table 38. vref4 fb4 reference voltage 784 800 816 mv ilfb4 fb4 leakage current 0.2 2 a il_en4 en4 leakage current 9 10 11 a gm4 feedback transconductance 50 78 95 s units in siemens. ioff4 #4 controller shutdown current 0.1 1.0 2 a en4 in disable mode 1 typical values at: ta = 25c, vp = 5vdc. typical specificat ions not 100% tested. performance guaranteed by design and/or other correlation methods. 2 guaranteed by design. not tested in production.
AS1860 akros silicon, inc. 6399 san ignacio avenue, suite 250, san jose, ca 95119 usa 408.746.9000 ? http://www.akrossilicon.com 16 table 11 - secondary side digital i/o and i 2 c electrical characteristics symbol parameter min typ 1 max unit conditions vdd3v_osec internally generated 3v source, referenced to sgnd. 3.0 3.3 3.6 v ivdd3v_osec vdd3v_osec current output (internally generated 3v source), referenced to sgnd. 5 ma vdd3v_isec power supply input voltage 3.0 3.3 3.6 v sourced from vdd3v_osec fclk_in external clock input frequency 23.75 25 26.25 mhz vclk_in_hi clk_in input voltage threshold - high 2.0 v vclk_in_low clk_in input voltage threshold - low 0.8 v iointb intb/at_det open drain current drive 1 ma with v pull-up = tbd and r pull-up = tbdk ? , v intb (typ) = tbd iopg pgood open drain current drive 1 ma with v pull-up = tbd and r pull-up = tbdk ? , v pgood (typ) = tbd tpgood pgood minimum pulse output (high-low-high) 10 2 ms twdog watchdog minimum reset pulse width (wdog pin) 100 2 ns vhgpos gpos voltage output ? high (referenced to sgnd) 3.0 v current at gpos = 1.0 ma (vdd3v_isec=3.3v, referenced to sgnd) vlgpos gpos voltage output ? low (referenced to sgnd) 0.4 v current at gpos = -1.0 ma (vdd3v_isec=3.3v, referenced to sgnd) vhgpis gpis voltage input ? high (referenced to sgnd) 2.0 v (referenced to sgnd) vlgpis gpis voltage input ? low (referenced to sgnd) 0.8 v (referenced to sgnd) fscl i 2 c clock frequency 10 400 khz 5v tolerant input vih i2c high level input voltage 1.4 v 5v tolerant input vili2c i2c low level input voltage 0.5 v 5v tolerant input voli2c i2c output low voltage for pull-up voltage (vdd) 0.4 v vdd > 2v, 2 ma sink 0.2vdd v vdd < 2v, 2 ma sink cdio capacitance for each digital i/o pin 10 2 pf 1 typical values at: ta = 25c, vin = 48vdc. typical specificat ions not 100% tested. performance guaranteed by design and/or oth er correlation methods. 2 guaranteed by design. not tested in production.
AS1860 akros silicon, inc. 6399 san ignacio avenue, suite 250, san jose, ca 95119 usa 408.746.9000 ? http://www.akrossilicon.com 17 table 12 - thermal protection electrical characteristics symbol parameter min typ 1 max unit conditions t sd thermal shutdown temperature 140 c above this temperature, the AS1860 is disabled. t i2c thermal warning temperature for i 2 c warning 115 c t hys thermal shutdown hysteresis 40 c temperature change required to restore full operation after thermal shutdown 1 typical values at: ta = 25c, vin = 48vdc. typical specificat ions not 100% tested. performance guaranteed by design and/or othe r correlation methods. table 13 - isolation electrical characteristics symbol parameter min ty p max unit conditions iio_iso input-output insulation 1.0 1 a rh (relative humidity) = 45%, ta = 25c, t = 5s leakage current vio_iso = 2250 vdc viso_dc withstand insulation voltage dc 2120 1 vdc rh 50%, ta = 25c, t = 1 min viso_ac withstand insulation voltage ac 1500 1 v rms rh 50%, ta = 25c, t = 1 min rio_iso resistance (i nput to output) tbd 1 tbd 1 ? vio = 250 vdc cm common mode transient 10.0 2 kv/s 1 device is considered a two terminal dev ice: primary pins are shorted togethe r and secondary pins are shorted together. 2 all outputs to remain within 3% tolerance during transient.
AS1860 akros silicon, inc. 6399 san ignacio avenue, suite 250, san jose, ca 95119 usa 408.746.9000 ? http://www.akrossilicon.com 18 typical performance characterist ics figure 2 - vin=38v 12v 2.5a start up figure 3 - vin=40v_12v_2.5a _start up with el load figure 4 - vin=57v_12v_3a _start up with el load figure 5 - vin=48v_12v_3a _start up with el load figure 6 - vin=48v_12v_3a _start up figure 7 - vin=57v_12v_3a _start up
AS1860 akros silicon, inc. 6399 san ignacio avenue, suite 250, san jose, ca 95119 usa 408.746.9000 ? http://www.akrossilicon.com 19 functional description figure 8 shows the block di agram of the AS1860. the individual blocks are described in greater detail in the following paragraphs. (please also refer to these separate akros documents for the AS1860: an080 for a detailed design guide and an082 for a detailed software users guide.) isolation as shown in figure 8, the AS1860 is divided internally into primary and secondary sides. all signals that interconnect the primary and secondary sides are isolated using akros greenedge ? technology eliminating the need for opto- isolators in both analog power control loop and the digital i2c paths between primary and secondary ground planes . figure 8 - AS1860 block diagram
AS1860 akros silicon, inc. 6399 san ignacio avenue, suite 250, san jose, ca 95119 usa 408.746.9000 ? http://www.akrossilicon.com 20 pd controller figure 9 - AS1860 pd controller block diagram the AS1860 contains a fully integrated pd controller (see figure 9) that meets all syst em requirements for the ieee ? 802.3 standard for ethernet, and, all pd power management requirements for ieee ? standards 802.3af and 802.3at and for the emerging 60/90w standar d. 60w/90w power delivery can be implemented in a number of ways using the AS1860?s flexible architecture. see the power over ethernet overview on page 43 in this datasheet for additional poe information. pd power mosfet ethernet power source current is controlled with an integrated low-leakage, low rdson, nmos power mosfet that is used to connect the 48rtn and 48n ground planes. if necessary the fet is throttled back or switched off to protect the AS1860 from damage due to problematic voltage, current, or temperature related conditions. for power levels greater than the af or at standards, an external power fet is placed in parallel with the internal fet. gate control of this external fet is detailed in t he 60/90w applications section. under-voltage lockout (uvlo) the uvlo circuitry detects low power source voltage conditions and disconnects t he power mosfet to protect the pd (see full power voltage activation and deactivation threshold specifications in the pd electrical characteristics). poe current limit/current sense current limit/current sense circuitry minimizes on-device temperature peaks by limiting both inrush current and operating current. it monitors the current via an integrated sense circuit that regulates the gate voltage to the pd power mosfet. this inrush current limiting maintains the cable voltage above the turn-off threshold as the input capacitor charges, an action that aids in preventing the pse from going into current limit mode. the poe current limit is set by the clim input pin during poe operating modes. when clim is set low (48rtn) current is limited to 350ma (min); when high, 720ma (min). if the maximum primary current is exce eded, control of the internal pd power mosfet is used to protect the system from overload. in local power mode (ldet active), this clim based current control is not used (primary side external fet sensed current control can always be used). over-temperature protection if die temperature exceeds 140c (typ) the AS1860 is shut down. power is automatically reapplied when the die temperature returns to 100c (typ). pd operating states the AS1860 has five states of pd operation: ? reset - the classification state machine is reset, and all circuitry blocks are disabled. ? signature detection - the pd signature resistance is applied across the input. ? classification - the AS1860 indicates power requirements to the pse. ? idle - this state is entered after classification, where it remains until full-power input voltage is applied. ? on - the pd is enabled, and supplies power to the dc-dc controller and the local application circuitry. in this state the pd also provides a maintain power signature (mps) state as required by the ieee ? poe standard.
AS1860 akros silicon, inc. 6399 san ignacio avenue, suite 250, san jose, ca 95119 usa 408.746.9000 ? http://www.akrossilicon.com 21 as the supply voltage from the pse increases from 0v, the AS1860 transitions through these operating states: these five operating states have specific transition criteria per the ieee ? poe standard. pd reset state when the voltage supplied to the AS1860 drops below vreset_min, the device enters the reset state. in reset state, the AS1860 consumes ve ry little power, the power supply to the pd is disconnec ted and state condition reverts to pre-classification. pd signature detection state during signature detection, th e pse applies a volt age to read the pd power signature and va lidates the pd as standards compliant. to ascertain the power signature the pse applies two voltages in the signature voltage range and extracts a signature resistance value from the i-v slope. the AS1860 signature resistance is specified by an external resistor connected between the rsig pin and the 48vin pin. a 26.7k ? external signature resistor is recommended. upon successful detection of the pd by a pse the AS1860 disconnects the external signature resistor at the rsig pin to conserve power. pd classification state each class represents a power allocation level for the pd and allows the pse to manage power requirements between multiple pds. the AS1860 supports both ieee ? std. 802.3af, and two event classification per ieee ? std. 802.3at (poe+), see figure 29. the AS1860 allows the user to set required classification current via an external resistor connected between the rclass pin and 48rtn (paddle #1). see table 14 for recommended rclass resistor values. during the classification st ate the pse pres ents a voltage between 14.5v and 20.5v which the AS1860 terminates in the rclass resistor resulting in a pse measurable current, iclass. table 14 - classification map class power (watts) iclass rclass 0 0.44-12.95 0 - 4 ma 2.05m ? , 1% 1 0.44-3.84 9 - 12 ma 221k ? , 1% 2 3.84-6.49 17 - 20 ma 115k ? , 1% 3 6.49-12.95 26 - 30 ma 75k ? , 1% 4 12.96-25.5 36 - 44 ma 49.9k ? , 1% upon successful classificati on of the pd by a pse the AS1860 disconnects the external classification resistor at the rclass pin. pd idle state in the idle state (between classification and the on state) the AS1860 current is limited to monitoring circuitry needed for detection of the on state threshold. pd on state at a voltage of 42v or higher t he AS1860 enters the on state and full power is available via the dc-dc controller. in ieee ? poe compliant systems the pse remotely detects either a dc or ac maintain po wer signature (mps) state in the pd platform. if either the pd poe dc current is less than 10ma or the pd input ac impedance is above 26.25k ? the pse may disconnect power. to guarantee such a power disconnect the pd poe dc current must be <5ma, and, the ac impedance must be >2m ? . at detection operation the AS1860 has both software (i 2 c register bit) and hardware (at_det pin) capabilities to indicate a poe plus platform operating mode. the at_det detect feat ure (either pin or software) provides an indication when a poe+ power source is available to the system, from either an ethernet cable to a type 2 pse or via use of local power supply using the ldet input pin. in the case of hardware mode the at_det pin can be used to directly drive an led indicator. since this pin is on the secondary side of the AS1860 the user can interface it directly to the pd system controller without additional interfacing isolation circuitry. a typical platform usage of at_det is to self-configure the pd platform based on available power. if not operating on local power, the at_det indicator stays low during the pd reset, detection and classification phases. this indicator will be set high once the pd recognizes completion of the 2-event physical layer classification as initiated by a type 2 pse. the pin will remain high and be reset to zero after the occurrence of a pd reset state (48vin < 2.7v) or a power-down event. at_det remains low if the pse partner is identified to be type 1 during the classification phase. local power source as mentioned above the AS1860 may also be powered from a dc source other than the ethernet line. this local source is detected when the voltage at the ldet pin is 2 volts (typ) below the voltage at pin 48vin. when such a local power is present the AS1860 will disable the power fet and thereby disconnect from the poe power source. when operating in local power mode the at_det pin does not indicate the far end pse, and is always high (see table 15).
AS1860 akros silicon, inc. 6399 san ignacio avenue, suite 250, san jose, ca 95119 usa 408.746.9000 ? http://www.akrossilicon.com 22 refer to figure 9 and table 16 for typical ldet external resistor designs to match the specified local power configuration. table 15 - at_det and ldet operation ldet mode at_det indication pse = type 1 pse = type 2 ldet = inactive (poe power usage) low high ldet = active (local power usage) high high table 16 - typical ldet external resistor design local adaptor or local voltage requirement typical ldet voltage range to cover adaptor(s) r1 1 ( ? ) r2 1 ( ? ) 12v, 18v 10.8-22 vdc 47k 15.6k 18v, 24v, 30v 14-32 vdc 47k 10k 30v, 36v, 48v 26-57 vdc 47k 5k 1 note: see figure 3 on 23. the maximum voltage allowed from 48vin to ldet is 6.0v; refer to table 3 on 7. therefore some ldet input range requirements (beyond those shown in table 16) might require the use of a zener, 5.1v typical, as shown in figure 3 on 23. pwm clock generation figure 10 shows the AS1860 pwm clock generation block diagram. during power-up, local oscillators on both sides of the isolation b oundary provide separate clocks for primary- side and secondary-side pwms. after power-up internal cross-isolation management aut omatically transitions all AS1860 pwm clocks such that t he secondary-side oscillator becomes the master, and source s multi-phase clocks to both primary and secondary pwms. pwm clock frequency configuration frequencies of all AS1860 pwm clocks are set with resistors connected to the pri_div and sec_div pins as shown in table 17. external clock source (clk_in) for additional emi management, the clk_in pin provides an optional input for an external clock source to govern overall device timing. if used the local secondary-side oscillator is slaved to clk_in, therefore primary-side and secondary- side pwm clocks are slaved to clk_in after power-up. the clk_in frequency should be 25mhz, and it is recommended that the ethernet phy clock be used . emi performance control a multi-phase clocking technique is used to generate clocks for the primary dc-dc controller and all outputs (1-4). this improves electromagnetic (em) radiation performance by reducing common mode noise and also reduces the size of external capacitors. note that in software mode, pbrs randomization and fractional-n modulation clocking is available for additional em performance to reduce pwm clock induced harmonics in the power supply. figure 10 - pwm clock generation block diagram
AS1860 akros silicon, inc. 6399 san ignacio avenue, suite 250, san jose, ca 95119 usa 408.746.9000 ? http://www.akrossilicon.com 23 table 17 - pwm clock rate configuration power output #1 output #1 is the main AS1860 power output and is typically used to supply the dc power t hat generates outputs #2 thru #4. as described in the previ ous section, the primary and secondary-side pwm cl ocks are generated and automatically synchronized ac ross the integrated isolation barrier. figure 11 shows a typical synchronous fly back design topology for output #1. three power control loop operations take place: ? primary-side dc-dc controll er fet driver switches the primary-side power fet from a loop error controlled pwm. ? secondary-side sync controller fet driver switches the secondary-side power fet to complete the flyback power transfer cycle. ? the automated AS1860 isolation management transmits secondary-side loop feedback to the primary-side pwm. a typical isolated synchronous flyback application is shown in more detail in figure 36. figure 11 - power output #1 block diagram primary-side dc-dc controller the primary-side dc-dc controller is a current-mode dc- dc controller which is easily configured with a minimal set of external components. isolation is provided by the internal akros greenedge ? circuitry which eliminates the need for external opto-isolators. in poe operation, the primar y-side dc-dc controller operates from a pd power mosfet switched power input (48n, see figure 2) and includes: an externally controlled soft start; a fixed (after resistor programming) frequency pwm; and a true voltage output error amplifier. in local AS1860 master clock rate = internal (or 25mhz if using clk_in) pri_div resistor ( ? ) 12.4k 43.2k 68.1k 100.0k sec_div resistor ( ? ) outputs #2/#3/#4 pwm clock rates (mhz) output #1 pwm clock rate (khz) 12.4k 2.08 / 2.08 / 0.520 reserved 521 417 347 43.2k 1.04 / 1.04 / 0.260 347 260 208 174 68.1k 0.69 / 0.69 / 0.173 231 174 139 116 100.0k 0.52 / 0.52 / 0.130 174 130 104 reserved
AS1860 akros silicon, inc. 6399 san ignacio avenue, suite 250, san jose, ca 95119 usa 408.746.9000 ? http://www.akrossilicon.com 24 power operation 48n is sourced directly. soft-start inrush current limit internal circuitry automatically controls the inrush current ramp by limiting the maximum current allowed in the transformer primary at startup. the amount of time required to perform this soft-start cycle is determined by a capacitor on the css pin. a css capac itor of 330nf provides approximately 7ms of soft startup ramp time. current-limit and current sense the primary side controller provides cycle-by-cycle current limiting to ensure the transformer primary current limits are not exceeded through use of an external resistor on isensep. in addition, the ma ximum average current in the transformer primary is set by in ternal pwm duty cycle limits. a short-circuit event is declared by the primary controller if this isensep sensed current limit is triggered on more than 50% of the clock cycles within any 64 cycle window. once a short-circuit event has been declar ed, output #1 will shut off for 1024 cycles before a restart is attempted. this process will repeat indefinitely until the output short is removed. secondary-side sync controller the efficiency of output #1 can be optimized by designing a non-overlapping solution for the external fets on the primary side and secondary side of the pd power transformer. the fet sync and overlap delays, as shown in figure 5, are controlled by the designer to compensate for rise, fall, and delay times for both primary and secondary- side external power fets. see table 18 and note the delay timing limit: (tsync + tovl) ? 25ns. the required resistors at sync_dly and sync_ovl to implement the desired tsync and tovl timing are then calculated; see an example in t able 19. the filt er capacitors to sgnd for these pins (see figure 5) are 1nf, typical. table 18 - sync & overlap delay timing limit sync delay (ns) overlap delay (ns) delay timing limit (ns) tsync tovl ( tsync + tovl ) ? table 19 - sync_dly & sync_ovl resistor calculation example desired sync delay (ns) desired overlap delay (ns) delay timing limit check (ns) sync_dly resistor required ( ? ) sync_ovl resistor required ( ? ) tsync tovl ( tsync + tovl ) ? 25ns r sync_dly = ( tsync + tovl ) x 2k ? r sync_ovl = tovl x 2k ? 10ns 15ns ok 50k ? 30k ? compensation and loop feedback the primary output (output #1) has two power compensation and feedback mechanisms: ? adaptive slope compensation ? primary-secondary (feedback based) control loop the adaptive slope compensation automatically provides an optimized ramp framework for t he overall loop performance, there are no user settings required. for the primary-secondary cont rol loop the device uses an internal transconductance error amplifier with external compensation control. an external secondary-side rc compensation network should be connecting to comp1. the resulting loop feedback path through the internal isolation channel to the prim ary-side pwm is automatic and completely user transparent. voltage feedback input is provided at the fb1 pin. at fb1, an internal reference of 1v (nominal) is compared to a resistor divided voltage from output #1. this sets the desired output #1 voltage level. with the top re sistor in the feedback divider designated r2 and the bottom resistor designated r1 (again refer to figure 5) the progra mmed voltage for output #1 is equal to vref times (r1+r2)/r1. so, for example, with r1=5k, r2=20k, and vref=1v, t he output voltage is set to 5v. low-load current operation - dcm the primary output (#1) uses both dcm and pulse skipping (burst mode) design techniques to optimize power efficiency. when a low-load output power condition is detected, the controller automatically enters a discontinuous current mode (dcm) of operation. over-voltage protection output #1 has a built-in over-voltage monitor set to +10% of nominal voltage. if tripped, the output shuts down until within +5% of the nominal voltage at which point normal operation is then resumed. if voltage margining is used (see software mode operation on 38) the over-voltage protection tracks to the margining selected. power outputs #2 and #3 secondary-side outputs #2 and #3 (see figure 12) are identical synchronous current mode pwm dc-dc buck regulators with: ? integrated pmos and nmos power fets ? independent low-noise remote ground sensing (agnd2, agnd3) ? output drivers (lx2, lx3) ? feedback voltage controls (fb2, fb3)
AS1860 akros silicon, inc. 6399 san ignacio avenue, suite 250, san jose, ca 95119 usa 408.746.9000 ? http://www.akrossilicon.com 25 ? output power enable/sequencing (en2, en3) figure 12 - power outputs #2, #3 block diagram under normal operation the r egulator uses the pwm to generate driver signals for internal high-side and low-side mosfets. to produce thes e pwm loop controlled outputs an error signal from the voltage-error amplifier is compared with a ramp signal generated by an oscillator in the pwm. a high-side switch is turned on at the beginning of the oscillator cycle and turns off when the ramp voltage exceeds the internally generated referenc e signal or the current-limit threshold is exceeded. a low-side switch is then turned on for the remainder of the oscillator cycle. loop feedback and compensation voltage feedback is provided at the fbx (fb2 / fb3) pins. at fbx an internal reference of 800mv (nominal) is compared to a resistor divided voltage from the output (#2/#3). this sets the desired output voltage level, which is equal to vref times (r1+r2)/r1. maximum voltage output level is constrained by the input level of vp: vout23 (ma x) = vp ? 0.7v (typ). loop compensation is integr ated for outputs #2 and #3. current-limit and current sense each regulator provides cycle-by-cycle current limiting to ensure that the maximum curr ent limits are not exceeded. for each pwm cycle during which the maximum current limit is tripped, a short-circuit counter is incremented. this counter is reset to zero if and only if two consecutive pwm cycles do not contain current limit events. if the counter reaches 16 a short-circuit event is declared and both output #2 and output #3 supplies are powered down. after 256 cycles of wait time both outputs will attempt restarts . if the short-circuit persists the counter will begin to increment and the cycle will repeat itself. note that the internal regulators for output #2 and output #3 are coupled together such that if one declares a short-circuit event they both reset regardless of the short-circuit counter status of the other. over-voltage protection outputs #2/#3 each have built-in over-voltage monitors set to +10% of nominal voltage. if tri pped the output is shut down until within +5% of nominal volt age, normal operation is then resumed. if voltage margining is used (see software mode operation on 38) the over-voltage prot ection tracks to the margining selected. power output #4 secondary-side output #4 is a synchronous current mode pwm dc-dc controller that drives external nmos power fets and supports buck or boost topologies. boost or buck operation is selected by the buck_en pin. key features: ? independent low-noise remote sensing ground (agnd4) ? current sense inputs (isenp4, isenn4) ? high side and low side nmos fet drivers (hsd4, lsd4) ? dc-dc switch sense and remote sense (lx4, lx4_sense) ? feedback voltage control (fb4) ? error amplifier compensation input (comp4) ? output power enable/sequencing input (en4) ? pwm dimmable led driver in boost mode for typical buck operation (figur e 13) the controller uses the pwm and generates driver signals for both high-side and low-side mosfets. to produce these pwm loop controlled outputs an error signal from t he voltage-error amplifier is compared with a ramp signal generated by an oscillator in the pwm. the external high-side switch is turned on at the beginning of the oscillator cycle and turns off when the ramp voltage exceeds the internally generated reference signal or the current-limit threshold is exceeded. the external low-side switch is then turned on for t he remainder of the oscillator cycle. for typical boost operation (see figure 14) the controller uses the pwm and generates only a low-side driver signal for a single external mosfet. to produce this pwm loop controlled output an error signal from the voltage-error amplifier is compared with the ramp signal generated by an oscillator in the pwm. the internal low-side switch is turned on at the beginning of the oscillator cycle and turns off when the ramp voltage exceeds the internally generated reference signal or the current-limit threshold is exceeded. the diode conducts for the remainder of the oscillator cycle.
AS1860 akros silicon, inc. 6399 san ignacio avenue, suite 250, san jose, ca 95119 usa 408.746.9000 ? http://www.akrossilicon.com 26 figure 13 - power output #4 block diagram - buck figure 14 - power output #4 block diagram - boost extending the boost mode to a pwm dimmable led driver (figure 15) requires only the addition of external circuitry to hold the comp4 and fb4 signal levels when the external pwm dim controller switches to dim (control on). the figure shows a low cost bipolar transistor solution, with an additional diode and resistor on fb4 to protect it from led string voltage during dimming. compensation and loop feedback as shown in figure 13 and figure 14 voltage feedback is provided at the fb4 pin in both buck and boost modes. at fb4 an internal reference of 800mv (nominal) is compared to a resistor divided voltage from output #4 to control the voltage level. with the top re sistor in the feedback divider designated r2 and the bottom resistor designated r1 the programmed voltage for output #4 is equal to vref times (r1+r2)/r1. so, in boost mode operation, with r1=100, r2=1.43k, and vref=0.8v, the output voltage is set to 12v. in the led driver boost a pplication, figure 15, the r fb resistor is used to keep a cons tant led string current rather than a constant output voltage as was the case in the other (two resistor divider) control feedback loops described above. the other resistor in the feedback loop path now is connected directly to fb4 for enhanced pin protection from the led string voltage during dimming. the diode to output #1 is also for fb4 pin protection. figure 15 - power output #4 block diagram - boost led driver the comp4 pin is connected to an external rc loop compensation network allowing design flexibility to optimize the system performance while insuring loop stability. in the led driver boost application, again figure 9, the compensation is held constant during dimming (control on) by the external transistor, and resumes compensation after pwm dimming control is removed (control off). please refer to the AS1860 design guide, an080, for details).
AS1860 akros silicon, inc. 6399 san ignacio avenue, suite 250, san jose, ca 95119 usa 408.746.9000 ? http://www.akrossilicon.com 27 current-limit and current sense the controller provides cycle- by-cycle current limiting to ensure that current limits are not exceeded, using an external resistor sensed at isenp4 and isenn4. for each pwm cycle during which the maximum isenp4-to- isenn4 sensed current limit volt age is tripped, a short-circuit counter is incremented. this count er is reset to zero if and only if two consecutive pwm cycles do not contain current limit events. if the counter reac hes 16 a short-circuit event is declared and output #4 is powered down. after 256 clock cycles of wait time output #4 will attempt a restart, if the short-circuit persists the counter will begin to increment and the cycle will repeat itself. over-voltage protection output #4 has a built-in over-voltage monitor set to +10% of nominal voltage. if tripped the output is shut down until within +5% of nominal voltage, normal operation is then resumed. if voltage margining is used (see software mode operation) the over-voltage protection tr acks to the margining selected. hardware mode operation the hardware mode of operation is designed to provide basic control and status of the device via hardware (pin) control signals. hardware mode functions and operation are described below. (please also refer to the akros document an080 for a detailed design guide.) device initialization & hardware mode selection primary-side digital logic is initialized while the mode pin is low, a required external capacitor between mode and 48n provides the power-on reset input required to initialize the device. hardware (hw) mode is selected when the mode pin is also pulled-up high (in addition to the power-on reset capacitor to 48n). the vdd3v_out pin can be used for the mode pin pull-up power source by using a 17.8k ? (maximum) resistor from mode to vdd3v_out. secondary-side digital logic is initialized while the sec_en pin is low, a required external capacitor between sec_en and sgnd will provide the power-on reset input required to initialize the secondary-side. hw mode power output controls power outputs #2 thru #4 each have independent output enable pins (en2, en3, and en4) that enable the corresponding power output, and, can also be used to delay the power outputs relative to each other. note that output #1, the main device power output, is always enabled and does not have an output enable pin. the enx pins have internal pull-ups, so outputs are enabled when an enx pin is simply connected to an external timing capacitor (c enx ), see figure 16. as shown in figure 17, a low voltage (ground) on an enx pin disables the corresponding power output. in addition, if an output is not used the associated fbx pin should in fact be pulled high to prevent a disabled output from affecting pgood status. figure 16 - hw mode output(s) hardware enabled figure 17 - hw mode output(s) hardware disabled hw mode power output sequencing connecting a grounded external capacitor to an enx pin establishes a delay before the corresponding power output is turned on. each power output delay capacitor can be selected to create a user defined power-on sequence. the time delay (t enx ) in seconds for a capacitor (c enx ) is defined by the formula: a 10 8 . 0 ? enx enx c t ? (must be > 8ms) for example, a 200nf cap creates an output delay of 16ms. each enx pin has an internal 0.8v threshold detector and sources 10a. when the enx pin reaches 0.8v, enable delay timing begins. each enx delay must be greater than 8ms for proper device startup assuming a typical 10nf capacitor on sec_en. all delays for power outputs #2-#4 are synchronized to the beginning of the output #1 voltage ramp (see figure 18).
AS1860 akros silicon, inc. 6399 san ignacio avenue, suite 250, san jose, ca 95119 usa 408.746.9000 ? http://www.akrossilicon.com 28 figure 18 - hw mode power output sequencing example hw mode power monitoring (pgood) all outputs (1-4) are monito red for power good status if enabled (2-4 can be disabled). once a supply output reaches a stable state, its internal power good status signal is asserted. an output?s power goo d is declared (good) at +/- 5% and at fault (bad) at +/- 10% of final voltage value. in either transition case (go od to/from bad), continuous operation of 10s is require d before the state change is declared. the user sees the resulting status on the pgood pin (10ms minimum pulse). in hardware mode, the pgood pin is the logical and of all enabled power outputs and any watchdog timeout events (if enabled) as shown in figure 19. figure 19 - hardware mode pgood generation if any of power outputs (2-4) are not required, the unused output(s) should be permanently disabled using the enx and fbx pins as described in hw mode power output controls on 34. permanently disabli ng an unused output is required to assure correct pgood signal ?anding?. hw mode watchdog timer watchdog ? configuration ???????????????????? ??????????????????? the watchdog timer is configured by the wd_mode pin as follows: ? when the wd_mode pin is set high the watchdog timer is set for a 32 second timeout period. ? when the wd_mode pin is floating the watchdog timer is set for a 1 second timeout period. decoupling the pin to 48n is also required. ? when the wd_mode pin is set low the watchdog timer function is disabled. watchdog ? service ??????????????????????????????? ?????????????????? the watchdog timer is serviced by pulsing the wdog pin for at least 100ns (here a pulse is defined as a continuous level of either polarity after the 1st edge). correct platform usage is to service before the watchdog timeout period expires. watchdog ? timeout ????????????????????????????? ??????????????????? if the watchdog times out, the following occur: ? the pgood pin is pulsed low for 10ms (min). if coincident with any volt age fault events the pgood output pulse could be longer. this pulse can be used for pd platform level alarm or reset. ? operation of the watchdog timer is automatically initialized and restarted. hw mode general-purpose i/o operation in hardware mode, the gpio pins provide a means for controlling and monitoring isolated primary-side signals from the secondary-side of the AS1860. the secondary-side gpos and gpis pins map to the primary-side pins gpip and gpop as shown in figure 20. figure 20 - hardware mode gpio pin mapping software mode operation software mode operation allows a host controller to access the AS1860 internal registers via an i 2 c interface. access to these registers provides ex tensive status and control functions. software mode functions and operation details are described below. (please also refer to akros document an082 for a detailed software users guide.) device initialization and software mode selection primary-side digital logic is initialized while the mode pin is low, a required external capacitor between mode and 48n provides the power-on reset input required to initialize the device. software (sw) mode is selected when the mode pin uses just this initialization capacitor. secondary-side digital logic is initialized while the s ec_en
AS1860 akros silicon, inc. 6399 san ignacio avenue, suite 250, san jose, ca 95119 usa 408.746.9000 ? http://www.akrossilicon.com 29 pin is low, a required external capacitor between sec_en and sgnd will provide the power-on reset required to initialize the secondary-side. sw mode power output controls once enabled in hardware, power outputs (2-4) can be independently enabled or disabled in both hardware (via pin control) and software (via i2c register). each output has an independent enable pin (en2, en3, en4) for hardware enabling, and, can also be used to delay one voltage output relative to other. note that output #1, the main device power output, is always enabled and does not have an output enable pin or software control mode. any power output (2-4) to be software controlled must first have been enabled in hardware. the enx pins have internal pull-ups so outputs are power-on enabled when the enx pins float. see figure 21. as shown in figure 22, a low voltage (ground) on an enx pin disables the corresponding power output; any hardware- disabled output will not be controllable in software. note that if an output is not used, the associated fbx pin should in fact be pulled high, which prevents a disabled output from affecting pgood status. figure 21 - sw mode output(s) hardware enabled figure 22 - sw mode output(s) hardware disabled sw mode power output sequencing connecting a grounded external capacitor to an enx pin establishes a delay before the corresponding power output is turned on. each power output delay capacitor can be selected to create a user defined power-on sequence. the time delay (t enx ) in seconds for a capacitor (c enx ) is defined by the formula: a 10 8 . 0 ? enx enx c t ? (must be > 8ms) for example, a 200nf cap creates an output delay of 16ms. each enx pin has an internal 0.8v threshold detector and sources 10a. when the enx pin reaches 0.8v, enable delay timing begins. each enx delay must be greater than 8ms for proper device startup assuming a typical 10nf capacitor on sec_en. all delays for power outputs (2-4) are synchronized to the beginning of the output #1 voltage ramp (see figure 23). sw mode power status monitoring (pgood) each power output (1-4) is monitored for power good status. once a supply output reaches a stable state its internal power good status signal is asserted. an output?s power status is declared good at +/- 5% and at fault (bad) at +/- 10% of final voltage value. in either transition case (good to/from bad) a continuous oper ation of 10s is required before state change is declared. figure 23 - sw mode power output sequencing example as shown in figure 24, once all enabled outputs are good the user will see the resulting de vice power status on both the pgood pin and the global pgood bit of register 00h. power good status for each supply is available in the alarms and power status register (00h). operation of the pgood pin is defined by register 03h as shown in table 26. register 03h allows the user to exclude any individual output?s power good status from affecting the pgood pin by clearing the associated output?s mask bit. if the default values in register 03h are used, pgood is the logical and of all four power status outputs. as shown in
AS1860 akros silicon, inc. 6399 san ignacio avenue, suite 250, san jose, ca 95119 usa 408.746.9000 ? http://www.akrossilicon.com 30 figure 18, a fault on any of the supplies will drive the pgood pin low (10ms minimum). in addition, the watchdog timer status can be included / excluded in the pgood pin logic. register 04h, bit 2 allows the user to either mask or allow a watchdog timeout to generate a pgood pulse. the pgood pin can be used as part of a board reset logic chain as it is asserted (high) only when all the enabled power outputs are stable. if any of power outputs (2-4) are not required, the unused output(s) should be permanently disabled using enx and fbx pins as described in sw mode power output controls on 36. permanently disabling an output will override any register control associated with a disabled output. power voltage monitoring will not restart any of the supplies. a pgood fault will restore all registers except the history register (reg 05h) to default st ate unless bit 4 in the device control register (reg 06h) is set. figure 24 - software mode pgood generation output #1 good output #4 good output #3 good output #2 good watchdog timer pgood hw enable (wd_mode) sw enable (register bit) hw enable (en & fb) sw enable (register bit) hw enable (en & fb) sw enable (register bit) hw enable (en & fb) sw enable (register bit) sw enable (register bit) history ? register ?????????????????????? ??????????????? ???????????????? the pgood & watchdog history register (05h) is used to identify the source of a pgood fault. one bit is provided for each power output (1-4) and one for the watchdog timer. in the event of a pgood fault, t he bit corresponding to the particular power output that caused the pgood fault is set. similarly, in the event of a watchdog timeout the watchdog timeout bit is set. once set these bits are latched, they will not change even after the pgood fault is reso lved unless there is a user command to do so. therefore the user must clear this register as desired. the pgood & watchdog history register is described in table 28. pd voltage and current measurements the AS1860 contains an a/d conv erter that measures pd input current to 5-bit accuracy and pd voltage to 8-bit accuracy. the a/d converter measurements are updated automatically at a 100hz (minimum) rate, and may be accessed at any valid i2c clock rate. a/d values are available in the pd voltage (0bh) and pd current (0ch) registers (see table 34 and table 35). current measurement is valid only for poe pd operation and not during local power operation. however, voltage measurement is valid for both poe and local power operation. pd over-current alarm threshold register 0dh (see table 36) allows the user to specify a maximum pd current value that when exceeded sets the pd over-current alarm bit in register 00h. sw mode power margining each of the four voltage ou tputs can be independently margined. output #1 has a margining range of -5% to +5% while outputs (2-4) can be independently margined from -8% to +6%. these are configured via the margin control registers 0eh and 0fh. this feature allows engineering and/or manufacturing testing where, for example, it is useful to make test adjustments to compensate for pc board trace ir drops. see table 37 and table 38 for details. if voltage margining is used, the AS1860 over-voltage protection tracks to the margining selected for any output. sw mode emi performance control in software mode the AS1860 provides two additional methods to generate pwm clo cks for optimum em radiation performance: prbs randomization and fractional-n. pwm ? clocks ?\? prbs ? randomization ?????????????????? this technique enables a randomized prbs sequence to modulate the clocks thus spreading the noise across the band and reducing the peaks. prbs randomization is selected via register 0ah as shown in table 33. pwm ? clocks ?\? fractional \ n ??????????????????????????????????? pwm clocks and harmonics can be a major source power supply emi. fractional-n clocking provides an ?fm like? modulation on the pwm clocks that spreads out the spectral energy thereby reducing peaks in emi tested frequency bands. one of three modulation rates can be selected via register 0ah as shown in table 33. sw mode general-purpose i/o & adc as shown in figure 25, the gpop, gpip, and adcin pins provide a means for controlling and monitoring isolated primary-side signals from the seco ndary side of the AS1860. gpio and a/d functions are updated automatically at a
AS1860 akros silicon, inc. 6399 san ignacio avenue, suite 250, san jose, ca 95119 usa 408.746.9000 ? http://www.akrossilicon.com 31 100hz (minimum) rate, and may be accessed at any valid i2c clock rate. ? general \ purpose ? i/o ? pins the gpop bit in the device c ontrol register (06h) specifies the state of the gpop output pin. the state of gpip input pin is reflected in gpip bit lo cated in the same register. maximum measurement latency is defined in table 6. general \ purpose ? adc ? (adcin ? pin) ????????????????????? the primary-side adcin pin is an input to an internal a/d converter with a continuous sample/conversion rate. the a/d process is automatic and therefore requires no user action to initiate. this internal 8-bit a/d sub-system contains a successive approximation a/d, track/hold circuitry, internal voltage reference, and conversion clocking. reading the converted value is done in the a/d voltage register (08h). maximum measurement latency is found in table 6. in addition, the a/d alarm thresh old register (09h) allows the user to specify a maximum a/d value that when exceeded automatically sets the a/d ov er-threshold alarm bit in register 00h. figure 25 - gpio and adc pin mapping sw mode watchdog timer operation the watchdog timer is serviced using either the wdog pin or the watchdog service control bit in register 04h. correct platform usage is to service before the watchdog timeout occurs. if a watchdog timeou t occurs, the pgood pin can generate an output pulse (10ms minimum) that may be used for pd platform level alarm or reset. in additi on, an interrupt can be generated and the stat us can be interrogated by querying the interrupt status regi ster (02h) which has a bit to indicate watchdog timeout. watchdog ? timer ? modes ?????????????????????? ?????????????????? in software mode (mode pin floating with cap to 48n), the wd_mode pin selects one of three watchdog timer operating modes as follows: watchdog timer function disabled when the wd_mode pin is set low, the watchdog timer function is disabled. watchdog timer enabled at startup when the wd_mode pin is connected to an external capacitor (to 48n), the watch dog timer function is enabled at startup. at startup the watchd og timeout counter defaults to the maximum period of 32 seconds. the timeout period may be changed via the watchdog timeout register (07h) as described below. watchdog timer disabled at startup setting the wd_mode pin high disables the watchdog timer function at startup and can only be enabled through software. at startup the watchdog tim eout counter defaults to the maximum period of 32 seconds. once the watchdog is enabled the timeout period may be changed via the watchdog timeout register (07h) as described below. watchdog timer operation watchdog enable enabling of the watchdog function in software must be done with two consecutive writes as follows: 1. the first write is to the watchdog register (04h) bit ?enable watchdog?, plus any other watchdog bit masks (for interrupts, pgood , and register reset functionality). 2. the next write must be to register 00h with the value bbh with no other intervening read or write operation to the AS1860. the time between the two writes can be infinite, but the operation wi ll not be enabled until the second write. if a write/read occurs to any other register or if a write occurs but the value is not bbh, the enable watchdog bit is cleared. note that once enabled, watchdo g operation cannot be disabled. watchdog service to service the watchdog via software, the user must issue two consecutive writes as follows: 1. the first write is to the watchdog register (04h) bit ?watchdog service control?. 2. the next write must be to register 00h with value aah with no other intervening read or write operation to the AS1860. the time between the two writes can vary; however, the second write must be completed before a watchdog timeout occurs. if the watchdog times out before the second write or the second write is not to the 00h register or the data val ue is not ?aah?, then the service request to the watchdog timer is cancelled. to service the watchdog via hardware (a valid operation in software mode) the wdog pin must be pulsed for at least 100ns (continuous pulse of eit her polarity after the 1st edge).
AS1860 akros silicon, inc. 6399 san ignacio avenue, suite 250, san jose, ca 95119 usa 408.746.9000 ? http://www.akrossilicon.com 32 correct platform usage is to service before the watchdog timeout period expires. watchdog timeout period at startup the watchdog tim eout counter defaults to the maximum period of 32 seconds. the current user programmed value in the watchdo g timeout register (07h) is always used for watchdog timeouts. a value of ffh in this register gives the maximum timeout of 32 seconds. a value 01h sets the minimum period of 125ms. note that 00h is reserved and is not to be used. intervening values are multiples of 125ms (e.g. a value of 04h = 500ms). watchdog timeout if the watchdog times out, the following occur: ? the watchdog timeout bit in t he history register (05h) is set. ? if the watchdog interrupt mask bit is set (register 04h) and interrupts are enabled, the watchdog timeout bit in the interrupt status register (02h) is set and the intb pin is driven low. ? if the watchdog pgood mask bit is set (register 04h), a 10ms (min.) low pulse is out put at the pgood pin. if coincident with other volt age fault events the pgood output pulse could be extended. ? if the watchdog register reset mask bit is not set (register 04h), the AS1860 registers are reset. this resets the watchdog timeout register value to 32 seconds. (note that an inde pendent pgood fault will also reset the registers unless bit 4 in device control register, reg 06h, is set). ? if the watchdog register reset mask bit is set (register 04h), operation of the watchdo g timer is automatically initialized, with the currently programmed value, and restarted. sw mode interrupt operation interrupts are disabled after a device power on. the device control register (06h) is used to enable (or disable) interrupts at a global device level. the interrupt mask (01h) and inte rrupt status (02h) registers are used to enable alarms and service any resulting alarms. ? interrupt ? masking positive masking is used; therefore a ?1? indicates that the specified fault or alarm will cause an interrupt. interrupts (except for watchdog timeout) are level-driven, thus if a fault condition is active upon enabling it will immediately generate an interrupt. interrupt ? status a read from the interrupt stat us register will return the conditions which have caused an interrupt, and will immediately clear all such pending interrupts. note that interrupts (except for watchdog timeout) are level driven, so if a fault condition still exists upon interrupts being cleared an interrupt will be re-asserted after a minimum off time of 10s. i 2 c interface the AS1860 provides a standard i 2 c compatible slave interface that allows a host controller (master) to access its single-byte registers. note the requirement of ?repeated start? for i 2 c reads. the primary-side gpio pin read/write or adcin pin conversion read/write have a 10ms (maximum) pin-to/from- register timing. the AS1860 registers are summarized in table 22 and described in table 23 through table 38. the i 2 c interface is active when the AS1860 is in software mode. there are four pins associated with the i 2 c interface: ? sdio: bi-directional serial data ? scl: clock input ? intb: interrupt output ? i2c_adr: device address configuration start/stop timing the master device initiates and terminates all i 2 c interface operations by asserting start and stop conditions respectively. as shown in figure 20, a start condition is specified when the sdio line transitions from high-to-low while the clock (scl) is high. a stop condition is specified when sdio transitions from low-to-high while scl is high. data timing as shown in figure 26, data on the sdio line may change only when scl is low and must remain stable during the high period of scl. all address and data words are serially transmitted as 8-bit words with the msb sent first. acknowledge (ack) ack and nack are generated by the addressed device that receives data on sdio. after eac h byte is transmitted, the receiving interface sends back an ack to indicate the byte was received. as shown in figure 27, to generate an ack, the transmitter first releases the sdio line (high) during the low period of the ack clock cycle. the receiver then pulls the sdio line low during the high period of the clock cycle. a nack occurs when the receiver does not pull the sdio line low during the high period of the clock cycle. device address/operation words, register address words, and write data words are transmitted by the master and are acknowledged by the AS1860. read data words transmitted by the device are also acknowledged by the master.
AS1860 akros silicon, inc. 6399 san ignacio avenue, suite 250, san jose, ca 95119 usa 408.746.9000 ? http://www.akrossilicon.com 33 figure 26 - i 2 c interface start/stop and data timing figure 27 - i 2 c acknowledge timing device address configuration the i 2 c interface is designed to support a multi-device bus system. at the start of an i 2 c read or write operation, the AS1860 compares its configured device address to the address sent by the master. the AS1860 will only respond (with ack) when the addresses match. the device address consists of 7 bits plus a read/write bit. as shown in table 20, bits a7, a6, a5 and a4 of the AS1860 device address are internally fixed to values a7 = 0, a6 = 1, a5 = 0 and a4 = 0. the i2c_adr pin is used to configure bits a3 thru a1 (using an external resistor). the device establishes the bit values of a3 thru a1 during start-up by measuring current flow through this resistor. note that a0 functions as the read/write operation bit. table 20 - AS1860 device address configuration bit function description a7 fixed device address bits internally fixed to 0 a6 internally fixed to 1 a5 internally fixed to 0 a4 internally fixed to 0 a3 configurable device address bits device address bits a3, a2 and a1 are configured by connecting a 1% resistor between pin i2c_adr and ground (48n) as follows: 100k ? sets a3, a2, a1 = 1,1,1 86.6k ? sets a3, a2, a1 = 1,1,0 75.0k ? sets a3, a2, a1 = 1,0,1 61.9k ? sets a3, a2, a1 = 1,0,0 49.9k ? sets a3, a2, a1 = 0,1,1 37.4k ? sets a3, a2, a1 = 0,1,0 29.4k ? sets a3, a2, a1 = 0,0,1 12.4k ? sets a3, a2, a1 = 0,0,0 a2 a1 a0 w r specifies read or write operation
AS1860 akros silicon, inc. 6399 san ignacio avenue, suite 250, san jose, ca 95119 usa 408.746.9000 ? http://www.akrossilicon.com 34 device ? address/operation ? word ????????????????????????? following a start condition the host transmits an 8-bit device address/operation word to initiate a read or write operation. this word consists of a 7-bit device address and the read/write operation bit as shown in figure 28. the AS1860 compares the received device address with its configured device address and sends back an ack only when the addresses match. bit 0 is the read/write operat ion bit. a read operation is specified when the w r bit is set high; a write operation when set low. figure 28 - device address/operation word register ? address ? word ??????????????????????? ?????????????????? for write operations (after the AS1860 acknowledges receipt of the device address/write word) the master sends the target 8-bit register address word to specify the AS1860 register to be accessed. table 21 specifies the valid AS1860 register addresses. ? data ? word ?????????????????????? ?????????????????????? ??????????????????? the 8-bit data word contains read/write data. data is transferred with the msb sent first. write ? cycle ??????????????????????? ?????????????????????? ???????????????? figure 29 illustrates the sequence of operations to perform an AS1860 register write cycle. read ? cycle ?????????????????????? ?????????????????????? ????????????????? figure 30 illustrates the sequence of operations to perform an AS1860 register read cycle. note that the master must first perform a ?dummy write? operation to write the AS1860 internal address pointer to the target register address. after the AS1860 sends back an ack, the master sends a repeated start, followed by a device address read word ( w r bit = 1). the AS1860 then transmits an ack followed by the data word that reflects the contents of the target register. upon receipt of the register address word, the AS1860 sends back an ack. table 21 - AS1860 register address word i 2 c register address word selected AS1860 register (hex) a7 a6 a5 a4 a3 a2 a1 a0 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 1 01 0 0 0 0 0 0 1 0 02 0 0 0 0 0 0 1 1 03 0 0 0 0 0 1 0 0 04 0 0 0 0 0 1 0 1 05 0 0 0 0 0 1 1 0 06 0 0 0 0 0 1 1 1 07 0 0 0 0 1 0 0 0 08 0 0 0 0 1 0 0 1 09 0 0 0 0 1 0 1 0 0a 0 0 0 0 1 0 1 1 0b 0 0 0 0 1 1 0 0 0c 0 0 0 0 1 1 0 1 0d 0 0 0 0 1 1 1 0 0e 0 0 0 0 1 1 1 1 0f register descriptions the AS1860 contains 16 single byte (8-bit) registers. the registers are accessible via the i 2 c interface when software mode is enabled. table 22 provides a summary of the AS1860 registers and bit functions. table 23 through table 38 provides detailed description of the function an d operation of each register.
AS1860 akros silicon, inc. 6399 san ignacio avenue, suite 250, san jose, ca 95119 usa 408.746.9000 ? http://www.akrossilicon.com 35 figure 29 - i 2 c interface write cycle timing figure 30 - i 2 c interface read cycle timing (with repeated start) table 22 - AS1860 register and bit summary register addr (hex) access data bits d7 d6 d5 d4 d3 d2 d1 d0 alarms and power status 00 read- only over- current alarm over- temp alarm a/d over- threshold alarm output #4 fault output #3 fault output #2 fault output #1 fault global pgood fault interrupt mask 01 r/w over- current alarm over- temp alarm a/d over- threshold alarm output #4 fault output #3 fault output #2 fault output #1 fault reserved interrupt status 02 read- only over- current alarm over- temp alarm a/d over- threshold alarm output #4 fault output #3 fault output #2 fault output #1 fault watchdog timeout pgood voltage masks 03 r/w reserved rese rved reserved output #4 mask output #3 mask output #2 mask output #1 mask reserved watchdog enable, mask, service 04 r/w reserved reserved reserved watchdog enable watchdog interrupt mask watchdog pgood mask watchdog register reset mask watchdog service control pgood & watchdog history 05 r/w reserved rese rved reserved output #4 caused pgood fault output #3 caused pgood fault output #2 caused pgood fault output #1 caused pgood fault watchdog timeout elapsed device control and i/o status 06 r/w reserved reset all registers enable interrupts disable pgood reset reserved reserved gpop gpip watchdog timeout 07 r/w wdog timeout counter (8 bits, in 125ms increments) adcin voltage read 08 read- only adcin pin input voltage measurement (8 bits) adcin alarm threshold 09 r/w alarm threshold for adcin (8 bits) pd status & system clock control 0a r/w reserved ldet at_det clim (not valid in local power mode) pwm clock modulate enable pwm clock modulate type pwm clock modulation amount d1, d0
AS1860 akros silicon, inc. 6399 san ignacio avenue, suite 250, san jose, ca 95119 usa 408.746.9000 ? http://www.akrossilicon.com 36 pd voltage read 0b read- only pd input voltage measurement (valid during both poe and local power operation modes) pd current read 0c read- only reserved reserved reserved pd input current measurement (poe only, does not measure local power current) pd over- current alarm threshold 0d r/w reserved reserved reserved pd over-current alarm trip threshold outputs 1,2 disable & margin control 0e r/w output #2 disable control output #2 voltage margin setting (d6, d5, d4) reserved output #1 voltage margin setting (d2, d1, d0) outputs 3,4 disable & margin control 0f r/w output #4 disable control output #4 voltage margin setting (d6, d5, d4) output #3 disable control output #3 voltage margin setting (d2, d1, d0) table 23 - alarms and power status (read-only) - 00h bit function description reset state d7 pd over-current alarm 1 = pd has exceeded current limit defined by pd current threshold register 0 = no alarm 0 d6 internal over-temp alarm 1 = temp has tripped warning threshold 0 = no alarm 0 d5 a/d threshold alarm 1 = a/d measurement is > a/d al arm threshold register setting 0 = no alarm 0 d4 power output #4 fault 1 = output #4 fault, not within spec 0 = output in spec this bit always tracks the output 4 voltage status regar dless of whether the output is disabled in hardware and/ or is masked off by register 03. 0 d3 power output #3 fault 1 = output #3 fault, not within spec 0 = output in spec this bit always tracks the output 3 voltage status regar dless of whether the output is disabled in hardware and/ or is masked off by register 03. 0 d2 power output #2 fault 1 = output #2 fault, not within spec 0 = output in spec this bit always tracks the output 2 voltage status regar dless of whether the output is disabled in hardware and/ or is masked off by register 03. 0 d1 power output #1 fault 1 = output #1 fault, not within spec 0 = output in spec this bit always tracks the output 1 voltage status regar dless of whether the output is masked off by register 03. 0 d0 global pgood fault 1 = at least one enabled output not within spec 0 = all enabled outputs within spec this bit always tracks the pgood pi n, so both hardware disabled outputs and register 03 masks will affect it. 0 table 24 - interrupt mask (r/w) - 01h bit function description (see also alarms and power reg) reset state d7 pd over-current alarm 1 = mask on (interrupt possible) 0 = masked off (no interrupt possible) 0 d6 internal over-temp alarm 1 = mask on (interrupt possible) 0 = masked off (no interrupt possible) 0 d5 a/d threshold alarm 1 = mask on (interrupt possible) 0 = masked off (no interrupt possible) 0
AS1860 akros silicon, inc. 6399 san ignacio avenue, suite 250, san jose, ca 95119 usa 408.746.9000 ? http://www.akrossilicon.com 37 d4 interrupt upon power output #4 fault 1 = mask on (interrupt possible) 0 = masked off (no interrupt possible) 0 d3 interrupt upon power output #3 fault 1 = mask on (interrupt possible) 0 = masked off (no interrupt possible) 0 d2 interrupt upon power output #2 fault 1 = mask on (interrupt possible) 0 = masked off (no interrupt possible) 0 d1 interrupt upon power output #1 fault 1 = mask on (interrupt possible) 0 = masked off (no interrupt possible) 0 d0 reserved do not write to this data bit 0 table 25 - interrupt status (read-only) - 02h bit function description (see also alarms and power reg) reset state d7 pd over-current alarm 1 = fault 0 = normal operation 0 d6 internal over-temp alarm 1 = fault 0 = normal operation 0 d5 a/d threshold alarm 1 = fault 0 = normal operation 0 d4 power output #4 fault 1 = fault 0 = normal operation 0 d3 power output #3 fault 1 = fault 0 = normal operation 0 d2 power output #2 fault 1 = fault 0 = normal operation 0 d1 power output #1 fault 1 = fault 0 = normal operation 0 d0 watchdog timeout 1 = timeout 0 = no timeout 0 table 26 - pgood voltage masks (r/w) - 03h bit function description reset state d7 reserved do not write to this data bit 0 d6 reserved do not write to this data bit 0 d5 reserved do not write to this data bit 0 d4 output #4 masked from pgood pin 1= output #4 part of pgood pin or register status 0= output #4 not part of pgood 1 d3 output #3 masked from pgood pin 1= output #3 part of pgood pin or register status 0= output #3 not part of pgood 1 d2 output #2 masked from pgood pin 1= output #2 part of pgood pin or register status 0= output #2 not part of pgood 1 d1 output #1 masked from pgood pin 1= output #1 part of pgood pin or register status 0= output #1 not part of pgood 1 d0 reserved do not write to this data bit 0
AS1860 akros silicon, inc. 6399 san ignacio avenue, suite 250, san jose, ca 95119 usa 408.746.9000 ? http://www.akrossilicon.com 38 table 27 - watchdog enable, mask, service (r/w) - 04h bit function description reset state d7 reserved do not write to this data bit 0 d6 reserved do not write to this data bit 0 d5 reserved do not write to this data bit 0 d4 d3 d2 d1 watchdog enable watchdog interrupt mask watchdog pgood mask watchdog register reset mask to change d4, d3, d2, or d1 a two stage write operation must occur: stage 1. the watchdog enable bit (d4) must be set along with any other (d3-d1) desired bit changes. if d4 is not set the entire write operation is ignored. stage 2. a write to reg 0 with data bb (hex) must be the next i 2 c operation to this device. if not, write will be ignored. once this operation is complete (and d4 is set) the d4- d1 bits are sticky and cannot be reset. d4 (watchdog enable): 1 = enable watchdog countdown operation (timeout value set in watchdog timeout register). 0 = watchdog disabled d3 (watchdog interrupt mask): 1 = mask on, interrupt possible 0 = masked off, no interrupt possible d2 (watchdog pgood mask): 1 = mask on, watchdog part of pgood operation 0 = mask off, watchdog not part of pgood operation d1 (watchdog register reset disable mask): 1 = mask on, a watchdog timeout will not reset i 2 c registers 0= mask off, a watchdog timeout will reset i 2 c registers d4 = 0 d3 = 0 d2 = 1 d1 = 0 d0 watchdog service control 1 = enable software service of watchdog 0 = no software service of watchdog servicing the watchdog is a 2-step procedure, after writing a ?1? to this bit the next i 2 c operation to the AS1860 must be a write to reg 0 with data aa (hex). 0 table 28 - pgood & watchdog history (r/w) - 05h bit function description reset state d7 reserved do not write to this data bit 0 d6 reserved do not write to this data bit 0 d5 reserved do not write to this data bit 0 d4 output #4 pgood history 1 = output #4 caused pgood fault 0 = output #4 did not cause pgood fault 0 d3 output #3 pgood history 1 = output #3 caused pgood fault 0 = output #3 did not cause pgood fault 0 d2 output #2 pgood history 1 = output #2 caused pgood fault 0 = output #2 did not cause pgood fault 0 d1 output #1 pgood history 1 = output #1 caused pgood fault 0 = output #1 did not cause pgood fault 0 d0 watchdog history 1 = watchdog timeout occurred 0 = no watchdog timeout occurred 0
AS1860 akros silicon, inc. 6399 san ignacio avenue, suite 250, san jose, ca 95119 usa 408.746.9000 ? http://www.akrossilicon.com 39 table 29 - device control and i/o status (r/w) - 06h bit function description reset state d7 reserved do not write to this data bit 0 d6 reset all registers 1 = force reset all registers 0 = no resets 0 d5 enable interrupts 1 = enable interrupts that are masked on 0 = no interrupts enabled 0 d4 disable pgood reset 1 = pgood fault will not reset registers 0 = pgood fault will reset registers 0 d3 reserved do not write to this data bit 0 d2 reserved do not write to this data bit 0 d1 general-purpose output (gpop) gpop pin reflects the state of this bit 0 d0 general-purpose input (gpip) this bit reflects the state of the gpip pin 0 table 30 - watchdog timeout (r/w) - 07h bit function description reset state d7 d7 of 8-bit watchdog timer watchdog timeout counter value (125ms increments), used in software mode only. ff = max value (32 sec) 01 = min value (125ms) 00 = reserved, do not use 1 d6 d6 of 8-bit watchdog timer 1 d5 d5 of 8-bit watchdog timer 1 d4 d4 of 8-bit watchdog timer 1 d3 d3 of 8-bit watchdog timer 1 d2 d2 of 8-bit watchdog timer 1 d1 d1 of 8-bit watchdog timer 1 d0 d0 of 8-bit watchdog timer 1 table 31 - adcin voltage (read-only) - 08h bit function description reset state d7 d7 of 8-bit voltage measure 8-bit measurement of voltag e at adcin pin (primary side). the a/d runs continuously with a 100hz sampling rate (minimum), and can be read at full i 2 c speed. ff (hex) = 2.5 v 00 (hex) = 0 v step size = 9.80 mv 0 d6 d6 of 8-bit voltage measure 0 d5 d5 of 8-bit voltage measure 0 d4 d4 of 8-bit voltage measure 0 d3 d3 of 8-bit voltage measure 0 d2 d2 of 8-bit voltage measure 0 d1 d1 of 8-bit voltage measure 0 d0 d0 of 8-bit voltage measure 0 table 32 - adcin alarm threshold (r/w) - 09h bit function description reset state d7 d7 of 8-bit a/d interrupt threshold 8 bit threshold for a/d alarm interrupt (if enabled) from adcin input pin. ff (hex) = 2.5v 00 (hex) = 0 v step size = 9.80 mv 1 d6 d6 of 8-bit a/d interrupt threshold 1 d5 d5 of 8-bit a/d interrupt threshold 1 d4 d4 of 8-bit a/d interrupt threshold 1 d3 d3 of 8-bit a/d interrupt threshold 1 d2 d2 of 8-bit a/d interrupt threshold 1 d1 d1 of 8-bit a/d interrupt threshold 1 d0 d0 of 8-bit a/d interrupt threshold 1 table 33 - pd status and system clock control (r/w) - 0ah bit function description reset state d7 reserved do not write to this data bit 0 d6 ldet 1 = local power supply detected 0 = no local power supply detected 0 d5 at_det 1 = ieee ? 802.3at, or, local power mode detection 0 = ieee ? 802.3af mode detection 0 d4 clim 1 = 750ma (min) poe current limit 0 = 375ma (min) poe current limit note that clim status is not valid in local power mode (ldet status bit d6=1). 0
AS1860 akros silicon, inc. 6399 san ignacio avenue, suite 250, san jose, ca 95119 usa 408.746.9000 ? http://www.akrossilicon.com 40 d3 pwm clock modulation enable 1 = clock modulation on 0 = off 0 d2 pwm clock modulation type 1 = fractional-n (see d1, d0 for modulation amount) 0 = random (prbs) 0 d1 pwm fractional-n modulation amount (not used for prbs modulation) d1, d0: 1,1 = reserved (do not use) 1,0 = 10% 0,1 = 5% 0,0 = 2% 0,0 d0 table 34 - pd voltage (read-only) - 0bh bit function description reset state d7 d7 of 8-bit voltage measure 8-bit measurement of pd input voltage (primary side). also valid during local power operation. ff (hex) = 60 v (1%) 00 (hex) = 0 v step size = 235.3 mv 0 d6 d6 of 8-bit voltage measure 0 d5 d5 of 8-bit voltage measure 0 d4 d4 of 8-bit voltage measure 0 d3 d3 of 8-bit voltage measure 0 d2 d2 of 8-bit voltage measure 0 d1 d1 of 8-bit voltage measure 0 d0 d0 of 8-bit voltage measure 0 table 35 - pd current (read-only) - 0ch bit function description reset state d7 reserved 5-bit measurement of pd input current (primary side). poe current measurement only, not valid during local power operating mode. with clim = low d4, d3, d2, d1, d0 11111 = 400 ma (10%) 00000 = 0 ma step size = 12.90 ma with clim = high d4, d3, d2, d1, d0 11111 = 800 ma (10%) 00000 = 0 ma step size = 25.81 ma n/a d6 reserved n/a d5 reserved n/a d4 d4 of 5-bit current measurement 0 d3 d3 of 5-bit current measurement 0 d2 d2 of 5-bit current measurement 0 d1 d1 of 5-bit current measurement 0 d0 d0 of 5-bit current measurement 0 table 36 - pd over-current alarm threshold (r/w) - 0dh bit function description reset state d7 reserved the over-current alarm bit is set when the pd input current (primary side) measurement exceeds this 5-bit value, not valid during local power operating mode. with clim = low d4, d3, d2, d1, d0 11111 = 400 ma (10%) 00000 = 0 ma step size = 12.90 ma with clim = high d4, d3, d2, d1, d0 11111 = 800 ma (10%) 00000 = 0 ma step size = 25.81 ma n/a d6 reserved n/a d5 reserved n/a d4 d4 of 5-bit current alarm trip setting 1 d3 d3 of 5-bit current alarm trip setting 1 d2 d2 of 5-bit current alarm trip setting 1 d1 d1 of 5-bit current alarm trip setting 1 d0 d0 of 5-bit current alarm trip setting 1
AS1860 akros silicon, inc. 6399 san ignacio avenue, suite 250, san jose, ca 95119 usa 408.746.9000 ? http://www.akrossilicon.com 41 table 37 - outputs 1, 2 disable & margin control (r/w) - 0eh bit function description reset state d7 output #2: disable control 0 = normal output operation, with bits d6, d5, d4 defining margining operation. 1 = output #2 is disabled. 0 d6 voltage margin for output #2 d6, d5, d4 (with d7=0): 1,1,1 = -2% 1,1,0 = -4% 1,0,1 = -6% 1,0,0 = -8% 0,1,1 = +6% 0,1,0 = +4% 0,0,1 = +2% 0,0,0 = no margining 0,0,0 d5 d4 d3 reserved do not write to this bit 0 d2 voltage margin for output #1 d2, d1, d0: 1,1,1 = reserved, do not use 1,1,0 = reserved, do not use 1,0,1 = reserved, do not use 1,0,0 = +5% 0,1,1 = +2.5% 0,1,0 = -2.5% 0,0,1 = -5% 0,0,0 = no margining 0,0,0 d1 d0 table 38 - outputs 3, 4 disable & margin control (r/w) - 0fh bit function description reset state d7 output #4: disable control 0 = normal output operation, with bits d6, d5, d4 defining margining operation. 1 = output #4 is disabled. 0 d6 voltage margin for output #4 d6, d5, d4 (with d7=0): 1,1,1 = -2% 1,1,0 = -4% 1,0,1 = -6% 1,0,0 = -8% 0,1,1 = +6% 0,1,0 = +4% 0,0,1 = +2% 0,0,0 = no margining 0,0,0 d5 d4 d3 output #3: disable control 0 = normal output operation, with bits d2, d1, d0 defining margining operation. 1 = output #3 is disabled. 0 d2 voltage margin for output #3 d2, d1, d0 (with d3=0): 1,1,1 = -2% 1,1,0 = -4% 1,0,1 = -6% 1,0,0 = -8% 0,1,1 = +6% 0,1,0 = +4% 0,0,1 = +2% 0,0,0 = no margining 0,0,0 d1 d0
AS1860 akros silicon, inc. 6399 san ignacio avenue, suite 250, san jose, ca 95119 usa 408.746.9000 ? http://www.akrossilicon.com 42 power over ethernet overview power over ethernet (poe) offers an economical alternative for powering end network appliances such as ip telephones, wireless access points, security and web cameras, and other powered devices (pds). the poe standard ieee ? std. 802.3af is intended to standardiz e the delivery of power over the ethernet cables in order to accommodate remotely powered client devices. ieee ? std. 802.3af defines a method for recognizing pds on the network and supplying different power levels according to power level classes with which each pd is identified. by empl oying this method, designers can create systems that minimi ze power usage, allowing more devices to be supported on an ethernet network. the end of the link that provi des power through the ethernet cables is referred to as the power sourcing equipment (pse). the powered device (pd) is the end of the link that receives the power. the poe method for recognizing a pd and determining the correct power level to allocate uses the following sequence: 1. reset - power is withdrawn from the pd if the applied voltage falls below a specified level. 2. signature detection - during which the pd is recognized by the pse. 3. classification - during which the pse reads the power requirement of the pd. the classification level of a pd identifies how much power the pd requires from the ethernet line. this permits optimum use of the total power available from the pse. (classification is considered optional by ieee ? standard 802.3af.) 4. on operation - during which the allocated level of power is provided to the pd. this sequence occurs as progressively rising voltage levels from the pse as shown in figure 29. a summary of the poe design framework is shown in table 39. table 39 - poe design framework summary requirement value maximum power to the pd 12.95w (type 1) 25.5w (type 2) voltage at the pse interface 44-57v (type 1) 50-57v (type 2) maximum operating current 350ma (type 1) 600ma (type 2) min voltage at the pd interface 37v (type 1) 42.5v (type 2) power feed alternatives for 10/100/1000m ethernet systems the power sourcing equipment (pse) supplies power to a single pd per node. a pse located in the data terminal equipment or repeat er is called an endpoint pse, while a pse located between mdis is called a mid-span pse. figure 31 illustrates the two power feed options allowed in the 802.3af/at standard for 10/100/100 0m ethernet systems (full duplex twisted pair data signaling is used in 1000m ethernet). in alternative a, a pse powers the end station by feeding current along the twisted pair cable used for the 10/100/1000m ethernet signal via center taps on the ethernet transformers. on the line side of the transformers for the pd, power is delivered through pins 1 and 2 and returned through pins 3 and 6. in alternative b, a pse powers the end station by feeding power through pins 4, 5, 7and 8. in a 10/100/1000m system, this is done through the cent er taps of the ethernet transformer. in a 10/100m system, power is applied directly to the spare cable pairs without using transformers. the ieee? std. 802.3af/at standards are intended to be fully compliant with all existing non- powered ethernet systems. as a result the pse is required to detect via a well-defined procedure whether or not the connected device is pd compliant and classify (optional in legacy 802.3af applications) the needed power prior to supplying it to the device. maximum allowed voltage is 57v to stay within selv (safety extra low voltage) limits.
AS1860 akros silicon, inc. 6399 san ignacio avenue, suite 250, san jose, ca 95119 usa 408.746.9000 ? http://www.akrossilicon.com 43 802.3at specification the AS1860 has been designed to be compatible with the ieee 802.3at high power poe standard. these devices are capable of providing the power needs of voip with video streaming, 802.11n multi-radi o waps, and ip cameras with ptz. the AS1860 provides the normal signature resistance during detection phase for the pse to recognize a pd. both devices also support the two-event classification method specified in the 802.3at standard (backwar d compatible to 802.3af classification modes) and can detect a type 2 pse. if the AS1860 detects a type 2 pse they wi ll indicate this either on the at_det pin or in i 2 c register 0a (hex) in the AS1860 software mode. at_det pin is active high. the AS1860 will issue the correct at_det state before pgood signal transitions to an ?all good? state. for a pd that is 802.3at compliant, class must be set to class 4 using appropriate rclass resistor. figure 31 - ieee ? std. 802.3af power feeding schemes 60w/90w applications the poe specification, 802.3at, was updated in 2009 to agree the standard for delivering up to 30w from a pse. power delivery was limited to two of the four pairs which exist in ethernet cables. since then several new applications such as thin clients, high power multiple band wap?s and communication clusters have emerged that benefit from the network controlled power management provided by poe. this has led to the need for pd controllers that can safely deliver up to 90w which the AS1860 provides. in applications above 30w, power is applied to all four pairs in the ethernet cable. typically, two pse?s are connected to two separate pairs so that each pair now transfers 30w/45w. at this time there is no standard for this configuration but the AS1860 provides the flexibility to complete this link in a number of different ways.
AS1860 akros silicon, inc. 6399 san ignacio avenue, suite 250, san jose, ca 95119 usa 408.746.9000 ? http://www.akrossilicon.com 44 lldp communication one of the most commonly depl oyed schemes for identifying the power capability of a powered device (pd) is using link layer discovery protocol (lldp). in this protocol, the pse communicates lldp packets to the pd over ethernet lines so that the pse determines the po wer capability of the pd. in applications using the AS1860, 60w/90w capability of the pd can be communicated to the pse in a number of ways:- a) a logic level can be set on the pd board or a bit set in the local pd microcontroller that responds to the pse lldp communications that the pd is capable of processing 60/90w b) an external power fet (m1) is used in the AS1860 applications for 60w/90w to pass the high currents needed for the high power requirements. m1 will be turned on by driving it?s gate terminal high which is accomplished in a number of ways shown in the following sections. the volt age on the gate of m1 can be read on the primary side using the gpip pin and transferred to the secondar y side onto the gpos pin. the logic level of gpos can be communicated to the pse to confirm that 60/ 90w is available. four pair voltage sense enabled the four pair sensing circuit enables the external bypass mosfet after the application of a second pse (four pair conducting). for proper pse/pd handshaking and inrush current limiting it is assume d that only one pse is applied initially and the second pse applies power after the at signature and classification is complete for the first. the second pse is turned on without handshaking. figure 32 ? four pair sensing enabling external mosfet m1 rsig 48vin rclass 48rtn 48n gpis switching converter primary bias enabled the switching converter primary bias method develops a bias from the dc-dc converter and applies this to the external bypass mosfet. after signature, classification and inrush of one poe pair, the switching converter is enabled. once the converter starts switching the bias winding is peak detected to develop the gate dr ive for the external bypass mosfet, m1. additional delay is added by way of an rc filter. in order to limit any leakage current prior to inrush complete (before internal bypass mosfet is enabled) a pnp transistor is used to hold off the gate drive to m1.
AS1860 akros silicon, inc. 6399 san ignacio avenue, suite 250, san jose, ca 95119 usa 408.746.9000 ? http://www.akrossilicon.com 45 figure 33 ? primary bias enabling external mosfet m1 rsig 48vin rclass 48rtn 48n gpis secondary side logic enable the secondary referenced logic enabled circuit accepts a logic signal from the secondary (gpis) and applies it through the AS1860 isolation barrier to gpop which allows the primary bias rail to be applied to the external bypass mosfet (m1) gate. figure 34 ? secondary side logic control of external mosfet m1 rsig 48vin rclass 48rtn 48n gpis
AS1860 akros silicon, inc. 6399 san ignacio avenue, suite 250, san jose, ca 95119 usa 408.746.9000 ? http://www.akrossilicon.com 46 poe power-on sequence the power-on sequence for poe operation is shown in figure 29. the waveform reflects typical voltages present at the pd during signature, classification and power-on. figure 35 - poe power-on sequence waveform 1 . voltages v1 and v2 are applied by the pse to extract a signature value. 2 . the pse takes current/impedance readings during class/mark events to determine the class of the pd. at this time, the pd pres ents a load current determined by the resistance connected to the rclass pin. 3 . after the pse measures the pd load current, if it is a high-pow er pse, it presents a mark voltage (6.9-10v), followed by a se cond classification voltage. the pd responds by presenting a load current as determi ned by the resistor on the rclass pin. after the pse measures t he pd load current the second time and determines that is can deliver the req uested power, it moves into the on state by raising the volta ge to approximately 42v after which the pd operates over the on range.
AS1860 akros silicon, inc. 6399 san ignacio avenue, suite 250, san jose, ca 95119 usa 408.746.9000 ? http://www.akrossilicon.com 47 figure 36 - typical isolated synchronous flyback application
AS1860 akros silicon, inc. 6399 san ignacio avenue, suite 250, san jose, ca 95119 usa 408.746.9000 ? http://www.akrossilicon.com 48 package specifications figure 37 - 64-pin qfn dimensions
AS1860 akros silicon, inc. 6399 san ignacio avenue, suite 250, san jose, ca 95119 usa 408.746.9000 ? http://www.akrossilicon.com 49
AS1860 akros silicon, inc. 6399 san ignacio avenue, suite 250, san jose, ca 95119 usa 408.746.9000 ? http://www.akrossilicon.com 50 contact information akros silicon, inc. 6399 san ignacio avenue, suite 250 san jose, ca 95119 usa tel: (408) 746 9000 fax: (408) 746-9391 email inquiries: marcom@akrossilicon.com website: http://www.akrossilicon.com important notices legal notice copyright ? 2011 akros silicon?. all right s reserved. other names, brands and trademarks are the property of others. akros silicon? assumes no responsibility or liability for in formation contained in this document. akros reserves the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or services with out notice. the information contained herein is believed to be accurate and reliable at the time of printing. reference design policy this document is provided as a design reference and ak ros silicon assumes no responsibility or liability for the information contained in this document. akros reserves t he right to make corrections, modifications, enhancements, improvements and other changes to this refere nce design documentation without notice. reference designs are created using akros silicon's published specifications as well as the published specifications of other device manufacturers. this information may not be current at the time the reference design is built. akros silicon and/or its licensors do not warrant the accuracy or completeness of the sp ecifications or any information contained therein. akros does not warrant that the desi gns are production worthy. customer s hould completely validate and test the design implementation to confirm the system f unctionality for the end use application. akros silicon provides its customers with limited product wa rranties, according to the st andard akros silicon terms and conditions. for the most current product information visit us at www.akrossilicon.com life support policy life support: akros' produc ts are not designed, intended, or authorized for use as components in life support d evices or systems. no warranty , express or implied, is made for this use. authorizatio n for such use shall not be gi ven by akros, and the products shall not be used in such devices or systems, except upon the written approval of the president of akros following a determination by akros that such use is feasible. such approval may be withheld fo r any or no reason. ?life support devices or systems? are devices or systems which (1) are intended for surgical implant into the human body, (2) support or sustain human life, or (3) monitor critic al bodily functions including, but not limited to, cardiac, respirator, and neurological functions, and whose failure to perform can be reasonably expected to result in a significant bodily injury to the user. a ?critical component ? is any component of a life s upport device or system whose failure to perform can be reasonably expected to cause the failu re of the life support device or system, or to affect its safety or effectiveness.
AS1860 akros silicon, inc. 6399 san ignacio avenue, suite 250, san jose, ca 95119 usa 408.746.9000 ? http://www.akrossilicon.com 51 substance compliance with respect to any representation by akros silicon that its produ cts are compliant with rohs, akros silicon complies with the restriction of the use of hazardous substances standard (?rohs?), which is more formally known as directive 2002/95/ec of the european parliament and of t he council of 27 january 2003 on the restriction of the use of certain hazardous substances in electrical and electronic equi pment. to the best of our knowledge the information is true and correct as of the date of the original publication of the information. akros silicon bears no responsibility to update such statements. revision: version 1.4 release date: july 1, 2015

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