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THC7984_rev.2.0_e 1 / 45 thine electronics, inc. copyright?2013 thine electronics, inc. THC7984 10-bit 3-channel vi deo signal digitizer general description the THC7984 integrates all the functions to digitize analog video signals on a single chip. acceptable signals pc graphics (rgb) : vga-uxga - separate sync - composite sync - sync on green component video (ypbpr) : - sdtv (480i / 480p) 2-level sync - hdtv (1080i / 720p / 1080p) 3-level sync - protection signal applications lcd tv / pdp tv rear-projection tv lcd display / pdp display front projector etc. features 170 msps 10-bit adc - internal 14-bit adcs - oversampling functions (2x, 4x, and 8x) line-locked pll with low jitter - phase adjustment: 64 steps fine clamp / preamp - pedestal / center clamp - clamp level auto adjust - very low gain mismatch - gain adjustment: 2048 steps video filter (lpf) - bandwidth adjustment: 28 steps (6mhz - 310mhz) sync processor - 2-level / 3-level sync slicer - advanced sync de tection / measurement - automatic sync processing mode - irq output 2-wire serial interface lqfp 80-pin package pga clamp adc 10-bit auto clamp level adjust pga clamp adc output formatter 10-bit red0-9 green0-9 blue0-9 hsync0 vsync0 serial i/f control sogout o/e field datack scl sda sync processing rain0 gain0 bain0 sogin0 sog slicer hsout 2:1 switch auto clamp level adjust pga clamp adc 10-bit auto clamp level adjust filt & clock generation block diagram clamp extclk/coast vsout/a0 voltage reference refhi refcm reflo rst 2:1 2:1 rain1 gain1 bain1 decimation filter & lpf lpf lpf switch switch sogin1 vsync1 hsync1
THC7984_rev.2.0_e 2 / 45 thine electronics, inc. copyright?2013 thine electronics, inc. specifications vd=1.8v, vdd=3.3v, pvd=1.8v, davdd=1.8v, adc clock=maximum conv ersion rate, full temperature range=0 c to 70 c analog input voltage=0.5 to 1.0vpp min typ max num ber of bits 10 bits lsb size 0.098 %fs 25 c i 0.75 1 lsb full vi -1.0/+1.25 lsb 25c i 1.5 3 lsb full vi 4 lsb no m issing code 25 c i guaranteed minimum input voltage full vi 0.5 v p-p maximum input voltage full vi 1.0 v p-p gain tempco 25 c v 100 ppm/ c 25 c iv 1 a full iv 1 a input offset voltage full vi 1 lsb input full-scale matching between channels full vi 0.2 0.8 % offset adjustment range full vi 50 %fs maximum conversion rate full vi 170 msps minimum conversion rate full iv 10 msps data setu p time to clock *2 full iv 0.48tpixel-2.1 ns data hold time to clock *2 full iv 0.48tpixel-0.4 ns dut y c y cle, datack *2 full iv 40 50 60 % hsync input frequency full iv 15 110 khz maximum pll clock rate full vi 170 mhz minimum pll clock rate full iv 10 mhz pll jitter *3 25 c v 500 ps p-p sampling phase tempco full iv 15 ps/ c scl clock frequency ( fscl ) full iv 100 khz tbuff full iv 4.7 s tstah full iv 4.0 s tdho full iv 0 3.45 s tdal full iv 4.7 s tdah full iv 4.0 s tdsu full iv 250 ns tstasu full iv 4.7 s tstosu full iv 4.0 s tr full iv 1000 ns tf full iv 150 ns capacitive load ( cb ) full iv 400 pf noise m argin at the low level ( vnl ) full iv 0.2 v noise m argin at the high level ( vnh ) full iv 0.25 v input voltage, high (vih) full vi 1.4 v input voltage, low (vil) full vi 0.8 v input current, high (iih) full v 10 a input current, low (iil) full v 10 a input capacitance 25 c v 2 pf output voltage, high (voh) full vi vdd-0.2 v output voltage, low (vol) full vi 0.2 v output coding binary vd supply voltage full iv 1.7 1.8 1.9 v vdd supply voltage full iv 2.3 3.3 3.45 v pvd supply voltage full iv 1.7 1.8 1.9 v davdd supply voltage full iv 1.7 1.8 1.9 v id supply current (vd) 25 c v 295 ma idd su pp l y current (vdd) *4 25 c v 180 ma ipvd supply current (pvd) 25 c v 30 ma idavdd supply current (davdd) 25 c v 65 ma total power dissipation full vi 1350 mw power-down supply current full vi 10 20 ma power-down dissipation full vi 20 40 mw operating ambient temperature iv 0 70 c jc junction-to-case thermal resistance 25 c v 4 c/w ja junction-to-ambient thermal resistance 25 c v 37 c/w *1 input bias voltage: 0.05v to vd-0.05v *2 see "data/clock output test condition". *3 THC7984-17: uxga@60hz *4 output load capacitance per pin: 15pf temp integral n onlinearity 2-wire serial interface dc accuracy differential nonlinearity resolution parameter thermal characteristics THC7984-17 unit digital inputs power supply analog input input bias current *1 digital outputs sw itching performance test level explanation of test levels test level i. 100% production tested. ii. 100% production tested at +25c and sample tested at specif ied temperatures. iii. sample tested only. iv. parameter is guaranteed by design and characterization test ing. v. parameter is a typical value only. vi. 100% production tested at +25c; guaranteed by design and c haracterization testing.
THC7984_rev.2.0_e 3 / 45 thine electronics, inc. copyright?2013 thine electronics, inc. absolute maximum ratings pin configuration 50 80 20 vdd gnd data setup time data datack < data setup/hold time to clock > 10pf 33ohm THC7984 probe < data /clock output test condition > output drive strength (vdd=3.3v) : medium datack: pixel clock datack phase: 4 output format: normal (not ddr) *datack output phase is register programmable. data hold time t pixel parameter min max unit vd 2.1 v vdd 3.8 v pvd 2.1 v davdd 2.1 v analog inputs -0.2 vd+0.2 or 2.1 *1 v digital inputs -0.3 pvd+3.6 or 5.5 v *1 v storage temperature -55 150 c maximum junction temperature 125 c *1 smaller value is adopted. 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 1 2 3 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 39 40 41 80 79 78 vd bain0 rain0 sogin0 gain1 sogin1 vd gnd gnd vd sogout rain1 o/e field hsout datack vsout/a0 red<9> gain0 vdd gnd refcm blue<2> 26 27 28 29 30 31 32 33 34 35 36 37 38 64 77 76 75 74 73 72 71 70 69 68 67 66 65 bain1 vd gnd rst reflo refhi gnd davdd THC7984 top view red<8> red<7> red<6> red<5> red<4> red<3> red<2> red<1> red<0> vdd gnd gnd green<9> green<8> green<7> green<6> green<5> green<4> green<3> green<2> green<1> green<0> vdd gnd blue<9> blue<8> blue<7> blue<6> blue<5> blue<4> blue<3> blue<1> blue<0> vdd gnd sda scl hsync1 vsync1 hsync0 clamp extclk/coast pvd gnd filt pvd gnd vsync0 pvd gnd
THC7984_rev.2.0_e 4 / 45 thine electronics, inc. copyright?2013 thine electronics, inc. pin list pin name type function vd p analog power supply vdd p output power supply pvd p pll power supply davdd p digital core power supply gnd p ground bain0 ai b-ch analog input, port 0 bain1 ai b-ch analog input, port 1 gain0 ai g-ch analog input, port 0 sogin0 ai sync on green input, port 0 gain1 ai g-ch analog input, port 1 sogin1 ai sync on green input, port 1 rain0 ai r-ch analog input, port 0 rain1 ai r-ch analog input, port 1 rst di reset input low: normal operation high: power down (stand-by) high -> low: chip reset reflo - connection for external capacitor refcm - connection for external capacitor refhi - connection for external capacitor o/e field do field parity output for interlaced video data enable (de) output sync processor irq output vsout/a0 dio vsync output / serial interface device address bit 0 (a0) hsout do hsync output sogout do sog slicer output datack do data clock output red<9:0> do r-ch data output green<9:0> do g-ch data output blue<9:0> do b-ch data output scl di serial port data clock input sda dio serial port data i/o hsync1 di hsync input, port 1 vsync1 di vsync input, port 1 hsync0 di hsync input, port 0 vsync0 di vsync input, port 0 extclk/coast di external clock input / coast signal input clamp di external clamp pulse input reference clock input for hsync period measure filt - connection for pll loop filter p:power ai:analog input di:digital input do:digital output dio: digital input/output
THC7984_rev.2.0_e 5 / 45 thine electronics, inc. copyright?2013 thine electronics, inc. functional description digital input - all digital inputs are 5v tolerant during power-on. analog input - the THC7984 has two ports that each in clude three analog inputs for rgb or yp bpr. the input port can be selected by register. - in case input signals are ypbpr, y may be input into gain0 (or gain1) and sogin0 (or sogin1) , pr into rain0 (or rain1) , and pb into bain0 (or bain1) . - the THC7984 accommodates analog signals ranging from 0.5 vpp to 1.0 vpp. video filter (lpf) the THC7984 has 2 kinds of low-pass filters. - 5th-order lpf for ypbpr, whose bandwidth is adjustable from 6 mhz to 92 mhz in 24 steps. - 2nd-order lpf for rgb, whose bandwidth is adjustable in 4 steps (40 mhz, 90 mhz, 170 mhz, and 310 mhz) . serial interface - the THC7984 is controlled by 2-wire serial interface. - serial clock scl supports up to 100 khz. sync input - the THC7984 has two ports that each in clude two digital inputs for the sepa rate sync (hsync and vsync) . the input port can be selected by register. - the THC7984 can process composite sync (csync) . csync may be input into hsync0 or hsync1. digital output - the digital outputs can operate from 2.5 v to 3.3 v (vdd) . - the output drive strength is programmable by 2-bit registers (except sda) . clamp - pedestal clamp for rgb and y (luminance) clamps black level to 0 with automatic offset cancel. - midscale clamp for pbpr clamps to 512 with automatic offset cancel. - 256-level clamp for y (luminance) clamps to 256 with automatic offset cancel. it can be used for a/d conversion of y including sync signal. in this case, input signal needs to be attenuated to put it within the input rang of a/d converter. - clamp pulses can be input from clamp pin when external clamp is selected. gain, offset - gain is programmable by 11-bit registers (2048 steps) . - offset from -256 to +255 can be added to the output code. - gain and offset can be adjusted independently. reference voltage - the THC7984 has band gap reference inside and doesn?t require external voltage reference. - the internal reference voltages (refhi, refcm, and refl o) must be bypassed to stabilize. each pin (refhi, refcm, and reflo) is conn ected to ground through a 10 f capacitor.
THC7984_rev.2.0_e 6 / 45 thine electronics, inc. copyright?2013 thine electronics, inc. sampling clock generation - the THC7984 has pll to generate the sampling clock from hsync. the sampling clock frequency range is from 10mhz to 170 mhz. - pll divider ratio (the number of horizontal total pixels per line) can be set to the value between 200 to 8191. - the sampling clock phase can be adjusted in 64 steps of t/64. - the external clock can be used as the sampling clock. - it is required to set vco frequency range and charge pu mp current according to the inpu t signal format (resolution) . oversampling - oversampling is the function that enables sampling analog signals with higher rate than the pixel clock and downsam- pling to the pixel clock rate with decimation filter, which is effective for improving s/n ratio. - oversampling ratio can be selected among 1x (normal operat ion) , 2x, 4x, and 8x. even if any is selected, output fre- quency of the output clock and data is same as normal operation. output clock (datack) - the output clock phase can be selected in 8 steps for the data setup/hold adjustment. - divide-by-2 clock can be selected as the output clock for the dual edge data clocking at th e subsequent stage. it can not be selected when oversampling. sog slicer - sync on green (sog) is sliced at the threshold level above the sync tip to extract the sync signal. the threshold level can be set by a register ranging from 15 mv to 240 mv in steps of 15mv. - low pass filer prior to the slicer can be used to re duce high frequency noise, which can be disabled by a register. - the slicer also has hysteresis (about 30 mv) , which can be disabled by a register. - 3-level sync signal can be processed by slicing at the pedestal level. sync processor sync processor implements vsync separation from csync, vertical timing generation, and detection and measure- ment of the sync signals. the various automatic sync-processi ng modes are realized by utili zing the sync detection and measurement. the THC7984 can process the copy protection signal. (1) vsync separation extracting vsync from composite sync (csync) or sync on green (sog) . (2) vertical timing generation - vsync output generation - pll coast generation - clamp coast generation - v-blank of de generation (3) sync detection/measurement - input sync type detection (separate sync, co mposite sync, sync on green, and no input signal) - hsync, vsync input polarity detection - 3-level sync detection - interlace detection - vertical total line measurement - vsync input pulse width measurement - hsync period measurement (reference cl ock needs to be input into clamp pin.) - sync change detection - hsync edge detection - sync processor irq output
THC7984_rev.2.0_e 7 / 45 thine electronics, inc. copyright?2013 thine electronics, inc. (4) automatic sync processing mode (manual setting modes are also available) - auto output mode (all outputs are enabled when input signal is active) - input port auto sel ect (selects the port whose input signal is active) - input sync type auto sele ct (hsync input, vsync input) - hsync, vsync input polarity auto select - hsync, vsync output polarity auto select - vsync output timing auto setting - pll coast timing auto setting power control - the THC7984 can be set to stand-by mode by a register or rst-pin. - in stand-by mode, most of the analog circuits are powered down for low power dissipation. - in stand-by mode, the sync detecti on and measurement are availa ble nonetheless because sog slicer, sync processor, and 2-wire serial interface are still power-on. - the THC7984 is set to stand-by mode when rst-pin is se t to high. if unused, rst-pin must be pull-down to ground with a resistor. reset - the logic circuit of the chip is reset when power is applied with rst-pin asserted low (power-on reset) . - the reset can be also triggered by rst-pin (manual rese t) . the reset is triggered when rst-pin falls from high to low, that means the reset is triggered whenever the THC7984 gets out of stand-by mode by rst-pin. - reset after power-up is necessary to access the serial inte rface. please power-up with rst-pin asserted low or make rst-pin high then low after power-up. if unused, rs t-pin must be pull-down to ground with a resistor. - the registers are set to the default values by the reset and the chip becomes stand-by mode and output disable (hi-z) . for normal operation, the registers must be set to power-on and output enable by the serial interface. - for manual reset, keep rst-pin low more than 20 us after the transition from high to low. device address - the lsb of 7-bit device address of serial interface (a0) is obtained from vsout/a0-pin at the reset. pull-down to ground with a resistor (10 k ) , then device address is set to 1001100 pull-up to vdd with a resistor (10 k ) , then device address is set to 1001101 - the pull-up resistor must be connected to vdd. rst (reset signal) vih vil min. 100ns min. 20us * reset timing
THC7984_rev.2.0_e 8 / 45 thine electronics, inc. copyright?2013 thine electronics, inc. registers register notation the register is notated with ?r? added to the head of the address in hexadecimal. e.g. r00: register of address 0x00 the bit position is notated with ?[]?. e.g. r04[1:0]: bit 1 and bit 0 of address 0x04 the register value in hexadecimal is notated with ?h? added to the end. e.g. r01=18h the register value in binary is notated w ith ?b? added to the end. e.g. r04[1:0]=11b the register value in decimal is notated without suffix. e.g. r15[7:0]=32 register classification default value all registers are set to the default values by the reset (power-on reset, manual reset) . minus number setting some registers can be configured by two's complement. < register classification> sign category description register r/w read/write registers for configuration and adjustment except below r read only registers which report the result of measurement and detection r00, r2cr30, r32r34 aauto registers which can be auto-configured - when auto-configuration is ena bled, the registers become read only and the value auto-configured can be read. - when auto-configuration is disabled, the registers become read/write and the value must be set manually. r12[3], r12[1:0], r13[5], r13[4], r13[2], r13[1], r20[6:0], r21[5:0], r22[6:0], r23[6:0] evrc event recorder registers which record the ev ent that has occurred in sync processor. - 1 is set when the event occurs. - the value is cleared by writing 1 to the register. r35 < minus number setting > function register range clamp level offset r0c/r0d, r0e/r0f, r10/r11 -256 to +255 hsync output start position r14 -128 to +127 vsync output start position r20 -64 to +63
THC7984_rev.2.0_e 9 / 45 thine electronics, inc. copyright?2013 thine electronics, inc. register map bit r/w default value fun ctio n descri ption r 00 7 r 0 revision code can be read 21h 6r 0 5r 1 4r 0 3r 0 2r 0 1r 0 0r 1 r01 7 6 5 4 r/w 0 chip power-on 0: power-down (stand-by mode) 1: power-on (n ormal operation) 3 r/w 0 auto output enable (all outpu ts become enable when input s i gn al is active) 0: disable 1: enable 2 r/w 0 output enable (except sogout & irq) 0: disable 1: enable 1 r/w 0 sogout output enable 0: disable 1: enable 0 r/w 0 reserved must be set to 0 (default value) r02 7 6 r/w 0 oversampling 00b: 1x(normal operation) 01b: 2x 10b: 4x 11b: 8x 5r/w 0 4 r/w 0 pll divi der ratio set the number of hori zon tal total pixels per line 3r/w 0 2r/w 1 1r/w 1 0r/w 0 r03 7 r/w 1 6r/w 0 5r/w 0 4r/w 1 3r/w 1 2r/w 0 1r/w 0 0r/w 0 r 04 7 r/w 1 reserved must be set to 1 (default value) 6 r/w 1 vco frequency range 00b: 1/8 01b: 1/4 10b: 1/2 11b: 1/1 5r/w 1 4 r/w 1 charge pump current 000b: 50ua 001b: 100ua 010b: 150ua 011b : 250ua 3r/w 0 100b: 350ua 101b: 500ua 110b: 750ua 111b: 1000ua 2r/w 0 1 r/w 0 sampling clock source 00b: internal clock 01b: reserved 0r/w 0 10b: external clock (10-20mhz) 11b: external clock (20-170mhz) r05 7 6 5 r/w 0 sampling clock phase set in 64 steps of t/64 4r/w 0 *bigger values me an more delay. 3r/w 0 2r/w 0 1r/w 0 0r/w 0 r06 7 6 5 4 3 2 r/w 1 r-ch gain gain = (register value + 1024) / 2048 1r/w 0 2048 steps from x0.5 to x1.5 0r/w 0 *bigger values me an higher gain. r07 7 r/w 0 6r/w 0 5r/w 0 4r/w 0 3r/w 0 2r/w 0 1r/w 0 0r/w 0 address
THC7984_rev.2.0_e 10 / 45 thine electronics, inc. copyright?2013 thine electronics, inc. r08 7 6 5 4 3 2 r/w 1 g-ch gain gain = (register value + 1024) / 2048 1r/w 0 2048 steps from x0.5 to x1.5 0r/w 0 *bi gger values mean higher gai n. r09 7 r/w 0 6r/w 0 5r/w 0 4r/w 0 3r/w 0 2r/w 0 1r/w 0 0r/w 0 r0a 7 6 5 4 3 2 r/w 1 b-ch gain gain = (register value + 1024) / 2048 1r/w 0 2048 steps from x0.5 to x1.5 0r/w 0 *bi gger values mean higher gai n. r0b 7 r/w 0 6r/w 0 5r/w 0 4r/w 0 3r/w 0 2r/w 0 1r/w 0 0r/w 0 r0c 7 6 5 4 3 2 1 0 r/w 0 r-ch clamp level offset 1 lsb of offset corresponds to 1 ls b of output code. r0d 7 r/w 0 -256 to +255 6r/w 0 *set in two's complement. 5r/w 0 4r/w 0 3r/w 0 2r/w 0 1r/w 0 0r/w 0 r0e 7 6 5 4 3 2 1 0 r/w 0 g-ch clamp level offset 1 lsb of offset corresponds to 1 ls b of output code. r0f 7 r/w 0 -256 to +255 6r/w 0 *set in two's complement. 5r/w 0 4r/w 0 3r/w 0 2r/w 0 1r/w 0 0r/w 0
THC7984_rev.2.0_e 11 / 45 thine electronics, inc. copyright?2013 thine electronics, inc. r10 7 6 5 4 3 2 1 0 r/w 0 b-ch clamp level offset 1 lsb of offset corresponds to 1 ls b of output code. r11 7 r/w 0 -256 to +255 6r/w 0 *set in two's complement. 5r/w 0 4r/w 0 3r/w 0 2r/w 0 1r/w 0 0r/w 0 r 12 7 r/w 0 reserved must be set to 0 6 r/w 0 reserved must be set to 0 5 r/w 1 input port automatic selection enable 0: disable 1: enable 4 r/w 0 reserved must be set to 0 3 a 0 input port 0: port-0 1: port-1 2 r/w 1 sync type automatic select enable 0: disable 1: enable 1 a 0 sync type select 00b: separate sync 01b: composite sync 0a 0 10b: sync on video (2-lelvel) 11b: sync on video (3-lelvel) r13 7 6 r/w 1 hsync input, vsync input polarity automatic selection enab le 0: disable 1: enable 5 a 0 hsync input polarity 0: active-low 1: active-high 4 a 0 vsync input polarity 0: active-low 1: active-high 3 r/w 1 hsync output, vsync output polarity automatic selection en able 0: disable 1: enable (output polarity is conformed to inpu t polarity) 2 a 0 hsync output (hsout) polarity 0: active-low 1: active-high 1 a 0 vsync output (vsout) polarity 0: active-low 1: active-high 0 r/w 1 vsync output (vsout) interlace mode 0: disable 1: enable r 14 7 r/w 0 hsync output (ho) start position set in 1 pixel steps wi th reference to the leading edge of hsync input 6r/w 0 -128 to +127 5r/w 0 *set in two's complement. 4r/w 0 3r/w 0 2r/w 0 1r/w 0 0r/w 0 r 15 7 r/w 0 hsync output (ho) pulse width set in 1 pixel steps 6r/w 0 1 to 255 5r/w 1 4r/w 0 3r/w 0 2r/w 0 1r/w 0 0r/w 0 r16 7 6 5 4 r/w 0 pll coast source 0: internal pll coast 1: external pll coa st 3 r/w 1 pll/clamp coast input polarity (if coast source is externa l) 0: active-low 1: active-high 2 r/w 0 clamp pulse source 0: internal clamp pulse 1: external cla mp pulse 1 r/w 1 clamp pulse input polarity (if coast source is external) 0: active-low 1: active-high 0 r/w 0 clamp coast source 0: internal clamp coast 1: external cla mp coast r17 7 6 r/w 1 clamp pulse start reference edge (pedestal clamp, midscale clamp) 0: the leading edge of hsync input 1: the trailing edge of hsync input 5 r/w 0 r-ch clamp mode 00b: pedestal clamp 01b: midscale clamp 4r/w 0 10b: reserved 11b: 256-level clamp 3 r/w 0 g-ch clamp mode 00b: pedestal clamp 01b: midscale clamp 2r/w 0 10b: reserved 11b: 256-level clamp 1 r/w 0 b-ch clamp mode 00b: pedestal clamp 01b: midscale clamp 0r/w 0 10b: reserved 11b: 256-level clamp
THC7984_rev.2.0_e 12 / 45 thine electronics, inc. copyright?2013 thine electronics, inc. r 18 7 r/w 0 clamp pulse start position set in 1 pixel steps with the reference edge of hsync input (r17[6]). 6r/w 0 0 to 255 5r/w 0 4r/w 0 3r/w 1 2r/w 0 1r/w 0 0r/w 0 r 19 7 r/w 0 clamp pulse width set in 1 pixel steps 6r/w 0 1 to 255 5r/w 0 4r/w 1 3r/w 0 2r/w 0 1r/w 0 0r/w 0 r1a 7 r/w 6 r/w 1 sog slicer hysterisis enable 0: disable 1: enable 5 r/w 1 sog input filter 00b: disable 01b: enable 4r/w 0 10b, 11b: reserved 3 r/w 0 sog slicer threshold set in 15mv steps 2r/w 1 15mv to 240mv above the sync tip 1r/w 0 0r/w 0 r 1b 7 r/w 0 sogout output polarity 0: active-low 1: active-high 6 r/w 0 sogout output signal 00b: raw hsync 01b: regenerated hsync 5r/w 0 10b: filtered hsync 11b: reserved 4 r/w 1 preamp bandwidth (low pass filter) 3r/w 1 2r/w 0 1r/w 1 0r/w 0 r 1c 7 r/w 0 output format 00b: 4: 4: 4 output 01b: 4: 4: 4 ddr outpu t 6r/w 0 10b: 4: 2: 2 output 11b: 4: 2: 2 ddr output 5 r/w 1 4:2:2 decimation filter enable 0: disable 1: enable 4 r/w 0 output clock (datack) 00b: pixel clock 01b: 1/2x pixel cloc k 3r/w 0 10b: internal oscillator (40mhz) 11b: reserved 2 r/w 1 output clock phase set in t/8 steps 1r/w 0 0 to 7/8t 0r/w 0 *bigger values mean more delay. r 1d 7 r/w 1 reserved must be set to 0 6 r/w 0 reserved must be set to 1 5 r/w 0 rgb data output drive strength 00b: weak 01b: medium 10b: s trong 11b: very strong 4r/w 1 3 r/w 0 sync (sogout/hsout/vsout/oefield) output drive strength 00b : weak 01b: medium 10b: strong 11b: very strong 2r/w 1 1 r/w 0 clock output drive strength 00b: weak 01b: medium 10b: stro ng 11b: very strong 0r/w 1 r 1e 7 r/w 0 hsout output signal 00b: ho 01b: regenerated hsync 10b: raw hsync 11b: filtered hsync 6r/w 0 5 r/w 0 vsout output signal 00b: vo 01b: regenerated vsync 10b: raw vsync 11b: filtered vsync 4r/w 1 3 r/w 0 o/e field output signal 000b: fo 001b: regenerated field 01 0b: de 011b: irq 2r/w 0 100b to 111b: reserved 1r/w 1 0 r/w 0 o/e field output polarity 0: odd fieldlow/even field=high 1: odd fieldhigh/even field=low r1f 7 6 r/w 0 reserved must be set to 0 5 r/w 0 reserved must be set to 0 4 r/w 1 pll hsync filter enable 0: disable (raw hsync) 1: enable ( filtered hsync) 3 r/w 0 hsync filter window width set in +/-100ns steps 2r/w 0 +/-100ns to +/-1600ns 1r/w 1 *bigger values mean wider window. 0r/w 1
THC7984_rev.2.0_e 13 / 45 thine electronics, inc. copyright?2013 thine electronics, inc. r 20 7 r/w 1 vsync output timing automatic setting enable (except ra w vsync) 0: disable 1: enable 6 a 0 vsync output (vo, regenerated vsync) start position set in 1 line steps 5a 0 -64 to +63 4a 0 *set in two's complement. 3a 0 *vsync output start position with reference to the leading edge of vsync input. 2a 0 1a 0 0a 0 r21 7 6 5 a 0 vsync output (vo, regenerated vsync) pulse width set in 1 lin e steps 4a 0 1 to 63 3a 0 2a 0 1a 0 0a 0 r 22 7 r/w 1 pll coast timing automatic setting enable 0: disable 1: enable 6 a 0 pll pre-coast (pll coast start position) set in 1 line steps 5 a 0 *pll free-runs during pll coast 0 to 127 4a 0 *pll coast start position prior to the leading edge of vsync in put. 3a 0 2a 0 1a 0 0a 0 r23 7 6 a 0 pll post-coast (pll coast end position) set in 1 line steps 5 a 0 *pll free-runs during pll coast 0 to 127 4a 0 *pll coast end position after the leading edge of vsync input. 3a 0 2a 0 1a 0 0a 1 r24 7 6 r/w 0 clamp pre-coast (clamp coast start position) set in 1 line steps 5 r/w 0 *clamp stops during clamp coast 0 to 127 4r/w 0 *clamp coast start position prior to the leading edge of vsync input. 3r/w 0 2r/w 1 1r/w 1 0r/w 0 r25 7 6 r/w 0 clamp post-coast (clamp coast end position) set in 1 line s teps 5 r/w 0 *clamp stops during clamp coast 0 to 127 4r/w 1 *clamp coast end position after the leading edge of vsync input . 3r/w 0 2r/w 1 1r/w 0 0r/w 0 r26 7 6 5 4 3 r/w 0 de start position set in 1 pixel steps 2r/w 0 *de start position after the leading edge of hsync input. 1r/w 0 0r/w 1 r27 7 r/w 0 6r/w 1 5r/w 1 4r/w 1 3r/w 0 2r/w 0 1r/w 0 0r/w 0
THC7984_rev.2.0_e 14 / 45 thine electronics, inc. copyright?2013 thine electronics, inc. r28 7 6 5 4 3 r/w 0 de width set in 1 pixel steps 2r/w 1 1r/w 0 0r/w 1 r29 7 r/w 0 6r/w 0 5r/w 0 4r/w 0 3r/w 0 2r/w 0 1r/w 0 0r/w 0 r2a 7 6 r/w 0 v-blank front porch (de low start position) set in 1 line s teps 5r/w 0 0 to 127 4r/w 0 *v-blank start position prior to the leading edge of vsync outp ut. 3r/w 0 2r/w 0 1r/w 0 0r/w 1 r2b 7 6 r/w 0 v-blank back porch (de low start position) set in 1 line st eps 5r/w 1 0 to 127 4r/w 0 *v-blank end position after the trailing edge of vsync output. 3r/w 0 2r/w 1 1r/w 1 0r/w 0 r2c 7 r 1 reserved 6r 1 5r 1reserved 4r 1 3 r 1 port-1 input sync type detection 00b: separate sync 01b: comp osite sync 2r 1 10b: sync on video 11b: no signal 1 r 1 port-0 input sync type detection 00b: separate sync 01b: comp osite sync 0r 1 10b: sync on video 11b: no signal r2d 7 6 5 4 3 2 r 0 vsync input polarity detection 0: active-low 1: active-high 1 r 0 hsync input polarity detection 0: active-low 1: active-high 0 r 0 sync on video 2-level/3-level detection 0: 2-level 1: 3-leve l r 2e 7 r 0 interlace detection 0: progressive 1: interlace 6 r 0 vertical total line measurement reports the number of vertica l total lines 5r 0 on the active input counted in 1/4 line unit. 4r 0 3r 0 2r 0 1r 0 0r 0 r2f 7 r 0 6r 0 5r 0 4r 0 3r 0 2r 0 1r 0 0r 0
THC7984_rev.2.0_e 15 / 45 thine electronics, inc. copyright?2013 thine electronics, inc. r 30 7 r 0 vsync input pulse width measurement reports the number of vsync pulse width 6r 0 on the active input counted in 1/4 line unit. 5r 0 4r 0 3r 0 2r 0 1r 0 0r 0 r31 7 6 5 4 3 2 r/w 0 reserved must be set to 0 1 r/w 0 reference clock enable from clamp-pin for hsync period mea surement 0: disable 1: enable 0 r/w 1 hsync period measurement run (must be stop before reading the result) 0: stop 1: run r32 7 6 5 4 3 r 0 hsync period measurement result 2r 0 1r 0 0r 0 r33 7 r 0 6r 0 5r 0 4r 0 3r 0 2r 0 1r 0 0r 0 r34 7 r 0 6r 0 5r 0 4r 0 3r 0 2r 0 1r 0 0r 0 r 35 7 evrc 0 sync signal valid flag 0: detect 1: not detect 6evrc 0 reserved 5evrc 0 reserved 4 evrc 0 port-1 input sync type change detection 0: detect 1: not d etect 3 evrc 0 port-0 input sync type change detection 0: detect 1: not d etect 2evrc 0 in p ut si g nal format chan g e detection 0: detect 1: not detec t 1 evrc 0 input hsync missing edge detection 0: detect 1: not detect 0 evrc 0 input hsync extraneous edge detection 0: detect 1: not det ect r 36 7 r/w 0 sync processor irq output enable by event recorder (r34 [7]) 0: disable 1: enable 6 r/w 0 reserved 5 r/w 0 reserved 4 r/w 0 sync processor irq output enable by event recorder (r34[4] )0: disable 1: enable 2 r/w 0 sync processor irq output enable by event recorder (r34[3] )0: disable 1: enable 2 r/w 0 sync processor irq output enable by event recorder (r34[2] )0: disable 1: enable 1 r/w 0 sync processor irq output enable by event recorder (r34[1] )0: disable 1: enable 0 r/w 0 sync processor irq output enable by event recorder (r34[0] )0: disable 1: enable r 37 7 r/w 0 input signal format change detection 000b: 0.5lines 001 b: 1line 010b: 2lines 011b: 4lines 6 r/w 0 - threshold of vertical total line change 100b: 8lines 10 1b: 16lines 110b: 32lines 111b: do not watching 5r/w 0 4 r/w 0 input signal format change detection 00b: 0.5lines 01b: 1l ine 10b: 4lines 11b: do not watching 2 r/w 0 - threshold of vsync input pulse width 2 r/w 0 input signal format change detection 000b: 8 001b: 16 010 b: 32 011b: 64 1 r/w 0 - threshold of hsync period 100b: 128 101b: 256 110b: 51 2 111b: do not watching 0r/w 0
THC7984_rev.2.0_e 16 / 45 thine electronics, inc. copyright?2013 thine electronics, inc. sync signal flow < sync processing block diagram > mux hsync filter pol mux pll mux sog slicer sync processor demux internal oscillator mux demux pol mux pol pol pol mux pol pol mux internal clamp pulse external clamp pulse clamp pulse external coast internal pll coast internal clamp coast clamp coast pll coast external clock external refclk fo regenerated field de irq vo regenerated vsync raw vsync ho regenerated hsync raw hsync filtered hsync regenerated hsync internal oscillator clock pll coast external clock hsync0 hsync1 vsync0 vsync1 sogin1 sogin0 clamp extclk/coast datack sogout hsout vsout o/e field 2-level sliced sogin0 2-level sliced sogin1 3-level sliced sogin pixel clock 1/2 x pixel clock pol mux csync csync r12[3]+r12[1:0] r13[5] r1f[4] r1c[4:3] r1b[6:5] r1b[7] r12[3]+r12[1:0] r13[4] r1e[7:6] r1e[5:4] r1e[3:1] r13[2] r13[1] r1e[0] r1e[0] r31[1] r16[1] r16[2] r04[1:0] r16[3] r16[4] r16[0] mux pol demux polarity select multiplexer demultiplexer mux mux pol filtered vsync mux raw hsync filtered hsync
THC7984_rev.2.0_e 17 / 45 thine electronics, inc. copyright?2013 thine electronics, inc. register function r00 revision code 21h can be read r01[4] chip power-on 1: all the circuits power-on for normal operation. 0: the chip is set to stand-by mode. in stand-by mo de, several circuits are ac tive for sync monitoring. stan-by mode can be triggered by rst-pin. * during the stand-by mode, all the output pins except sogout and sda are disable (hi-z) . r01[3] auto output enable 1: all the output pins are automatically enabled regardless of ?output enable except sogout (r01[2]) ? or ?sogout output enable (r01[1]) ? while input sync is detected. input sync detection is processed in sync processor. * output pins are red<9:0>, green<9:0>, blue<9:0>, datack, sogout, hsout, vsout, and o/e field r01[2] output enable (except sogout) 1: output pins except sogout-pin are enabled. r01[1] sogout output enable 1: sogout-pin is enabled. * when disabled, output pins are hi-z. * sda-pin is always enabled. r01[0] reserved * must be se t to 0 (default value: 0) < power control > r01[4] rst-pin status adc/pll serial interface sog slicer sync processor 1 low normal operation power-on power-on power-on power-on 1 high stand-by power-down power-on power-on power-on 0 low stand-by power-down power-on power-on power-on 0 high stand-by power-down power-on power-on power-on < output control > r01[3] r01[2] r01[1] input signal output signal except sogout sogout 0 0 0 inactive disable disable 000active disable disable 0 0 1 inactive disable enable 0 0 1 active disable enable 0 1 0 inactive enable disable 0 1 0 active enable disable 0 1 1 inactive enable enable 0 1 1 active enable enable 1 0 0 inactive disable disable 1 0 0 active enable enable 1 0 1 inactive disable enable 1 0 1 active enable enable 1 1 0 inactive enable disable 1 1 0 active enable enable 1 1 1 inactive enable enable 1 1 1 active enable enable
THC7984_rev.2.0_e 18 / 45 thine electronics, inc. copyright?2013 thine electronics, inc. r02[6:5] oversampling oversampling is the function that enables sampling an alog signals with higher rate than the pixel clock and downsampling to the pixel clock rate with the decimation filter. when setting it as oversampling, setting of the pll divider ratio (r02 [4:0] /r03 [7:0]) and the charge pump current (r04 [4:2]) is unnecessary, but it's necessary to change the vco frequency range (r04 [6:5]) . every time the oversampling setting is increased one step , vco frequency range also must be increased one step. 00b: normal operation 01b: 2x oversampling 10b: 4x oversampling 11b: 8x oversampling (ex) in case of 480i (hsync freque ncy: 15.75khz / pixel clock: 13.51mhz) oversampling(r02[6:5]) vco range(r04[6:5]) charge pump(r04[4:2]) 1x(00b) 1/8(00b) 250ua(011b) 2x(01b) 1/4(01b) 250ua(011b) 4x(10b) 1/2(10b) 250ua(011b) 8x(11b) 1/1(11b) 250ua(011b) * under the output of 4:4:4 ddr (r1c[7:6]=01b) or 4:2:2 ddr (r1c[7:6]=11b), the oversampling function can't be used. * ?internal pll divider ratio? can?t be over 8191. ?internal pll divider ratio? = pll divider ratio setting * oversampling setting * sampling frequency can?t be over 170mhz sampling frequency = input hsync frequency * pll divider ratio * oversampling setting * even if oversampling setting is changed, the output clock frequency and the output data rate don't change. * the latency of the data output chan ges according to the oversampling setting. r02[4:0]/r03[7:0] pll divider ratio the internal pll generates sampling clock from hsync. set the number of horizontal total pixels per line according to the input signal. *when the external clock input which is supplied through extclk/coast-pin is used as sampling clock (r04[1:0]=10b or 11b), pll divider ratio setting is unnecessary. r04[7] reserved *must be set to 1 (default value: 1) r04[6:5] vco frequency range *set according to ?recommended pll settings? r04[4:2] charge pump current *set according to ?reco mmended pll settings?
THC7984_rev.2.0_e 19 / 45 thine electronics, inc. copyright?2013 thine electronics, inc. r04[1:0] sampling clock source set to 00b, when the internal pll generates sampling clock (pixel clock) from the hsync input. when an external clock input supplied through extclk/coast-pin is used and the clock frequency is from 10 to 20mhz, set to 10b. when an external clock input supplied through extclk/coast-pin is used and the clock frequency is from 20 to 170mhz, set to 11b. * even though the external clock is used as sampling cloc k(r04[1:0]=10b or 11b) , setting like a recommended pll settings are necessary. * when the external clock is used as sampling clock(r04[ 1:0]=10b or 11b) , pll coast and clamp coast can not be input (r16[4]=1, r16[0]=1) . * other than the settings above, please refer to the other document, ?t hc7984 pll setting sheet?. r05[5:0] sampling clock phase the sampling clock phase can be shifted in 64 st eps of t/64. bigger values mean more delay. * even the external clock is used as sampling clock(r04[1:0]=10b or 11b) , the clock phase can be shifted. r06[2:0]/r07[7:0] r-ch (pr-ch) gain r08[2:0]/r09[7:0] g-ch (y-ch) gain r0a[2:0]/r0b[7:0] b-ch (pb-ch) gain the gain can be adjusted from 0.5 to 1.5 in 2048 steps. bigger value means higher gain. gain = (register value + 1024) / 2048 because the full scale of adc input is 0.7 vpp (typical va lue) , the gain is set to [0.7 / video signal level*]. * signal level without sync on video (vpp) example. video signal level: 0.5 vpp gain = 0.7/0.5 =1.4 register value=1843 video signal level: 0.7 vpp gain = 0.7/0.7 =1.0 register value=1024 video signal level: 1.0 vpp gain = 0.7/1.0 =0.7 register value=410 * the setting method above is not always necessary for the purpose of contrast adjustment . bigger gain means higher contrast. < recommended pll settings > r04[6:5] r04[4:2] r04[1:0] r04 r04[6:5] r04[4:2] r04[1:0] r04 480i 15.750 13.51 858 00 011 00 8c 00 000 10 82 480p 31.469 27.00 858 01 011 00 ac 01 000 11 a3 720p 45.000 74.25 1650 10 101 00 d4 10 000 11 c3 1080i 33.750 74.25 2200 10 100 00 d0 10 000 11 c3 1080p 67.500 148.50 2200 11 101 00 f4 11 000 11 e3 vga-60 31.479 25.18 800 01 011 00 ac 01 000 11 a3 vga-72 37.861 31.50 832 01 100 00 b0 01 000 11 a3 vga-75 37.500 31.50 840 01 100 00 b0 01 000 11 a3 vga-85 43.269 36.00 832 01 101 00 b4 01 000 11 a3 svga-56 35.156 36.00 1024 01 100 00 b0 01 000 11 a3 svga-60 37.879 40.00 1056 01 101 00 b4 01 000 11 a3 svga-72 48.077 50.00 1040 10 100 00 d0 10 000 11 c3 svga-75 46.875 49.50 1056 10 100 00 d0 10 000 11 c3 svga-85 53.674 56.25 1048 10 100 00 d0 10 000 11 c3 xga-60 48.363 65.00 1344 10 100 00 d0 10 000 11 c3 xga-70 56.476 75.00 1328 10 101 00 d4 10 000 11 c3 xga-75 60.023 78.75 1312 10 101 00 d4 10 000 11 c3 xga-80 64.000 85.50 1336 11 011 00 ec 11 000 11 e3 xga-85 68.677 94.50 1376 11 100 00 f0 11 000 11 e3 sxga-60 63.981 108.00 1688 11 100 00 f0 11 000 11 e3 sxga-75 79.976 135.00 1688 11 101 00 f4 11 000 11 e3 sxga-85 91.146 157.50 1728 11 101 00 f4 11 000 11 e3 uxga-60 75.000 162.00 2160 11 101 00 f4 11 000 11 e3 sampling clock: internal sampling clock: external hsync [khz] pixel rate pll divider
THC7984_rev.2.0_e 20 / 45 thine electronics, inc. copyright?2013 thine electronics, inc. r0c[0]/r0d[7:0] r-ch (pr-ch) clamp level offset r0e[0]/r0f[7:0] g-ch (y-c h) clamp level offset r10[0]/r11[7:0] b-ch (pb-ch) clamp level offset clamping restores dc level of the vide o signals. three clamp modes can be se lected; pedestal clamp, center clamp (midscale clamp) , and sync tip clamp (r17[5:4]/r17[3:2]/r17[1:0]) . it's possible to give an offset to the clamp level by the 1lsb unit by a clamp level offset. the register value is configured by two's complement from -256 to +255. r12[7:6] reserved *must be set to 00b (default value: 00b) r12[5] input port auto matic selection enable 1: selection input port (r12[3]) is done automatically. under automatic setting, with the judgement result of the i nput sync type by sync processor, an activated port is selected with the following rules. -when the selected port is activated, even if the other port becomes activated , selection of port doesn't change. -both ports are activate and one port wh ich is selected became inactivate, select ion of port changes to the other port. clamp level offset = 0 output code < clamp level offset > clamp level offset clamp level offset > 0 clamp level offset < 0 0 1023 (pedestal clamp) clamp level offset = 0 output code clamp level offset clamp level offset > 0 clamp level offset < 0 0 1023 (center clamp) 512 clamp level offset = 0 output code clamp level offset clamp level offset > 0 clamp level offset < 0 0 1023 (256-level clamp) 256
THC7984_rev.2.0_e 21 / 45 thine electronics, inc. copyright?2013 thine electronics, inc. r12[4] reserved * must be set to 0 (default value: 0) r12[3] input port select 0: port-0 is selected. port-0: hsync0, vsync0, rain0, gain0, sogin0, bain0 1: port-1 is selected. port-1: hsync1, vsync1, rain1, gain1, sogin1, bain1 r12[2] input sync type automatic select enable 1: input sync type select (r12[1:0]) is automatically set. when automatic select is enabled, input sync type select is determined by sync processor based on the result of input sync type detection(r2c[6:5]/r2c[4:3]/r2c[0]) . r12[1:0] input sync type select select the input sync type. the combination of input port select (r12[3]) and input sync type select (r12[1:0]) determines the input pin for hsync and vsync. *3-level sliced (pedestal slice) . r13[6] hsync input, vsync input po larity automatic select enable 1: hsync input polarity (r13[5]) and vsync input polarity (r13[4]) are automatically set. when automatic select is enabled, the sync input polarity is determined by sync processor based on the result of hsync input polarity detection (r2c[1]) and vsync input polarity detection (r2c[2]) . r13[5] hsync input polarity hsync input polarity must be correctly set for normal operation. set to 0 when the input polarity is active-low. set to 1 when the input polarity is active-high. * set to 0 when input sync type select is set to ?sync on video (3-level) ? (r12[1:0]=11b) . r13[4] vsync input polarity vsync input polarity must be correctly set for normal operation. set to 0 when the input polarity is active-low. set to 1 when the input polarity is active-high. < input port / sync type > r12[3] input port r12[1:0] sync type hsync input pin vsync input pin 0 port-0 00b separate sync hsync0 vsync0 0 port-0 01b composite sync hsync0 hsync0 0port-010b sync on video (2-level) sogin0 sogin0 0port-011b sync on video (3-level) sogin0* sogin0* 1 port-1 00b separate sync hsync1 vsync1 1 port-1 01b composite sync hsync1 hsync1 1port-110b sync on video (2-level) sogin1 sogin1 1port-111b sync on video (3-level) sogin1* sogin1*
THC7984_rev.2.0_e 22 / 45 thine electronics, inc. copyright?2013 thine electronics, inc. r13[3] hsync output, vsync output po larity automati c select enable 1: hsync output polarity (r13[2]) and vsync output polarity (r13[1]) are automatically set to the same polarity as the input. when automatic select is enabled, the sync output polarity is determined by sync processor based on the result of hsync input polarity detection (r2d[1]) a nd vsync input polarity detection (r2d[2]) . r13[2] hsync output (hsout) polarity select the hsync output polarity of hsout-pin. 0: output polarity is active-low. 1: output polarity is active-high. * the polarity of hsync availa ble from hsout-pin (ho, regenerated hsync) is selected. r13[1] vsync output (vsout) polarity select the vsync output polarity of vsout-pin. 0: output polarity is active-low. 1: output polarity is active-high. * the polarity of vsync available from vsout-pin (vo, regenerated vsync, raw vsync) is selected. r13[0] vsync output (v sout) interlace mode select the output mode of vsync ava ilable from vsout-pin (vo, regenerate d vsync) for interlaced video input. 1: vsync output (vo, regenerated vsync) is produced at the center of horizontal period when video field of interlaced video changes from odd field to even field. 0: vsync output is produced only at the start position of hor izontal period. consequently, the vertical total line number of interlaced video changes by 1 depending on video field. * the output mode of vsync available from vsout-pin (v o, regenerated vsync) is selected. raw vsync is not affected by this mode. * the edge of vsync output always occurs at the st art position of horizontal period for non-interlaced video (detection result: r2e[7]=0) . therefore, r13[0]=0 and r13[0]=1 produce the same result for non-interlaced video. input sync vsout (r13[0]=1) vsout (r13[0]=0) horizontal cycle input sync vsout (r13[0]=1) vsout (r13[0]=0) even field -> odd field odd field -> even field < vsout interlace mode > horizontal cycle
THC7984_rev.2.0_e 23 / 45 thine electronics, inc. copyright?2013 thine electronics, inc. r14[7:0] hsync output (ho) start position set the start position of ho available from hsout-pin in st eps of 1 pixel with reference to the leading edge of the hsync (it is the leading edge of the positive pulse when it is 3-level sync) . the register value is configured by two's complement from -128 to +127. * when the external clock input is used (r04[1:0]=10b or 11b) , minus number is prohibited. r15[7:0] hsync output (ho) pulse width set the pulse width of ho available from hsout-pin in steps of 1 pixel. r16[4] pll coast source pll should stop synchronization with the hsync input during the vertical blank time including the pulses disturbing pll lock and the sampling clock generation such as equali zation pulses and copy protect ion signal. pll coast signal causes pll to stop synchronization with the hsync input and free-run. 0: pll coast signal is internally generated in the device. 1: pll coast signal can be externally input from coast-pin. * when pll coast signal is internally generated, automatic setting mode (r22[7]) is available. r16[3] pll coast input polarity select the input polarity of pll coast signal when externally input (r16[4]=1) . set to 0 when the input polarity is acti ve-low (pll free-runs at coast-pin=low) . set to 1 when the input polarity is acti ve-high (pll free-runs at coast-pin=high) . r16[2] clamp pulse source select the generation source of clamp pulse which is a timing signal of a clamp 0: the clamp pulse is generated internally. 1: clamp pulse must be inputted through clamp-pin. r16[1] clamp pulse input polarity select input polarity when the extern al clamp pulse is used (r16[2]=1). 0: input polarity becomes active-low. 1: input polarity becomes active-high. input hsync ho (start position < 0) ho (start position > 0) start position start position pulse width < ho start position / pulse width > input hsync ho (start position < 0) ho (start position > 0) start position start position pulse width hsync / csync / sync on video (2-level) sync on video (3-level)
THC7984_rev.2.0_e 24 / 45 thine electronics, inc. copyright?2013 thine electronics, inc. r16[0] clamp coast source it's sometimes necessary to make the cl amp suspend while the period which is including the signals that disturb the clamp such as a copy protection si gnal. the clamp coast signal is the signal which makes the clamp stop. 0: internal clamp coast 1: external clamp coast r17[6] clamp pulse start reference edge the timing of clamp pulse is set based on the edge of the hsync input. selecting the edge of the hsync input 0: the leading edge of the hsync input is referred. 1: the trailing edge of the hsync input is referred. * in case of 3-level sync, the leading edge or trailing edge of the positive pulse is referred. r17[5:4] r-ch (pr-ch) clamp mode r17[3:2] g-ch (y-ch) clamp mode r17[1:0] b-ch (pb-ch) clamp mode as a clamp method, pede stal clamp, midscale clamp, and 256-level clamp can be selected. 00b: pedestal clamp for rgb and y (lumin ance) clamps black level to 0 with au tomatic offset cancel (if clamp level off- set is set to 0) . the automatic offset can cel circuitry eliminates any offset errors. 01b: midscale clamp for pbpr clamps to 512 with automatic offset cancel (if clamp level offset is set to 0) . the automatic offset cancel circuitr y eliminates any offset errors. 10b: reserved 11b: 256-level clamp clamps to 256 with automatic offset cancel (if clamp level offs et is set to 0). the automatic offset cancel circuitry eliminat es any offset errors. * it's possible to set a clamp pulse on sync part and reali ze sync tip clamp by a pedestal cl amp (r17 [5:4], r17 [3:2] and r17 [1:0] =00b) . r18[7:0] clamp pulse start position set the clamp pulse start position in steps of 1 pixel with reference to clamp pulse start reference edge (selected by r17[6]) . r19[7:0] clamp pulse width set the clamp pulse width in steps of 1 pixel. * when the register is set to 0, clamp pulse is not generated. * set the end position of clamp pulse (r18[7:0] + r19[7:0]) more than 16 pixels front of active video period because clamp offset cancel is completed af ter 16 pixels from the clamp pulse.
THC7984_rev.2.0_e 25 / 45 thine electronics, inc. copyright?2013 thine electronics, inc. r1a[6] sog slicer hysterisis enable 1: sog slicer works with about 30mv hysteresis. r1a[5:4] sog input filter sog input filter (low pass filter) can reduce th e noise and the ringing, etc. of sog input. 00b: off (through) 01b: on 10b,11b: reserved *the default value is 10b(reserved) , so please change the setting to 00b (off) or 01b (on) . r1a[3:0] sog slicer threshold when input sync type select is set to ?sync on video (2 -level) ? (r12[1:0]=10b) , inpu t signal from sogin0 or sogin1 is sliced at the selected level by r1a[3:0] relative to the lowest level (sync tip) to extract the sync signal. sog slicer threshold can be adjusted from15 mv to 240 mv in steps of 15 mv. *set the value of sog slicer threshold to 3 and over. input hsync clamp pulse (r17[6]=0) start position start position pulse width < clamp pulse start position / pulse width > input hsync start position start position pulse width hsync / csync / sync on video (2-level) sync on video (3-level) clamp pulse (r17[6]=1) clamp pulse (r17[6]=0) clamp pulse (r17[6]=1) sog slice level (r1a[3:0]) sync on video extracted sync < sog slicer >
THC7984_rev.2.0_e 26 / 45 thine electronics, inc. copyright?2013 thine electronics, inc. * *when setting the input sync signal as sync on video (2-level ) at the time of 3-level sync signal input, (r12 [1:0], =10b) , it is sliced by the sog slicer threshold. r1b[7] sogout output polarity select the output polarity of sogout-pin. 0: output polarity is active-low. 1: output polarity is active-high. * the polarity of signals available from sogout-pin (raw hsync, regenerated hsync, and filtered hsync) is selected. r1b[6:5] sogout output signal select the output signal from sogout-pin. the source signal of the output is hsync se lected by the combination of input port select (r12[3]) and input sync type select (r12[1:0]) . 00b: raw hsync --- buffered signal of the hsync input. 01b: regenerated hsync --- this hsync is generated by using the internal oscillator (about 40 mhz) from raw hsync. it has jitter of several internal oscillator clock cycles. 10b: filtered hsync --- by the hsync f ilter, the pulses which are not related to horizontal period is eliminated. 11b: reserved sync on video (2-level) sync on video (3-level) sync on video extracted sync sync on video extracted sync sliced at pedestal level sliced at sog slice level (r1a[3:0]) <2-level slice / 3-level slice> input hsync raw hsync regenerated hsync filtered hsync < output signal from sogout> horizontal period
THC7984_rev.2.0_e 27 / 45 thine electronics, inc. copyright?2013 thine electronics, inc. r1b[4:0] pre-amp bandwidth (low pass filter) the THC7984 has the internal 5th-order low pass filters as anti-aliasing filter for component video input (ypbpr) , and it's possible to control cut-off frequency in 24 steps between 6 to 92mhz by setting the register. the THC7984 also has the internal 2nd-order low pass filters to filter the noise and glitch of pc input (rgb) , and it's possible to control cut-off frequency in 4 steps (40 mhz/90 mhz/170 mhz/310 mhz) by setting the register. *setting example component video input: about 0.5 times of the sampling frequency is used as cut-off frequency. pc input: about 1.5 times of the sa mpling frequency is used as cutoff frequency. *when r54[4] is set to 1, it's possible to cont rol the cut-off frequency of a 5th-order lowpass filter in steps of 1mhz between 25mhzto 39mhz by using register r54 [3:0]. in this case, r1b [4:0] is ignored. < preamp bandwidth> analog input preamp output (adc input) < cutoff frequency > dec dec 0 0 0 0 0 0 6mhz 16 1 0 0 0 0 39mhz 1 0 0 0 0 1 7mhz 17 1 0 0 0 1 42mhz 2 0 0 0 1 0 8mhz 18 1 0 0 1 0 46mhz 3 0 0 0 1 1 9mhz 19 1 0 0 1 1 52mhz 4 0 0 1 0 0 10mhz 20 1 0 1 0 0 58mhz 5 0 0 1 0 1 11mhz 21 1 0 1 0 1 66mhz 6 0 0 1 1 0 12mhz 22 1 0 1 1 0 78mhz 7 0 0 1 1 1 13.5mhz 23 1 0 1 1 1 92mhz 8 0 1 0 0 0 15mhz 24 1 1 0 0 0 40mhz 9 0 1 0 0 1 18mhz 25 1 1 0 0 1 90mhz 10 0 1 0 1 0 21mhz 26 1 1 0 1 0 170mhz 11 0 1 0 1 1 24mhz 27 1 1 0 1 1 310mhz 12 0 1 1 0 0 27mhz 28 1 1 1 0 0 13 0 1 1 0 1 30mhz 29 1 1 1 0 1 14 0 1 1 1 0 33mhz 30 1 1 1 1 0 15 0 1 1 1 1 36mhz 31 1 1 1 1 1 note fc note reserved 5th-order lpf for component video 5th-order lpf for component video 2nd-order lpf for pc reserved reserved reserved binary r1b[4:0] r1b[4:0] fc binary < cutoff frequency > dec 0 0000 25mhz 1 0001 26mhz 2 0010 27mhz 3 0011 28mhz 4 0100 29mhz 5 0101 30mhz 6 0110 31mhz 7 0111 32mhz 8 1000 33mhz 9 1001 34mhz 10 1010 34mhz 11 1011 35mhz 12 1100 36mhz 13 1101 37mhz 14 1110 38mhz 15 1111 39mhz r54[3:0] binary fc note 5th-order lpf for component video
THC7984_rev.2.0_e 28 / 45 thine electronics, inc. copyright?2013 thine electronics, inc. r1c[7:6] output format 4 output formats can be selected. 00b: 4:4:4 output 01b: 4:4:4 ddr output 10b: 4:2:2 output 11b: 4:2:2 ddr output * 4:4:4 ddr output and 4:2:2 ddr output are supported up to 85 mhz of sampling clock. * the pins not assigned to output data are disabled (hi-z) . < 4:4:4 normal output > * datack can be shifted in 8 steps (r1c[2:0]) . < 4:4:4 ddr output > * "m" indicates upper 5 bits in msb side. "l" indicates lower 5 bits in lsb side. * datack can be shifted in 8 steps (r1c[2:0]) . edge987654321098765432109876543210 normal normal cb/cr y 4:2:2 cb/cr y ddr g[4:0] b[9:0] r[9:0] g[9:5] blue output format 4:4:4 r[9:0] g[9:0] b[9:0] ddr red green red[9:0] green[9:0] blue[9:0] datack r0 r1 r2 r3 r4 r5 g0 g1 g2 g3 g4 g5 b0 b1 b2 b3 b4 b5 ho, de start position = even ho, de ho, de start position = odd r1c[4:3]=00b r1c[2:0]=000b red[9:5] red[4:0] green[9:5] g0l r0m r2m r3m r4m r5m r1m b0l r2l r3l r4l r5l r1l g1l g2l g3l g4l g5l g1m g2m g3m g4m g5m b1l b2l b3l b4l b5l r0l g0m b0m b1m b2m b3m b4m b5m datack ho, de start position = odd ho, de start position = even ho, de r1c[4:3]=00b r1c[2:0]=000b
THC7984_rev.2.0_e 29 / 45 thine electronics, inc. copyright?2013 thine electronics, inc. < 4:2:2 normal output > * datack can be shifted in 8 steps (r1c[2:0]) . < 4:2:2 ddr output > * datack can be shifted in 8 steps (r1c[2:0]) . r1c[5] 4:2:2 decima tion filter enable set the way of downsampling (process of changing from 4:4:4 to 4:2:2) of cbcr in 4:2:2 output and 4:2:2 ddr output 0: cbcr is sampled every two pixel by pixel skipping. 1: cbcr is decimated by digital filter. cb0 cr0 cb2 cr2 cb4 cr4 y0 y1 y2 y3 y4 y5 red[9:0] green[9:0] datack ho, de ho, de start position = even ho, de start position = odd r1c[4:3]=00b r1c[2:0]=000b cb0 y0 cr0 y1 cb2 y2 cr2 y3 cb4 y4 cr4 y5 blue[9:0] datack ho, de start position = odd ho, de start position = even ho, de r1c[4:3]=00b r1c[2:0]=000b
THC7984_rev.2.0_e 30 / 45 thine electronics, inc. copyright?2013 thine electronics, inc. r1c[4:3] output clock select select a output signal from datack-pin. 00b: pixel clock: the same frequency as the sampling clock 01b: 1/2 x pixel clock: half the frequency of the sampling clock 10b: internal oscillator (approximately 40 mhz) 11b: reserved r1c[2:0] output clock phase since the output clock phase can be shifted in 8 steps, the setup and hold time of output data can be adjusted. * if dataclk is pixel clock(r1c[4:3]= 00b) , phase setteing 0-2 is not recommended to use (except for ddr output) because rising edge of output clock will be around the transition period of output data. * the phase of internal oscillator clock (r1c[4:3]=10b) can not be controlled. * when oversampling setting is 8 times, the output clock pahse is possible to set in only 4 steps. (the value of 0 and 1 , 2 and 3, 4 and 5, 6 and 7 will be the same phase setting.) ho, de start position =even ho, de start position =odd output data (normal output) ho, de r1c[2:0]=0 r1c[2:0]=1 r1c[2:0]=2 r1c[2:0]=3 r1c[2:0]=4 r1c[2:0]=5 r1c[2:0]=6 r1c[2:0]=7 r1c[2:0]=0 r1c[2:0]=1 r1c[2:0]=2 r1c[2:0]=3 r1c[2:0]=4 r1c[2:0]=5 r1c[2:0]=6 r1c[2:0]=7 datack: pixel clock datack: 1/2 x pixel clock output data (ddr output) < datack phase shift>
THC7984_rev.2.0_e 31 / 45 thine electronics, inc. copyright?2013 thine electronics, inc. r1d[7:6] reserved *must be set to 01b for proper operation (default value: 10b) r1d[5:4] rgb data output drive strength output pins: red<9:0>, green<9:0>, blue<9:0> r1d[3:2] sync output drive strength output pins: sogout, hsout, vsout, o/e field r1d[1:0] clock output drive strength output pins: datack bigger values mean stronger output drive strength. * output drive strength should be adju sted according to the load capacitance, the trance length on pcb, and the power supply voltage of output buffer (vdd) . * clock output drive strength is stronger than others. r1e[7:6] hsout output signal select select a output signal from hsout-pin. 00: ho --- hsync generated from the hsync input, and synchronous with the pll clock. output polarity (r13[2]) , start position (r14[7:0]) , and puls e width (r15[7:0]) can be selected by the register setting. pll parameter settings (r02 to r04) are necessary for normal output. ho can be used as a reference of the image (rgb data) alignment. 01: regenerated hsync --- hsync generated from the hsync input, and synchronous with the internal oscillator clock (approximately 40 mhz) . the start position is delayed so me internal oscillator clock cy cles after the leading edge of the hsync input, and the pulse width is approximately 1/16 of horizontal period. the polarity is selected by register (r13[2]) . pll parameter settings (r02 to r04) are unnece ssary for normal output. it has jitter of several internal oscillator clock cycles. 10b: raw hsync --- buffered signal of the hsync input. 11b: filtered hsync --- the raw hsync?s pulse which is not relate to horizontal period is removed by the hsync filter (r1f[3:0]. input vsync ho regenerated hsync < output signal from hsout> horizontal period raw hsync filtered hsync
THC7984_rev.2.0_e 32 / 45 thine electronics, inc. copyright?2013 thine electronics, inc. r1e[5:4] vsout output signal select select a output signal from vsout-pin. 00b: vo --- vsync generated from the hsync and vs ync input, and synchronous with the pll clock. output polarity (r13[1]) , start position (r20[6:0]) , and pulse width (r21[5:0]) can be select by the register setting (auto setting modes are availa ble) . pll parameter settings (r02 to r04) are necessary for normal output. it is synchronous with ho. 01b: regenerated vsync --- vsync generated from the hsync and vsync input, and synchronous with the internal oscillator clock (approximately 40 mhz) . output po larity (r13[1]) , start position (r20[6:0]) , and pulse width (r21[5:0]) can be selected by the re gister setting (auto setting modes are available) . pll parameter settings (r02 to r04) are unnecessary for normal output. it has jitter of seve ral internal oscillator clock cycles. it is synchronous with regenerated hsync. 10b: raw vsync --- buffered signal of the vsync input 11b: filtered vsync --- vsync generated from the hsync and vsync input, and digitally filtered with the internal oscillator clock (approximately 40 mhz). it's possible to set polarity (r13 [1]) by register. (an automatic setting mode is available.) it's generated regardless of pl l setting (r02-r04). it has jitter of severa l internal oscillator clock cycles. the output phase is delayed about 3/4 h to input vsync. input vsync vo regenerated vsync < output signal from vsout> horizontal period raw vsync filtered vsync
THC7984_rev.2.0_e 33 / 45 thine electronics, inc. copyright?2013 thine electronics, inc. r1e[3:1] o/e field output signal select select a output signal from o/e field-pin. 000b: fo --- odd / even field generated from the hsync and vsync input, and synchronous with the pll clock. output polarity (r1e[0]) can be select by the register setting. pll parameter settings (r02 to r04) are necessary for normal output. it is synchronous with vo. 001b: regenerated field --- odd / even field generate d from the hsync and vsync input, and synchronous with the internal oscillator clock (approximately 40 mhz) . output polarity (r1e[0]) can be sel ected by the register setting. pll parameter settings (r02 to r04) are unnecessary for norm al output. it has jitter of several internal oscillator clock cycles. it is synchronous with regenerated vsync. 010b: de --- data enable signal generated from the hs ync and vsync input, and synchronous with the pll clock. the polarity is active-high. start position (r26[3:0]/r27[7:0 ]) , pulse width(r28[3:0]/r29[7:0]) , vertical blank front porch (r2a[6:0]) and back porch (r2b[6:0]) are program mable by registers (auto setting modes are not available) . 011b: irq --- interrupt request signal from sync processor. 100b - 111b: reserved r1e[0] o/e field output polarity select the polarity of fo and regenerated field available from o/e field-pin 0: o/e field=low in odd field, o/e field=high in even field. 1: o/e field=high in odd field, o/e field=low in even field. vsync input fo regenerated field < fo / regenerated field> horizontal period sync input field (r1e[0]=0) < fo / regenerated field> horizontal period input sync field (r1e[0]=1) field (r1e[0]=1) field (r1e[0]=0) odd field -> even field even field -> odd field horizontal period
THC7984_rev.2.0_e 34 / 45 thine electronics, inc. copyright?2013 thine electronics, inc. r1f[6:5] reserved *must be set to 00b for proper operation (default value: 00b) r1f[4] pll hsync filter enable by using filtered hsync generated by hsync filter that elim inates the extraneous pulses such as equalization pulses and copy protection signal from the hsync input (raw hs ync) , the pll coast period (pll free-run period) can be set shorter. however, the hsync input with high jitter makes hsync filter window unstable and possibly causes pll unlock. 0: raw hsync is used as the reference signal of pll. 1: filtered hsync is used as the reference signal of pll. r1f[3:0] hsync filter window width set hsync filter window width of hsync filter. the settin g range is from about +/-100ns (internal oscillator clock +/-4 cycles) to about +/-1600ns (internal oscillator cloc k +/-64 cycles) around the leading edge of the hsync input (the leading edge of the positive pulse for 3-level sync) . th e setting step is +/-100ns (internal oscillator clock +/-4 cycles) and bigger value results in wider width. input hsync leading edge input hsync with extraneous pulses excessive edge suppressed filter window width filter window filtered hsync filter window = high: not suppressed filter window = low: falling edges are suppressed < hsync filter > *input hsync into hsync filter is always active-low
THC7984_rev.2.0_e 35 / 45 thine electronics, inc. copyright?2013 thine electronics, inc. *about timing of input vsync when the transition of vsync is in ?input vsync forbidden re gion?, it is possible that following vertical timing fluc- tuates about one line. vsync output (vo, regenerated vsync ) ---setting register: r20[6:0]/r21[5:0] pll coast timing ---setting register: r22[6:0]/r23[6:0] clamp coast timing ---setting register: r24[6:0]/r25[6:0] de restraint period ---setting register: r2a[6:0]/r2b[6:0] the edge of input vsync must be outside "input vsync fo rbidden region" to prevent fluctuation of these vertical timing. r20[7] vsync output (vo, regenerated vs ync) timing automatic setting enable when set to 1, vsync output start position (r20[6:0]) a nd vsync output pulse width (r21[5:0]) are automatically set to match the vsync input timing. the vsync output start position is set to 0 and the vsync output pulse width is determined by sync processor based on the result of vsync input pulse width measurement (r2f[7:0]). r20[6:0] vsync output (vo, re generated vsync) start position the starting position of vo and regenerated vsync, which are the possible output from vsout-pin, is set in steps of 1 line based on leading edge of input vsync. the set value is expressed by complement of 2 and the set range is from - 64 to +63. r21[5:0] vsync output (vo, re generated vsync) pulse width the pulse width of vo and regenerated vsync, which are the possible output from vsout-pin, is set in steps of 1 line. 0% 15% 35% 65% 85% 100% input hsync input vsync input vsync forbidden region input vsync forbidden region input vsync < output vsync start position / pulse width > horizontal period (r20[6:0]= -1) output vsync (r20[6:0]= 0) (r20[6:0]= +1) output vsync pulse width output vsync output vsync
THC7984_rev.2.0_e 36 / 45 thine electronics, inc. copyright?2013 thine electronics, inc. r22[7] pll coast timing automatic setting enable pll should stop synchronization with the hsync input during the vertical blank time including the pulses disturbing pll lock and the sampling clock generation such as equali zation pulses and copy protect ion signal. pll coast signal causes pll to stop synchronization with the hsync input and free-run. 1: pll pre-coast (r22[6:0]) and pll post-coast (r23[6:0]) are automatically set pll coast period generated by automatic setting is depend on the setting of pll hsync filter enable (r1f[4]) . * when hsync filter is disabled (r1f[4]=0) , the pl l coast period covers the period including extraneous and missing pulses in vertical blank time. * even in the case input sync type is set to ?separate sync? (r12[1:0]=00b) , the pll coast signal covers the vsync pulse period. * when hsync filter is enabled (r1f[4]=1) , the pl l coast period covers the vsync pulse period because extraneous pulses are elim inated by hsync filter. r22[6:0] pll pre-coast set the start position of pll coast in steps of 1 line with reference to the leading edge of the vsync input. r23[6:0] pll post-coast set the end position of pll coast in steps of 1 line wi th reference to the leadin g edge of the vsync input. input hsync raw hsync pll coast filtered hsync < pll coast auto mode> horizontal period hsync filter disable (r1f[4]=0 ) hsync filter enable (r1f[4]=1 ) pll coast input vsync pll coast < pll coast timing> horizontal period pll pre-coast pll post-coast
THC7984_rev.2.0_e 37 / 45 thine electronics, inc. copyright?2013 thine electronics, inc. r24[6:0] clamp pre-coast clamp should be suspended during the vertical blank time including the pulses disturbing clamp such as copy protection signal. clamp coast signal causes clamp to be suspend. set the start position of clamp coast in steps of 1 line with reference to the leadi ng edge of the vsync input. r25[6:0] clamp post-coast set the end position of clamp coast in steps of 1 line with reference to the leading edge of the vsync input. * clamp coast timing is related to a 3-level slicer. in cas e that sync type select is "sync on video (3-level) " (r12[1:0]=11b) , clamp coast timing should cover vsync pulse (and the period which includes equalization pulses in interlace signal) , and end at least 12 lines prio r to the active line start. (setting example: clamp pre- coast=2 / clamp post-coast=8). r26[3:0] / r27[7:0] de start position set the start position of de (data enable) available from o/e field-pin in steps of 1 pixel with reference to the leading edge of the hsync input (the leading edge of the positive pulse for 3-level sync) . r28[3:0] / r29[7:0] de pulse width set the pulse width of de (data enable) available from o/e field-pin in steps of 1 pixel. the output polarity of de is active-high. r2a[6:0] v-blank front porch (de end line position) set the end line of de (data enable) av ailable from o/e field-pin in steps of 1 line with reference to the vsync output start position (r20[6:0]) . r2b[6:0] v-blank back porc h (de start line position) set the start line of de (data enable) available from o/e field-pin in steps of 1 line with reference to the vsync output end position (r20[6:0]+r21[5:0]) . analog input clamp coast < clamp coast timing> horizontal period clamp pre-coast clamp post-coast de input hsync de pulse width de start position < de horizontal timing> input vsync output vsync < v-blank front porch / v-blank back porch > horizontal period de v-blank front porch v-blank back porch output vsync pulse width
THC7984_rev.2.0_e 38 / 45 thine electronics, inc. copyright?2013 thine electronics, inc. r2c[3:2] port-1 input sync type detection r2c[1:0] port-0 input sync type detection the result of input sync type detection can be read. r2d[2] vsync input polarity detection the result of vsync input polarity detection can be read. 0: input polarity is active-low. 1: input polarity is active-high. r2d[1] hsync input polarity detection the result of hsync input polarity detection can be read. 0: input polarity is active-low. 1: input polarity is active-high. r2d[0] sync on video 2-level / 3-level detection when the result of input sync type detection of the sel ected input port (r12[3]) is sync on video (r2c[6:5], r2c[4:3]=10b) , the result of sync on video 2-level / 3-level detection can be read. 0: sync on video is 2-level. 1: sync on video is 3-level. * when input sync type is not sync on video, 0 can be read. r2e[7] interlace detection the result of interlace detection detected by the hsync and vsync input can be read. 0: input signal is non-interlace (progressive) . 1: input signal is interlace. r2e[6:0] / r2f[7:0] vertical total line measurement the result of vertical total line measurement measured by the hsync and vsync input can be read in 1/4 line unit. r30[7:0] vsync input pulse width measurement the result of vsync input pulse width measurement measur ed by the hsync and vsync input can be read in 1/4 line unit. r31[2] reserved * must be set to 0 (default value: 0) r31[1] external refclk input enable 1: it is possible to measure the horizont al period (r32[3:0] / r33[7:0] / r34[7:0]) by inputting clock which is 7 - 40 mhz to clamp-pin. the frequency precision of the input clock in fluences a result of measurement directly, so please input the clock with the high frequency precision. * if the external refclk input is enable (r31[1]=1) , the function of external clamp pulse (r16[2]) can not be used. < input sync type detection > hsync vsync sogin input sync type r2c[3:2] r2c[1:0] not active not active not active no signal 11b not active not active active sync on video 10b not active active not active no signal 11b not active active active sync on video 10b active not active not active composite sync 01b active not active active composite sync 01b active active not active separate sync 00b active active active separate sync 00b
THC7984_rev.2.0_e 39 / 45 thine electronics, inc. copyright?2013 thine electronics, inc. r31[0] hsync period measurement run 0: stop the measurement of hsync period. 1: start measurement of hsync period. (a result of measurement is renewed every 100 lines.) . *when reading the result of measurement (r32[3:0] / r33[7:0] / r34[7:0]) , please suspend measurement. r32[3:0]/r33[7:0]/r34[7:0] hs ync period measurement result the period of 100 lines of horizontal period is counted by external refclk and the result can be read. the horizontal period and frequency are calculated by the following formula. horizontal period [us] = meas urement result / (100 * frefclk) horizontal frequency [khz] = frefclk * 10 5 / measurement result * frefclk is refclk frequency (unit :mhz) *input a reference clock (7-40mhz) to clamp-pin to m easure period of horizontal, and the setting of external ref- clk input should be enabled(r31[1]=1) . *stop the measurement after more than 20ms(or more than 300 lines) from the start of measurement of horizontal period (r31[0]=1), and read the result(r32[3:0] / r33[7:0] / r34[7:0]) . r35[7] sync signal valid flag (event recorder) 1 is set when hsync and vsync are det ected in input sync. at this point, all the measurement and detection are completed. r35[4] port-1 input sync type ch ange detection (event recorder) r35[3] port-0 input sync type ch ange detection (event recorder) 1 is set when port-1 input sync type detection (r2c[6:5]) , port-0 input sync type detection (r2c[4:3]) changes. r35[2] input signal format change detection when following even one detection and re sult of measurement changed, 1 is set hsync input pola rity detection vsync input pola rity detection vertical total line measurement (change detection threshod(r37[7:5]) default setting is +/-1 line) vsync input pulse width measurement (change detection threshold (r37 [4:3]) default setting:+/- 1 line.) hsync period measurement (change detection threshold (r37 [2:0]) default setting:+/- 64) *it's possible to detect the switching of seamless input fo rmat change of which the input sync type doesn't change. r35[1] input hsync missing edge detection (event recorder) 1 is set when hsync edges are not detected inside the pr ospective period. the pll coas t period (r22[6:0]/r23[6:0]) is not the subject of detection. * in case input sync signal includes no pulses during the vertical sync time such as or-type csync, these missing pulses should be covered by pll coast signal. r35[0] input hsync extraneous ed ge detection (event recorder) ?1? is read when hsync edges are detected outside the prospective period. the pll coast period (r22[6:0]/ r23[6:0]) is not the subject of detection. * in case input sync signal includes extr aneous pulses such as equalization pulses and copy protection signal during the vertical blank time, these pulses should be covered by pll coast signal or eliminated by hsync filter (r1f[4]) . * event recorders must be cleared by writing 1 to them to start th e measurement and detection by them.
THC7984_rev.2.0_e 40 / 45 thine electronics, inc. copyright?2013 thine electronics, inc. r36[7]/r36[4:0] sync processor irq output enable by event recorder 1: when corresponding bit of event recorders r34[5:0] is set to 1, interrupt request is triggered. interrupt request signal is available from o/e field-pin (r1e[3:1]=011b) . r37[7:5] input signal format change detection---threshold of vertical total line change set the change detection threshold of vertical total line for input signal format change detection (r35[2]). when the result of vertical total line measurement (r2e[6:0] / r2f[ 7:0]) change more than this value, r35[2] will be 1. 000b: 0.5 lines 001b: 1 line 010b: 2 lines 011b: 4 lines 100b: 8 lines 101b: 16 lines 110b: 32 lines 111b: do not observe the change r37[4:3] input signal format change detection---threshold of vsync input pulse width set the change detection threshold of vsync input pulse width for input signal format change detection (r35[2]). when the result of vsync input pulse widt h measurement (r30[7:0]) change more than this value, r35[2] will be 1. 00b: 0.5 lines 01b: 1 line 10b: 4 lines 11b: do not observe the change r37[2:0] input signal fo rmat change detection---t hreshold of hsync period set the change detection threshold of vsync input pulse width for input signal format change detection (r35[2]). when the result of vsync input pulse wi dth measurement (r32[3:0]/r33[7:0]/r34[7:0]) change more than this value, r35[2] will be 1. 000b: 8 001b: 16 010b: 32 011b: 64 100b: 128 101b: 256 110b: 512 111b: do not observe the change r39[7:2] reserved *must be set to 111111b for proper operation (default value: 111111b) r39[1] sog slicer port 1 (sogin1) power-on r39[0] sog slicer port 0 (sogin0) power-on when the sog slicer is not used, it?s possible to be powered down. when making only sog slicer port 1 to be powered down, set r39=fdh when making only sog slicer port 0 to be powered down, set r39=feh when making both of sog slicer port to be powered down, set r39=fch. *r38 and the registers after r 39 are for test purpose. don?t wr ite values to these registers. < sync processor irq enable > event recorder ev ent irq enable r35[7] sync signal valid flag r36[7] r35[6] reserved r36[6] r35[5] reserved r36[5] r35[4] port-1 input sync ty pe change detection r36[4] r35[3] port-0 input sync ty pe change detection r36[3] r35[2] input signal format change r36[2] r35[1] input hsync missing edge detection r36[1] r35[0] input hsync extraneous edge detection r36[0]
THC7984_rev.2.0_e 41 / 45 thine electronics, inc. copyright?2013 thine electronics, inc. note1. power-down / reset - when it is not used, set this pin to low. (e.g., pull-down to gnd by a resistor (10kohm) ) . - rst-pin is not made pull-up or pull-down inside of device. note2. device address setting pull-down vsout/a0-pin to gnd by a resistor (10kohm) : device address will be 1001100. pull-up vsout/a0-pin to vdd by a resistor (10kohm) : device address will be 1001101. - in case of pull-up, conn ect a resistor to vdd. - don?t connect vsout/a0-pin to the input pin with bus hold circuit of the subsequent device (device address can?t be acquired properly). - vsout-pin is not made pull-up or pull-down inside the device, so please be sure to connect the resistor to this pin. note3. sync signal input - the outside circuit should be designed not to apply higher voltage above absolute maximum rating (pvd+3.6v) to the digital input pins when power is not supplied, - fix the input level when there is no sync signal on the sync input pins (e.g., pull-down to gnd by resistor (10kohm) ) . 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 1 2 3 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 39 40 41 80 79 78 vd bain0 rain0 sogin0 gain1 sogin1 vd gnd gnd vd sogout rain1 o/e field hsout datack vsout/a0 red<9> gain0 vdd gnd refcm blue<2> 26 27 28 29 30 31 32 33 34 35 36 37 38 64 77 76 75 74 73 72 71 70 69 68 67 66 65 bain1 vd gnd rst reflo refhi gnd davdd THC7984 top vi ew red<8> red<7> red<6> red<5> red<4> red<3> red<2> red<1> red<0> vdd gnd gnd green<9> green<8> green<7> green<6> green<5> green<4> green<3> green<2> green<1> green<0> vdd gnd blue<9> blue<8> blue<7> blue<6> blue<5> blue<4> blue<3> blue<1> blue<0> vdd gnd sda scl hsync1 vsync1 hsync0 clamp extclk/coast pvd gnd filt pvd gnd vsync0 pvd gnd 10 f 10 f 10 f 75 100nf 1nf 1nf 75 75 75 75 75 pvd 2.2k 56nf 5.6nf vdd note2 note3 10k 10k note 1 application example 100nf 100nf 100nf 100nf 100nf alternative
THC7984_rev.2.0_e 42 / 45 thine electronics, inc. copyright?2013 thine electronics, inc. notice about the crosstal k when using 2 ports (port 0/ port 1 ) . crosstalk of video signal although the input signal to the non-selected port will give w eak noise to the signal on the selected port by crosstalk, it has little influence as long as the signal level is normal. if the input signal to non-selected port is abnormally higher amplitude than normal signals (nominally 1.15v peak to peak from the bottom of the sync to the peak level of copy protection signal) and supply voltage vd is lower (1.7v) than the typical value, the crosstalk may increas e and has influence to the selected port. the component video signal on the non-selected port should be muted (output disable) by the video switch or video buffer prior to the device to prevent the crosstalk. * the amplitude of component video signal (ypbpr) with sync and copy protection signal is relatively high. crosstalk of sog slicer the sog slicer extracts a sync signal from sync-on-video signa l (sog, soy). in case that the input sync type of the selected port is sync-on-video(2-level) (r12[1:0]=10b) and a signal is inputted to the non-selected port, there is a pos- sibility to have an influence on the clock jitter by crosstalk. * when the sog slicer is not used (including ypbpr with se parated sync input) , sog crosstalk doesn?t influence on the clock jitter. to prevent crosstalk of the sog slicer, take one of following countermeasures. 1. sog slicer of non-selected port should be power-down when port 0 is selected (r12[3]=0) : sog slicer of port 1 should be powered down (r39=fdh) when port 1 is selected (r12[3]=1) : sog slicer of port 0 should be powered down (r39=feh) * the sog slicer of the port which doesn?t support sog (e .g., pc input) can be powered down and the capacitor (1nf) of the sog input can be eliminated. 2. the video signal on the non-selected port should be muted (o utput disable) by the video switch or video buffer prior to the device to prevent the crosstalk. by above countermeasures, the sog activity detection of the non-selected po rt can?t work and th e following function can not be used. sync type detection of non-selected port (r2c[3:2]/r2c[1:0]) input port automatic selection (r12[5]) port selection rgb selected port non-selected port ypbpr mute (pc input) (component input) mute of non-selected port ( e.g. ) video switch THC7984
THC7984_rev.2.0_e 43 / 45 thine electronics, inc. copyright?2013 thine electronics, inc. 2-wire serial interface < 2-wire serial interface protocol > * the THC7984 operates as a slave device. * while scl is high, sda must be stable. sda can change when scl is low. (excep t for start/end conditions) * a sda high to low transition when scl is high defines "start condition". a sda low to high transition when scl is high defines "stop condition". * in write or read cycle, whenever data is written or read, the register address (address pointer) is incremented. the address pointer is hold when the write cycle ends. however, the address pointer is undefined when the read cycle ends. * to read the register data, specify a register address by the write cycl e, and read the data by read cycle. * embedded watch dog timer monitors scl transitions. when scl stays high more than 39ms (min.) or stays low more than 19ms (min.) , 2-wire serial interface is reset to initial state (t his is different from chip reset) . device id r/w ack scl sda i6 i5 i0 d7 d6 d0 d1 a/a a stop condition ack r/w register address write data read data -write cycyle- s device id w a register address a write data p -read cycyle- s device id w a register address a read data p s device id r a a a s: start condition p: stop condition from master to THC7984 from THC7984 to master a a 9 cycle start condition 9 cycle 0 1 0 w: write (low) r: read (high) a: acknowledge (low) a : not acknowledge (high) d7 d6 d0 d1 ack a 9 cycle d7 d7 d6 d0 d1 ack a 9 cycle sda scl t buff t stah t dho t dal t dah t dsu t stasu t stosu stop start stop start < 2-wire serial interface timing > vihmin=1.4v vilmax=0.8v vihmin=1.4v vilmax=0.8v tf
THC7984_rev.2.0_e 44 / 45 thine electronics, inc. copyright?2013 thine electronics, inc. package dimension (unit: mm) THC7984 top view 16.00 bsc. 14.00 bsc. 16.00 bsc. 14.00 bsc. 1 20 21 40 41 60 61 80 1.60 max 0 - 7 deg. 0.65 bsc 0.38 0.30 0.22 0.75 0.60 0.45 0.15 1.45 1.40 1.35 gauge plane 0.25 mirror finish 0.05
THC7984_rev.2.0_e 45 / 45 thine electronics, inc. copyright?2013 thine electronics, inc. other precautions and requirements 1. the specification in this data sheet ar e subject to change without prior notice. 2. circuit diagrams shown in this data sheet are examples of application. therefore, please pay more particular attention to circuit designing. even if there ar e improper expressions in the documents, we are not responsible for any problem due to them. please note that improper expressions may not be correct ed immediately even if found. 3. our copyright and know-how ar e included in this data sheet. duplication of the data sheet and disclosure to the third party are strictly prohibited without our permission. 4. we are not responsible for any problem on industrial pr oprietorship occurring due to the use of the THC7984, except for those directly related to the product stru cture, manufacturing methods and functions. 5.the THC7984 is designed on the premise that it should be used for ordinary electronic devices. therefore, it shall not be used for applications that requ ire extremely high-reliability (s pace equipment, nuclear control equipment, medical equipment that affects the human life, etc.) . in addition, when the THC7984 is used for traffic signals, safety devices and control/safety units in transporta tion equipment, etc., appropriate measures should be taken. 6. we are making every effort to improve the quality and re liability of our products. however, a very low probability of failure will occur in semiconductor devices. to avoid damage to social or official organizations, much care should be taken to provide sufficient redundancy and fail-safe design. 7. radiation-resistant design is not incorporated in the THC7984. 8. it is due to user's judgement whether or not the THC7984 pertains to one of the strategic products prescribed by the foreign exchange and foreign trade control law. thine electronics, inc. sales@thine.co.jp

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