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an important notice at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. production data. LM5113-Q1 snvsar1 ? march 2017 LM5113-Q1 100-v, 1.2-a, 5-a, half-bridge gate driver for enhancement mode gan fets 1 1 features 1 ? qualified for automotive applications ? aec-q100 qualified with the following results: ? device temperature grade 1: -40 c to 125 c ambient operating temperature range ? device hbm esd classification level 1c ? device cdm esd classification level c6 ? independent high-side and low-side ttl logic inputs ? 1.2-a peak source, 5-a peak sink output current ? high-side floating bias voltage rail operates up to 100-vdc ? internal bootstrap supply voltage clamping ? split outputs for adjustable turnon and turnoff strength ? 0.6- ? pulldown, 2.1- ? pullup resistance ? fast propagation times (28 ns typical) ? excellent propagation delay matching (1.5 ns typical) ? supply rail undervoltage lockout ? low power consumption 2 applications ? mobile wireless chargers ? audio power amplifiers ? audio power supplies ? current-fed push-pull converters ? half- and full-bridge converters ? synchronous buck converters 3 description the LM5113-Q1 is designed to drive both the high- side and the low-side enhancement mode gallium nitride (gan) fets or silicon mosfets in a synchronous buck, boost, or half bridge configuration for automotive applications. the device has an integrated 100-v bootstrap diode and independent inputs for the high-side and low-side outputs for maximum control flexibility. the high-side bias voltage is internally clamped at 5.2 v, which prevents the gate voltage from exceeding the maximum gate- source voltage rating of enhancement mode gan fets. the inputs of the device are ttl-logic compatible, which can withstand input voltages up to 14 v regardless of the vdd voltage. the LM5113-Q1 has split-gate outputs, providing flexibility to adjust the turnon and turnoff strength independently. in addition, the strong sink capability of the lm5113- q1 maintains the gate in the low state, preventing unintended turnon during switching. the LM5113-Q1 can operate up to several mhz. the LM5113-Q1 is available in a standard 10-pin wson package with an exposed pad to aid power dissipation. device information (1) part number package body size (nom) LM5113-Q1 wson (10) 4.00 mm 4.00 mm (1) for all available packages, see the orderable addendum at the end of the data sheet. simplified application diagram LM5113-Q1 hb hoh hol hs vdd hi li loh lol vss 0.1 f vin 1 f ep load copyright ? 2017, texas instruments incorporated productfolder ordernow technical documents tools & software support &community
2 LM5113-Q1 snvsar1 ? march 2017 www.ti.com product folder links: LM5113-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated table of contents 1 features .................................................................. 1 2 applications ........................................................... 1 3 description ............................................................. 1 4 revision history ..................................................... 2 5 pin configuration and functions ......................... 3 6 specifications ......................................................... 4 6.1 absolute maximum ratings ...................................... 4 6.2 esd ratings ............................................................ 4 6.3 recommended operating conditions ....................... 4 6.4 thermal information ................................................. 4 6.5 electrical characteristics .......................................... 5 6.6 switching characteristics .......................................... 6 6.7 typical characteristics .............................................. 8 7 detailed description ............................................ 11 7.1 overview ................................................................. 11 7.2 functional block diagram ....................................... 11 7.3 feature description ................................................. 11 7.4 device functional modes ........................................ 12 8 application and implementation ........................ 13 8.1 application information ............................................ 13 8.2 typical application ................................................. 14 9 power supply recommendations ...................... 18 10 layout ................................................................... 19 10.1 layout guidelines ................................................. 19 10.2 layout example .................................................... 19 11 device and documentation support ................. 20 11.1 documentation support ........................................ 20 11.2 receiving notification of documentation updates 20 11.3 community resources .......................................... 20 11.4 trademarks ........................................................... 20 11.5 electrostatic discharge caution ............................ 20 11.6 glossary ................................................................ 20 12 mechanical, packaging, and orderable information ........................................................... 20 4 revision history note: page numbers for previous revisions may differ from page numbers in the current version. date revision notes march 2017 * initial release
3 LM5113-Q1 www.ti.com snvsar1 ? march 2017 product folder links: LM5113-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated 5 pin configuration and functions dpr package 10-pin wson with exposed thermal pad top view (1) i = input, o = output, g = ground, p = power pin functions pin type (1) description no. name 1 vdd p 5-v positive gate drive supply: locally decouple to vss using low esr/esl capacitor located as close as possible to the ic. 2 hb p high-side gate driver bootstrap rail: connect the positive terminal of the bootstrap capacitor to hb and the negative terminal to hs. the bootstrap capacitor must be placed as close to the ic as possible. 3 hoh o high-side gate driver turnon output: connect to the gate of high-side gan fet with a short, low inductance path. a gate resistor can be used to adjust the turnon speed. 4 hol o high-side gate driver turnoff output: connect to the gate of high-side gan fet with a short, low inductance path. a gate resistor can be used to adjust the turnoff speed. 5 hs p high-side gan fet source connection: connect to the bootstrap capacitor negative terminal and the source of the high-side gan fet. 6 hi i high-side driver control input. the LM5113-Q1 inputs have ttl type thresholds. unused inputs must be tied to ground and not left open. 7 li i low-side driver control input. the LM5113-Q1 inputs have ttl type thresholds. unused inputs must be tied to ground and not left open. 8 vss g ground return: all signals are referenced to this ground. 9 lol o low-side gate driver sink-current output: connect to the gate of the low-side gan fet with a short, low inductance path. a gate resistor can be used to adjust the turn-off speed. 10 loh o low-side gate driver source-current output: connect to the gate of high-side gan fet with a short, low inductance path. a gate resistor can be used to adjust the turn-on speed. ep ? ? exposed pad: ti recommends that the exposed pad on the bottom of the package be soldered to ground plane on the pc board to aid thermal dissipation. thermal pad vdd 1 hb hoh hol loh 10 lol vss li hs hi 2 9 3 8 4 7 5 6
4 LM5113-Q1 snvsar1 ? march 2017 www.ti.com product folder links: LM5113-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions . exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 6 specifications 6.1 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) (1) min max unit vdd to vss ? 0.3 7 v hb to hs ? 0.3 7 v li or hi input ? 0.3 15 v loh, lol output ? 0.3 vdd + 0.3 v hoh, hol output v hs ? 0.3 v hb + 0.3 v hs to vss ? 5 93 v hb to vss 0 100 v operating junction temperature 150 c storage temperature, t stg ? 55 150 c (1) aec q100-002 indicates that hbm stressing shall be in accordance with the ansi/esda/jedec js-001 specification. 6.2 esd ratings value unit v (esd) electrostatic discharge human-body model (hbm), per aec q100-002 (1) 1000 v charged-device model (cdm), per aec q100-011 1500 6.3 recommended operating conditions over operating free-air temperature range (unless otherwise noted) min nom max unit vdd 4.5 5.5 v li or hi input 0 14 v hs ? 5 90 v hb v hs + 4 v hs + 5.5 v hs slew rate 50 v/ns operating junction temperature ? 40 125 c (1) for more information about traditional and new thermal metrics, see the semiconductor and ic package thermal metrics application report. 6.4 thermal information thermal metric (1) LM5113-Q1 unit dpr (wson) 10 pins r ja junction-to-ambient thermal resistance 37.5 c/w r jc(top) junction-to-case (top) thermal resistance 35.8 c/w r jb junction-to-board thermal resistance 14.7 c/w jt junction-to-top characterization parameter 0.3 c/w jb junction-to-board characterization parameter 14.9 c/w r jc(bot) junction-to-case (bottom) thermal resistance 4.1 c/w
5 LM5113-Q1 www.ti.com snvsar1 ? march 2017 product folder links: LM5113-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated (1) parameters that show only a typical value are ensured by design and may not be tested in production. 6.5 electrical characteristics specifications are t j = 25 c. unless otherwise specified: v dd = v hb = 5 v, v ss = v hs = 0 v. no load on lol and hol or hoh and hol (1) . parameter test conditions min typ max unit supply currents i dd vdd quiescent current li = hi = 0 v t j = 25 c 0.07 ma t j = ? 40 c to 125 c 0.1 i ddo vdd operating current f = 500 khz t j = 25 c 2 ma t j = ? 40 c to 125 c 3 i hb total hb quiescent current li = hi = 0 v t j = 25 c 0.08 ma t j = ? 40 c to 125 c 0.1 i hbo total hb operating current f = 500 khz t j = 25 c 1.5 ma t j = ? 40 c to 125 c 2.5 i hbs hb to vss quiescent current hs = hb = 90 v t j = 25 c 0.1 a t j = ? 40 c to 125 c 10 i hbso hb to vss operating current f = 500 khz t j = 25 c 0.4 ma t j = ? 40 c to 125 c 1 input pins v ir input voltage threshold rising edge t j = 25 c 2.06 v t j = ? 40 c to 125 c 1.89 2.18 v if input voltage threshold falling edge t j = 25 c 1.66 v t j = ? 40 c to 125 c 1.48 1.76 v ihys input voltage hysteresis 400 mv r i input pulldown resistance t j = 25 c 200 k ? t j = ? 40 c to 125 c 100 300 undervoltage protection v ddr vdd rising threshold t j = 25 c 3.8 v t j = ? 40 c to 125 c 3.2 4.5 v ddh vdd threshold hysteresis 0.2 v v hbr hb rising threshold t j = 25 c 3.2 v t j = ? 40 c to 125 c 2.5 3.9 v hbh hb threshold hysteresis 0.2 v bootstrap diode v dl low-current forward voltage i vdd-hb = 100 a t j = 25 c 0.45 v t j = ? 40 c to 125 c 0.65 v dh high-current forward voltage i vdd-hb = 100 ma t j = 25 c 0.90 v t j = ? 40 c to 125 c 1 r d dynamic resistance i vdd-hb = 100 ma t j = 25 c 1.85 ? t j = ? 40 c to 125 c 3.60 hb-hs clamp regulation voltage t j = 25 c 5.2 v t j = ? 40 c to 125 c 4.7 5.45
6 LM5113-Q1 snvsar1 ? march 2017 www.ti.com product folder links: LM5113-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated electrical characteristics (continued) specifications are t j = 25 c. unless otherwise specified: v dd = v hb = 5 v, v ss = v hs = 0 v. no load on lol and hol or hoh and hol (1) . parameter test conditions min typ max unit low and high side gate driver v ol low-level output voltage i hol = i lol = 100 ma t j = 25 c 0.06 v t j = ? 40 c to 125 c 0.10 v oh high-level output voltage v oh = vdd ? loh or v oh = hb ? hoh i hoh = i loh = 100 ma t j = 25 c 0.21 v t j = ? 40 c to 125 c 0.31 i ohl peak source current hoh, loh = 0 v 1.2 a i oll peak sink current hol, lol = 5 v 5 a i ohlk high-level output leakage current hoh, loh = 0 v t j = ? 40 c to 125 c 1.5 a i ollk low-level output leakage current hol, lol = 5 v t j = ? 40 c to 125 c 1.5 a 6.6 switching characteristics over operating free-air temperature range (unless otherwise noted) parameter test conditions min typ max unit t lphl lo turnoff propagation delay li falling to lol falling t j = 25 c 26.5 ns t j = ? 40 c to 125 c 45 t lplh lo turnon propagation delay li rising to loh rising t j = 25 c 28.0 ns t j = ? 40 c to 125 c 45 t hphl ho turnoff propagation delay hi falling to hol falling t j = 25 c 26.5 ns t j = ? 40 c to 125 c 45 t hplh ho turnon propagation delay hi rising to hoh rising t j = 25 c 28 ns t j = ? 40 c to 125 c 45.0 t mon delay matching lo on and ho off t j = 25 c 1.5 ns t j = ? 40 c to 125 c 8 t moff delay matching lo off and ho on t j = 25 c 1.5 ns t j = ? 40 c to 125 c 8 t hrc ho rise time (0.5 v ? 4.5 v) c l = 1000 pf 7 ns t lrc lo rise time (0.5 v ? 4.5 v) c l = 1000 pf 7 ns t hfc ho fall time (0.5 v ? 4.5 v) c l = 1000 pf 3.5 ns t lfc lo fall time (0.5 v ? 4.5 v) c l = 1000 pf 3.5 ns t pw minimum input pulse width that changes the output 10 ns t bs bootstrap diode reverse recovery time i f = 100 ma, i r = 100 ma 40 ns
7 LM5113-Q1 www.ti.com snvsar1 ? march 2017 product folder links: LM5113-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated figure 1. timing diagram li hi t hplh t lplh t hphl t lphl lo ho li hi t moff t mon lo ho
8 LM5113-Q1 snvsar1 ? march 2017 www.ti.com product folder links: LM5113-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated 6.7 typical characteristics figure 2. peak source current vs output voltage figure 3. peak sink current vs output voltage figure 4. i ddo vs frequency figure 5. i hbo vs frequency figure 6. i dd vs temperature figure 7. i hb vs temperature
9 LM5113-Q1 www.ti.com snvsar1 ? march 2017 product folder links: LM5113-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated typical characteristics (continued) figure 8. uvlo rising thresholds vs temperature figure 9. uvlo falling thresholds vs temperature figure 10. input thresholds vs temperature figure 11. input threshold hysteresis vs temperature figure 12. bootstrap diode forward voltage figure 13. propagation delay vs temperature
10 LM5113-Q1 snvsar1 ? march 2017 www.ti.com product folder links: LM5113-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated typical characteristics (continued) note: unless otherwise specified, v dd = v hb = 5 v, v ss = v hs = 0 v. figure 14. lo and ho gate drive ? high/low level output voltage vs temperature figure 15. hb regulation voltage vs temperature
11 LM5113-Q1 www.ti.com snvsar1 ? march 2017 product folder links: LM5113-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated 7 detailed description 7.1 overview the LM5113-Q1 is a high-frequency, high- and low- side gate driver for enhancement mode gallium nitride (gan) fets in a synchronous buck, boost, or half bridge configuration. the high-side bias voltage is generated using a bootstrap technique and is internally clamped at 5.2 v, which prevents the gate voltage from exceeding the maximum gate-source voltage rating of enhancement mode gan fets. the LM5113-Q1 has split-gate outputs with strong sink capability, providing flexibility to adjust the turnon and turnoff strength independently. the LM5113-Q1 can operate up to several mhz, and is available in a standard 10-pin wson package that contains an exposed pad to aid power dissipation. 7.2 functional block diagram 7.3 feature description 7.3.1 input and output the input pins of the LM5113-Q1 are independently controlled with ttl input thresholds and can withstand voltages up to 12 v regardless of the vdd voltage. this allows the inputs to be directly connected to the outputs of an analog pwm controller with up to 12-v power supply, eliminating the need for a buffer stage the output pulldown and pullup resistance of LM5113-Q1 is optimized for enhancement mode gan fets to achieve high frequency and efficient operation. the 0.6- pulldown resistance provides a robust low impedance turnoff path necessary to eliminate undesired turnon induced by high dv/dt or high di/dt. the 2.1- pullup resistance helps reduce the ringing and over-shoot of the switch node voltage. the split outputs of the lm5113- q1 offer flexibility to adjust the turnon and turnoff speed by independently adding additional impedance in either the turn-on path and/or the turnoff path. if the input signal for either of the the two channels, hi or li, is not used, the control pin must be tied to either vdd or vss. these inputs must not be left floating. 7.3.2 start-up and uvlo the LM5113-Q1 has an undervoltage lockout (uvlo) on both the vdd and bootstrap supplies. when the vdd voltage is below the threshold voltage of 3.8 v, both the hi and li inputs are ignored to prevent the gan fets from being partially turned on. also, if there is insufficient vdd voltage, the uvlo actively pulls the lol and hol low. when the vdd voltage is above its uvlo threshold, but the hb to hs bootstrap voltage is below the uvlo threshold of 3.2 v, only hol is pulled low. both uvlo threshold voltages have 200 mv of hysteresis to avoid chattering. loh uvlo hoh level shift hb hs vdd vss hi li hol lol uvlo & clamp copyright ? 2017, texas instruments incorporated
12 LM5113-Q1 snvsar1 ? march 2017 www.ti.com product folder links: LM5113-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated feature description (continued) table 1. vdd uvlo feature logic operation condition (v hb-hs > v hbr for all cases below) hi li ho lo v dd ? v ss < v ddr during device start-up h l l l v dd ? v ss < v ddr during device start-up l h l l v dd ? v ss < v ddr during device start-up h h l l v dd ? v ss < v ddr during device start-up l l l l v dd ? v ss < v ddr ? v ddh after device start-up h l l l v dd ? v ss < v ddr ? v ddh after device start-up l h l l v dd ? v ss < v ddr ? v ddh after device start-up h h l l v dd ? v ss < v ddr ? v ddh after device start-up l l l l table 2. v hb-hs uvlo feature logic operation condition (v dd > v ddr for all cases below) hi li ho lo v hb-hs < v hbr during device start-up h l l l v hb-hs < v hbr during device start-up l h l h v hb-hs < v hbr during device start-up h h l h v hb-hs < v hbr during device start-up l l l l v hb-hs < v hbr ? v hbh after device start-up h l l l v hb-hs < v hbr ? v hbh after device start-up l h l h v hb-hs < v hbr ? v hbh after device start-up h h l h v hb-hs < v hbr ? v hbh after device start-up l l l l 7.3.3 hs negative voltage and bootstrap supply voltage clamping due to the intrinsic nature of enhancement mode gan fets, the source-to-drain voltage of the bottom switch is usually higher than a diode forward voltage drop when the gate is pulled low. this causes negative voltage on hs pin. moreover, this negative voltage transient may become even more pronounces due to the effects of board layout and device drain/source parasitic inductances. with high-side driver using the floating bootstrap configuration, negative hs voltage can lead to an excessive bootstrap voltage, which can damage the high-side gan fet. the LM5113-Q1 solves this problem with an internal clamping circuit that prevents the bootstrap voltage from exceeding 5.2 v typical. 7.3.4 level shift the level-shift circuit is the interface from the high-side input to the high-side driver stage, which is referenced to the switch node (hs). the level shift allows control of the ho output, which is referenced to the hs pin and provides excellent delay matching with the low-side driver. typical delay matching between lo and ho is around 1.5 ns. 7.4 device functional modes table 3 shows the device truth table. table 3. truth table hi li hoh hol loh lol l l open l open l l h open l h open h l h open open l h h h open h open
13 LM5113-Q1 www.ti.com snvsar1 ? march 2017 product folder links: LM5113-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated 8 application and implementation note information in the following applications sections is not part of the ti component specification, and ti does not warrant its accuracy or completeness. ti ? s customers are responsible for determining suitability of components for their purposes. customers should validate and test their design implementation to confirm system functionality. 8.1 application information to operate gan transistors at very high switching frequencies and to reduce associated switching losses, a powerful gate driver is employed between the pwm output of controller and the gates of the gan transistor. also, gate drivers are indispensable when the outputs of the pwm controller do not meet the voltage or current levels needed to directly drive the gates of the switching devices. with the advent of digital power, this situation is often encountered because the pwm signal from the digital controller is often a 3.3-v logic signal, which cannot effectively turn on a power switch. a level-shift circuit is needed to boost the 3.3-v signal to the gate-drive voltage (such as 12 v) to fully turn on the power device and minimize conduction losses. traditional buffer-drive circuits based on npn/pnp bipolar transistors in totem-pole arrangement prove inadequate with digital power because they lack level-shifting capability. gate drivers effectively combine both the level-shifting and buffer-drive functions. gate drivers also address other needs such as minimizing the effect of high-frequency switching noise (by placing the high-current driver ic physically close to the power switch), driving gate-drive transformers and controlling floating power-device gates, reducing power dissipation and thermal stress in controllers by moving gate-charge power losses from the controller into the driver. the LM5113-Q1 is a mhz high- and low-side gate driver for enhancement mode gan fets in a synchronous buck, boost, or half-bridge configuration. the high-side bias voltage is generated using a bootstrap technique and is internally clamped at 5.2 v, which prevents the gate voltage from exceeding the maximum gate-source voltage rating of enhancement mode gan fets. the LM5113-Q1 has split gate outputs with strong sink capability, providing flexibility to adjust the turnon and turnoff strength independently.
14 LM5113-Q1 snvsar1 ? march 2017 www.ti.com product folder links: LM5113-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.2 typical application the circuit in figure 16 shows a synchronous buck converter to evaluate the LM5113-Q1 device. detailed synchronous buck converter specifications are listed in design requirements . the active clamping voltage mode controller lm5025 is used for close-loop control and generates the pwm signals of the buck switch and the synchronous switch. for more information, see figure 16 . input 15 v to 60 v, output 10 v, 800 khz figure 16. lp5113-q1 application circuit 2.2 f 2.2 f 2.2 f 2.2 f 2.2 f 2.2 f vin j3 c2 c3 c4 c5 c6 c7 vin j1 tp4 + + - gnd gnd gnd gnd gnd gnd out in on/off byp c18 0.1 f c19 1 f r7 33.2 k c17 nu r4 1% 49.9 u1 lp2982aim5-5.0 5v 5 4 c20 100 pf c21 2.2 f 2 c24 1 f 6.3v c25 0.1 f gnd d3 nu r11 0r d4 gnd u3 hb hs vdd hoh hi hol loh lol vss li 2 5 3 4 10 9 8 7 6 1 ep lm5113 gnd nu r14 0r c27 nu c28 nu r15 4.02k ? ? ? ? ? ? ? ? ? ? r18 comp sync rt time ref vcc agnd pgnd outb ss ramp outa uvlo cs2 cs1 vin u4 16 1 2 12 15 14 6 34 8 9 13 5 11 10 7 lm5025 c30 0.01 f c31 0.1 f r17 7.50k c32 1 f gnd gnd 0 d5 d6 mbr130t1g 1n4148w-7-f r19 21.0k gnd gnd r16 21.0k c29 1 f gnd u2 lm8261m5 c26 1 f c23 1500 pf c22 330 pf r8 16.9k 2 4 1 5 3 r5 374 c15 1.5 nf r6 21.0k r1 10.0 c1 330 f c12 22 f c10 22 f c11 1 f c14 1 uf c13 nu ser1360-272kl 2.7 h l1 1 2 35 7 9 11 46 8 10 q2 epc2001 d2 mbr130t1g gnd gnd gnd j4 vout 10v j2 vout tp2 tp5 11 10 9 75 3 8 6 4 2 q1 epc2001 1 c9 0.01 uf c8 0.1 uf tp3 tp1 ex vcc gnd d1 mbr130t1g r2 100k 1% r3 150k c16 220 pf r13 6.98k r9 2r r10 0r ? 1 3
15 LM5113-Q1 www.ti.com snvsar1 ? march 2017 product folder links: LM5113-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated typical application (continued) 8.2.1 design requirements table 4 lists the design requirements for the typical application. table 4. design parameters parameter specification input operating range 15 ? 60 v output voltage 10 v output current, 48-v input 10 a output current, 60-v input 7 a efficiency at 48 v, 10 a > 90% frequency 800 khz 8.2.2 detailed design procedure this procedure outlines the design considerations of LM5113-Q1 in a synchronous buck converter with enhancement mode gan fet. refer to figure 16 for component names and network locations. for additional design help, see figure 16 . 8.2.2.1 vdd bypass capacitor the vdd bypass capacitor provides the gate charge for the low-side and high-side transistors and to absorb the reverse recovery charge of the bootstrap diode. the required bypass capacitance can be calculated with equation 1 . where ? q gh and q gl are gate charge of the high-side and low-side transistors, respectively. ? q rr is the reverse recovery charge of the bootstrap diode, which is typically around 4 nc. ? v is the maximum allowable voltage drop across the bypass capacitor. (1) ti recommends a 0.1-uf or larger value, good quality, ceramic capacitor. the bypass capacitor must be placed as close as possible to the pins of the icto minimize the parasitic inductance. 8.2.2.2 bootstrap capacitor the bootstrap capacitor provides the gate charge for the high-side switch, dc bias power for hb uvlo circuit, and the reverse recovery charge of the bootstrap diode. the required bypass capacitance can be calculated with equation 2 . where ? i hb is the quiescent current of the high-side driver. ? t on is the maximum on-time period of the high-side transistor. (2) a good-quality, ceramic capacitor must be used for the bootstrap capacitor. ti recommends placement of the bootstrap capacitor as close as possible to the hb and hs pin. gh hb on rr bst q i t q c v u ! ' gh gl rr vdd q q q c v ! '
16 LM5113-Q1 snvsar1 ? march 2017 www.ti.com product folder links: LM5113-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.2.2.3 power dissipation the power consumption of the driver is an important measure that determines the maximum achievable operating frequency of the driver. it must be kept below the maximum power-dissipation limit of the package at the operating temperature. the total power dissipation of the LM5113-Q1 is the sum of the gate driver losses and the bootstrap diode power loss. the gate driver losses are incurred by charge and discharge of the capacitive load. it can be approximated as where ? c loadh and c loadl are the high-side and the low-side capacitive loads, respectively. (3) it can also be calculated with the total input gate charge of the high-side and the low-side transistors as (4) there are some additional losses in the gate drivers due to the internal cmos stages used to buffer the lo and ho outputs. figure 17 shows the measured gate-driver power dissipation versus frequency and load capacitance. at higher frequencies and load capacitance values, the power dissipation is dominated by the power losses driving the output loads and agrees well with the above equations. this plot can be used to approximate the power losses due to the gate drivers. gate-driver power dissipation (lo+ho), vdd = +5 v figure 17. neglecting bootstrap diode losses the bootstrap diode power loss is the sum of the forward bias power loss that occurs while charging the bootstrap capacitor and the reverse bias power loss that occurs during reverse recovery. because each of these events happens once per cycle, the diode power loss is proportional to the operating frequency. larger capacitive loads require more energy to recharge the bootstrap capacitor resulting in more losses. higher input voltages (v in ) to the half bridge also result in higher reverse recovery losses. figure 18 and figure 19 show the forward bias power loss and the reverse bias power loss of the bootstrap diode, respectively. the plots are generated based on calculations and lab measurements of the diode reverse time and current under several operating conditions. the plots can be used to predict the bootstrap diode power loss under different operating conditions. gh gl dd sw p q q v f u u 2 loadh loadl dd sw p c c v f u u
17 LM5113-Q1 www.ti.com snvsar1 ? march 2017 product folder links: LM5113-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated the load of high-side driver is a gan fet with total gate charge of 10 nc. figure 18. forward bias power loss of bootstrap diode v in = 50 v the load of high-side driver is a gan fet with total gate charge of 10 nc. figure 19. reverse recovery power loss of bootstrap diode v in = 50 v the sum of the driver loss and the bootstrap diode loss is the total power loss of the ic. for a given ambient temperature, the maximum allowable power loss of the ic can be defined as equation 5 . (5) 8.2.3 application curves conditions: input voltage = 48 v dc, load current = 5 a traces: top trace: gate of low-side egan fet, volt/div = 2 v bottom trace: li of LM5113-Q1, volt/div = 5 v bandwidth limit = 600 mhz horizontal resolution = 0.2 s/div figure 20. low-side driver input and output conditions: input voltage = 48 v dc, load current = 10 a traces: trace: switch-node voltage, volts/div = 20 v bandwidth limit = 600 mhz horizontal resolution = 50 ns/div figure 21. switch-node voltage (t j - t a ) t ja p =
18 LM5113-Q1 snvsar1 ? march 2017 www.ti.com product folder links: LM5113-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated 9 power supply recommendations the recommended bias supply voltage range for LM5113-Q1 is from 4.5 v to 5.5 v. the lower end of this range is governed by the internal undervoltage lockout (uvlo) protection feature of the vdd supply circuit. ti recommends keeping proper margin to allow for transient voltage spikes while not violating the LM5113-Q1 absolute maximum vdd voltage rating and the gan transistor gate breakdown voltage limit. the uvlo protection feature also involves a hysteresis function. this means that once the device is operating in normal mode, if the vdd voltage drops, the device continues to operate in normal mode as far as the voltage drop do not exceeds the hysteresis specification, vddh. if the voltage drop is more than hysteresis specification, the device shuts down. therefore, while operating at or near the 4.5-v range, the voltage ripple on the vdd power supply output must be smaller than the hysteresis specification of LM5113-Q1 uvlo to avoid triggering device shutdown. a local bypass capacitor must be placed between the vdd and vss pins. this capacitor must be located as close as possible to the device. a low esr, ceramic surface-mount capacitor is recommended. ti recommends using 2 capacitors across vdd and gnd: a 100-nf ceramic surface-mount capacitor for high frequency filtering placed very close to vdd and gnd pin, and another surface-mount capacitor, 220 nf to 10 f, for ic bias requirements.
19 LM5113-Q1 www.ti.com snvsar1 ? march 2017 product folder links: LM5113-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated 10 layout 10.1 layout guidelines small gate capacitance and miller capacitance enable enhancement mode gan fets to operate with fast switching speed. the induced high dv/dt and di/dt, coupled with a low gate-threshold voltage and limited headroom of enhancement mode gan fets gate voltage, make the circuit layout crucial to the optimum performance. following are some recommendations. 1. the first priority in designing the layout of the driver is to confine the high peak currents that charge and discharge the gan fets gate into a minimal physical area. this decreases the loop inductance and minimize noise issues on the gate terminal of the gan fets. the gan fets must be placed close to the driver. 2. the second high current path includes the bootstrap capacitor, the local ground referenced vdd bypass capacitor, and low-side gan fet. the bootstrap capacitor is recharged on a cycle-by-cycle basis through the bootstrap diode from the ground referenced vdd capacitor. the recharging occurs in a short time interval and involves high peak current. minimizing this loop length and area on the circuit board is important to ensure reliable operation. 3. the parasitic inductance in series with the source of the high-side fet and the low-side fet can impose excessive negative voltage transients on the driver. ti recommends connecting the hs pin and vss pin to the respective source of the high-side and low-side transistors with a short and low-inductance path. 4. the parasitic source inductance, along with the gate capacitor and the driver pulldown path, can form an lcr resonant tank, resulting in gate voltage oscillations. an optional resistor or ferrite bead can be used to damp the ringing. 5. low esr/esl capacitors must be connected close to the ic, between vdd and vss pins and between the hb and hs pins to support the high peak current being drawn from vdd during turnon of the fets. keeping guideline number 1 above (minimized gan fets gate driver loop) as the first priority, it is also desirable to place the vdd decoupling capacitor and the hb to hs bootstrap capacitor on the same side of the pc board as the driver. the inductance of vias can impose excessive ringing on the ic pins. 6. to prevent excessive ringing on the input power bus, good decoupling practices are required by placing low esr ceramic capacitors adjacent to the gan fets. figure 22 and figure 23 show recommended layout patterns for the 10-pin wson package. two cases are considered: (1) without any gate resistors, and (2) with an optional turnon gate resistor. note that 0402 surface mount package is assumed for the passive components in figure 22 and figure 23 . 10.2 layout example figure 22. 10-pin wson without gate resistors figure 23. 10-pin wson with hoh and loh gate resistors to low-side fet hi li vss loh lol 9 10 to hi-side fet lo gnd hs 6 7 8 1 2 5 vdd hb bypass capacitor 4 hs bootstrap capacitor ho hoh hol 3 to low-side fet hi li vss loh lol 9 10 to hi-side fet lo gnd ho hs 6 7 8 1 2 3 4 5 vdd hb bootstrap capacitor bypass capacitor hs
20 LM5113-Q1 snvsar1 ? march 2017 www.ti.com product folder links: LM5113-Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated 11 device and documentation support 11.1 documentation support 11.1.1 related documentation for related documentation see: an-2149 lm5113 evaluation board 11.2 receiving notification of documentation updates to receive notification of documentation updates, navigate to the device product folder on ti.com. in the upper right corner, click on alert me to register and receive a weekly digest of any product information that has changed. for change details, review the revision history included in any revised document. 11.3 community resources the following links connect to ti community resources. linked contents are provided "as is" by the respective contributors. they do not constitute ti specifications and do not necessarily reflect ti's views; see ti's terms of use . ti e2e ? online community ti's engineer-to-engineer (e2e) community. created to foster collaboration among engineers. at e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. design support ti's design support quickly find helpful e2e forums along with design support tools and contact information for technical support. 11.4 trademarks e2e is a trademark of texas instruments. 11.5 electrostatic discharge caution these devices have limited built-in esd protection. the leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the mos gates. 11.6 glossary slyz022 ? ti glossary . this glossary lists and explains terms, acronyms, and definitions. 12 mechanical, packaging, and orderable information the following pages include mechanical, packaging, and orderable information. this information is the most current data available for the designated devices. this data is subject to change without notice and revision of this document. for browser-based versions of this datasheet, refer to the left-hand navigation.
package option addendum www.ti.com 26-mar-2017 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples lm5113qdprrq1 active wson dpr 10 4500 green (rohs & no sb/br) cu sn level-1-260c-unlim -40 to 125 l5113q (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
package option addendum www.ti.com 26-mar-2017 addendum-page 2 other qualified versions of LM5113-Q1 : ? catalog: lm5113 note: qualified version definitions: ? catalog - ti's standard catalog product
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant lm5113qdprrq1 wson dpr 10 4500 330.0 12.4 4.3 4.3 1.3 8.0 12.0 q1 package materials information www.ti.com 22-mar-2017 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) lm5113qdprrq1 wson dpr 10 4500 367.0 367.0 35.0 package materials information www.ti.com 22-mar-2017 pack materials-page 2

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