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integrated circuits inc. a p89 682k/ 341 k/170k/085k ver 2 .5 .1 1 may 24 2016 a plus make your production a - plus ap8 9682k ? 682sec p8 9341k ? 341sec a p89170k ? 170sec a p89085k ? 85sec a plus integrated circuits inc. address: 3 f - 10, no. 32, sec. 1, chenggung rd., taipei, taiwan 115, r.o.c. ( 115) ???^?? 32 ? 3 ? 10. tel: 886- 2- 2782- 9266 fax: 886- 2- 2782- 9255 website : http: //www.aplusinc.com.tw sales e - mail: sales@aplusinc.com.tw support e - mail: edit @aplusinc.com.tw
integrated circuits inc. a p89 682k/ 341 k/170k/085k ver 2 .5 .1 2 may 24 2016 ? features : ? standard cmos process. ? embedded 16m/8 m/4m/2m eprom. ? 682 /341/170/85 sec voice length at 6khz sampling and 4 - bit s adpcm compression. ? maximum 1024 voice groups. ? maximum 48khz sample rate. ? combination of voice blocks to extend playback duration. ? user selectable pcm16 or u la w 8 or pcm8 or adpcm 4 data compression . ? 7 triggering modes are available : - key mode : s1 ~ s8 to trigger up to 57 voice groups; power on play function. - sbt mode : sbt to trigger up to 102 4 voice groups sequentially ; power on play function. - cpu parallel mode : s[8:1] services as 8 - bits a ddress to trigger up to 25 6 voice groups . with sbt goes high to stro b e the address bits. - spi mode : cs b , sck , di . 3 wire address control up to 102 4 voice groups. - i2c mode : sck , di . 2 wire address control up to 102 4 voice groups. - mp3 mode : s1 : bac kward , s2 : forward , s3 : ( pause / stop ) , s4 : reset , sbt : ( play/pause ) or ( play/ stop) trigger up to 1024 voice groups. - ap89 mode ? function setting similar a p89341/ a p89170/ a p89085 . ? voice group trigger o ptions: edge / level; hold / un hold able ; retrigger / non - retrigger. ? optional 16ms or 65u s selectable debounce time. ? rst pin set high to stop the playback at once . ? lv d ( low voltage detect ) . ? p rogrammable outputs pin out1,out2,out3 : for busy - h , busy - l , stop - h , stop - l , prog busy - h , prog busy - l , load , led flash ( led high active ) , ~led flash ( led low active ) . ? three kind oscillator: internal - rosc external - rosc crystal. ? 2v ? 5v single power supply and < 5ua low stand- by current. ? 16 /8/4 level volume control setting available . ? 16 bit s a udio out . ? pwm vout1 and vout2 drive speaker directly . ? d/a cout pin drives speaker through an external bjt or a u dio amp . ? development system support for voice compilation.
integrated circuits inc. a p89 682k/ 341 k/170k/085k ver 2 .5 .1 3 may 24 2016 ? description : aP89682K/341k/170k/085k series high performance voice otp is fabricated with standard cmos process with embedded 16m/8m/4m/2m bits eprom. it can store up to 682/341/170/85 sec v oice message with 4 - bits adpcm compression at 6khz sampling rate. 16 - bits pcm 8- bits pcm and 8- bits ulaw at (4k to 48k sample rate) is also available for user selecting. user selectable triggering and output signal options provide maximum flexibility to various applications. built - in resistor controlled oscillator, 16 - bits curren t mode dac output and 14 - bits pwm direct speaker driving output minimize the number of external components. pc controlled programmer and developing software are available.
integrated circuits inc. a p89 682k/ 341 k/170k/085k ver 2 .5 .1 4 may 24 2016 ? pin names : pin (24 - pin) playback mode otp program mode descri ption 1 s7 trigger pin (i/o pin with internal pull - down) . 2 s8 trigger pin (i/o pin with internal pull - down) . 3 vpp vpp supply ground . 4 vout1 pwm output to drive speaker directly . 5 vout2 pwm output to drive speaker directly . 6 vdd p vdd p supply voltage . 7 vdd a vdd a analog supply voltage . 8 nc 9 osc oscillator input . 10 cout da c current output . 11 vss vss supply ground . 12 out3 programmable output (i/o pin) . 13 out2 programmable output (i/o pin) . 14 out1 programmable output (i/o pi n) . 15 rst rst reset pin (input pin with internal pull - down) . 16 sbt sbt trigger pin (i/o pin with internal pull - down) . 17 m1 mode select pin 1 (input with internal pull - down) . 18 m0 mode select pin 0 (input with internal pull - down) . 19 ~ 24 s1~s6 s2 s3 trigger pin (i/o pin with internal pull - down) .
integrated circuits inc. a p89 682k/ 341 k/170k/085k ver 2 .5 .1 5 may 24 2016 ? pin descriptions : ? s1 ~ s8 : input trigger pins: - in key mode : s1 to s8 is use d to trigger 57 voice groups. - in cpu parallel mode : this pin low to high [ latch ] t he address at s1(lsb) to s8(msb) and starts the voice playback. - in spi mode : s1 is chip select ( csb ) pin to initiate the command input. s2 is the serial clock (sck) pin which clocks the input command and data bits into the chip. s3 is the data in (d i) pin in which command and data bits a re shifted input into the chip. - in i2c mode : s2 is the serial clock (sck) pin which clocks the input command and data bits into the chip. s3 is the data in (di) pin in which command and data bits a re shifted input in to the chip. - in mp3 mode : s1:backward. s2 :forward. s3: ( pause / stop ) . s4: reset . - in ap89 mode : similar with aplus 1st generation otp ic . (ap89341/ap89170/ap89085 ) usage . ? sbt : input trigger pin: - in sbt mode :t his pin is trigger pin to play v oice groups one time or looping sequentially up to 1024 voice groups. - in cpu parallel mode : t his pin is used as address strobe to latch the voice group address input at s1 to s8 and starts the voice playback. - in mp3 mode : t his pin is ( play/ p ause ) or (pla y/stop) . ? vdd p and vdd a : power supply pins: these two pins must be connected to the positive power supply. ? vss : power ground pins: vss and vpp pins must be connected together to the power ground during voice playback . i n circuit program : vss and vpp pins must be separated to the power ground. connect resistor between power ground and vpp . ? m0 and m1 : in key mode sbt mode ? cpu parallel mode ? mp3 mode ? spi mode ? and i2c mode , m0 and m1 can be used for crystal oscillator or volume control. in ap89 mode operating mode setting pins: - m1=0, m0=0 set the chip into key trigger mode . - m1=0, m0=1 set the chip into cpu para llel command mode . - m1=1, m0=0 set the chip into cpu serial command mode . ? vout1 and vout2 : 14 - bit s pwm output pins which can drive speaker and buzz er directly for voice playback. ? osc :
integrated circuits inc. a p89 682k/ 341 k/170k/085k ver 2 .5 .1 6 may 24 2016 during voice playback, an external resistor is connected betwee n this pin and the vdd pin to set the sampli ng frequency. or keep osc floating if choosing int - rosc. note : external resistor is 68k . ? vpp : during voice playback, this pin and vss must be connected together to the power ground . i n c ircuit p rogram : t his pin is connected to a separate 8 .5v power supply voltage for otp programming. connect resistor between power ground and vpp . not e : r esistor is 10k . ? out1, out2 and out3 : out1,out2 and out3 can select output function as below : 1. busy - h : when voice is playing, output high level signal. 2. busy - l : inverted output of busy - h . 3. led - flash : when voice is playing, output le d fl ash pulse. 4. ~led - flash : inverted output of led - flash . 5. stop- h : when voice plays finished, output stop pulse. 6. stop- l : inverted output of stop- h . 7. load : after load voice data to buffer success, o utput logic high signal. 8. prog - busy - h : when voice of prog - busy set 1, high pulse output. when voice of prog - busy set 0, low pulse output . 9. prog - busy - l : inverted output of prog - busy - h . ? cout : 16 - bit s current mode da c output for voice playback . ? rst : chip reset in playback mode. e xternal reset pull high a capacitor if used internal reset not. capacitor : 100nf
integrated circuits inc. a p89 682k/ 341 k/170k/085k ver 2 .5 .1 7 may 24 2016 ? voice section combinations : voice files created by the pc base developing system are stored in the built - in eprom of th e ap89 682k/ 341k /170 k /085 k chip as a number of fixed length voice blocks . voice blocks are then selected and grouped into voice groups for playback. up to 1024 voice groups are allowed. a voice blocks table is used to store the information of combinat ions of voice blocks and then group them together to form voice group. chip aP89682K ap89341k ap89170k ap89085k memory size 16m bits 8m b its 4m bits 2m bits max no. of voice block 2016 2016 2016 2016 max. no. of voice group 1024 1024 1024 1024 v oice length 682 sec 341 sec 170 sec 85 sec (@ 6khz 4 - bit adpcm) ? example of voice block combination : assume here we have three voice files, they are ? how are you? ? , sound effect and music. each of the voice file is divided into a number of fixed length voice block and stored into the memory. v oice block : b 1 = ? how ? b 2 = ? are ? b 3 = ? you ? b 4 = sound effect b 5 = music1 b 6 = music2 voice blocks are grouped together using voice table to form voice group for playback: group no. voice group contents voice table e nt ries group 1 ? how are you? ? b1+b2+b3 group 2 sound effect + ? how are you? ? b4+ b1+b2+b3 group 3 ? how are you? ? + music1 b1+b2+b3+b5 group 4 music2 b6 ? voice data compression : voice file data is stored in the on - chip eprom as either 4 - bit s adpcm or 8 - bit s pcm / ulaw format or 16 - bit s pcm format. v oice data are stored as 16 - bit s pcm forma is without compression. the voi ce playback quality is best. voice data stored as 4 - bit s adpcm or 8- bit s pcm / ulaw provide 4:2 data compression to save memory space. but voice playback quality with be lower than 16 - bit s pcm format.
integrated circuits inc. a p89 682k/ 341 k/170k/085k ver 2 .5 .1 8 may 24 2016 ? group options : user selectable options that affect ea ch individual group are called group options. they are: ? edge or level trigger . ? unholdable or holdable option. ? re - triggerable or n on- retriggerable option. ? stop pulse disable or enable . fig. 1 to fig. 6 show the voice playback with different combination of triggering mode and the relationship between outputs and voice playback. fig. 1 level, unholdable, non- retriggerable fig. 2 level holdable fig. 3 sbt sequential trigger with level holdable and unholdable
integrated circuits inc. a p89 682k/ 341 k/170k/085k ver 2 .5 .1 9 may 24 2016 fig. 4 edge, unholdable, non- retrigge r fig. 5 edge, holdable fig. 6 sbt sequential trigger with edge holdable and unholdable ? trigger modes : there are seven trigger modes available for ap89 682k/ 341k /170 k /085 k series . ? key mode . ? sbt mode . ? cpu parallel mode . ? spi mode . ? i2c mode . ? mp3 mode . ? ap89 mode .
integrated circuits inc. a p89 682k/ 341 k/170k/085k ver 2 .5 .1 10 may 24 2016 key mode : with t his trigger mode, the beginning 57 voice groups are triggered by setting s1 to s8 to high or low in different combinations. each voice group can have its only independent trigger options (see fig. 1,2,4 and 5 for trigg er options definition). the setting of s1 to s8 for triggering the 1st to the 57 nd voice groups are as follow: voice group s1 s2 s3 s4 s5 s6 s7 s8 sw 1 high nc nc nc nc nc nc nc sw 2 nc high nc nc nc nc nc nc sw 3 nc nc high nc nc nc nc nc sw 4 nc nc nc high nc nc nc nc sw 5 nc nc nc nc high nc nc nc sw 6 nc nc nc nc nc high nc nc sw 7 nc nc nc nc nc nc high nc sw 8 nc nc nc nc nc nc nc high sw 9 high high nc nc nc nc nc nc sw 10 nc high high nc nc nc nc nc sw 11 nc nc high high nc nc nc nc sw 12 nc nc nc high high nc nc nc sw 13 nc nc nc nc high high nc nc sw 14 nc nc nc nc nc high high nc sw 15 nc nc nc nc nc nc high high sw 16 high nc nc nc nc nc nc high sw 17 high high high nc nc nc nc nc sw 18 nc high high high nc nc nc high sw 19 nc nc high high high nc nc nc sw 20 nc nc nc high high high nc nc sw 21 nc nc nc nc high high high nc sw 22 nc nc nc nc nc high high high sw 23 high nc nc nc nc nc high high sw 24 high high nc nc nc nc nc high sw 25 high high high high nc nc nc nc sw 26 nc high high high high nc nc nc sw 27 nc nc high high high high nc nc sw 28 nc nc nc high high high high nc sw 29 nc nc nc nc high high high high sw 30 high nc nc nc nc high high high sw 31 high high nc nc nc nc high high sw 32 high high high nc nc nc nc high sw 33 high high hi gh high high nc nc nc sw 34 nc high high high high high nc nc sw 35 nc nc high high high high high nc sw 36 nc nc nc high high high high high sw 37 high nc nc nc high high high high sw 38 high high nc nc nc high high high sw 39 high high high nc nc nc high high sw 40 high high high high nc nc nc high sw 41 high high high high high high nc nc sw 42 nc high high high high high high nc sw 43 nc nc high high high high high high sw 44 high nc nc high high high high high sw 45 high high nc nc high high high high sw 46 high high high nc nc high high high sw 47 high high high high nc nc high high sw 48 high high high high high nc nc high sw 49 high high high high high high high nc sw 50 nc high high high high high high high sw 51 high nc high high high high high hig h sw 52 high high nc high high high high high sw 53 high high high nc high high high high
integrated circuits inc. a p89 682k/ 341 k/170k/085k ver 2 .5 .1 11 may 24 2016 sw 54 high high high high nc high high high sw 55 high high high high high nc high high sw 56 high high high high high high nc high sw 57 high high high high high hig h high high note: nc represents open or no connection sbt mode : a maximum of 1024 voice groups are available . and can be triggered one by one sequentially with the sbt key (see fig. 3 and 6). cpu parallel mode : in this mode, s8 to s1 serve as 8 - bit addresses input for 256 voice groups with s8 represents the msb and s1 represents lsb. after group address is set and ready, setting the sbt input pin low to high will [ latch ] and trigger the corresponding voice group to playback . trigger opti ons defined in fig. 1,2, 4 and 5 are valid for this mode. fig. 7 cpu parallel trigger mode note that sbt pin cannot be used as single button sequential trigger in this mode. instead , it acts as a strobe input to clock - in the voice group address set a t s8 to s1 into the chip. voice groups are represented in binary address format. for example: [s8:s1] = 0000 0000 (00 hex) for voice group #1 [s8:s1] = 0000 0001 (01 hex) for voice group #2 ? ? ? [s8:s1] = 0000 1000 (08 hex) for voice group #9 ? ? ? [s8:s1] = 1000 1000 (88 hex) for voice group #137 ? ? ? [s8:s1] = 1111 1111 (ff hex) for voice group #256
integrated circuits inc. a p89 682k/ 341 k/170k/085k ver 2 .5 .1 12 may 24 2016 cpu serial command description : cpu serial command include spi mode and a a and d . the command support to reference fig.8 cpu serial command description. load / prefetch 1. th is command pre - load the next voice group address into the address buffer. 2. the "full/load" signal will become hih g once the group address is loaded. 3. the voice group will be played once the playing of the current voice group is finished. 4. the "full/load" signal will become low once the voice group is played and the address buffer is released and ready for nex t prefect action. 5. using this command make sure there is no gap be tween each voice group. play 1. t his command load the voice group address into the address buffer . 2. the current voice group will be stopped and play the new one. pu1 power up the chi p without ramp - up (suitable for pwm direct drive). pu2 power up the chip with ramp - up (suitable for cout transistor drive). pd1 power down the chip without ramp - down (suitable for pwm direct drive). pd2 power down the chip with ramp - do wn (suitable for cou t transistor drive). vol s et volume index of volume table . vol -- decrease the volume index of volume table. vol++ increase the volume index of volume table. pause pause the current voice group. resume resume the current voice gr oup. rewind play the current voice group from it's beginning . stout device status output. fig. 8 cpu serial command description
integrated circuits inc. a p89 682k/ 341 k/170k/085k ver 2 .5 .1 13 may 24 2016 state description : state name description reset include power on reset (typ 5us) and external reset (depends on the external reset circuit). all pins are input floating. serial command inhibited . after reset, state transfer to the " configure " state. configure internal chip configuration. all pins are input floating. serial command inhibited . (max con figure time = 2ms) after configuration, state transfer to the "idle" state. idle state transfer to the "play" state if "active command" received before timeout. after time out without active command, state transition to the "sleep" state. play p laying vo ice group include ramp. state transfer to the "wait" state if nothing to be played. wait wait new serial command and back to the play state without time limit. state transition to the "sleep" state if " de - active command" received. ramp down before transit ion to the sleep if the "pd2" command be accepted. sleep state transition to the "wakeup" state if selected by the host cpu. (w ait sleep to wake up state time = 20us.) wakeup single command be buffered and wait to execute after wakeup state!! (max wakeup time = 2ms). state transition to the "play" state if active command received else to the "idle" state. fig. 9 state description *** active commands are "load", "play", "pu1" and "pu2". de - active commands are "pd1" and "pd2". in cpu serial command co ntrol : a . using pu1/pu2 c ommand first from de - active state. add 2ms delay after pu1/pu 2 command is necessary. b . max "output delay of busy/full signal" equal 2ms during active . c. out2's s elect is different from the ap89xx x series. ( pout) outp ut select to reference pin descriptions of out1 out2 and out3.
integrated circuits inc. a p89 682k/ 341 k/170k/085k ver 2 .5 .1 14 may 24 2016 ap89 mode : this trigger mode is function setting similar with aplus 1st generation otp ic (ap89341/ap89170/ap89085 ) . in ap89 mode operating mode setting: m1=0, m0=0 set the chip into key trigger mode . it operate s to reference key mode . m1=0, m0=1 set the chip into cpu parallel command mode . it operate s to reference cpu parallel mode . m1=1, m0=0 set the chip into cpu serial command mode . the cpu serial command c ompatible with aplus 1st generation otp ic . it i s controlled by command sent to it from the host cpu .s1 to s3 are used to input command word into the chip while out1 to out3 as output from the chip to the host cpu for feedback response. - s1 acts as cs (chip select) to initiate the command word input - s2 acts as sck (serial clo ck) to clock - in the command word at rising edge. - s3 acts as di (data - in) to input the command bits. - out1 acts as busy to indicate the chip is in busy state (include play and ramp) . - out2 acts as out function to output user selected information. - out3 acts as load signal to indicate the voice group address buffer is full and waiting for play . ap89mode - cpu serial command table [lsb first, command byte first] : fig. 10 ap89mode cpu serial command table d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 g 7 g 6 g 5 g 4 g 3 g 2 g 1 g 0 prefetch 0 1 1 1 0 0 0 1 voice group address number play 0 1 0 1 0 1 0 1 voice group address number pu1 w /o ramp 1 1 0 0 0 1 0 1 none pu2 with ramp 1 0 0 0 1 1 0 1 none pd1 w /o ramp 1 1 1 0 0 0 0 1 none pd2 with ramp 1 0 1 0 1 0 0 1 none vol 1 0 1 1 0 0 1 0 0 0 0 0 vol [3:0] vol -- 1 0 1 1 0 0 0 1 none vol++ 1 0 1 1 0 1 0 0 none pause 0 0 1 1 1 0 0 1 none resume 0 0 0 1 1 1 0 1 none
integrated circuits inc. a p89 682k/ 341 k/170k/085k ver 2 .5 .1 15 may 24 2016 ap89mode - cpu serial command timing diagram: fig.1 1(a) ap89mode cpu serial command tim ing fig.1 1(b) ap89mode c pu serial command tim ing * data is latched at rising edge of sc k. * ap89mode cpu serial command function reference fig. 8 cpu serial command description . power up with ramp - up (pu2 ) or without ramp - up (pu1 ) fig. 1 2 power - up command timing * ramp up t ime : 160ms power down with ramp - down (pd2 ) or without ramp - down (pd1 ) fig . 13 power - down command timing * ramp down time : 160ms
integrated circuits inc. a p89 682k/ 341 k/170k/085k ver 2 .5 .1 16 may 24 2016 (1) . prefetch voice group address : a . c ommand timing reference fig.1 1(b) ap89mode cpu serial command timing . b. g 7 to g 0 total 8 bits to be the group address . c. the out3 output ( load ) will become logic high once the group address is successfully loaded. d. the load signal will become logic low once the voice group is played and the address buffer is released and ready fo r next play action. (2) . play voice group address : a . c ommand timing reference fig.1 1(b) ap89mode cpu serial command timing . b. g 7 to g 0 total 8 bits to be the group address . c. playing assign group address i mmediately . (3). power up with ramp - up (pu2 ) or without ramp - up (pu1 ) : a. c ommand timing reference fig.1 2 power - up command timing . b. pu1 : will power - up the chip and set the vout to center value immediately and stay there. c. pu2 : will power - up the chip and ramp - up cout from bottom to center val ue and stay there. (4) . power down with ramp - down (pd2 ) or without ramp - down (pd1 ) : a. c ommand timing reference fig.1 3 power - down command timing . b . pdn1 will power - down the chip and set the v out data to bottom value immediately. pdn1 will be executed correctly only if pu 1 is executed before. c . pdn2 will power - down the chip and r amp - down the cout from its current to bottom value . pdn2 will be executed correctly only if pu2 is executed before. (5) . volume set (vol[3:0]) : a . c ommand timing refere nce fig.1 1(b) ap89mode cpu serial command timing . b. g 3 to g 0 total 4bits(0 ~ 15) set volume level (max : 0, min : 15) (6).volume - - ( vol --) : a. c ommand timing reference fig.1 1(a) ap89mode cpu serial command timing . b. set volume level decrease. (7) .volume + + ( vol++ ) : a. c ommand timing reference fig.1 1(a) ap89mode cpu serial command timing . b. set volume level i ncrease. (8). pause and resume (pause; resume) : a. c ommand timing reference fig.1 1(a) ap89mode cpu serial command timing . b. in pause state, vout1 and vout2 will stay at logic low while the cout will stay at the current d/a data level . when resume , the cout data will continue at the current d/a data level .
integrated circuits inc. a p89 682k/ 341 k/170k/085k ver 2 .5 .1 17 may 24 2016 spi mode : this trigger mode is specially desi gned for simple cpu i nterface. the aP89682K/341k/170k/085k is controlled by command sent to it from the host cpu. s1 to s3 are used to input command word into the chip while out1 to out3 as output from the chip to the host cpu for feedback response. ? s1 acts as cs b (chip select) to initiate the command word input . ? s2 acts as sck (serial clock) to clock - in the command word at rising edge. ? s3 acts as di (data - in) to input the command bits. ? out1 acts as busy to indicate the chip is in busy state (include play and ramp) . ? out2 acts as out function to output user selected information. ? out3 acts as load signal to indicate the voice group address buffer is full and waiting for play . ? m0 acts as volume level i ncrease . ? m1 acts as volume level decrease. spi command tab le [msb first] : command input into the chip 16 - bit s data. command d15 d14 d13 d12 d11 d10 d[9:0] load 1 0 0 1 0 1 voice group address number. play 1 0 0 1 1 0 voice group address number. pu1 w/o ramp 1 0 1 0 0 1 don't care. pu2 with ramp 1 0 1 0 1 0 don't care. pd1 w/o ramp 1 0 1 1 0 1 don't care. pd2 with ramp 1 0 1 1 1 0 don't care. vol 0 1 0 0 0 1 0 0 0 0 0 0 v ol [3:0] vol -- 0 1 0 0 1 0 don't care. vol++ 0 1 0 1 0 1 don't care. pause 0 1 1 0 0 1 don't care. resume 0 1 1 0 1 0 don't care. rew ind 0 1 1 1 0 1 don't care. fig. 1 4 spi command table
integrated circuits inc. a p89 682k/ 341 k/170k/085k ver 2 .5 .1 18 may 24 2016 spi command timing diagram: fig.1 5 spi command tim ing * data is latched at rising edge of sc k. * spi command function reference fig. 8 cpu serial command description. power up wi th ramp - up (pu2 ) or without ramp - up (pu1 ) fig. 1 6 power - up command timing * ramp up time : 160ms power down with ramp - down (pd2 ) or without ramp - down (pd1 ) fig . 17 power - down command timing * ramp down time : 160ms
integrated circuits inc. a p89 682k/ 341 k/170k/085k ver 2 .5 .1 19 may 24 2016 (1). load voice group a ddress : a. command timing reference fig.1 5 spi command timing. b. d9 to d 0 total 10 bits to be the group address . c. the out3 output ( load ) will become logic high once the group address is successfully loaded. d. the load signal will become logic low onc e the voice group is played and the address buffer is released and ready for next play action. (2) . play voice group address : a. command timing reference fig. 15 spi command timing. b. d9 to d 0 total 10 bits to be the group address . c. playing assign g roup address i mmediately . (3). power up with ramp - up (pu2 ) or without ramp - up (pu1 ) : a. command timing reference fig. 1 6 power - up command timing . b. pu1 : will power - up the chip and set the vout to center value immediately and stay there. c. pu2 : will pow er - up the chip and ramp - up cout from bottom to center value and stay there. (4). power - down with ramp - down (pd2 ) or without ramp - down (pd1 ) : a. command timing reference fig. 1 7 power - down command timing. b . pdn1 will power - down the chip and set the v out d ata to bottom value immediately. pdn1 will be executed correctly only if pu 1 is executed before. c . pdn2 will power - down the chip and r amp - down the cout from its current to bottom value . pdn2 will be executed correctly only if pu2 is executed befo re. (5) . volume set (vol[3:0]) : a. command timing reference fig.1 5 spi command timing. b. d 3 to d 0 total 4bits(0 ~ 15) set volume level (max : 0, min : 15) . (6). volume - - ( vol --) : a. command timing reference fig.1 5 spi command timing. b. set volume level decrease. (7). volume + + ( vol++ ) : a. command timing reference fig.1 5 spi command timing. b. set volume level i ncrease. (8). pause and resume (pause; resume) : a. command timing reference fig.1 5 spi command timing. b. in pause state, vout1 an d vout2 will stay at logic low while the cout will stay at the current d/a data level . when resume , the cout data will continue at the current d/a data level . (9) . r ewind : a. command timing reference fig.1 5 spi command timing. b. play the current v oice group from it i s beginning.
integrated circuits inc. a p89 682k/ 341 k/170k/085k ver 2 .5 .1 20 may 24 2016 i2c mode : this trigger mode is specially desi gned for simple cpu interface. the aP89682K/341k/170k/085k is controlled by command sent to it from the host cpu. s2 and s3 are used to input command word into the chi p while out1 to out3 as output from the chip to the host cpu for feedback response. ? s2 acts as sck (serial clock) to clock - in the command word at rising edge. ? s3 acts as di (data - in) to input the command bits. ? out1 acts as busy to indicate the chip is in busy state (include play and ramp) . ? out2 acts as out function to output user selected information. ? out3 acts as load signal to indicate the voice group address buffer is full and waiting for play . ? m0 acts as volume level i ncrease . ? m1 acts as volume level decrease. i2c command table [msb first] : command input into the chip 16 - bit s data. command d15 d14 d13 d12 d11 d10 d[9:0] load 1 0 0 1 0 1 voice group address number. play 1 0 0 1 1 0 voice group address number. pu1 w/o ramp 1 0 1 0 0 1 don't care. pu2 with ramp 1 0 1 0 1 0 don't care. pd1 w/o ramp 1 0 1 1 0 1 don't care. pd2 with ramp 1 0 1 1 1 0 don't care. vol 0 1 0 0 0 1 0 0 0 0 0 0 v ol [3:0] vol -- 0 1 0 0 1 0 don't care. vol++ 0 1 0 1 0 1 don't care. pause 0 1 1 0 0 1 don't care. resume 0 1 1 0 1 0 don't care. rewind 0 1 1 1 0 1 don't care. fig. 1 8 i2c command table
integrated circuits inc. a p89 682k/ 341 k/170k/085k ver 2 .5 .1 21 may 24 2016 i2c command timing diagram: fig. 19 i2c command tim ing * the data bit only can be changed in sc k low level , but it has to be latched before rising edge of sc k. * i2c command function reference fig. 8 cpu serial command description. power up with ramp - up (pu2 ) or without ramp - up (pu1 ) fig. 20 power - up command timing * ramp up time : 160ms add stop condition after power on and internal chip config uration time finish . in power up command : after start condition signal, add delay time more than 300us to wake up device. power - down with ramp - down (pd2 ) or without ramp - down (pd1 ) fig . 21 power - down command timing * ramp down time : 160ms
integrated circuits inc. a p89 682k/ 341 k/170k/085k ver 2 .5 .1 22 may 24 2016 (1) . load voice group address : a. command timing reference fig. 19 i2c command timing. b. d9 to d 0 total 10 bits to be the group address . c. the out3 output ( load ) will become logic high once the group address is successfully loaded. d. the load signal will become logic low once the voice group is played and the address buffer is released and ready for next play action. (2) . play voice group address : a. command timing reference fig. 19 i2c command timing . b. d9 to d 0 total 10 bits to be the group address . c. playing assign group address i mmediately . (3). power up with ramp - up (pu2 ) or without ramp - up (pu1 ) : a. command timing reference fig. 20 power - up command timing . b. pu1 : will power - up the chip and set the vout to center value immediately and stay ther e. c. pu2 : will power - up the chip and ramp - up cout from bottom to center value and stay there. (4). power - down with ramp - down (pd2 ) or without ramp - down (pd1 ) : a. command timing reference fig. 21 power - down command timing. b . pdn1 will power - down the ch ip and set the v out data to bottom value immediately. pdn1 will be executed correctly only if pu 1 is executed before. c . pdn2 will power - down the chip and r amp - down the cout from its current to bottom value. pdn2 will be executed correctly only if pu2 is executed before. (5) . volume set (vol[3:0]) : a. command timing reference fig. 19 i2c command timing . b. d 3 to d 0 total 4bits(0 ~ 15) set volume level (max : 0, min : 15) . (6). volume - - ( vol --) : a. command timing reference fig. 19 i2c command ti ming . b. set volume level decrease. (7). volume + + ( vol++ ) : a. command timing reference fig. 19 i2c command timing . b. set volume level i ncrease. (8). pause and resume (pause; resume) : a. command timing reference fig. 19 i2c command timing . b. in pa use state, vout1 and vout2 will stay at logic low while the cout will stay at the current d/a data level . when resume , the cout data will continue at the current d/a data level . (9). r ewind : a. command timing reference fig. 19 i2c command timing . b. play the current voice group from it i s beginning.
integrated circuits inc. a p89 682k/ 341 k/170k/085k ver 2 .5 .1 23 may 24 2016 mp3 mode : this trigger mode is specially designed for simple mp3 function. user can start to p lay or pause the voice by sbt pin, and backward or forward play by s1 pin or s2 pin, up to 1024 v oice sections. ? sbt acts as ( play/ pause ) or ( play/ stop) . ? s1 acts as backward . ? s2 act as forward . ? s3 acts as stop (sbt = play/ pause) or s3 acts as pause (sbt = play/ stop) . ? s4 act as reset . ? m0 acts as volume level increase. ? m1 act s as volume level decreas e .
integrated circuits inc. a p89 682k/ 341 k/170k/085k ver 2 .5 .1 24 may 24 2016 option : spi mode and i2c mode are pin s4 as data output (do)using. do (pin s4) as output from the chip to the host cpu for feedback response. do( p in s4) o utput the status bits : status description s [15 : 9 ] reserved . s [ 8 ] sto_tag. s [7] sto_busyb. s [6] sto_fullb / sto_empty. s [5] reserved. s [4] reserved. s [3] reserved. s [2] sto_validb. s [1] sto_parity. s [0] sto_tag. fig . 22 spi output status table s [15:9] : reserved. s [8] : sto _tag : when received valid command the bit toggle. s [7] : sto_busyb : w hen voice is playing the bit indicate 0 otherwise 1 . s [6] : sto_fullb/sto_empty : if voice group is waiting to be played ,the bit indicate 0 otherwise 1. s [5:3] : reserved. s [2] : sto_validb : if the last serial command is valid the bit indicate 0 otherwise 1. s [1] : sto_parity : if digit 1 in group address[d9~d 0] total are odd numbers, the bit indicate 0 otherwise 1. s [0] : sto_tag : when received valid command the bit toggl e.
integrated circuits inc. a p89 682k/ 341 k/170k/085k ver 2 .5 .1 25 may 24 2016 spi mode : fig . 23 spi data output command tim ing * data output to be changed at falling edge of sck. spi timing waveforms fig . 24 part a : using command reference fig. 14 spi command table . part b : using comma nd is stout. stout command [msb first] : command input into the chip 16- bit s data. command d15 d14 d13 d12 d11 d10 d[9:0] stout 0 1 1 1 1 0 don't care. (1). stout (status out) : a. command timing reference fig. 23 spi data output command timing. b. get device status.
integrated circuits inc. a p89 682k/ 341 k/170k/085k ver 2 .5 .1 26 may 24 2016 i2c mode : fig . 25 i2c data output command tim ing * data output to be changed at falling edge of sck. i2c timing waveforms fig . 26 part a : using command reference f ig. 1 8 i2c command table . part b : using command is stout. stout command [msb first] : command input into the chip 16- bit s data. command d15 d14 d13 d12 d11 d10 d[9:0] stout 1 1 1 1 1 1 don't care. (1). stout (status out) : a. command timing referen ce fig. 25 i2c data output command timing. b. get device status.
integrated circuits inc. a p89 682k/ 341 k/170k/085k ver 2 .5 .1 27 may 24 2016 ? oscillator resistance : we have 3 modes can choose: internal resistor external resistor crystal resistance. rosc int ? no need to add resist or for osc. rosc ext ? use 68k ohm resist or in osc pin. xt - setting c rystal mode in m0 pin and m1 pin. 1 . the crystal use 16mhz. 2. u se c1 , c2 for capacitor depend on crystal spec.
integrated circuits inc. a p89 682k/ 341 k/170k/085k ver 2 .5 .1 28 may 24 2016 ? reset circuit for hot plug - in applications : lvd provide basic voltage monitoring and prevent chip malfunction at low supply voltage which is around 1.3v to 2.0v.the supply voltage m ay be lower than 1.3v in hot plug - in applications. we recommend adding a resistor as an external low voltage reset circuit to promote system stability in hot plug - in applications. the drawing shown below is the external low voltage reset circuit. if t here is no more out pin to act as busy - h, you can add a resistor between vdda and rst to implement the external low voltage reset circuit . but there is dc current which is about 100ua.
integrated circuits inc. a p89 682k/ 341 k/170k/085k ver 2 .5 .1 29 may 24 2016 ? block diagram : fig. 27 block diagram ? a bsolute m aximum rating s : symbol rating unit v dd - v ss - 0.5 ~ +5. 0 v v in v ss - 0.3 < v in < v dd + 0.3 v v out v ss < v out < v dd v t (operating) : - 10 ~ +85 t (junction) - 10 ~ +85 t (storage) - 10 ~ +85
integrated circuits inc. a p89 682k/ 341 k/170k/085k ver 2 .5 .1 30 may 24 2016 note1: note2: note 3: no load dac off pwm on
integrated circuits inc. a p89 682k/ 341 k/170k/085k ver 2 .5 .1 31 may 24 2016 timing waveforms : ? key sbt and mp3 trigger mode : fig. 28 ? cpu parallel mode : fig. 29
integrated circuits inc. a p89 682k/ 341 k/170k/085k ver 2 .5 .1 32 may 24 2016 ? spi mode : fig. 30 ? ap89 mode cpu serial : fig. 31
integrated circuits inc. a p89 682k/ 341 k/170k/085k ver 2 .5 .1 33 may 24 2016 ? i2c mode : fig. 32
integrated circuits inc. a p89 682k/ 341 k/170k/085k ver 2 .5 .1 34 may 24 2016 ? ac characteristics ( t a = 0 to 70 symbol parameter min. typ. max. unit note t k d key trig ger debounce time (long) ? 16 ? ms 1 t k d key trigger debounce time (long) ? r etrigger during voice playback . ? 24 ? ms 1 t k d key trigger debounce time (sho rt) ? 1 ? ms 1 t k d key trigger debounce time (short) ? r etrigger during voice playback . ? 1.5 ? ms 1 t stpw stop pulse width (long) ? 128 ? m s 1 t stpw stop pulse width (short) ? 500 ? s 1 t as address set - up time 300 ? ? ns t ah address hold time 300 ? ? ns t sbtw sbt stroke pulse width (long) 16 ? ? ms 1 t sbtw sbt stroke pulse width (short) 1 ? ? ms 1 t bo busy signal output delay time(long) ? 24 ? ms 1 t bo busy signal output delay time(short) ? 1 ? ms 1 t cs chip select set - up time 100 ? ? ns t ch chip select hold time 100 ? ? ns t sckw serial clock pulse width 1 ? ? s t ds data set - up time 100 ? ? ns t dh data hold time 100 ? ? ns t sbo busy signal output delay time ? ? 2 m s t rp ramp up time ? 160 ? m s t rp ramp up time at cpu parallel mode ? 20 ? m s t rd ramp down time ? 160 ? m s t rd ramp down time at cpu parallel mode ? 20 ? m s t fd full signal output delay time ? ? 2 m s notes : 1. the long or short debounce time is selectable as whole chip option during vo ice files compiling.
integrated circuits inc. a p89 682k/ 341 k/170k/085k ver 2 .5 .1 35 may 24 2016 in circuit program a pplications : fig. 33 note: 1. b etween vpp and gnd should add r1( 10k ) . 2. between writer and circuit connect wire less than 10cm is the better . 3. if voltage is higher than 4.0v, c (0.1uf (typ) ) is necessary for endure high voltage and protect it from noise which may affect its performance . distance between caps and ics sh ould be minimized to reduce spreading inductance. the wiring length between the ic and caps may be less than 150mil. 4. rp is used to filter noise from power line. a. rp is unnecessary in dac mode or vdd less than 3.6v. the value of rp is 0 ohm in dac mode. b. if voltage is higher than 3.6v and chip is configured as pwm mode, rp is necessary for system stability. the value of rp is 56 ohm in pwm mode. the minimum operating voltage would be lifted from 2.0v to 2.2v, when rp is added. c. if rp is adde d and there are led drove by out[1:3] pin, please configure the out pin as active low to drive led.
integrated circuits inc. a p89 682k/ 341 k/170k/085k ver 2 .5 .1 36 may 24 2016 typical applications : key mode fig. 34 note: 1. if voltage is higher than 4.0v, c (0.1uf (typ) ) is necessary for endure high voltage and protec t it from noise which may affect its performance . distance between caps and ics should be minimized to reduce spreading inductance. the wiring length between the ic and caps may be less than 150mil. 2. rp is used to filter noise from power line. a. rp is unnecessary in dac mode or vdd less than 3.6v. the value of rp is 0 ohm in dac mode. b. if voltage is higher than 3.6v and chip is configured as pwm mode, rp is necessary for system stability. the value of rp is 56 ohm in pwm mode. the minimum oper ating voltage would be lifted from 2.0v to 2.2v, when rp is added. c. if rp is added and there are led drove by out[1:3] pin, please configure the out pin as active low to drive led. ex: single key control volume . if volume l evel is 8 , 1 ? 2 ? 3 ? 4 ? 5 ? 6 ? 7 ? 8 ? 1 ? 2 ? 3 ? 4 ? ?.
integrated circuits inc. a p89 682k/ 341 k/170k/085k ver 2 .5 .1 37 may 24 2016 cpu parallel mode fig. 35 note: 1. c is capacitor from 0.1uf to 4.7uf depends on the kind of vdd source and sound loudness. 2. rb is base resistor from 120 ohm to 390 ohm depends on vdd value and transistor gain. 3. t is an npn transistor wit h beta larger than 150. 4. reference value for the above components are rb = 390 ohm and t = 8050d. 5. if voltage is higher than 4.0v, c (0.1uf (typ) ) is necessary for endure high voltage and protect it from noise which may affect its performance . distance between caps and ics should be minimized to reduce spreading inductance. the wiring length between the ic and caps may be less than 150mil. 6. rp is used to filter noise from power line. a. rp is unnecessary in dac mode or vdd less than 3.6v. the value of rp is 0 ohm in dac mode. b. if voltage is higher than 3.6v and chip is configured as pwm mode, rp is necessary for system stability. the value of rp is 56 ohm in pwm mode. the minimum operating voltage would be lifted from 2.0v to 2.2v, when rp is ad ded. c. if rp is added and there are led drove by out[1:3] pin, please configure the out pin as active low to drive led .
integrated circuits inc. a p89 682k/ 341 k/170k/085k ver 2 .5 .1 38 may 24 2016 spi mode fig. 36 note: 1. if voltage is higher than 4.0v, c (0.1uf (typ) ) is necessary for endure high voltage and protect it from noise which may affect its performance. distance between caps and ics should be minimized to reduce spreading inductance. the wiring length between the ic and caps may be less than 150mil. 2. rp is used to filter noise from power line. a. rp is unnecessa ry in dac mode or vdd less than 3.6v. the value of rp is 0 ohm in dac mode. b. if voltage is higher than 3.6v and chip is configured as pwm mode, rp is necessary for system stability. the value of rp is 56 ohm in pwm mode. the minimum operating vol tage would be lifted from 2.0v to 2.2v, when rp is added. c. if rp is added and there are led drove by out[1:3] pin, please configure the out pin as active low to drive led.
integrated circuits inc. a p89 682k/ 341 k/170k/085k ver 2 .5 .1 39 may 24 2016 i2c mode fig. 37 note: 1. if voltage is higher than 4.0v, c (0.1uf (typ) ) is n ecessary for endure high voltage and protect it from noise which may affect its performance . distance between caps and ics should be minimized to reduce spreading inductance. the wiring length between the ic and caps may be less than 150mil. 2. rp is used to filter noise from power line. a. rp is unnecessary in dac mode or vdd less than 3.6v. the value of rp is 0 ohm in dac mode. b. if voltage is higher than 3.6v and chip is configured as pwm mode, rp is necessary for system stability. the value of rp is 56 ohm in pwm mode. the minimum operating voltage would be lifted from 2.0v to 2.2v, when rp is added. c. if rp is added and there are led drove by out[1:3] pin, please configure the out pin as active low to drive led.
integrated circuits inc. a p89 682k/ 341 k/170k/085k ver 2 .5 .1 40 may 24 2016 mp3 mode fig. 38 note: 1 . if voltage is higher than 4.0v, c (0.1uf (typ) ) is necessary for endure high voltage and protect it from noise which may affect its performance . distance between caps and ics should be minimized to reduce spreading inductance. the wiring length between the ic and caps may be less than 150mil. 2. rp is used to filter noise from power line. a. rp is unnecessary in dac mode or vdd less than 3.6v. the value of rp is 0 ohm in dac mode. b. if voltage is higher than 3.6v and chip is configured as pwm mode , rp is necessary for system stability. the value of rp is 56 ohm in pwm mode. the minimum operating voltage would be lifted from 2.0v to 2.2v, when rp is added. c. if rp is added and there are led drove by out[1:3] pin, please configure the out pin as act ive low to drive led.
integrated circuits inc. a p89 682k/ 341 k/170k/085k ver 2 .5 .1 41 may 24 2016 bonding pad diagrams (aP89682K/ap89341k) notes: 1. b etween vpp and gnd should add 10k . 2. vdd a and vddp should be connected to the positive power supply. 3. vss a and vssp should be connected to the power gnd. 4. substrate should be connecte d to the power gnd.
integrated circuits inc. a p89 682k/ 341 k/170k/085k ver 2 .5 .1 42 may 24 2016 bonding pad diagrams (ap89170k/ap89085k) notes: 1. b etween vpp and gnd should add 10k . 2. vdd a and vddp should be connected to the positive power supply. 3. vss a and vssp should be connected to the power gnd. 4. substrate should be co nnected to the power gnd.
integrated circuits inc. a p89 682k/ 341 k/170k/085k ver 2 .5 .1 43 may 24 2016 packages dimension outlines 24- pin 300mil p - dip package 28- pin 300mil sop package
integrated circuits inc. a p89 682k/ 341 k/170k/085k ver 2 .5 .1 44 may 24 2016 h istory 2015 /03/ 10 aP89682K_341k__1 70k_085k spec . 2015/07/20 aP89682K_341k__170k_085k spec : modify cpu cont rol timing waveforms modify page. 18 dc characteristics r educe o utput function from 1 4 to 9. remove ap89 mode1 and ap89 mode2 and new add ing ap89mode . 2015/09/08 aP89682K_341k__170k_085k spec : modify ulaw5 to ulaw8 add sbt mode independent description. optimize the cpu mode control. add in circuit program application on page. 34. 2016/ 01/ 20 aP89682K_341k__170k_085k spec : add decoupling cap suggestion at high voltage application. page 34 to 39. add testing condition of iop on page 29. 2016/04/26 aP89682K_341k__170k_085k spec : add rp to filter noise from power line. page 35 to 40. add reset circuit for hot plug - in applications. 2016/05/24 aP89682K_341k__170k_085k spec : modify in circuit program schematic to support copier. page 4, 35.

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