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| Datasheet File OCR Text: |
| this is information on a product in full production. november 2016 docid029145 rev 4 1/162 L99DZ120 automotive door actuator driver with embedded lin datasheet - production data features ? aec-q100 qualified ? 1 half bridge for 7.5 a load (r on = 100 m ? ) ? 1 half bridge for 7.5 a load (r on = 150 m ? ) ? 2 half bridges for 3 a load (r on = 300 m ? ) ? 1 configurable high-side driver for up to 1.5 a (r on = 500 m ? ) or 0.35 a (r on = 1600 m ? ) load ? 1 configurable high-side driver for 0.8 a (r on = 800 m ? ) or 0.35 a (r on = 1600 m ? ) load ? 3 configurable high-side drivers for 0.15 a/0.35 a (r on =2 ? ) ? 1 configurable high-side driver for 0.25 a/0.5 a (r on = 2 ? ) ? 4 configurable high-side drivers for 0.15 a/0.25 a (r on = 5 ? ) ? internal 10bit pwm timer for each stand-alone high-side driver ? buffered supply for voltage regulators and 2 high-side drivers (out15 & out_hs / both ? p-channel) to supply e.g. external contacts ? programmable soft-start function to drive loads with higher inrush curren ts as current limitation value (for out1-6 , out7, out8 and out_hs) with thermal expiration feature ? all the embedded outputs come with protection and supervision features: ? current monitor (high-side only) ? open-load ? overcurrent ? thermal warning ? thermal shutdown ? fully protected driver for external mosfets in h-bridge configuration ? two 5 v voltage regulators for microcontroller and peripheral supply ? programmable reset generator for power-on and undervoltage ? configurable window watchdog ? lin 2.2a compliant ( saej2602 compatible) transceiver ? separated (isolated) fail-safe block with 2 ls (r on = 1 ? ) to pull down the gates of the external hs mosfets ? thermal clusters ? a/d conversion of supply voltages and internal temperature sensors ? embedded and programmable vs duty cycle adjustment for led driver outputs applications door zone applications. www.st.com
contents L99DZ120 2/162 docid029145 rev 4 contents 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2 block diagram and pin descripti ons . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.2 esd protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.3 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.3.1 lqfp64 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.4.1 supply and supply monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.4.2 oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.4.3 power-on reset (vsreg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.4.4 voltage regulator v1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.4.5 voltage regulator v2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.4.6 reset output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.4.7 watchdog timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.4.8 current monitor output (cm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.4.9 charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.4.10 outputs out1 - out15, out_hs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.4.11 power outputs switching times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.4.12 over current recovery settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.4.13 current monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.4.14 h-bridge driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.4.15 gate drivers for the external power- mos switching times . . . . . . . . . . 42 3.4.16 drain source monitoring external h-bridge . . . . . . . . . . . . . . . . . . . . . . 45 3.4.17 open-load monitoring external h-bridge . . . . . . . . . . . . . . . . . . . . . . . . 45 3.4.18 fail safe low-side switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.4.19 wake up input wu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.4.20 lin transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.4.21 spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3.4.22 input lin_flash for flash mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 3.4.23 inputs dir, dirh, pwmh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 3.4.24 debug input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 docid029145 rev 4 3/162 L99DZ120 contents 6 3.4.25 adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 3.4.26 temperature diode characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 3.4.27 interrupt outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 3.4.28 timer1 and timer2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 3.4.29 sgnd loss comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 4 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 4.1 supply v s , v sreg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 4.2 voltage regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 4.2.1 voltage regulator: v1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 4.2.2 voltage regulator: v2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 4.2.3 voltage regulator failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 4.2.4 short to ground detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 4.2.5 voltage regulator behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 4.3 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 4.3.1 active mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 4.3.2 flash mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 4.3.3 sw-debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 4.3.4 v1_standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 4.3.5 interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 4.3.6 vbat_standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 4.4 wake-up from standby modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 4.4.1 wake up input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 4.5 functional overview (truth table) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 4.6 configurable window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 4.6.1 change watchdog timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 4.7 fail-safe mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 4.7.1 temporary failures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 4.7.2 non-recoverable failures ? forced vbat_s tandby mode . . . . . . . . . . . . . 70 4.8 reset output (nreset) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 4.9 lin bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 4.9.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 4.9.2 error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 4.9.3 wake up from standby modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 4.9.4 receive-only mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 4.10 serial peripheral interface (st spi standard) . . . . . . . . . . . . . . . . . . . . . 74 contents L99DZ120 4/162 docid029145 rev 4 4.11 power supply failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 4.11.1 v s supply failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 4.11.2 v sreg supply failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 4.12 temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . 77 4.13 power outputs out1..15 and out_hs . . . . . . . . . . . . . . . . . . . . . . . . . . 78 4.14 auto-recovery alert and thermal expiration . . . . . . . . . . . . . . . . . . . . . . . 79 4.15 charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 4.16 inductive loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 4.17 open-load detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 4.18 overcurrent detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 4.19 current monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 4.20 pwm mode of the power outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 4.21 cross-current protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 4.22 programmable soft-start function to drive loads with higher inrush current ? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 4.23 h-bridge control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 4.24 h-bridge driver slew-rate control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 4.25 resistive low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 4.26 short circuit detection / drain source monitoring . . . . . . . . . . . . . . . . . . . 87 4.27 h-bridge monitoring in off-mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 4.28 programmable cross current protection . . . . . . . . . . . . . . . . . . . . . . . . . . 91 4.29 power window h-bridge safety switch off block . . . . . . . . . . . . . . . . . . . . 91 4.30 temperature warning and shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 4.31 thermal clusters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 4.32 v s compensation (duty cycle adjustment) module . . . . . . . . . . . . . . . . . . 95 4.33 analog digital converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 5 serial peripheral interface (spi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 5.1 st spi 4.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 5.1.1 physical layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 5.2 signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 5.2.1 clock and data characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 5.2.2 communication protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 5.2.3 address definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 docid029145 rev 4 5/162 L99DZ120 contents 6 5.2.4 protocol failure detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 6 application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 7 spi registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 7.1 global status byte gsb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 7.2 control register overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 7.3 status register overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119 7.4 control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 7.4.1 control register cr1 (0x01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 7.4.2 control register cr2 (0x02) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 7.4.3 control register cr3 (0x03) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 7.4.4 control register cr4 (0x04) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 7.4.5 control register cr5 (0x05) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 7.4.6 control register cr6 (0x06) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 7.4.7 control register cr7 (0x07) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 7.4.8 control register cr8 (0x08) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 7.4.9 control register cr9 (0x09) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 7.4.10 control register cr10 (0x0a) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 7.4.11 control register cr11 (0x0b) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 7.4.12 control register cr12 (0x0c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 7.4.13 control register cr13 (0x0d) to cr17 (0x11) . . . . . . . . . . . . . . . . . . 139 7.4.14 control register cr18 (0x1 2) to cr22 (0x16) . . . . . . . . . . . . . . . . . . 140 7.4.15 control register cr34 (0x22) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 7.4.16 configuration register (0x3f) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 7.5 status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 7.5.1 status register sr1 (0x31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 7.5.2 status register sr2 (0x32) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 7.5.3 status register sr3 (0x33) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 7.5.4 status register sr4 (0x34) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 7.5.5 status register sr5 (0x35) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 7.5.6 status register sr6 (0x36) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 7.5.7 status register sr7 (0x37) to sr9 (0x39) . . . . . . . . . . . . . . . . . . . . . 153 7.5.8 status register sr10 (0x3a) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 7.5.9 status register sr11 (0x3b) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 contents L99DZ120 6/162 docid029145 rev 4 8.1 lqfp-64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 8.2 lqfp-64 marking information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 9 order code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 10 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 docid029145 rev 4 7/162 L99DZ120 list of tables 9 list of tables table 1. pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 2. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 3. esd protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 4. operating junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 5. temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 6. supply and supply monitoring. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 7. oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 8. power-on reset (v sreg ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 9. voltage regulator v1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 10. voltage regulator v2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 11. reset output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 12. watchdog timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 13. current monitor output (cm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 14. charge pump electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 15. outputs out1 - out15, out_hs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 16. power outputs switching times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 17. half bridges (out1, out4, out5 and out6) ocr timing parameters . . . . . . . . . . . . . . 38 table 18. high-side (out7, out8 and out_hs) ocr timing parameters. . . . . . . . . . . . . . . . . . . . 38 table 19. current monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 20. h-bridge driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 21. gate drivers for the external power-mos switching times . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 22. drain source monitoring external h-bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 23. open-load monitoring external h-bridge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 24. fail safe low-side switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 25. wake-up inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 26. lin transmit data input: pin txd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 27. lin receive data output: pin rxd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 28. lin transmitter and receiver: pin lin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 29. lin transceiver timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 30. input: csn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 31. inputs: clk, di . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 32. di, clk and csn timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 33. output: do . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 34. do timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 35. csn timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 36. inputs lin_flash for flash mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 table 37. inputs dir, dirh, pwmh. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 38. debug input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 39. adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 40. temperature diode characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 41. interrupt outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 42. timer1 and timer2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 43. sgnd loss comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 44. wake-up events description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 45. status of different functions/features vs operatin g modes . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 46. temporary failures description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 47. non-recoverable failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 48. power output settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 list of tables L99DZ120 8/162 docid029145 rev 4 table 49. h-bridge control truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 table 50. h-bridge monitoring in off-mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 table 51. thermal cluster definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 table 52. operation codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 table 53. global status byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 table 54. device application access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 table 55. device information read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 table 56. ram address range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 table 57. rom address range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 table 58. information registers map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 table 59. spi mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 table 60. burst read bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 table 61. spi data length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 table 62. data consistency check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 table 63. wd type/timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 table 64. wd bit position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 table 65. global status byte (gsb) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 table 66. gsb signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 table 67. control register overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 table 68. status register overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 table 69. control register cr1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 table 70. cr1 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 table 71. wake-up input1 filter configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 table 72. voltage regulator v2 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 table 73. standby transition configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 table 74. control register cr2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 table 75. cr2 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 table 76. configuration of timer x on-time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 table 77. control register cr3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 table 78. cr3 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 table 79. control register cr4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 table 80. cr4 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 table 81. control register cr5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 table 82. cr5 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 table 83. outx configuration bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 table 84. control register cr6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 table 85. cr6 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 table 86. control register cr7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 table 87. cr7 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 table 88. control register cr8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 table 89. cr8 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 table 90. control register cr9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 table 91. cr9 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 table 92. control register cr10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 table 93. cr10 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 table 94. control register cr11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 table 95. cr11 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 table 96. control register cr12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 table 97. cr12 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 table 98. control register cr13 to cr17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 39 table 99. cr13 to cr17 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 39 table 100. control register cr18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 docid029145 rev 4 9/162 L99DZ120 list of tables 9 table 101. cr18 to cr22 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 table 102. control register cr34 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 table 103. cr34 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 table 104. configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 table 105. cr signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 table 106. status register sr1 (0x31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 table 107. sr1 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 table 108. status register sr2 (0x32) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 table 109. sr2 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 table 110. status register sr3 (0x33) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 table 111. sr3 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 table 112. status register sr4 (0x34) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 table 113. sr4 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 table 114. status register sr5 (0x35) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 table 115. sr5 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 table 116. status register sr6 (0x36) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 table 117. sr6 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 table 118. status register sr7 (0x37) to sr9 (0x39) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 table 119. sr7 to sr9 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 table 120. status register sr10 (0x3a) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 table 121. sr10 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 table 122. status register sr11 (0x3b) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 table 123. sr11 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 table 124. lqfp-64 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 table 125. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 table 126. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 list of figures L99DZ120 10/162 docid029145 rev 4 list of figures figure 1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 2. pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 3. activation profile 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 4. activation profile 1 (first cycle) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 5. activation profile 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 6. activation profile 2 (first cycle) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 7. lqfp64 package and pcb thermal configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 8. voltage regulator v1 characteristics (quiescent current and accuracy) . . . . . . . . . . . . . . . 28 figure 9. watchdog timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 10. watchdog early, late and safe windows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 11. hard short case, the oc threshold is reache d before end of blanking time. . . . . . . . . . . . 39 figure 12. overload case, the oc threshold is reached af ter end of blanking time. . . . . . . . . . . . . . . 39 figure 13. h-driver delay times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 14. ighxr ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 15. ighxf ranges. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 16. lin transmit, receive timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 17. spi ? transfer timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 18. spi input timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 figure 19. spi output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 figure 20. spi csn - output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 figure 21. spi ? csn high to low transition and global st atus bit access . . . . . . . . . . . . . . . . . . . . . . 58 figure 22. voltage regulator behaviour and diagnosis during supply voltage . . . . . . . . . . . . . . . . . . . 61 figure 23. nint pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 figure 24. main operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 figure 25. watchdog in normal operating mode (no errors) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 figure 26. watchdog with error conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 figure 27. watchdog in flash mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 figure 28. nreset pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 figure 29. rxdl pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 figure 30. wake-up behavior according to lin 2.2a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 figure 31. thermal shutdown protection and diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 figure 32. example of long auto-recovery on out7. temperature acquisition starts after t ar , thermal ? expiration occurs after a ? t = 30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 figure 33. block diagram of physical realization of ar alert and thermal expiration . . . . . . . . . . . . . . 81 figure 34. charge pump low filtering and start up implementat ion . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 figure 35. software strategy for half bridges before applying auto-recover y mode. . . . . . . . . . . . . . . 84 figure 36. overcurrent recovery mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 figure 37. h-bridge gshx slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 figure 38. h-bridge diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 figure 39. h-bridge open-load-detection (no open-load detecte d) . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 figure 40. h-bridge open-load-detection (open-load detected) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 figure 41. h-bridge open-load-detection (short to ground de tected) . . . . . . . . . . . . . . . . . . . . . . . . . . 90 figure 42. h-bridge open-load detection (short to v s detected) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 figure 43. pwmh cross current protection time implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 figure 44. lsx_fso: low-side driver ?passively? turned on, taking supply from output pin (if main supply ? fails), can guarantee v lsx_fso < v out_max . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 figure 45. safety concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 figure 46. thermal clusters identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 docid029145 rev 4 11/162 L99DZ120 list of figures 11 figure 47. block diagram v s compensation (duty cycle adjustment) module . . . . . . . . . . . . . . . . . . . 95 figure 48. sequential adc read out for v sreg , v s , wu and thcl1 ..thcl6 . . . . . . . . . . . . . . . . . 96 figure 49. spi pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 figure 50. sdo pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 figure 51. spi signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 figure 52. sdi frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 figure 53. sdo frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 figure 54. window watchdog operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 figure 55. typical application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 figure 56. timer_x controlled by dir1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 figure 57. lqfp-64 package dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 figure 58. lqfp-64 footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 figure 59. lqfp-64 marking information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 description L99DZ120 12/162 docid029145 rev 4 1 description the L99DZ120 is a door zone systems ic providing electronic control modules with enhanced power management power supply functionality, including various standby modes, as well as lin physical communication layers. the two low-drop voltage regulators of the devices supply the system microcontroller and external peripheral loads such as sensors and provide enhanced system standby functionality with programmable local and remote wake-up capability. in addition 8 high-side drivers to supply leds, 2 high-side drivers to supply bulbs increase the system integration level. up to 3 dc motors and 4 external mos transi stors in h-bridge configuration can be driven. all outputs are sc protected and implement an open-load diagnosis. the st standard spi interface (4.0) allows control and diagnosis of the device and enables generic software development. docid029145 rev 4 13/162 L99DZ120 block diagram and pin descriptions 161 2 block diagram and pin descriptions figure 1. block diagram table 1. pin definitions and functions pin symbol function 1 wu wake-up input: input pin for static or cyclic monitoring of external contacts 2 cp2m charge pump pin for capacitor 2, negative side 3 cp2p charge pump pin for capacitor 2, positive side 4 cp charge pump output 5 cp1p charge pump pin for capacitor 1, positive side 6 cp1m charge pump pin for capacitor 1, negative side ' u l y h u , q w h u i d f h / r j l f ' l d j q r v w l f 6 3 , , q w h u i d f h : l q g r z : d w f k g r j & 6 1 & / . ' 2 ' , 9 b & 3 2 8 7 p ? ? $ u h v s ? ? $ : d w w % x o e & 3 0 & 3 3 & 3 0 & 3 3 9 6 [ * / ' h e x j 3 * 1 ' & 0 * + 6 + 9 5 ( * 9 5 ( * + 6 + 6 + 6 + 6 + 6 + 6 + 6 + 6 3 & k d q q h o 9 b 1 5 ( 6 ( 7 / , 1 / , 1 b ) / $ 6 + 5 [ ' b / 1 , 1 7 7 [ ' b / / , 1 : 8 ' , 5 ' , 5 + 3 : 0 + + 6 2 8 7 ? ? p $ 2 8 7 ? ? p $ 2 8 7 ? ? p $ 2 8 7 ? ? p $ 2 8 7 p ? ? $ 2 8 7 p ? ? $ 2 8 7 p ? ? $ 2 8 7 p ? ? $ 9 6 5 ( * 2 8 7 b + 6 ? ? p $ 2 8 7 ? ? p $ * 1 ' 6 * 1 ' 2 8 7 ? ? $ $ 2 8 7 ? ? $ % x i i h u h g 9 6 ' , 5 2 8 7 p ? ? $ u h v s ? ? $ : d w w % x o e / 6 b ) 6 2 1 , 1 7 ) d l o 6 d i h / 6 b ) 6 2 [ % l w $ ' & 6 $ 5 9 6 5 ( * 9 6 [ 7 m & o + 6 3 & k d q q h o & k d u j h 3 x p s [ 7 m & o * $ 3 * & ) 7 block diagram and pin descriptions L99DZ120 14/162 docid029145 rev 4 7 nc not connected 8 nc not connected 9 out14 high-side-driver output to drive leds 10 out13 high-side-driver output to drive leds 11 out12 high-side-driver output to drive leds 12 out9 high-side-driver output to drive leds 13 out10 high-side-driver-output 14 out11 high-side-driver output to drive leds 15 ls1_fso fail safe low-side switch (active low) 16 ls2_fso fail safe low-side switch (active low) 17 vs power supply voltage for power stage outputs (external reverse battery protection required), for this input a ceramic capacitor as close as possible to gnd is recommended. import ant: for the capability of driving, the full current at the outputs all pins of vs must be connected externally! 18 vs; 2nd pin current capability (pin description see above) 19 out7 high-side-driver output to drive leds or a 10 watt bulb (programmable r dson ) 20 out6 half-bridge outputs: the output is built by a high-side and a low-side switch which are internally connected. the output stage of both switches is a power dmos transistor. each driver has an internal parasitic reverse diode (bulk-drain-diode: high-side driver from output to vs, low-side driver from gnd to output) 21 out1 half-bridge outputs: the output is built by a high-side and a low-side switch which are internally connected. the output stage of both switches is a power dmos transistor. each driver has an internal parasitic reverse diode (bulk-drain-diode: high-side driver from output to vs, low-side driver from gnd to output) 22 nc not connected 23 out5 half-bridge outputs: the output is built by a high-side and a low-side switch which are internally connected. the output stage of both switches is a power dmos transistor. each driver has an internal parasitic reverse diode (bulk-drain-diode: high-si de driver from output to v s , low-side driver from gnd to output) 24 out5; 2nd pin current capability (pin description see above) 25 v sreg power supply voltage to supply the internal voltage regulators, out15 and the out_hs (external reverse battery protection required / diode) for this input a ceramic capacitor as close as possible to gnd and an electrolytic back up capacitor is recommended. 26 out_hs high-side-driver output to drive leds or to supply contacts table 1. pin defi nitions and functions (continued) pin symbol function docid029145 rev 4 15/162 L99DZ120 block diagram and pin descriptions 161 27 out4 half-bridge outputs: the output is built by a high-side and a low-side switch which are internally connected. the output stage of both switches is a power dmos transistor. each driver has an internal parasitic reverse diode (bulk-drain-diode: high-si de driver from output to v s , low-side driver from gnd to output) 28 out4; 2 nd pin current capability (pin description see above) 29 nc not connected 30 vs; 3rd pin current capability (for the pin description see above) 31 out15 high-side-driver output to drive leds 32 pgnd power gnd 33 out8 high-side-driver output to drive leds or a 5 watt bulb (programmable r dson ) 34 nc not connected 35 sgnd signal ground 36 cm current monitor output: depending on the selected multiplexer bits cm_sel_x ( cr 7 ) of the; control register this output sources an image of the instant current; through the corresponding high-side driver with a fixed ratio 37 nc not connected 38 clk spi: serial clock input 39 do spi: serial data output (push pull output stage) 40 di spi: serial data input 41 csn spi: chip select not input 42 txd_l lin transmit data input 43 rxd_l/nint rxdl -> lin receive data output; nint -> indicates loca l/remote wake-up events (push pull output stage) 44 lin_flash lin flash mode enable (former tx d_c pin, to guarantee family compatibility) 45 nc not connected 46 dir1 direct drive input 1 47 pwmh pwmh input: this input signal can be used to control the h-bridge gate drivers. 48 dirh direction input: this input controls the h-bridge drivers for the external mosfets 49 dir2 direct drive input 2 50 nreset nreset output to micro controller; (r eset state = low) (low-side switch with drain connected to the output pin and internal pull up resistance to 5v_1) 51 5v_1 voltage regulator 1 output: 5 v supply e.g. micro controller 52 nc not connected table 1. pin defi nitions and functions (continued) pin symbol function block diagram and pin descriptions L99DZ120 16/162 docid029145 rev 4 53 nint interrupt output (low active; push -pull output stage) to indicate v sreg early warning (active mode); indicates wake-up events from v1_standby mode 54 nc not connected 55 nc not connected 56 debug debug input to deactivate the window watchdog (high active) 57 lin lin bus line 58 5v_2 voltage regulator 2 output: 5 v supply for external loads (potentiometer, sensors). v 2 is protected against reverse supply 59 gl1 gate driver for powermos low-side switch in half-bridge 1 60 sh1 source of high-side switch in half-bridge 1 61 gh1 gate driver for powermos high-side switch in half-bridge 1 62 gh2 gate driver for powermos high-side switch in half-bridge 2 63 sh2 source of high-side switch in half-bridge 2 64 gl2 gate driver for powermos low-side switch in half-bridge 2 table 1. pin defi nitions and functions (continued) pin symbol function docid029145 rev 4 17/162 L99DZ120 block diagram and pin descriptions 161 figure 2. pin connection (top view) 6 + * + * / 6 + * + * / & 3 & 3 3 & 3 3 & 3 0 & 3 0 1 & 1 & 1 & 2 8 7 2 8 7 2 8 7 2 8 7 2 8 7 2 8 7 : 8 9 b 2 8 7 2 8 7 2 8 7 2 8 7 2 8 7 1 & 9 6 5 ( * / , 1 7 [ ' b / 5 [ ' b / 1 , 1 7 & 6 1 ' 2 ' , & / . ' , 5 + 1 & 3 : 0 + / , 1 b ) / $ 6 + & 0 ' , 5 1 & 1 & 6 * 1 ' 1 5 ( 6 ( 7 9 b 1 & 2 8 7 9 6 9 6 3 * 1 ' 2 8 7 1 & 1 & 9 6 2 8 7 2 8 7 ' h e x j ' , 5 / 6 b ) 6 2 / 6 b ) 6 2 1 , 1 7 2 8 7 b + 6 * $ 3 * & ) 7 electrical specifications L99DZ120 18/162 docid029145 rev 4 3 electrical specifications 3.1 absolute maximum ratings stressing the device above the rating listed in table 2 may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specif ication is not implied. exposure to absolute maximum rating condit ions for extended periods may affect device reliability table 2. absolute maximum ratings symbol parameter / test condition value [dc voltage] unit v s, v sreg dc supply voltage / ?jump start? -0.3 to +28 v load dump -0.3 to +40 v 5v_1 stabilized supply voltage, logic supply -0.3 to 6.5 v1 < v sreg v 5v_2 (1) stabilized supply voltage -0.3 to +28 (2) v v di , v clk v csn v do, v rxdl/nint, v nreset, v cm, v dir , v dir2 , v pwmh , v dirh, v int logic input / output voltage range -0.3 to v1+0.3 v v lin_flash, v txdl multi level inputs -0.3 to 40 v v debug debug input pin voltage range -0.3 to 40 v v ls1_fso, v ls2_fso output voltage range of fail-safe low-side switches -0.3 to 35 v v wu dc wake up input voltage / ?jump start? -0.3 to +28 v load dump -0.3 to +40 v v lin lin bus i/o voltage range -20 to +40 v i input (3) current injection into v s related input pins 20 ma i out_inj (3) current injection into v s related outputs 20 ma v outn, v out_hs output voltage (n = 1 to 15) -0.3 to v s +0.3 v v gh1 , v gh2 (v gxy ) high voltage signal pins v sxy -0.3 to v sxy +13; v cp +0.3 v v gl1, v gl2 , (v gxy ) high voltage signal pins v sxy -0.3 to v sxy +13; v cp -0.3v to +12v; vcp+0.3v v v sh1 , v sh2 (v sxy ) high voltage signal pins -1 to 40 v high voltage signal pins; single pulse with t max = 200ns -5 to 40 v v cp1p high voltage signal pins v s -0.3 to v s +14 v v cp2p high voltage signal pins v s -0.6 to v s +14 v docid029145 rev 4 19/162 L99DZ120 electrical specifications 161 note: all maximum ratings are absolu te ratings. leaving the limitation of any of these values may cause an irreversible damage of the integrated circuit! v cp1m , v cp2m high voltage signal pins -0.3 to v s +0.3 v v cp high voltage signal pin v s 26 v v s -0.3 to v s +14 v high voltage signal pin v s > 26 v v s -0.3 to +40 v i out9, i out10, i out11, i out12, i out13, i out14, i out15, i out_hs output current (2) 1.25 a i out8 2.5 a i out7 5 a i out1,6 5 a i out4,5 10 a i vscum maximum cumulated current at v s drawn by out1 (2) 7.5 a maximum cumulated current at v s drawn by out8 & out10 (2) 2.5 a maximum cumulated current at v s drawn by out4 (2) 10 a maximum cumulated current at v s drawn by out5 (2) 10 a maximum cumulated current at v s drawn by out6 & out7 (2) 7.5 a maximum cumulated current at v s drawn by out9, out11, out12, out13, out14, out15 and cp 2.5 a i vsreg maximum current at v sreg pin (2) (5v_1. 5v_2 and out_hs) 2.5 a i pgndcum maximum cumulated current at pgnd drawn by out1 & out6 (2) 7.5 a maximum cumulated current at pgnd drawn by out5 (2) 12.5 a maximum cumulated current at pgnd drawn by out4 (2) 12.5 a i sgnd maximum current at sgnd (2) 1.25 a gnd pins pgnd versus sgnd -0.3 to 0.3 v 1. 5v_2 is robust against sc to 28 v only in case v sreg is supplied. 2. values for the absolute maximum dc current thr ough the bond wires. this value does not consider maximum power dissipation or other limits. 3. guaranteed by design. table 2. absolute maximum ratings (continued) symbol parameter / test condition value [dc voltage] unit electrical specifications L99DZ120 20/162 docid029145 rev 4 note: loss of ground or ground shift with ex ternally grounded loads: esd structures are configured for nominal currents only. if external loads are connected to different grounds, the current load must be limited to this nominal current. 3.2 esd protection 3.3 thermal data all parameters are guaranteed in the juncti on temperature range -40 to 150c (unless otherwise specified); the device is still operative and functional at highe r temperatur es (up to 175c). note: parameters limits at higher junction temper atures than 150c may change respect to what is specified as per the standard temperature range. note: device functionality at high junction temperature is guaranteed by characterization. table 3. esd protection parameter value unit all pins (1) 1. hbm (human body model, 100 pf, 1.5 k ? ) according to mil 883c, method 3015.7 or eia/jesd22a114-a. +/-2 kv all power output pins (2) : out1 ? out15, out_hs +/-4 kv lin +/-8 (2) +/-10 (3) +/-6 (4) 2. hbm with all none zapped pins grounded. 3. indirect esd test according to iec 61000-4-2 (150 pf, 330 ? ) and ?hardware requirements for lin, can and flexray interfaces in automotive applications? (version 1.3, 2012-05-04). 4. direct esd test according to iec 61000-4-2 (150 pf, 330 ? ) and ?hardware requirements for lin, can and flexray interfaces in automotive applications? (version 1.3, 2012-05-04). kv all pins (5) 5. charged device model. +/-500 v corner pins (5) +/-750 (6) 6. for wu, these limits are referred to one-zap stress; in case of three-zap stress, the limits are +750v/-400v. v all pins (7) 7. machine model; c = 220 pf, r = 0 ? . +/- 200 v table 4. operating junction temperature symbol parameter value unit t j operating junction temperature -40 to 175 c docid029145 rev 4 21/162 L99DZ120 electrical specifications 161 3.3.1 lqfp64 thermal data devices belonging to l99dzxxx family embed a multitude of junctions (i.e. outputs based on a powermosfet stage) housed in a relative ly small piece of silicon. the most complex device contains, among all the described features, 6 half-bridges (12 n-channel powermos), 10 high-sides and two voltage regula tors; all the other derivatives, even if smaller than the family super set device, still contain a significant nu mber of junctions. for this reason, using the thermal impedance of a single junction (i.e. voltage regulator or major power dissipation contributor) does not a llow to predict thermal behavior of the whole device and therefore it is not possible to assess if a device is thermally suitable for a given activation profile and loads characteristics. thermal information is provided as temperature re ading by different clusters placed close to the most dissipative junctions. some representative and realistic worst-case thermal profiles are described in the below paragraph. following measurement methods can be easily im plemented, by final user, for a specific activation profile. L99DZ120 thermal profiles profile 1 battery voltage: 16v, ambient temperature start: 85c dc activation ? v1 charged with 70 ma (dc activation) ? v2 charged with 30 ma (dc activation) ? out7: 1 x10w bulb (dc activation) ? out8: 1 x 5w bulb (dc activation) ? out11: 300 ? resistor (dc activation) ? out12: 300 ? resistor (dc activation) ? out13: 300 ? resistor (dc activation) ? out14: 300 ? resistor (dc activation) table 5. temperature warning and thermal shutdown symbol parameter min. typ. max. unit t w thermal overtemperature warning threshold t j (1) 1. non-overlapping. 140 150 160 c t sd1 thermal shutdown junction temperature 1 t j (1) cluster 1-4 cluster 5-6 165 165 175 175 185 190 c t sd2 thermal shutdown junction temperature 2 t j (1) 175 185 195 c t sd12hys hysteresis 5 c t jtft thermal warning / shutdown filter time 32 s electrical specifications L99DZ120 22/162 docid029145 rev 4 cyclic activation ? out4 ? out5: 3,3 ? resistor placed across those outputs ? 10 activations of lock/un-lock (250 ms on lock; 500 ms wait; 250 ms on un- lock unlock; 500 ms wait) ? out5 ? out6: 10 ? resistor placed across those outputs ? (250 ms on safe lock; 500 ms wait; 250 ms on safe unlock; 500 ms wait) test execution: once thermal equilibrium is reached with all dc load acti ve, the ?cyclic activation? sequence is applied. temperature reading is logged just at the end of the whole sequence. figure 3. activation profile 1 figure 4. activation profile 1 (first cycle) * $ 3 * & ) 7 7 l p h v & o x v w h u & o x v w h u & o x v w h u & o x v w h u & o x v w h u 7 h p s h u d w x u h ? & * $ 3 * & ) 7 & x u u h q w $ 7 l p h v & o x v w h u & o x v w h u & o x v w h u & o x v w h u & o x v w h u 2 8 7 b 7 h p s h u d w x u h ? & docid029145 rev 4 23/162 L99DZ120 electrical specifications 161 note: all curves are plotted interpolating measured samples with 15 ms of period . profile 2 battery voltage: 16v, ambient temperature start: 85c dc activation ? v1 charged with 70 ma (dc activation) ? v2 charged with 30 ma (dc activation) ? out7: 1 x10w bulb (dc activation) ? out8: 1 x 5w bulb (dc activation) ? out11: 300 ? resistor (dc activation) ? out12: 300 ? resistor (dc activation) ? out13: 300 ? resistor (dc activation ? out14: 300 ? resistor (dc activation) cyclic activation ? out1 ? out6: 6,8 ? resistor placed across those outputs ? 2 activations (3s on; 1s off; 2x) test execution: once thermal equilibrium is reached with all dc load acti ve, the ?cyclic activation? sequence is applied. figure 5. activation profile 2 * $ 3 * & ) 7 $ [ l v 7 l w o h $ [ l v 7 l w o h & o x v w h u & o x v w h u & o x v w h u & o x v w h u & o x v w h u electrical specifications L99DZ120 24/162 docid029145 rev 4 figure 6. activation profile 2 (first cycle) note: all curves are plotted interpolating measured samples with 15 ms of period. figure 7. lqfp64 package and pcb thermal configuration note: layout condition for thermal characte rization (board finishing thickness 1.5 mm +/- 10%, board four layers, board dimension 77 mm x 114 mm, board material fr4, cu thickness 0,070 mm for outer layers, 0.0035 mm for inner layers, thermal vias separation 1.2 mm). * $ 3 * & ) 7 & x u u h q w $ 7 l p h v & o x v w h u & o x v w h u & o x v w h u & o x v w h u & o x v w h u 2 8 7 b 7 h p s h u d w x u h ? & docid029145 rev 4 25/162 L99DZ120 electrical specifications 161 3.4 electrical characteristics 3.4.1 supply and supply monitoring all spi communication, logic and oscillato r parameters are working down to v sreg = 3.5 v and parameters are as specified in the fo llowing chapters (guaranteed by design). ? spi thresholds ? oscillator frequency (delay times correctly elapsed) ? internal register status correctly kept (reset at default values for v sreg < v por ) ? reset threshold correctly detected the voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6 v v s 28 v; 6 v v sreg 28 v; t j = -40 c to 150 c, unless otherwise specified. table 6. supply and supply monitoring symbol parameter test condition min. typ. max. unit v suv v s undervoltage threshold v s increasing / decreasing 4.7 5.4 v v hyst_uv v s undervoltage hysteresis 0.04 0.1 0.2 v v sov v s overvoltage threshold v s increasing 20 22.5 v v s decreasing 18.5 22.5 v hyst_ov v s overvoltage hysteresis 0.5 1 1.5 v v sreg_uv v sreg undervoltage threshold v sreg increasing / decreasing 4.2 4.9 v v hyst_uv v sreg undervoltage hysteresis 0.04 0.1 0.2 v v sreg_ov v sreg overvoltage threshold v sreg increasing 20 22.5 v v sreg decreasing 18.5 22.5 v hyst_ov v sreg overvoltage hysteresis 0.5 1 1.5 v t ovuv_filt v s /v sreg over/undervoltage filter time 64 s i v(act) current consumption in active mode v s = v sreg = 12 v; ? txd lin = high; v1 = on; v2 = on; hs/ls driver off; cp = on 11 14 ma i v(bat) current consumption in v bat _standby mode (1) v s = 12 v; both voltage regulators deactivated; hs/ls driver off 81630a i v(bat)cs current consumption in v bat _standby mode with cyclic sense enabled (1) v s = 12 v; both voltage regulators deactivated; t = 50 ms, t on = 100 s 30 80 130 a i v(bat)cw current consumption in v bat _standby mode with cyclic wake enabled (1) v s = 12 v; both voltage regulators deactivated during standby phase 30 80 130 a electrical specifications L99DZ120 26/162 docid029145 rev 4 3.4.2 oscillator the voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6 v v s 28 v; 6 v v sreg 28 v; t j = -40 c to 150 c, unless otherwise specified. 3.4.3 power-on reset (v sreg ) all outputs open; t j = -40 c to 150 c, unless otherwise specified. i v(v1stby) current consumption in v 1 _standby mode (1) v s = 12 v; voltage regulator v1 active; (i v1 = 0); hs/ls driver off 16 50 70 a current consumption in v 1 _standby mode (1) (2) v s = 12 v; voltage regulator v1 active; (i v1 = i cmp ); hs/ls driver off 196 a current consumption in v 1 _standby mode (1) v s = 12v; voltage regulator v1 active; (i v1 = i peak ); hs/ls driver off 436 a i qlin quiescent current adder for lin wake up activated guaranteed by design 0 a i out_hs additional bias quiescent current for switched on out_hs or out15 by dir or timer; value for 1 output guaranteed by design 620 1100 a i ouths_dir quiescent current adder if out_hs and/or out15 are configured for direct drive; value during output off guaranteed by design 0 5 a i timer quiescent current adder if timer1 and/or timer 2 are active to provide interrupt on nint upon timer expiration guaranteed by design 65 110 a 1. conditions for specif ied current consumption: ? ? v lin > (v s -1.5 v) ? ? v wu < 1 v or v wu > (v s ? 1.5 v) 2. i q = i q0 + 2% * i load (see also figure 8: voltage regulator v1 characteristics (quiescent current and accuracy) table 6. supply and suppl y monitoring (continued) symbol parameter test condition min. typ. max. unit table 7. oscillator symbol parameter test condition min. typ. max. unit f clk1 (1) 1. osc1: charge pump, spi, output drivers, watchdog ? osc2: adc oscillation frequency osc1 1.66 2.0 2.34 mhz f clk2 (1) oscillation frequency osc2 30.4 32.0 33.6 mhz docid029145 rev 4 27/162 L99DZ120 electrical specifications 161 3.4.4 voltage regulator v1 the voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 4.5 v v s 28 v; 4.5 v v sreg 28 v; t j = -40 c to 150 c, unless otherwise specified. table 8. power-on reset (v sreg ) symbol parameter test condition min. typ. max. unit v por_r v por threshold v sreg rising 3.45 4.5 v v por_f v por threshold v sreg falling (1) 1. this threshold is valid if v sreg had already reached v por_r(max) previously. 2.45 3.5 v table 9. voltage regulator v1 symbol parameter test condition min. typ. max. unit v1 output voltage v sreg = 13.5v 5.0 v v sreg_absmin v sreg absolute minimum value for controlling nreset output v sreg rising/falling 2 v v1 _low_acc output voltage tolerance low accuracy mode i load = 0 ma to i cmp ; (active mode) or i load = 0 ma to i peak (v1stdby); v sreg = 13.5 v -3 3 % v1_ hi_acc output voltage tolerance high accuracy mode i load = i cmp to 100 ma; (active mode) or i load = i peak to 100 ma (v1stdby); v sreg = 13.5 v -2 2 % v1_ 250ma output voltage tolerance (100 to 250ma) i load = 250 ma; v sreg = 13.5 v -3 3 % v dp1 drop-out voltage i load = 50 ma; v sreg = 5 v 0.2 0.4 v i load = 100 ma; v sreg = 5 v 0.3 0.5 v i load = 150 ma; v sreg = 5 v 0.45 0.6 v i cc1 output current in active mode max. continuous load current 250 ma i ccmax1 short circuit output current current limitation 340 600 900 ma c load1 load capacitor1 ceramic (+/- 20%) 0.22 (1) f t tsd v1 deactivation time after thermal shut-down 1sec i cmp_ris current comp. rising thresh rising current 2 4 6 ma i cmp_fal current comp. falling threshold falling current 1.4 2.8 4.2 ma electrical specifications L99DZ120 28/162 docid029145 rev 4 figure 8. voltage regulator v1 characteristics (quiescent current and accuracy) i cmp_hys current comp. hysteresis 1.2 ma i peak_ris (2) current comp. rising thresh. rising current 6 12 18 ma i peak_fal (2) current comp. falling threshold falling current 5 10 15 ma i peak_hys (2) current comp. hysteresis 2ma v1 fail v1 fail threshold v1 forced 2 v t v1fail v1 fail filter time 2 s t v1short v1 short filter time 4 ms t v1fs v1 fail-safe filter time 2 ms t v1off v1 deactivation time after 8 consecutive wd failures tested by scan 150 200 250 ms 1. nominal capacitor value required for stabi lity of the regulator. tested with 220 nf ceramic (+/- 20%). capacitor must be located close to the regulator output pin. a 2.2 f capacito r is recommended to minimize the dpi stress in the application. 2. in active mode, v1 regulator is switched to high accuracy mode, dropping below the i cmp threshold regulator switches to low accuracy mode. table 9. voltage regulator v1 (continued) symbol parameter test condition min. typ. max. unit , / r d g , 3 h d n , & 0 3 , t , t 6 o r s h , / r d g 9 v w g e \ p r g h / r z d f f x u d f \ 9 9 : ' r q / r z d f f x u d f \ 9 9 9 v w g e \ : ' r i i $ f w l y h p r g h : ' r q $ f w l y h p r g h + l j k d f f x u d f \ 9 9 : ' r q $ f w l y h 9 v w g e \ p r g h + l j k d f f x u d f \ 9 9 : ' r q ( " 1 ( $ ' 5 docid029145 rev 4 29/162 L99DZ120 electrical specifications 161 3.4.5 voltage regulator v2 the voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 4.5 v v s 28 v; 4.5 v v sreg 28 v; t j = -40 c to 150 c, unless otherwise specified. 3.4.6 reset output the voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 4v v sreg 28v; t j = -40 c to 150 c, unless otherwise specified. table 10. voltage regulator v2 symbol parameter test condition min. typ. max. unit v2 output voltage v sreg = 13.5 v 5.0 v v2 _1ma output voltage tolerance (0 to 1 ma) i load = 1 ma; v sreg = 13.5 v -6.5 6.5 % v2 _25ma output voltage tolerance (1 to 25 ma) i load = 25 ma; v sreg = 13.5 v -3 3 % v2_ 50ma output voltage tolerance (25 to 50 ma) i load = 50 ma; v sreg = 13.5 v -4 4 % v2_ 100ma output voltage tolerance (50 to 100 ma) i load = 100 ma; v sreg = 13.5 v -4 4 % v dp2 drop-out voltage i load = 25 ma; v sreg = 5.25 v 0.3 0.4 v i load = 50 ma; v sreg = 5.25 v 0.4 0.8 v i load = 100 ma; v sreg = 13.5 v 1 1.6 v i cc2 output current in active mode max. continuous load current 50 ma i ccmax2 short circuit output current current limitation 100 150 250 ma c load load capacitor ceramic (+/- 20%) 0.22 (1) f v2 fail v2 fail threshold v2 forced 2 v t v2fail v2 fail filter time 2 s t v2short v2 short filter time 4 ms 1. nominal capacitor value required for stabi lity of the regulator. tested with 220 nf ceramic (+/- 20%). capacitor must be located close to the regulator output pin. a 2.2 f capacito r is recommended to minimize the dpi stress in the application. table 11. reset output symbol parameter test cond ition min. typ. max. unit v rt1falling reset threshold voltage1 v v1 decreasing 3.25 3.5 3.7 v v rt2falling reset threshold voltage2 v v1 decreasing 3.55 3.8 4 v v rt3falling reset threshold voltage3 v v1 decreasing 3.75 4.0 4.2 v electrical specifications L99DZ120 30/162 docid029145 rev 4 v rt4falling reset threshold voltage4 v v1 decreasing 4.1 4.3 4.5 v v rtrising reset threshold voltage4 v v1 increasing 4.67 4.8 4.87 v v reset reset pin low output voltage v1 > 1 v; i reset = 5 ma 0.2 0.4 v r reset reset pull up int. resistor 10 20 30 k ? t rr reset reaction time i load = 1 ma 6 40 s t uv1 v1 undervoltage filter time 16 s t v1r reset pulse duration (v1 undervoltage and v1 power on reset) 1.5 2.0 2.5 ms t wdr reset pulse duration (watchdog failure) 345ms table 11. reset output (continued) symbol parameter test cond ition min. typ. max. unit docid029145 rev 4 31/162 L99DZ120 electrical specifications 161 3.4.7 watchdog timing 4.5 v v sreg 28 v; t j = -40 c to 150 c, unless otherwise specified. table 12. watchdog timing symbol parameter test condition min. typ. max. unit t lw long open window 160 200 240 ms t efw1 early failure window 1 4.5 ms t lfw1 late failure window 1 20 ms t sw1 safe window 1 7.5 12 ms t efw2 early failure window 2 22.3 ms t lfw2 late failure window 2 100 ms t sw2 safe window 2 37.5 60 ms t efw3 early failure window 3 45 ms t lfw3 late failure window 3 200 ms t sw3 safe window 3 75 120 ms t efw4 early failure window 4 90 ms t lfw4 late failure window 4 400 ms t sw4 safe window 4 150 240 ms electrical specifications L99DZ120 32/162 docid029145 rev 4 figure 9. watchdog timing 7 / : o r q j r s h q z l q g r z 7 ( ) : h d u o \ i d l o x u h z l q g r z 7 6 : v d i h w u l j j h u z l q g r z w u l j j h u v l j q d o 7 : ' 5 z d w f k g r j u h v h w g x u d w l r q w l p h p v w l p h p v w l p h p v 1 r u p d o v w d u w x s r s h u d w l r q d q g w l p h r x w i d l o x u h v : ' w u l j j h u f r u u h f w w u l j j h u w l p l q j 7 / : 7 ( ) : 7 6 : 0 l v v l q j 0 l f u r f r q w u r o o h u w u l j j h u v l j q d o 7 ( ) : 7 ( ) : 7 6 : 1 5 ( 6 2 x w 7 : ' 5 7 / : h d u o \ w u l j j h u w l p l q j p l v v l q j w u l j j h u 7 / : 7 : ' 5 q r u p d o r s h u d w l r q p l v v l q j w u l j j h u h d u o \ z u l w h 7 / : 1 5 ( 6 2 x w 7 : ' 5 7 : ' 5 : ' w u l j j h u 7 / : 7 / : 7 : ' 5 w l p h p v ( " 1 ( $ ' 5 docid029145 rev 4 33/162 L99DZ120 electrical specifications 161 figure 10. watchdog early, late and safe windows 3.4.8 current monitor output (cm) the voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6 v v s 28v; 6 v v sreg 28 v; t j = -40 c to 150 c, unless otherwise specified v d i h w u l j j h u d u h d 7 ( ) : q b p d [ 7 6 : q b p l q 7 / ) : q b p l q 7 6 : q 6 d i h z l q g r z 7 ( ) : q ( d u o \ ) d l o x u h z l q g r z 7 / ) : q / d w h i d l o x u h z l q g r z w l p h ( d u o \ : d w f k g r j i d l o x u h x q g h i l q h g x q g h i l q h g 7 6 : q b p d [ / d w h z d w f k g r j i d l o x u h ( " 1 ( $ ' 5 table 13. current monitor output (cm) symbol parameter test condition min. typ. max. unit v cm functional voltage range 0 v 1 -1v v i cmr current monitor output ratio: i cm /i out1,4,5,6 and 7 (low on- resistance) 0 v v cm (v 1 - 1 v) 1/10000 i cm /i out8 (low on-resistance) 1/6500 i cm /i out 7,8 (high on-resistance) 1/2000 i cm /i out9,10,11,12,13,14,15 and hs 1/1000 electrical specifications L99DZ120 34/162 docid029145 rev 4 3.4.9 charge pump the voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6 v v s 28v; t j = -40 c to 150 c, unless otherwise specified. i cm acc current monitor accuracy acci cmout1,4,5,6 and 7 (low on- resistance) 0 v v cm (v 1 - 1 v); i outmin = 500 ma; i out4,5max =7.4 a; i out1,6max = 2.9 a; i out7max = 1.4 a 4% + 1% fs (1) 8% + 2% fs (1) current monitor accuracy acci cmout 8 (low on-resistance) 0 v v cm (v 1 - 1 v); i outmin = 100 ma; i out8max =0.9 a current monitor accuracy acci cmout9,10,11,12, 13,14,15 ,hs and out7,8 (high on-resistance) 0 v v cm (v 1 - 1 v); i out.min = 100 ma; i out11,12, 15 hs = 0.2 a; i out7,8 max = 0.3 a i cm acc_2ol current monitor accuracy acci cmout1,4,5,6 and 7 (low on- resistance) 0 v v cm (v 1 - 1 v); i outmin = 2 * i old ; i out4,5max = 7.4 a; i out1,6max = 2.9 a; i out7max = 1.4 a 4% + 1% fs (1) 8% + 2% fs (1) current monitor accuracy acci cmout 8 (low on-resistance) 0 v v cm (v 1 - 1 v); i outmin = 2 * i old ; i out8max = 0.9 a current monitor accuracy acci cmout9,11,12,13,14,15, hs and out7,8 (high on-resistance) 0 v v cm (v 1 - 1 v); i out.min = 2 * i old ; i out9,13,14max = 0.3 a; i out11,12,15 hs = 0.2 a; i out7,8 max = 0.3 a current monitor accuracy acci cmout10 0 v v cm (v 1 - 1 v); i out.min = 2 * i old ; i out10max = 0.4 a 4% + 1% fs (1) 8% + 4% fs (1) t cmb current monitor blanking time 32 s 1. fs (full scale) = i outmax * i cmr table 13. current monitor output (cm) (continued) symbol parameter test condition min. typ. max. unit table 14. charge pump electrical characteristics symbol parameter test condition min. typ. max. unit v cp charge pump output voltage v s = 6 v, i cp = -15 ma v s +6 v s +7 v v s 10 v, i cp = -15 ma v s +11 v s +12 v s +13.5 v i cp charge pump output current (1) v cp = v s + 10 v; ? v s = 13.5 v; c 1 = c 2 = c cp = 100 nf 22.5 ma docid029145 rev 4 35/162 L99DZ120 electrical specifications 161 3.4.10 outputs out1 - out15, out_hs the voltages are referred to power ground and currents are assumed positive, when the current flows into the pin. 6 v v s 28 v; 6 v v sreg 28 v, all outputs open; ? t j = -40 c to 150 c, unless otherwise specified. i cplim charge pump output current limitation (2) v cp = v s ; ? v s = 13.5 v; c 1 = c 2 = c cp = 100 nf 70 ma v cp_low charge pump low threshold voltage v s +4.5 v s +5 v s +5.5 v t cp charge pump low filter time 64 s f cp charge pump frequency 400 khz 1. i cp is the minimum current the device can pr ovide to an external circuit without v cp going below v s + 10 v. 2. i cplim is the maximum current, which flows out of the device in case of a short to v s . table 14. charge pump electrical characteristics (continued) symbol parameter test condition min. typ. max. unit table 15. outputs out1 - out15, out_hs symbol parameter test cond ition min. typ. max. unit r on out1,6 on-resistance to supply or gnd v s = 13.5 v; t j = 25 c; i out1,6 = 1.5a 300 m ? v s = 13.5v; t j = 130 c ? i out1,6 = 1.5 a 600 m ? r on out4 on-resistance to supply or gnd v s = 13.5v; t j = 25 c; i out4 = 3 a 150 m ? v s = 13.5 v; t j = 130 c ; i out4 = 3 a 300 m ? r on out5 on-resistance to supply or gnd v s = 13.5 v; t j = 25c; i out5 = 3 a 100 m ? v s = 13.5 v; t j = 130 c ; i out5 = 3 a 200 m ? r on out7 on-resistance to supply in low resistance mode v s = 13.5 v; t j = 25 c; ? i out7 = -0.8 a 500 m ? v s = 13.5 v; t j = 130 c ; ? i out7 = -0.8 a 1000 m ? on-resistance to supply in high resistance mode v s = 13.5 v; t j = 25c; ? i out7 = -0.2 a 1600 m ? v s = 13.5 v; t j = 130 c; ? i out7 = -0.2 a 3200 m ? electrical specifications L99DZ120 36/162 docid029145 rev 4 r on out8 on-resistance to supply in low resistance mode v s = 13.5 v; t j = 25 c; i out8 = -0.4 a 800 m ? v s = 13.5 v; t j = 130 c; ? i out8 = -0.4 a 1600 m ? on-resistance to supply in high resistance mode v s = 13.5 v; t j = 25 c; ? i out8 = -0.2 a 1600 m ? v s = 13.5 v; t j = 130 c; ? i out8 = -0.2 a 3200 m ? r on out9,10,13,14 on-resistance to supply v s = 13.5 v; t j = 25 c; i out9,10,13,14 = -75 ma 2000 m ? v s = 13.5 v; t j = 130 c ; i out9,10,13,14 = -75 ma 4000 m ? r on out11,12,15, hs on-resistance to supply v s = 13.5 v; t j = 25 c; i out11,12,15, hs = -75 ma 5 ? v s = 13.5 v; t j = 130 c ; i out11,12,15, hs = -75 ma 10 ? i qlh switched-off output current ? high-side drivers of out7- 15, out_hs v out = 0 v; standby mode -5 a v out = 0 v; active mode -10 a i qlh switched-off output current ? high-side drivers of out1-6 v out = 0 v; standby mode -5 a v out = 0 v; active mode -100 a i qll switched-off output current ? low-side drivers of out1-6 v out = v s ; standby mode 165 a v out = v s - 0.5 v; active mode -100 a table 15. outputs out1 - out15, out_hs (continued) symbol parameter test cond ition min. typ. max. unit docid029145 rev 4 37/162 L99DZ120 electrical specifications 161 3.4.11 power output s switching times the voltages are referred to power ground and currents are assumed positive, when the current flows into the pin. 6 v v s 28 v; 6 v v sreg 28 v; t j = -40 c to 150 c, unless otherwise specified. table 16. power outputs switching times symbol parameter test condition min. typ. max. unit t d on h output delay time high-side driver on (out 1,4,5,6 ) v s = 13.5 v; v 1 = 5 v; corresponding low-side driver is not active (1)(2)(3) (from csn 50% to out 50%) see figure 20 15 40 80 s output delay time high-side driver on (out 7,8 ) 20 40 90 s t d off h output delay time high-side driver off (out 1,4,5,6 ) v s = 13.5 v; v 1 = 5 v (1)(2)(3) (from csn 50% to out 50%) see figure 20 50 150 300 s output delay time high-side driver off (out 7,8 ) 20 70 130 s t d on h output delay time high-side driver on (out9 ?out15, out_hs) v s /v sreg = 13.5 v; v 1 = 5 v; (from csn 80% to out 80%) 30 s t d off h output switch off delay time high- side driver on (out9 ?out15, out_hs) v s /v sreg = 13.5 v; v 1 = 5 v; (from csn 80% to out 20%) 35 s t d on l output delay time low-side driver (out 1-6 ) on v s = 13.5 v; v 1 = 5 v; corresponding high-side driver is not active (1)(2)(3) (from csn 50% to out 50%) see figure 20 15 30 70 s t d off l output delay time low-side driver (out 1-6 ) off v s = 13.5 v; v 1 = 5 v (1)(2)(3) (from csn 50% to out 50%) see figure 20 40 150 300 s t d hl cross current protection time (out 1-6 ) t cc onls_offhs ? t d off h (4) 50 200 400 s t d lh t cc onhs_offls ? t d off l (4) dv out /dt slew rate of out 1 -out 8 v s = 13.5 v; v 1 = 5 v (1)(2)(3) 0.1 0.2 0.6 v/s dvmax/dt maximum external applied slew rate on out1-out6 without switching on the ls and hs (only in active mode) guaranteed by design 20 v/s dv out /dt slew rate of out9-out15, out_hs v s /v sreg = 13.5 v; v 1 = 5 v (1)(2)(3) 2v/s f pwmx (00) pwm switching frequency v s /v sreg = 13.5 v; v 1 = 5 v 100 hz f pwmx (01) pwm switching frequency v s /v sreg = 13.5 v; v 1 = 5 v 200 hz electrical specifications L99DZ120 38/162 docid029145 rev 4 3.4.12 over curre nt recovery settings f pwmx (10) pwm switching frequency v s /v sreg = 13.5 v; v 1 = 5 v 330 hz f pwmx (11) pwm switching frequency v s /v sreg = 13.5 v; v 1 = 5 v 500 hz 1. r load = 16 ? at out 1,6 and out 7,8 in low on-resistance mode 2. r load = 4 ? at out 4,5 3. r load = 128 ? at out 4,9,10,11,12,13,15,15,hs and out 7,8 in high on-resistance mode 4. t cc is the switch-on delay time if complement in half bridge has to switch off table 16. power outputs switching times (continued) symbol parameter test condition min. typ. max. unit table 17. half bridges (out1, out4, out5 and out6) ocr timing parameters symbol parameter test condition min. typ. max. unit tblanking guaranteed by design 33 40 47 s tocr_hb over current filter time for half bridges guaranteed by design 26 32 38 s toff_hb off time for half bridges ocr_freq=0 guaranteed by design 218 264 310 s off time for half bridges ocr_freq=1 106 128 150 s table 18. high-side (out7, out8 and out_hs) ocr timing parameters symbol parameter test condition min. typ. max. unit tblanking guaranteed by design 33 40 47 s tocr_hs over current filter time for high-side guaranteed by design 53 64 75 s toff_hs off time for high-side ocr_freq=0 guaranteed by design 398 480 562 s off time for high-side ocr_freq=1 192 232 272 s docid029145 rev 4 39/162 L99DZ120 electrical specifications 161 figure 11. hard short case, the oc threshol d is reached before end of blanking time figure 12. overload case, the oc threshold is reached after end of blanking time 3.4.13 current monitoring the voltages are referred to power ground and currents are assumed positive, when the current flows into the pin. 6 v v s 28 v; 6 v v sreg 28 v; t j = -40 c to 150 c, unless otherwise specified. electrical specifications L99DZ120 40/162 docid029145 rev 4 table 19. current monitoring symbol parameter test condition min. typ. max. unit |i oc1 |, |i oc6 | overcurrent threshold hs & ls v s = 13.5 v; v1 = 5 v; sink and source 35a |i oc4 | v s = 13.5 v; v1 = 5 v; sink and source; t j = -40 c to 70 c 7.5 10 a v s = 13.5 v; v1 = 5 v; sink and source; t j = 130 c 610a |i oc5_1 | v s = 13.5 v; v1 = 5 v; sink and source 34 5a |i oc5_2 |4.567.5a |i oc5_3 |7.510a |i oc7 | overcurrent threshol d hs in low on- resistance mode v s /v sreg = 13.5 v; v 1 = 5 v; source 1.5 2.5 a overcurrent threshold hs in high on-resistance mode 0.35 0.65 a |i oc8 | overcurrent threshol d hs in low on- resistance mode 0.7 1.3 a overcurrent threshold hs in high on-resistance mode 0.35 0.65 a |i oc9 |, |i oc13 |, |i oc14 | overcurrent threshold hs in high current mode 0.35 0.7 a overcurrent threshol d to hs in low current mode 0.15 0.3 a |i oc10 | overcurrent threshold hs in high current mode 0.5 1 a overcurrent threshold hs in low current mode 0.25 0.5 a |i oc11 |, |i oc12 |, |i oc15 |, |i oc_hs | overcurrent threshold hs in high current mode 0.25 0.5 a overcurrent threshold hs in low current mode 0.15 0.3 a t ar auto recovery time limit out1 to out6 100 ms out7, out8, out_hs 120 ms |i old1 |, |i old6 | under-current threshold hs & ls v s = 13.5 v; v 1 = 5 v; sink and source 10 30 80 ma |i old4 |, |i old5 | 60 150 300 ma docid029145 rev 4 41/162 L99DZ120 electrical specifications 161 3.4.14 h-bridge driver the voltages are referred to power ground and currents are assumed positive, when the current flows into the pin. 6 v v s 28 v; 6 v v sreg 28 v; t j = -40c to 150 c, unless otherwise specified. |i old7 | under-current threshold hs in low on-resistance mode v s /v sreg = 13.5 v; v 1 = 5 v; source 15 40 60 ma under-current threshold hs in high on-resistance mode 51015ma |i old8 | under-current threshold hs in low on-resistance mode 10 30 45 ma under-current threshold hs in high on-resistance mode 51015ma i old9 |, |i old13 |, |i old14 | under-current threshold hs in high current mode 612ma under-current threshold hs in low current mode 0.5 4 ma |i old10 | under -current thre shold hs in high current mode 10 30 ma under -current threshold hs in low current mode 0.3 4 ma |i old11 |, |i old12 |, |i old15 |, |i old_hs | under -current thre shold hs in high current mode 612ma under -current threshold hs in low current mode 0.85 4 ma t ol_out filter time of open-load signal duration of open-load condition to set the status bit 150 200 250 s table 19. current monitoring (continued) symbol parameter test condition min. typ. max. unit table 20. h-bridge driver symbol parameter test condition min. typ. max. unit drivers for external high-side powermos i ghx(ch) average charge current (charge stage) t j = 25 c 0.3 a r ghx on-resistance (discharge- stage) v shx = 0 v; i ghx = 50 ma; t j = 25 c 610 14 ? v shx = 0 v; i ghx = 50 ma; t j = 130 c 14 20 ? v ghhx gate-on voltage v s = sh = 6 v; i cp = 15 ma v shx + 6 v v s = sh = 12 v; i cp = 15 ma v shx + 8 v shx + 10 v shx + 11.5 v electrical specifications L99DZ120 42/162 docid029145 rev 4 3.4.15 gate drivers for the exte rnal power-mos switching times the voltages are referred to power ground and currents are assumed positive, when the current flows into the pin. 6 v v s 28 v; 6 v v sreg 28 v; t j = -40 c to 150 c, unless otherwise specified. r gshx passive gate-clamp resistance v ghx = 0.5 v 15 k ? drivers for external low-side power-mos i glx(ch) average charge-current (charge stage) t j = 25 c 0.3 a r glx on-resistance (discharge- stage) v slx = 0 v; i ghx = 50 ma; t j = 25 c 610 14 ? v slx = 0 v; i ghx = 50 ma; t j = 130 c 14 20 ? v ghlx gate-on voltage v s = 6 v; i cp = 15 ma v slx + 6 v v s = 12 v; i cp = 15 ma v slx + 8 v slx + 10 v slx + 11.5 v r gslx passive gate-clamp resistance 15 k ? table 20. h-bridge driver (continued) symbol parameter test condition min. typ. max. unit table 21. gate drivers for the external power-mos switching times symbol parameter test condition min. typ. max. unit t g(hl)xhl propagation delay time high to low (switch mode (1) v s = 13.5 v; v shx = 0; r g = 0 ? ; c g = 2.7 nf 1.5 s t g(hl)xlh propagation delay time low to high (switch mode) (1) v s = 13.5 v; v slx = 0; r g = 0 ? ; c g = 2.7 nf 1.5 s i ghxrmax maximum source current (current mode) v s = 13.5 v; v shx = 0; v ghx = 1 v; slew<4:0> = 1 f h 32 ma i ghxfmax maximum sink current (current mode) v s = 13.5 v, v shx = 0; v ghx = 2 v; slew<4:0> = 1 f h 32 ma di ighxr source current accuracy v s = 13.5 v; v shx = 0; v ghx = 1 v see figure 14: ighxr ranges di ighxf sink current accuracy v s = 13.5 v; v shx = 0; v ghx = 2 v see figure 15: ighxf ranges v dshxrsw switching voltage (v s -v sh ) between current mode and switch mode (rising) v s = 13.5 v 2.8 v v dshxfsw switching voltage (v s -v sh ) between switch mode and current mode (falling) v s = 13.5 v 2.8 v docid029145 rev 4 43/162 L99DZ120 electrical specifications 161 t0 ghxr rise time (switch mode) v s = 13.5 v; v shx = 0; r g = 0 ? ; c g = 2.7 nf 45 ns t0 ghxf fall time (switch mode) v s = 13.5 v; v shx = 0; r g = 0 ? ; c g = 2.7 nf 85 ns t0 glxr rise time v s = 13.5 v; v slx = 0; r g = 0 ? ; c g = 2.7 nf 45 ns t0 glxf fall time v s = 13.5 v; v slx = 0; r g = 0 ? ; c g = 2.7 nf 85 ns tccp 0001 programmable cross-current protection time 500 ns tccp 0010 programmable cross-current protection time 750 ns tccp 0011 programmable cross-current protection time 1000 ns tccp 0100 programmable cross-current protection time 1250 ns tccp 0101 programmable cross-current protection time 1500 ns tccp 0110 programmable cross-current protection time 1750 ns tccp 0111 programmable cross-current protection time 2000 ns tccp 1000 programmable cross-current protection time 2250 ns tccp 1001 programmable cross-current protection time 2500 ns tccp 1010 programmable cross-current protection time 2750 ns tccp 1011 programmable cross-current protection time 3000 ns tccp 1100 programmable cross-current protection time 3250 ns tccp 1101 programmable cross-current protection time 3500 ns tccp 1110 programmable cross-current protection time 3750 ns tccp 1111 programmable cross-current protection time 4000 ns f pwmh pwmh switching frequency v s = 13.5 v; v slx = 0; r g = 0 ? ; c g = 2.7 nf; pwmh-duty-cycle = 50%; tccp configured as 0001 50 khz 1. table 21. gate drivers for the external power-mos switching times (continued) symbol parameter test condition min. typ. max. unit electrical specifications L99DZ120 44/162 docid029145 rev 4 figure 13. h-driver delay times figure 14. ighxr ranges 9 * 6 + / [ w 9 & 6 1 3 : 0 + ' , 5 w w 9 & 6 1 3 : 0 + ' , 5 7 * + / [ / + 7 * + / [ + / * $ 3 * & ) 7 , * + [ u d f f x u d f \ , * + [ u 0 d [ , * + [ u 7 \ s , * + [ u 0 l q ' d w d l q s x w ( " 1 ( $ ' 5 docid029145 rev 4 45/162 L99DZ120 electrical specifications 161 figure 15. ighxf ranges 3.4.16 drain source m onitoring external h-bridge the voltages are referred to power ground and currents are assumed positive, when the current flows into the pin. 6 v v s 28 v; 6 v v sreg 28 v; t j = -40c to 150 c, unless otherwise specified. 3.4.17 open-load monito ring external h-bridge the voltages are referred to power ground and currents are assumed positive, when the current flows into the pin. 6 v v s 28 v; 6 v v sreg 28 v; t j = -40 c to 150 c, unless otherwise specified. , * + [ i d f f x u d f \ ' d w d l q s x w , * + [ i 0 d [ , * + [ i 7 \ s , * + [ i 0 l q ( " 1 ( $ ' 5 table 22. drain source monitoring external h-bridge symbol parameter test condition min. typ. max. unit v scd1_hb drain-source threshold voltage 0.375 0,5 0.625 v v scd2_hb drain-source threshold voltage 0.6 0,75 0.9 v v scd3_hb drain-source threshold voltage 0,85 1 1,15 v v scd4_hb drain-source threshold voltage 1,06 1,25 1,43 v v scd5_hb drain-source threshold voltage 1,27 1,5 1,73 v v scd6_hb drain-source threshold voltage 1,49 1,75 2,01 v v scd7_hb drain-source threshold voltage 1,7 2 2,3 v t scd_hb drain-source monitor filter time 6 s t scs_hb drain-source comparator settling time v s = 13.5 v; v sh = jump from gnd to v s 5s electrical specifications L99DZ120 46/162 docid029145 rev 4 3.4.18 fail safe low-side switch the voltages are referred to power ground and currents are assumed positive, when the current flows into the pin. 6 v v s 18 v; t j = 40 c to 150 c, unless otherwise specified. table 23. open-load monitoring external h-bridge symbol parameter test condition min. typ. max. unit v odsl low-side drain-source monitor low off-threshold voltage v slx = 0 v; v s = 13.5 v 0.15 v s v v odsh low-side drain-source monitor high off-threshold voltage v slx = 0 v; v s = 13.5 v 0.85 v s v v olshx output voltage of selected shx in open-load test mode v slx = 0 v; v s = 13.5 v 0.5 v s v r pdol pull-down resistance of the non- selected shx pin in open-load mode v slx = 0 v; v s = 13.5 v; v shx = 4.5 v 20 k ? t ol_hb open-load filter time 2 ms table 24. fail safe low-side switch symbol parameter test condition min. typ. max. unit v out_max max output voltage in case of missing supply i out = 1 ma; v s = v sreg = 0 v 2 2.5 v r dson dc output resistance i load = 250 ma; t j = 25 c 1.4 ? i load = 250 ma; t j = 130 c 2.2 ? i olimit overcurrent limitation 8 v < v s < 16 v 500 1500 ma t onhl turn on delay time to 10% v out 100 s t offlh turn off delay time to 90% v out 100 s t scf short circuit filter time 64 s dv max /dt maximum external applied slew rate on ls1_fso and ls2_fso without switching on ls guaranteed by design 60 v/s docid029145 rev 4 47/162 L99DZ120 electrical specifications 161 3.4.19 wake up input wu the voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6 v v sreg 28 v; t j = 40 c to 150 c, unless otherwise specified. 3.4.20 lin transceiver lin 2.2 compliant for bi t-rates up to 20 kbi t/s sae j2602 compatible. the voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6 v v sreg 18 v; t junction = -40 c to 150c unless otherwise specified. table 25. wake-up inputs symbol parameter test condition min. typ. max. unit v wuthn wake-up negative edge threshold voltage 0.4 v sreg 0.45 v sreg 0.5 v sreg v v wuthp wake-up positive edge threshold voltage 0.5 v sreg 0.55 v sreg 0.6 v sreg v v hyst hysteresis 0.05 v sreg 0.1 v sreg 0.15 v sreg v t wu_stat static wake filter time 64 s i wu_stdby input current in standby mode v wu < 1 v or ? v wu > (v sreg ? 1.5 v) 53060 a r wu_act input resistor to gnd in active mode and in standby mode during wake-up input sensing 80 160 300 k ? t wu_cyc cyclic wake filter time 16 s table 26. lin transmit data input: pin txd symbol parameter test condition min. typ. max. unit v txdlow input voltage dominant level active mode 1.0 v v txdhigh input voltage recessive level active mode 2.3 v v txdhys v txdhigh -v txdlow active mode 0.2 v r txdpu txd pull up resistor active mode 13 29 46 k ? table 27. lin receive data output: pin rxd symbol parameter test condition min. typ. max. unit v rxdlow output voltage dominant level active mode 0.2 0.5 v v rxdhigh output voltage recessive le vel active mode v1-0.5 v1-0.2 v electrical specifications L99DZ120 48/162 docid029145 rev 4 table 28. lin transmitter and receiver: pin lin symbol parameter test condition min. typ. max. unit v thdom receiver threshold voltage recessive to dominant state 0.4 v sreg 0.45 v sreg 0.5 v sreg v v busdom receiver dominant state 0.4v sre g v v threc receiver threshold voltage dominant to recessive state 0.5 v sreg 0.55 v sreg 0.6 v sreg v v busrec receiver recessive state 0.6 v sreg v v thhys receiver threshold hysteresis: v threc -v thdom 0.07 v sreg 0.1 v sreg 0.175 v sreg v v thcnt receiver tolerance center value: (v threc +v thdom )/2 0.475 v sreg 0.5 v sreg 0.525 v sreg v v thwkup activation threshold for wake-up comparator 1.0 1.5 2 v v thwkdwn activation threshold for wake-up comparator v sreg - 3.5 v sreg - 2.5 v sreg - 1.5 v t linbus lin bus wake-up dominant filter time sleep mode; edge: rec-dom 64 s t dom_lin lin bus wake-up dominant filter time sleep mode; edge: rec-dom- rec 28 s i lindomsc transmitter input current limit in dominant state v txd = v txdlow ; v lin = v batmax = 18 v 40 100 180 ma i bus_pas_dom input leakage current at the receiver incl. pull-up resistor v txd = v txdhigh ; v lin = 0 v; v bat = 12 v; slave mode -1 ma i bus_pas_rec transmitter input current in recessive state in standby modes; v txd = v txdhigh ; v lin > 8 v; v bat < 18 v; v lin v bat 20 a i bus_no_gnd input current if loss of gnd at device gnd = v sreg ; 0 v < v lin < 18 v; v bat = 12 v -1 1 ma i bus input current if loss of v bat at device gnd = v s ; 0 v < v lin < 18 v tj=-40 c ....105 c (1) 30 a gnd = v s ; 0 v < v lin < 18 v tj= 130 c (2) 35 a v lindom lin voltage level in dominant state active mode; v txd = v txdlow ; ? r bus = 500 ? 1.2 v v linrec lin voltage level in recessive state active mode; v txd = v txdhigh ; i lin = 10 a 0.8*v s v r linup lin output pull up resistor v lin = 0 v 20 40 60 k ? c lin lin input capacitance guaranteed by design 100 pf docid029145 rev 4 49/162 L99DZ120 electrical specifications 161 the voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6v < v s < 28v; t j = -40 c to 150 c, unless otherwise specified. 1. 105c is the maximum junction temperature of an unpowered devic e according to this test condition within the specified ambient temperature range 2. used for device test only table 29. lin transceiver timing symbol parameter test condition min. typ. max. unit t rxpd receiver propagation delay time t rxpd = max(t rxpdr , t rxpdf ); t rxpdf = t(0.5 v rxd )-t(0.45 v lin ); t rxpdr = t(0.5 v rxd )-t(0.55 v lin ); v sreg = 12 v; c rxd =20 pf; r bus = 1 k ? , c bus = 1 nf; r bus = 660 ? , c bus = 6.8 nf; r bus = 500 ? , c bus = 10 nf 6 s t rxpd_sym symmetry of receiver propagation delay time (rising vs. falling edge) t rxpd_sym = t rxpdr - t rxpdf ; v sre = 12 v; r bus = 1 k ? ; c bus = 1 nf ; c rxd = 20 pf -2 2 s d1 duty cycle 1 th rec (max) = 0.744 * v sreg ; th dom (max) = 0.581 * v sreg ; v sreg = 7 to 18 v, t bit = 50 s; d1 = t bus_rec (min) / (2 x t bit ); r bus = 1 k ? , c bus = 1 nf; r bus = 660 ? , c bus = 6.8 nf; r bus = 500 ? , c bus = 10 nf 0.396 d2 duty cycle 2 th rec (min) = 0.422* v sreg ; th dom (min) = 0.284* v sreg ; v sreg = 7.6 to 18 v, t bit = 50 s; d2 = t bus_rec (max) / (2 x t bit ); r bus = 1 k ? , c bus = 1 nf; r bus = 660 ? , c bus = 6.8 nf; r bus = 500 ? , c bus = 10 nf 0.581 d3 duty cycle 3 th rec (max) = 0.778* v sreg ; th dom (max) = 0.616* v sreg ; v sreg = 7 to 18 v, t bit = 96 s; d3 = t bus_rec (min) / (2 x t bit ); r bus = 1 k ? , c bus = 1 nf; r bus = 660 ? , c bus = 6.8 nf; r bus = 500 ? , c bus = 10 nf 0.417 d4 duty cycle 4 th rec (min) = 0.389* v sreg ; th dom (min) = 0.251* v sreg ; v sreg = 7.6 to 18 v, t bit = 96 s; d4 = t bus_rec (max) / (2 x t bit ); r bus = 1 k ? , c bus = 1 nf; r bus = 660 ? , c bus = 6.8 nf; r bus = 500 ? , c bus = 10 nf 0.590 t dom(txdl) txdl dominant time- out 12 ms electrical specifications L99DZ120 50/162 docid029145 rev 4 figure 16. lin transmit, receive timing 3.4.21 spi the voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6 v < v sreg < 18 v; v1 = 5 v; all outputs open; t j = -40 c to 150 c, unless otherwise specified. t lin lin permanent recessive time-out 40 s t dom(bus) lin bus permanent dominant time-out 12 ms table 29. lin transceiver timing (continued) symbol parameter test condition min. typ. max. unit w l p h w l p h 9 7 [ ' 9 / , 1 9 7 + u h f 9 7 + g r p w l p h 9 5 [ ' 9 / , 1 g r p 9 / , 1 u h f w 7 ; s g i w 7 ; s g u w 5 ; s g i w 5 ; s g u * $ 3 * & ) 7 table 30. input: csn symbol parameter test condition min. typ. max. unit v csnlow input voltage low level normal mode 1.0 v v csnhigh input voltage high level normal mode 2.3 v v csnhys v csnhigh - v csnlow normal mode 0.2 v i csnpu csn pull up resistor normal mode 13 29 46 k ? table 31. inputs: clk, di symbol parameter test condition min. typ. max. unit t set delay time from standby to active mode time until spi, adc and out15/out_hs are operative 10 s t set_cp delay time from standby to active mode time until power stages that are supplied by the cp are operative 560 750 960 s docid029145 rev 4 51/162 L99DZ120 electrical specifications 161 note: see figure 18: spi input timing . v in_l input low level 1.0 v v in_h input high level 2.3 v v in_hyst input hysteresis 0.2 v i pdin pull down current at input v in = 1.5 v 5 30 60 a c in (1) input capacitance at input csn, clk, di and pwm 1,2 guaranteed by design 15 pf f clk spi input frequency at clk 4mhz 1. value of input capacity is not measured in production test. parameter guaranteed by design. table 32. di, clk and csn timing symbol parameter test condition min. typ. max. unit t clk clock period 250 ns t clkh clock high time 100 ns t clkl clock low time 100 ns t set_csn csn setup time, csn low before rising edge of clk 150 ns t set_clk clk setup time, clk high before rising edge of csn 150 ns t set_di di setup time 25 ns t hold_di di hold time 25 ns t r_in rise time of input signal di, clk, csn 25 ns t f_in fall time of input signal di, clk, csn 25 ns table 31. inputs: clk, di (continued) symbol parameter test condition min. typ. max. unit table 33. output: do symbol parameter test condition min. typ. max. unit v dol output low level i do = -4 ma 0.5 v v doh output high level i do = 4 ma v1 - 0.5 v i dolk 3-state leakage current v csn = v1, 0 v < v do < v1 -10 10 a c do 3-state input capacitance guaranteed by design 10 15 pf electrical specifications L99DZ120 52/162 docid029145 rev 4 note: see figure 19: spi output timing . note: see figure 20: spi csn - output timing . 3.4.22 input lin_flash for flash mode the voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6v v sreg 18; v1 = 5 v; t j = -40 c to 150 c. table 34. do timing symbol parameter test condition min. typ. max. unit t r do do rise time c l = 50 pf; i load = -1 ma 25 ns t f do do fall time c l = 50 pf; i load = -1 ma 25 ns t en do tri l do enable time from 3-state to low level c l = 50 pf; i load = -1 ma; pull-up load to v1 50 100 ns t dis do l tri do disable time from low level to 3-state c l = 50 pf; i load = -1 ma; pull-up load to v1 50 100 ns t en do tri h do enable time from 3-state to high level c l = 50 pf; i load = -1 ma; pull-down load to gnd 50 100 ns t dis do h tri do disable time from high level to 3-state c l = 50 pf; i load = -1 ma; pull-down load to gnd 50 100 ns t d do do delay time v do < 0.3 v1; v do > 0.7 v1; c l = 50 pf 30 60 ns table 35. csn timing symbol parameter test condition min. typ. max. unit t csn_hi,min minimum csn high time, active mode transfer of spi-command to input register 6 s t csnfail csn low timeout 20 35 50 ms table 36. inputs lin_flash for flash mode symbol parameter test condition min. typ. max. unit v flashl input low level (v lin_flash for exit from flash mode) 6.1 7.25 8.4 v v flashh input high level (v lin_flash for transition into flash mode) 7.4 8.4 9.4 v v flashhys input voltage hysteresis 0.6 0.8 1.0 v docid029145 rev 4 53/162 L99DZ120 electrical specifications 161 3.4.23 inputs dir, dirh, pwmh the voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6 v v sreg 18 v; t j = -40 c to 150 c. 3.4.24 debug input the voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6 v v sreg 18 v; t j = -40 c to 150 c. 3.4.25 adc characteristics the voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6 v v sreg 18 v, t j = -40 c to 150 c. table 37. inputs dir, dirh, pwmh symbol parameter test condition min. typ. max. unit v il input voltage low level v sreg = 13.5 v 1 v v ih input voltage high level v sreg = 13.5 v 2.3 v v ihys input hysteresis v sreg = 13.5 v 0.2 v i in input pull-down current v sreg = 13.5 v 5 30 60 a table 38. debug input symbol parameter test condition min. typ. max. unit v dil input voltage low level v sreg = 13.5 v 1 v v dih input voltage high level v sreg = 13.5 v 2.3 v v dihys input hysteresis v sreg = 13.5 v 0.2 v r din pull-down resistor v debug = 6 to 18 v 2.5 5 7.5 k ? table 39. adc characteristics symbol parameter test condition min. typ. max. unit t con conversion time 2.5 s f adc clock frequency (see f clk 2) 8mhz acc accuracy voltage divider + reference (1) -2 2 % overall accuracy for wu input: wu = 22 v -3 3 overall accuracy for wu input: wu = 18 v -3.5 3.5 overall accuracy for wu input: wu = 6 v -4 4 overall accuracy for wu input: wu = 4.5 v -4.6 4.6 electrical specifications L99DZ120 54/162 docid029145 rev 4 3.4.26 temperature diode characteristics the voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6 v v sreg 18 v, t j = -40 c to 150 c 3.4.27 interrupt outputs the voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6 v v sreg 18 v, t j = -40 c to 150c ie i i integral linearity error 4 lsb ie d i differential linearity error 2lsb v ainvs conversion voltage range (v s , v sreg & wu) 122v v aintemp conversion voltage range (t cl 1 ?t cl 6) 02v 1. guaranteed by design. table 39. adc characteristics (continued) symbol parameter test condition min. typ. max. unit table 40. temperature diode characteristics symbol parameter test condition min. typ. max. unit v troom 1-6 t sense output voltage at 25 c v s = 12 v; t = 25 c ? 1.4 v v tsense1-6 t sense output voltage 1 - 8 t = 25 c; t = 130 c; ? t = -40 c ?-4 mv/k table 41. interrupt outputs symbol parameter test condition min. typ. max. unit v intl output low level i int = -4 ma 0.5 v v inth output high level i int = 4 ma v1 - 0.5 v i intlk 3-state leakage current 0 v < v int < v1 -10 10 a t interrupt interrupt pulse duration (nint, rxd_l/nint) 56 ? s t int_react interrupt reaction time tested by scan chain 6 40 s docid029145 rev 4 55/162 L99DZ120 electrical specifications 161 3.4.28 timer1 and timer2 6 v v sreg 18 v; t j = -40 c to 150 c figure 17. spi ? transfer timing diagram the spi can be driven by a micro controller wit h its spi peripheral running in the following mode: cpol = 0 and cpha = 0. for this mode input data is sampled by the low to high transition of the clock clk, and output data is changed from the high to low transition of clk. table 42. timer1 and timer2 symbol parameter test condition min. typ. max. unit ton 1 timer on time 0.1 ms ton 2 timer on time 0.3 ms ton 3 timer on time 1 ms ton 4 timer on time 10 ms ton 5 timer on time 20 ms t1 timer period 10 ms t2 timer period 20 ms t3 timer period 50 ms t4 timer period 100 ms t5 timer period 200 ms t6 timer period 500 ms t7 timer period 1000 ms t8 timer period 2000 ms & 6 1 & / . ' , ' 2 , q s x w ' d w d 5 h j l v w h u & 6 1 k l j k w r o r z ' 2 h q d e o h g w l p h ' , g d w d z l o o e h d f f h s w h g r q w k h u l v l q j h g j h r i & / . v l j q d o w l p h w l p h w l p h w l p h ' 2 g d w d z l o o f k d q j h r q w k h i d o o l q j h g j h r i & / . v l j q d o * o r e d o ( u u r u & 6 1 o r z w r k l j k d f w x d o g d w d l v w u d q v i h u h g w r r x w s x w s r z h u v z l w f k h v r o g g d w d q h z g d w d ; ; ; ; ; ; & r p p d q g % \ w h * o r e d o 6 w d w x v % \ w h ' d w d * $ 3 * & ) 7 electrical specifications L99DZ120 56/162 docid029145 rev 4 figure 18. spi input timing 9 d o l g 9 d o l g & 6 1 & / . ' , w v h w & 6 1 w & / . + w v h w & / . w & / . / w k r o g ' , w v h w ' , * $ 3 * & ) 7 7 $ $ 7 $ $ 7 $ $ 7 $ $ 7 $ $ 7 $ $ docid029145 rev 4 57/162 L99DZ120 electrical specifications 161 figure 19. spi output timing 7 i & / . 7 u & / . & / . 9 f f 9 f f 9 f f ' 2 o r z w r k l j k 9 f f 9 f f 7 u ' 2 7 g ' 2 9 f f 9 f f 7 i ' 2 ' 2 k l j k w r o r z 7 i & 6 1 7 u & 6 1 & 6 1 9 f f 9 f f 9 f f 7 h q ' 2 b w u l b / 7 h q ' 2 b w u l b + 7 g l v ' 2 b / b w u l 7 g l v ' 2 b + b w u l ( " 1 ( $ ' 5 electrical specifications L99DZ120 58/162 docid029145 rev 4 figure 20. spi csn - output timing figure 21. spi ? csn high to low transition and global status bit access 3.4.29 sgnd loss comparator t j = -40 c to 150 c, unless otherwise specified. & 6 1 g 2 1 w w u l q i l q w 2 ) ) w g 2 ) ) w 2 ) ) v w d w h 2 1 v w d w h 2 ) ) v w d w h 2 1 v w d w h 2 1 w r x w s x w f x u u h q w r i d g u l y h u r x w s x w f x u u h q w r i d g u l y h u & 6 1 o r z w r k l j k g d w d i u r p v k l i w u h j l v w h u l v w u d q v i h u u h g w r r x w s x w s r z h u v z l w f k h v w & 6 1 b + , p l q ( " 1 ( $ ' 5 & 6 1 & / . ' , ' 2 & 6 1 k l j k w r o r z d q g & / . v w d \ v o r z v w d w x v l q i r u p d w l r q r i g d w d e l w i d x o w f r q g l w l r q l v w u d q v i h u h g w r ' 2 ' , g d w d l v q r w d f f h s w h g ' 2 v w d w x v l q i r u p d w l r q r i g d w d e l w * 6 7 % i d x o w f r q g l w l r q z l o o v w d \ d v o r q j d v & 6 1 l v o r z w l p h w l p h w l p h w l p h ( " 1 ( $ ' 5 table 43. sgnd loss comparator symbol parameter test condition min. typ. max. unit v sgndloss v sgnd loss threshold (v sgnd ? v pgnd ) 100 270 500 mv t sgndloss v sgnd loss filter time 5 7 9 s docid029145 rev 4 59/162 L99DZ120 application information 161 4 application information 4.1 supply v s , v sreg v sreg supplies voltage regulators v1 and v2, all internal regulated voltages for analog and digital functionality, lin and both p-chann el high-side switches out15 and out_hs. all other high-sides, fail safe block and the charge pump are supplied by v s . in case the v sreg pin is disconnected, all power outputs connected to v s are automatically switched off. 4.2 voltage regulators the device contains two independent and fully protected low drop voltage regulators designed for very fast transient response and do not require electrolytic output capacitors for stability. the output voltage is stable with ceramic load capacitors >220 nf. 4.2.1 voltage regulator: v1 the v1 voltage regulator provides 5 v supply voltage and up to 250 ma continuous load current to supply the system microcontroller. the v1 regulator is embedded in the power management and fail-safe functionality of the de vice and operates according to the selected operating mode. the v1 voltage regulator is supplied by pin v sreg . in addition, the v1 regulator supplies the devices internal loads. the voltage regulator is protected against overload and overtemperature. an external reverse current protection has to be provided by the application circuitry to prevent the input capacitor from being discharged by negative transients or low input voltage. current limitation of the regulator ensures fast charge of external bypass capacito rs. the output voltage is stable for ceramic load capacitors >220 nf. in case the device temperature exceeds the tsd1 threshold (either cluster or grouped mode) the v1 regula tor remains on. the micro controller ha s the possibility fo r interaction or error logging. if the chip te mperature exceeds t he tsd2 threshold (tsd2 > tsd1), v1 will be deactivated and all wakeup sources (lin, wu and timer) are disabled. after t tsd , the voltage regulator will restart au tomatically. if the restart fails 7 times within one minute the devices enter the forced vbat_standby mode. the status bit forced_sleep_tsd2/v1sc (sr1) is set. 4.2.2 voltage regulator: v2 the voltage regulator v2 is supplied by pin v sreg and can supply additional 5 v loads such as sensors or potentiometers. the maximum continuous load current is 50 ma. the regulator is protected against: ? overload ? overtemperature ? short-circuit (short to ground and battery supply voltage) ? reverse biasing application information L99DZ120 60/162 docid029145 rev 4 4.2.3 voltage regulator failure the v1, and v2 regulator output voltages are monitored. in case of a drop below the failure thresholds (v1 < v1 fail for t > t v1fail , v2 < v2 fail for t > t v2fail ), the failure bits v1fail, v2fail (sr 2) are latched. 4.2.4 short to ground detection at turn-on of the v1 and v2 regulators, a short-to-gnd condition is detected by monitoring the regulator output voltage. if v1 or v2 is below the v1 fail (or v2 fail ) threshold for t > t v1short (t > t v2short ) after turn-on, the devices will identify a short circ uit condition at the related re gulator will be switched off. in case of v1 short-to-gnd the device enters forced vbat_standby mode automatically. bits forced_sleep_tsd2/v1sc and (sr 1) v1fail (sr 2) are set. in case of a v2 short-to-gnd failure the v2sc (sr 2) and v2fail (sr 2) bits are set. once the output voltage of the corr esponding regulator exceeded the v1 fail (v2 fail ) threshold the short-to-ground detection is disabled. in case of a short-to-ground condition, the regulator is switched off due to thermal shutdown. v1 is s witched off at tsd2, v2 is switched off at tsd1. docid029145 rev 4 61/162 L99DZ120 application information 161 4.2.5 voltage regulator behavior figure 22. voltage regulator behaviour and diagnosis during supply voltage 4.3 operating modes the devices can be operated in the following operating modes: ? active ? lin flash ? v1_standby ? vbat_standby ? debug 4.3.1 active mode all functions are available and th e device is controlled by spi. 9 v u h j > 9 @ 9 > 9 @ 1 u h v h w r x w s x w 9 3 2 5 5 6 7 % e l w l v v h w d q g u h j l v w h u v d u h v h w w r g h i d x o w d w 9 3 2 5 b 5 x v 9 5 7 + + l j k / r z 9 i d l o , i w ! w y v k r u w 9 v k r u w g h w h f w h g 9 e d w w v w d q g e \ w ! w 9 i d l o 9 i d l o e l w l v v h w 9 v u h j x y e l w l v v h w i l o w h u w l p h w 2 9 8 9 b i l o w w w 8 9 w u u w u u w ! w 8 9 1 r 5 h v h w j h q h u d w h g w ! w 8 9 w y u w y u 9 6 u h j 8 9 w 9 ) 6 9 v s h f l i l f & r q w u r o 5 h j l v w h u v d u h v h w w r g h i d x o w y d o x h v 9 v u h j $ % 6 p l q + l j k = * u r x q g h g 9 v u h j $ % 6 p l q p l q l p x p 9 v u h j w r f r q w u r o 1 5 h v h w 9 6 u h j 8 9 9 v u h j x q g h u y r o w d j h 9 3 2 5 b 5 ) 9 v u h j s r z h u r q u h v h w y r o w d j h u l v l q j i d o o l q j 9 5 7 + 9 u h v h w w k u h v k r o g y r o w d j h 9 ) $ , / 9 i d l o w k u h v k r o g y r o w d j h w 8 9 9 x q g h u y r o w d j h i l o w h u w l p h w 9 i d l o 9 i d l o i l o w h u w l p h w u u u h v h w s x o v h u h d f w l r q w l p h w y u u h v h w s x o v h g x u d w l r q w 9 v k r u w 9 v k r u w i l o w h u w l p h w 9 ) 6 9 i d l o v d i h i l o w h u w l p h w 2 9 8 9 b i l o w 9 v u h j r y h u x q g h u y r o w d j h i l o w h u w l p h & r q w u r o 5 h j l v w h u v v h w w r g h i d x o w d w 9 3 2 5 b ) ( " 1 ( $ ' 5 application information L99DZ120 62/162 docid029145 rev 4 4.3.2 flash mode to program the system microcontroller via lin bus signals, the devices can be operated in lin flash mode. the watchdog is disabled in this mode. the flash mode is entered by applying an external voltage at the pin: ? v lin_flash v flashh (lin flash mode) in lin flash mode the maximum bitrate is increased to 100 kbit/s automatically (lin_hs_en = 1). a transition from flash mode to v1_stan dby or vbat_standby mode is not possible. at exit from flash modes (v lin_flash < v flashl ) no nreset pulse is generated. the watchdog starts with a long open window (t lw ). 4.3.3 sw-debug mode to allow software debugging, the watchdog can be deactivated by applying an external voltage to the debug input pin (v debug > v dih ). in debug mode, all device functionality and operating modes are available. the watchdog is deactivated. at exit from debug mode (v debug < v dil ) the watchdog starts with a long open window. note: the device includes a test mode. this mo de is activated by a dedicated sequence which includes a high voltage at the debug pin. t he debug pin must be kept at nominal voltage levels in order to avoid accidental activation of the test mode. 4.3.4 v1_standby mode the transition from active mode to v1_standby mode is controlled by spi. to supply the micro controller in a low power mode, the v1 voltage regulator remains active. after the v1_standby command (csn low to high transition), the device enters v1_standby mode immediately and the watchdog starts a long open window (t lw ). the watchdog is deactivated as soon as the v1 load current drops below the i cmp threshold (i v1 < i cmp_fal ). the v1 load current monitoring can be deactivated by setting icmp = 1. in this configuration the watchdog will be deactivated up on transition into v1_standby mode without monitoring the v1 load current. writing icmp (cr 34) = 1 is only possibl e with the first spi command after setting icmp_config_en (config reg) = 1. the icmp_config_en bit is reset to 0 automatically with the next spi command. power outputs (except out_hs & out15) are switched off in v1_standby mode. out_hs & out15 remain in the configuration programmed prior to the standby command in order to enable (cyclic) supply of external contacts. the timer signal (timer1 or timer2) can be mirrored to the nint output pin during v1_standby mode. lin transmitter (txdl) is off. docid029145 rev 4 63/162 L99DZ120 application information 161 4.3.5 interrupt figure 23. nint pins rxdl/nint indicates: ? a wake-up event from v1_standby mode and the programmable timer interrupt rxdl/nint pin is pulled low for t = t interrupt . nint indicates: ? in active mode: v sreg dropped below the programmed early warning threshold in control register 3 (v sreg < vsreg_ew_th); feature is deactiva ted if vsreg_ew_th is set to 0 v. in v1_standby mode ? programmable timer interrupt; an nint pulse is generated at the beginning of the timer on-time (timer 1 or timer2) ? wake-up from v1_standby mode by any wake-up source nint is pulled low for t = t interrupt in case of increasing v1 load current during v1_standby mode (i v1 > i cmp_ris ), the device remains in standby mode and the watchdog starts with a long open window. no interrupt signal is generated. 4.3.6 vbat_standby mode the transition from active mode to vbat_st andby mode is initiated by an spi command. in vbat_standby mode, the voltage regulators v1 and v2 (depending on configuration in cr 1), the power outputs (except out15 and out_hs) as well as lin transmitter are switched off. an nreset pulse is generated upon wake-up from vbat_standby mode. 4.4 wake-up from standby modes a wake-up from standby mode will switch the device to active mo de. this can be initiated by one or more of the following events: ' l j l w d o o r j l f * 1 ' 9 ' d w d 2 x w ' d w d , q ( q d e o h * 1 ' ( 6 ' s u r w ( " 1 ( $ ' 5 application information L99DZ120 64/162 docid029145 rev 4 4.4.1 wake up input the wu input can be configured as wake-up so urce. the wake-up input is sensitive to any level transition (positive and negative edge) an d can be configured for static or cyclic monitoring of the input voltage level. for static contact monitoring, a filter time of t wu_stat is implemented. the filter is started when the input voltage passes the specified threshold v wu_thp or v wu_thn . cyclic contact monitoring allows periodical activation of the wake-up input to read the status of the external contact. the periodical activation can be configured to timer 1 or timer 2. the input signal is filtered with a filter time of t wu_cyc after a delay (80% of the configured timer on-time). a wake- up will be processed if the status has changed versus the previous cycle. the buffered output out_hs can be us ed to supply the external contacts with the timer setting according to the cyclic monitoring of the wake-up input. in standby modes, the input wu is configurable with an internal pull-up or pull-down current source according to the setup of the external contact. in active mode the inputs have an internal pull down resistor (r wu_act ) and the input status can be read by spi. static sense should be configured before the read operation is started in order to reflect the actual input level. 4.5 functional over view (truth table) table 44. wake-up events description wake up source description lin bus activity always enabled level change of wu can be configured or disabled by spi i v1 >i cmp_ris device remains in v1_standby mode but watchdog is enabled (if i cmp = 0). no interrupt is generated. timer interrupt / wake up of c by timer programmable by spi: ? v 1 _standby mode : device wakes up after programmable timer expiration. nint and rxdl/nint interrupt signals are generated ? v bat _standby mode : device wakes up after programmable timer expiration, v1 regulator is turned on and nreset signal is generated spi access always active (except in v bat_standby mode ) wake up event: csn is low and first rising edge on clk table 45. status of different functions/features vs operating modes function comments operating modes active mode v 1 -standby static mode (cyclic sense) v bat -standby static mode (cyclic sense) voltage regulator v1 v out = 5 v on on (1) off voltage regulator v2 v out = 5 v on/ off (2) on (2) / off on (2) / off reset generator on on off docid029145 rev 4 65/162 L99DZ120 application information 161 window watchdog v 1 monitor on off (on if i v1 > i cmp and i cmp = 0) off wake up off active (3) active (3) hs-cyclic supply oscillator time base on / off on (2) / off on (2) / off lin lin 2.2a on off (4) off (4) oscillator osc1 2 mhz on on/off (5) on/off (5) oscillator osc2 32 mhz on off off v sreg-monitor on (6) (6) v s-monitor on off off h-bridge gate driver, bridge drivers, all high-side drivers (except out_hs & out15) supplied by v s on/ off (2) off off fail-safe low-side switches on/ off (7) on on short circuit protection for fail-safe low-side switches (in case ls is switched on) on on on out_hs & out15 (p- channel hs) supplied by v sreg on/ off (2) on/ off (2) on/ off (2) charge pump on off off adc (spi read out and v sreg early warning interrupt) on off off thermal shutdown tsd2 on on off thermal shutdown tsd1x for out_hs and out15 (p- channel hs) on on/ off (2) on/ off (2) 1. supply the processor in low current mode. 2. according to spi setting and dir. 3. unless disabled by spi. 4. the bus state is internally stored when going to standby mode. a change of bus state will lead to a wake-up after exceeding of internal filter time. 5. on, if cyclic sense is e nabled or during wake-up request. 6. cyclic activation = puls ed on during cyclic sense. 7. on in fail-safe mode; if standby mode is entered with acti ve fail-safe mode the output remains on in standby mode. table 45. status of different functions/features vs operating modes (continued) function comments operating modes active mode v 1 -standby static mode (cyclic sense) v bat -standby static mode (cyclic sense) application information L99DZ120 66/162 docid029145 rev 4 figure 24. main operating modes 4.6 configurable window watchdog during normal operation, the watchdog monitors the micro controller within a programmable trigger cycle. after power-on or standby mode, the watchdog is started with a timeout (long open window t lw ). the timeout allows the micro controller to run its own setup and then to start the window watchdog by setting trig (cr1,configreg) =1 subsequently, the micro controller has to serve the watchdog by alternating the watchdog trigger bit trig (cr1,config reg) within the safe trigger area t swx . the trigger time is configurab le by spi. a correct watchdog trigger signal will immediately start the next cycle. after 8 watchdog failures in sequence, the v1 regulator is switched off for t v1off . after 7 additional watchdog failures the v1 regulator is turned off permanently and the device goes into forced vbat_stand by mode. the status bit forced_sleep_wd (sr 1) is set. a wake-up is possible by lin. after wake-up from forced vb at_standby mode and the watc hdog trigger still fails, the device enters forced vbat_standby mo de again after one long open window. $ f w l y h 0 r g h 9 2 1 5 h v h w * h q h u d w r u d f w l y h : d w f k g r j d f w l y h 9 6 w d q g e \ 0 r g h 9 2 1 5 h v h w * h q h u d w r u d f w l y h : d w f k g r j 2 ) ) l i , y , f p s r u , & 0 3 9 e d w 6 w d q g e \ 0 r g h 9 2 ) ) 5 h v h w * h q h u d w r u 2 ) ) 1 u h v h w o r z : d w f k g r j 2 ) ) : d n h x s ( y h q w : d n h x s ( y h q w 6 3 , f r p p d q g 9 e d w v w d u w x s $ o o u h j l v w h u v 6 h w w r g h i d x o w & k l s 5 h v h w e l w 5 6 7 % 9 v ! 9 s r u [ 7 k h u p d o 6 k x w g r z q 7 6 ' 2 5 [ : ' i d l o ) o d v k 0 r g h / , 1 ) x q f w l r q d o l w \ d v l q $ f w l y h 0 r g h : d w f k g r j 2 ) ) / , 1 ) o d v k 0 r g h / , 1 b + 6 b h q 9 / , 1 b ) / $ 6 + ! 9 i o d v k 9 i o d v k 6 3 , f r p p d q g 2 5 [ 7 k h u p d o 6 k x w g r z q 2 5 9 v k r u w w r * 1 ' 9 9 i r u p v d i w h u v z l w f k 2 1 2 5 [ : ' ) d l o x u h ( " 1 ( $ ' 5 9 / , 1 b ) / $ 6 + 9 / , 1 b ) / $ 6 + ! 9 i o d v k 9 / , 1 b ) / $ 6 + ! 9 i o d v k docid029145 rev 4 67/162 L99DZ120 application information 161 this actually produces an a dditional watchdog failure bu t the watchdog fail counter will remain at maximum value of 15 failures. this sequence is repeated until a valid watchdog trigger event is performed by writing trig = 1. in case of a watchdog failure, the power outputs and v2 are switched off and the status bit wdfail (sr 1) is set to 1. a reset pulse is generated at nreset output and the device enters fail-safe mode. control registers are se t to their fail safe va lues and the fail-safe low-side switches are turned on. please refer to chapter section 4.7: fail-safe mode for more details. the following diagrams illustrate the watchdog behavior of th e devices. the diagrams are split into 3 parts. the first diagram shows the functional behavior of the watchdog without any error. the second diagram covers the behav ior covering all the error conditions, which can affect the watchdog behavior. figure 27: watchdog in flash mode shows the transition in and out of flash modes. figure 25 , figure 26 and figure 27 can be overlapped to get all the possible state transitions under all circumstances. for a better readability, they were split in normal operating, operating with errors and flash mode. figure 25. watchdog in normal operating mode (no errors) : ' 2 ) ) o r q j r s h q z l q g r z : l q g r z 0 r g h s u r s s h u w u l j j h u l q : l q g r z p r g h 7 5 , * ? 9 e d w v w d q g e \ p r g h 9 6 w d q g e \ , 9 , & 0 3 $ f w l y h p r g h $ f w l y h p r g h : d n h x s 9 ! 9 5 7 [ * r 9 e d w v w e \ 2 u * r 9 v w e \ $ 1 ' , y , f p s * r 9 v w e \ j r 9 e d w v w e \ ( " 1 ( $ ' 5 application information L99DZ120 68/162 docid029145 rev 4 figure 26. watchdog with error conditions figure 27. watchdog in flash mode note: whenever the device is operated without se rvicing the mandatory watchdog trigger events, a sequence of 15 consecutive reset event s is performed and the device enters the forced_vbat_stby mode with bi t forced_sleep_wd in sr1 set. if the device is woken up after such a forced vbat_standby condition and the watchdog is still not serviced, the device, after one long open watchdog window will re-enter the same forced_vbat_stby mode until the next wake up event. in this case, an additional watchdog failure is generated, but the fail counter is not cleared, keeping the maximum number of 15 failures. this sequence is repeated until a valid watchdog trigger event is performed by writing trig = 1. ( " 1 ( $ ' 5 : ' 2 ) ) o r q j r s h q z l q g r z : l q g r z 0 r g h s u r s s h u w u l j j h u l q : l q g r z p r g h 7 5 , * ? 9 9 u w k 9 e d w v w d q g e \ p r g h i r u f h g 9 % $ 7 [ : ' i d l o [ 7 6 ' 6 k r u w 9 $ f w l y h p r g h $ f w l y h p r g h ) d l o 6 d i h ( y h q w ) d l o 6 d i h ( y h q w i r u f h g 9 e d w v w e \ 9 9 u w k 9 ! 9 u w k : ' 2 ) ) o r q j r s h q z l q g r z : l q g r z 0 r g h ) / $ 6 + ' h e x j p r g h $ f w l y h p r g h $ f w l y h p r g h ( q w h u ) / $ 6 + ' h e x j p r g h ( [ l w i u r p ) / $ 6 + ' h e x j p r g h ( q w h u ) / $ 6 + ' h e x j p r g h ( " 1 ( $ ' 5 docid029145 rev 4 69/162 L99DZ120 application information 161 4.6.1 change watchdog timing the watchdog trigger time is configured by se tting wd_time_x (cr 2). writing to these bits is possible only using the first spi command after setting wd_config_en = 1 (config reg). the wd_config_en bit is reset to 0 automatically with the next spi command. 4.7 fail-safe mode 4.7.1 temporary failures the devices enter fail-safe mode in case of: ? watchdog failure ? v1 turn on failure ? v1 short (v1 < v1 fail for t > t v1short ) ? v1 failure (v1 < v rtxfalling for t > t v1fs ) ? thermal shutdown tsd2 the fail safe functionality is also available in v1_standby mode. during v1_standby mode the fail safe mode is entered in the following cases: ? v1 failure (v1 < v rtxfalling for t > t v1fs ) ? watchdog failure (if watch dog still running due to i v1 > i cmp_fal ) ? thermal shutdown tsd2 in fail safe mode the devices re turn to a fail safe state. the fail safe condition is indicated to the system in the global status byte. the conditions during fail safe mode are: ? all outputs beside ls1_fso and ls2_fso are turned off ? all control registers are set to fail safe default values ? write operations to control registers are blocked until the fail safe condition is cleared. the following bits are not write protected: ? trig (cr1 application information L99DZ120 70/162 docid029145 rev 4 4.7.2 non-recoverable failure s ? forced vbat_standby mode if the fail-safe condition persists and all attemp ts to return to normal system operation fail, the devices enter the forced vbat_standby mode in order to prevent damage to the system. the forced vbat_standby mode can be terminated by any wake-up source. the root cause of the forced vbat_standby mode is in dicated in the spi status registers. in forced vbat_standby mode, all control re gisters are set to power-on default values except: ? cp_dith_dis (config. reg docid029145 rev 4 71/162 L99DZ120 application information 161 4.8 reset output (nreset) figure 28. nreset pin if v1 is turned on and the voltage exceeds the v1 reset threshold, the reset output nreset is pulled up to v1 by an internal pull-up resistor after a reset delay time (t v1r ). this is necessary for a defined start of the micro controller when the application is switched on. since the nreset output is realized as an open drain out put it is also possible to connect an external nreset open drain nreset source to the output. as soon as the nreset is released by the devices the watchdog starts with a long open window. a reset pulse is generated in case of: ? v1 drops below v rtxfalling (configurable by spi) for t > t uv1 ? watchdog failure ? turn-on of the v1 regulator (v sreg power-on or wake-up from vbat_standby mode) 4.9 lin bus interface figure 29. rxdl pin ' l j l w d o o r j l f * 1 ' 9 ' d w d 2 x w ' d w d , q * 1 ' ( 6 ' s u r w . 2 k p v ( " 1 ( $ ' 5 ' l j l w d o o r j l f * 1 ' 9 ' d w d 2 x w ' d w d , q ( q d e o h * 1 ' ( 6 ' s u r w ( " 1 ( $ ' 5 application information L99DZ120 72/162 docid029145 rev 4 4.9.1 features ? lin 2.2a compliant (saej260 2 compatible) transceiver ? lin cell has been designed according to ?hardware requirements for transceivers (version 1.3)? ? bitrate up to 20 kbit/s ? dedicated lin flash mode with bitrate up to 100 kbit/s ? gnd disconnection fail safe at module level ? off mode: does not disturb network ? gnd shift operation at system level ? micro controller interface with cmos-compatible i/o pins ? internal pull-up resistor ? receive-only mode ? esd and transient immunity according to iso7637 and en / iec61000-4-2 ? matched output slopes and propagation delay ? wake-up behaviour according to lin2.2a and hardware requirements for lin, can and flexray interfaces (version 1.3) at v sreg > v por (i.e. v sreg power-on reset threshold), the lin transceiver is enabled. the lin transmitter is disabled in case of the following errors: ? dominant txdl time out ? lin permanent recessive ? thermal shutdown 1 ? v sreg overvoltage/ undervoltage the lin receiver is not disabled in case of any failure condition. the default bitrate of the transceiver allows communication up to 20 kbit/s. to enable fast flashing via the lin bus, the transceiver can be operated in high speed mode by setting bit lin_hs_en (config reg) = 1. this feature is enabled automatically in lin flash mode. 4.9.2 error handling the devices lin transceiver provides the following 3 error handling features. dominant txdl time out if txd_l is in dominant state (low) for t > t dom(txdl) the transmitter will be disabled, the status bit lin_txd_dom (sr 2) will be set. the transmitter remains disabled un til the status bit is cleared. the txd dominant timeout detection can be disabled via spi (lin_txd_tout_en = 0). permanent recessive if txd_l changes to dominant (low) state but rxd_l signal does not follow within t < t lin the transmitter will be disabled, the status bit lin_perm_rec (sr 2) will be set. the transmitter remains disabled until the status bit is cleared. docid029145 rev 4 73/162 L99DZ120 application information 161 permanent dominant if the bus state is dominant (low) for t > tdo m(bus) a bus permanent do minant failure will be detected. the status bit li n_perm_dom (sr 2) will be set. the transmitter will not be disabled. 4.9.3 wake up from standby modes in low power modes (v1_standby mode and vb at_standby mode) the devices can receive two types of wake up signals from the lin bus (configurable by spi bit lin_wu_config (config reg)): ? recessive-dominant-recessive pattern with t > t dom_lin (default, according to lin 2.2a) ? state change recessive-to-dominant or do minant-to-recessive (according to lin 2.1) pattern wake-up (default) figure 30. wake-up behavior according to lin 2.2a status change wake-up - recessive-to-dominant normal wake-up can occur when the lin transceiver was set in standby mode while lin was in recessive (high) state. a dominant level at lin for t > t linbus , will switch the devices to active mode. status change wake-up - dominant-to-recessive if the lin transceiver was set in standby mode while lin was in dominant (low) state, recessive level at lin for t > t linbus , will switch the devices to active mode. 4.9.4 receive-only mode the lin transmitter can be disabled in active mode by setting the bit lin_rec_only (cr2). in this mode it is possible to listen to the bus but not sending to it. / , 1 u h f h v v l y h / , 1 g r p l q d q w 9 6 x s s o \ 9 6 x s s o \ w g r p / , 1 v o h h s p r g h v w d q g e \ p r g h 9 r o w d j h d w / , 1 3 l q r i / , 1 3 k \ v l f d o / d \ h u g h y l f h r u v l p l o d u p r g h q d p l q j * $ 3 * & ) 7 application information L99DZ120 74/162 docid029145 rev 4 4.10 serial peripheral interface (st spi standard) a 32-bit spi is used for bi-directional communication with the microcontroller. the spi is driven by a microcontroller with it s spi peripheral running in following mode: cpol = 0 and cpha = 0. for this mode input dat a is sampled by the low to high transition of the clock clk, and output data is changed from the high to low transition of clk. this device is not limited to microcontroller with a built-in spi. only three cmos-compatible output pins and one input pin is needed to communicate with the device. a fault condition can be detected by setting csn to low. if csn = 0, the do-pin reflects the global error flag (fault condition) of the device. ? chip select not (csn) the input pin is used to select the serial in terface of this device. when csn is high, the output pin (do) is in high impedance state. a low signal activates the output driver and a serial communication can be started. the state during csn = 0 is called a communication frame. if csn = low for t > t csnfail the do output is switched to high impedance in order not to block the signal line for other spi nodes. ? serial data in (di) the input pin is used to transfer data serial into the device. the data applied to the di is sampled at the rising edge of the clk signal and shifted into an internal 32-bit shift register. at the rising edge of the csn signal the content of the shift register is transferred to data in put register. the writing to the selected data input register is only enabled if exactly 32-bit are transmitte d within one communication frame (i.e. csn low). if more or less clock pulses are counted within one frame the complete frame is ignored. this safety function is implemente d to avoid an activati on of the output stages by a wrong communication frame. note: due to this safety functionality a daisy c haining of spi is not possible. instead, a parallel operation of the spi bus by controlling t he csn signal of the connected ic's is recommended. ? serial data out (do) the data output driver is activated by a l ogical low level at the csn input and will go from high impedance to a low or high level depending on the global error flag (fault condition). the first rising edge of the clk input after a high to low transition of the csn pin will transfer the content of the selected status register into the data out shift register. each subsequent falling edge of the clk will shift the next bit out. ? serial clock (clk) the clk input is used to synchronize the inpu t and output serial bit streams. the data input (di) is sampled at the rising edge of the cl k and the data output (do) will change with the falling edge of the clk signal. the spi can be driven with a clk frequency up to 4 mhz. docid029145 rev 4 75/162 L99DZ120 application information 161 4.11 power supply failure 4.11.1 v s supply failure v s overvoltage if the supply voltages v s reaches the overvoltage threshold v sov : ? lin remains enabled ? out1 to out_14 are turned off (default). the shutdown of outputs may be disabled by spi (vs_ov_sd_en (cr 3) = 0) ? charge pump is disabled (and is switched on automatically in case the supply voltage recovers to normal operating voltage) ? h-bridge gate driver is s witched into sink condition ? recovery of outputs after overvoltage condition is configurable by spi: ? vs_lock_en (cr 3) = 1: outputs are off until read&clear vs_ov (sr 2). ? vs_lock_en (cr 3) = 0: outputs turned on automatically after v s overvoltage condition has recovered. ? the overvoltage bit vs_ov (sr 2) is set and can be cleared with a ?read&clear? command. the overvoltage bit is reset auto matically if vs_lock_en (cr 3) = 0 and the overvoltage condition has recovered. v s undervoltage if the supply voltage v s drops below the under voltage threshold voltage (v suv ): ? lin remains enabled ? out1 to out14 are turned off (default). ? the shutdown of outputs may be disabled by spi (vs_uv_sd_en (cr 3) = 0) ? recovery of outputs after undervoltage condition is configurable by spi: ? vs_lock_en (cr 3) = 1: outputs ar e off until read&clear vs_uv (sr 2). ? vs_lock_en (cr 3) = 0: outputs turned on automatically after v s undervoltage condition has recovered. ? the undervoltage bit vs_uv (sr 2) is set and can be cleared with a ?read&clear? command. the undervoltage bit is removed aut omatically if vs_lock_en (cr 3) = 0 and the undervoltage condition has recovered. application information L99DZ120 76/162 docid029145 rev 4 4.11.2 v sreg supply failure v sreg overvoltage if the supply voltages v sreg reaches the overvoltage threshold v sreg_ov : ? lin is switched to high impedance ? out15 and out_hs are turned off (default). the shutdown of outputs may be disabled by spi (v sreg_ov_sd_en (cr 3) = 0) ? recovery of outputs after overvoltage condition is configurable by spi: ? vsreg_lock_en (cr 3) = 1: outputs are off until read&clear vsreg_ov (sr 2). ? vsreg_lock_en (cr 3) = 0: outputs turned on automatically after v sreg overvoltage condition has recovered. ? the overvoltage bit vsreg_ov (sr 2) is set and can be cleared with a ?read&clear? command. the overvoltage bit is reset auto matically if vsreg_lock_en (cr 3) = 0 and the overvoltage condition has recovered. v sreg undervoltage if the supply voltage v sreg drops below the under voltage threshold voltage (v sreg_uv ): ? lin is switched to high impedance ? out15 and out_hs are turned off (default). ? the shutdown of outputs may be disabled by spi (vsreg_uv_sd_en (cr 3) = 0) ? recovery of outputs after undervoltage condition is configurable by spi: ? vsreg_lock_en (cr 3) = 1: outputs are off until read&clear vsreg_uv (sr 2). ? vsreg_lock_en (cr 3) = 0: output s turned on automatically after v sreg undervoltage condition has recovered. ? the undervoltage bit vsreg_uv (sr 2) is set and can be cleared with a ?read&clear? command. the undervoltage bit is removed automatically if vsreg_lock_en (cr 3) = 0 and the undervoltage condition has recovered. docid029145 rev 4 77/162 L99DZ120 application information 161 4.12 temperature warnin g and thermal shutdown figure 31. thermal shutdown protection and diagnosis note: the thermal state machine will recover the same state as before entering standby mode. in case of a tsd2 it will enter tsd1 state. $ f w l y h 0 r g h 6 w d q g e \ 0 r g h v g x u l q j f \ f o l f v h q v h 7 h p s h u d w x u h : d u q l q j ' l d j q r v l v 7 : 7 6 ' $ o o r x w s x w v d q g 9 r i i 9 r q ' l d j q r v l v 7 6 ' 7 m ! 7 6 ' ? 5 h d g d q g & o h d u ? 2 5 3 r z h u r q u h v h w 7 6 ' $ o o r x w s x w v d q g 9 r i i 9 r i i i r u w w 7 6 ' ' l d j q r v l v 7 6 ' 7 m ! 7 6 ' ) r u f h g 9 e d w b v w d q g e \ 0 r g h [ 7 6 ' : d n h x s h y h q w 3 r z h u r q u h v h w ? 5 h d g d q g & o h d u ? 2 5 3 r z h u r q u h v h w 7 m ! 7 z w ! w 7 6 ' 3 r z h u 2 q 5 h v h w $ o o r x w s x w v l q f o 9 r i i 9 v ! 9 s r u 1 r w h , q w k h u p d o f o x v w h u p r g h 7 6 ' & r q i l j r q o \ w k h f r q f h u q h g r x w s x w f o x v w h u z l o o e h v z l w f k h g r i i ( " 1 ( $ ' 5 application information L99DZ120 78/162 docid029145 rev 4 4.13 power outputs ou t1..15 and out_hs the component provides a total of 4 half brid ges outputs out1, out4-6 to drive motors and 10 stand alone high-side outputs out7..15 and out_hs to drive e.g. led?s, bulbs or to supply contacts. all high-side outputs beside out_hs and out15 are supplied by the pin vs and out_hs and out15 are supplied by the buffered supply v sreg . out_hs is intended to be used as contact supply. be side out15 and out_hs the high-side switches can be activated only in case of running charge pump. out15 and out_hs can be activated also in standby modes. all high-side and low-side outp uts switch off in case of: ? v s (v sreg ) overvoltage and undervoltage (d epending on configuration, see section 4.11.2: v sreg supply failure ) ? overcurrent (depending on configuration, auto recovery mode (see below) ? overtemperature (tsd1x/ cluster or single mode) ? fail safe event ? loss of gnd at sgnd pin in case of overcurrent or ov ertemperature (tsd1_clx (sr 6) ) condition, the drivers will switch off. the relevant status bit will be latched and can be read and optionally cleared by spi. the drivers remain off until the status is cleared. in case overvoltage/ undervoltage condition, the drivers will be switched off. the relevant status bit will be latched and can be read and optionally cleared by spi. if vsreg_lock_en (cr 3) respectively vs_lock_en (cr 3) are set, the drivers remain off until the status is cleared. if the vs_lock_en or vsreg_lock_en) bit is set to 0, the drivers will swit ch on automatically if the error condition disappears. undervoltage and overvoltage shutdown can be disabled by spi. in case of open-load condition, the relevant status register will be latched. the status can be read and optionally cleared by spi. the high and low-side outputs are not switched off in case of open-load condition. for out1, out4-8 and out_hs the auto recovery feature (outx_ocr (cr 7)) can be enabled; half-bridges and high-side drivers have different auto recovery frequencies (frecx_hs and frecx_hb). if these bits are set to 1 the driver will automatic ally restart from an overload condition. this overload recovery feat ure is intended for loads which have an initial current higher than the overcurrent limit of the output (e.g. inrush current of cold light bulbs). the spi bits outx_ocr_alert (sr4) indica te that the output reached auto-recovery condition. note: the maximum voltage and current applied to the high-side outputs is specified in the ?absolute maximum ratings?. appropriate external protection may be required in order to respect these limits under application conditions. in case of outputs switch off due to loss of ground at sgnd pin, the device has to be re-started through a power off on both v s and v sreg . each of the stand alone high-side driver outputs out7 ? out15 and out_hs can be driven with an internally genera ted pwm signal, an internal timer or with dir1 respectively dir2. see table 48 . docid029145 rev 4 79/162 L99DZ120 application information 161 4.14 auto-recovery alert and thermal expiration the thermal expiration feature provides a robust protection against possible microcontroller malfunction, switching off a given channel if co ntinuously driven in auto-recovery. if the temperature of the related cluster increases by more than 30 c after reaching the auto- recovery time t ar , the channel is switched off. the thermal expiration status bit outx_th_ex (sr 3) is set. during auto-recovery condition, outx_ocr_alert (sr 4) is set. the alert bit indicates that an overload condition (load in-rush, short-circuit, etc) is present. the thermal expiration feature is cont rolled by spi (outx_ocr_thx_en (cr 8). table 48. power output settings outx_3 outx_2 outx_1 outx_0 description 00 0 0off 00 0 1on 00 1 0 timer1 output is controlled by timer1; starting with on phase after timer restart 00 1 1 timer2 output is controlled by timer2; starting with on phase after timer restart 01 0 0pwm1 01 0 1pwm2 01 1 0pwm3 01 1 1pwm4 10 0 0pwm5 10 0 1pwm6 10 1 0pwm7 10 1 1pwm8 11 0 0pwm9 11 0 1pwm10 11 1 0dir1 11 1 1dir2 application information L99DZ120 80/162 docid029145 rev 4 figure 32. example of long auto-recovery on ou t7. temperature acquisition starts after t ar , thermal expiration occurs after a ? t = 30 docid029145 rev 4 81/162 L99DZ120 application information 161 figure 33. block diagram of physical realization of ar alert and thermal expiration 4.15 charge pump the charge pump uses two external capacitors, which are switched with f cp . the output of the charge pump has a current limitation. in standby mode and after a thermal shutdown has been triggered the charge pump is disabled . if the charge pump output voltage remains too low for longer than t cp , the power-mos outputs and the ec-control are switched off. the h-bridge mosfet gate drivers are switch ed to resistive low and cp_low (sr 2) is set. this bit has to be cleared to reacti vate the drivers. if the bit cp_low_config (configuration register 0x3f) is set to ?1?, cp_low (sr2) behaves as a ?live? bit and the outputs are re-activated automatically upon recovery of the charge pump output voltage. in case of reaching the overvoltage shutdown threshold v sov the charge pump is disabled and automatically restarted after v s recovered to normal operating voltage. figure 34. charge pump low filtering and start up implementation 4.16 inductive loads each of the half bridges is built by internally connected high-side and low-side power dmos transistors. due to the built-in reverse diodes of the output transistors, inductive loads can # b u u 4 v q q m z 0 w f s d v s s f o u d p n q $ v s s f o u 4 f o t f * u i 5 @ e b u b - b n q % s j w f s * $ ( b u f e s j w f s 0 / d p n n b o e % j b h o p t u j d ? $ ) 4 @ & o b c " 3 m j n j u s f b d i f e 0 4 $ % j h j u b m 4 u b u f . b d i j o f " % $ 5 f n q t f o t f " n q 1 p x f s . 0 4 * $ 3 * & ) 7 0 $ 9 & 3 o r z & 3 ) l o w h u 7 l p h 7 & 3 w \ s ? v 6 w d u w 8 s % o d q n l q j 7 l p h w v h w b & 3 w \ s l f d o ? v 3 r z h u 6 w d j h ' l v d e o h $ o o s r z h u v w d j h e h v l g h 3 & k d q q h o g l v d e o h g * d w h ' u l y h 2 x w s x w v g l v d e o h g & 3 o r z ' & / . * $ 3 * & ) 7 application information L99DZ120 82/162 docid029145 rev 4 be driven at the outputs out1 and out4-6 wit hout external freewheeling diodes. the high- side drivers out7 to out15 and out_hs are intended to drive resistive loads only. therefore only a limited energy (e < 1 mj) can be dissipated by the internal esd-diodes in freewheeling condition. for inductive loads (l > 100 h) an external freewheeling diode connected between gnd and the corresponding output is required. 4.17 open-load detection the open-load detection monitors the load current in each activa ted output stage. if the load current is below the open-load detection threshold for t > t ol_out the corresponding open- load bit outx_ol (sr 5) is set in the status register. 4.18 overcurrent detection an overcurrent condition is detected after a filter time (see figure 11 and figure 12 ) and is indicated by the status bit outx_oc (sr 3). in case of overcurrent, the corresponding driver switches off to reduce the power dissipati on and to protect the integrated circuit. if the outputs are not configured in recovery mode, the microcontroller has to clear the relevant status bits to reactivate the corresponding drivers. 4.19 current monitor the current monitor sources a current image of the power stage output current at the current monitor pin cm, which has a fixed ratio (i cmr ) of the instantaneous current of the selected high-side driver. the sign al at output cm is blanked for t cmb after switching on the driver until the correct settlement of the circui try. the bits cm_selx (cr 7) define which of the outputs is multiplexed to the current monitor output cm. the current monitor output allows a more precise analysis of the actual stat e of the load rather than the detection of an open-load or overload condition. for example, it can be used to detect the motor state (starting, free running, stalled). the current monitor output is enabled after the current- monitor blanking time, when the selected output is switched on. if this output is off, the current monitor output is in high impedance mode. the current monitor can be deactivated by cm_en (cr 7). 4.20 pwm mode of the power outputs description see section 7.3: status register overview . 4.21 cross-current protection the four half-bridges of the device are cross-cu rrent protected by an internal delay time. if one driver (ls or hs) is turned off, the activation of the other driver of the same half-bridge will be automatically delayed by the crosscurren t protection time. af ter the crosscurrent protection time is expired the slew-rate limited switch-off phase of the driver is changed to a fast turn-off phase and the opposite driver is turned-on with slew-rate limitation. due to this behavior, it is always guaranteed that the previously activated dr iver is completely turned off before the opposite driver starts to conduct. docid029145 rev 4 83/162 L99DZ120 application information 161 4.22 programmable soft-start functi on to drive loads with higher inrush current loads with start-up currents higher than the overcurrent limits (e.g. inrush current of lamps, start current of motors) can be driven by using the programmable soft-start function (i.e. overcurrent recovery mode). each driver has a corresponding overcurrent recovery bit outx_ocr (cr 7). if this bit is set, the device automatically switches the outputs on again after a programmable recovery time. the pw m modulated current will provide sufficient average current to power up the load (e.g. heat up the bulb) until the load reaches operating condition. the pwm frequency is defined by setting ocr_freq (cr7). the device itself cannot distinguish between a re al overload (e.g. short-circuit condition) and a load characterized by operation currents exceeding the short-circuit threshold. examples are non-linear loads like a light bulb used on the hs outputs or a motor used on the half bridge output with inrush and stall currents that shall be limited by the auto recovery feature. for the bulb, a real overload condition can only be qualified by time. for overload detection the microcontroller can switch on the light bu lbs by setting the overcu rrent recovery bit for the first e.g. 50 ms. after clearing the recovery bi t, the output will be switched off automatically if the overload condition remains. for the half bridges the high current can be pr esent during all motor activation and another sw strategy must be applied to identify a sc to gnd or supply. before running the motor e.g. with a first spi command all bridges ls are switched on (without auto recovery functionality / cleared overcurrent recovery bit) , all hs are switched off and a sc to battery can be diagnosed. with a next spi command, all hs are switched on (without auto recovery functionality/ cleared overcurrent recovery bit) and all ls are switched off. in this sequence, a short to gnd can be diagnosed. if in both se quences no overload condition is identified, the motor can be run by switching on the relevant hs and ls each configured in auto recovery mode (see figure 35 ). such sequence can be applied before any motor activation to identify sc just before o perating the motor (in case the delay due to the 2 additional spi commands is not limiting the application) or in case of power up of the system resp. applied on a certain time base. application information L99DZ120 84/162 docid029145 rev 4 figure 35. software strategy for half bridges before applying auto-recovery mode as soon as an output reaches auto-recovery condition, outx_ocr_alert (sr 4)) is set. the alert bit indicates that an overload condition (load in-rush, short-circuit, etc) is present. / ' = / ' = 2 ) ) 2 1 2 8 7 [ + 6 2 8 7 [ / 6 2 8 7 \ / 6 2 8 7 [ 2 8 7 \ 9 6 0 * 1 ' 2 8 7 \ + 6 9 6 * 1 ' 9 e d w 2 1 2 ) ) 6 k r u w w r 9 v " 1 < " " / ' = / ' = 2 ) ) 2 1 2 8 7 [ + 6 2 8 7 [ / 6 2 8 7 \ / 6 2 8 7 [ 2 8 7 \ 9 6 0 * 1 ' 2 8 7 \ + 6 9 6 * 1 ' 9 e d w 6 : 6 w h s 6 k r u w w r j u r x q g g h w h f w l r q 2 1 2 ) ) 6 k r u w w r * 1 ' " 1 < 6 : 6 w h s 6 k r u w w r e d w w h u \ g h w h f w l r q % ( * , 1 6 : 5 r x w l q h + 6 2 ) ) / 6 2 1 6 : 6 w h s + 6 2 1 / 6 2 ) ) . h h s $ 5 2 ) ) 6 z l w f k / 6 2 ) ) 6 : 6 w h s ( 1 ' 6 : 5 r x w l q h 6 h w $ 5 2 1 . h h s $ 5 2 ) ) 6 z l w f k + 6 2 ) ) " " $ 5 2 ) ) ( " 1 ( $ ' 5 docid029145 rev 4 85/162 L99DZ120 application information 161 figure 36. overcurrent recovery mode 4.23 h-bridge control the pwmh and dirh inputs control the drivers of the external h-bridge transistors. in single motor mode the motor direction can be chosen with the direction input (dirh), the duty cycle (a) and frequency with the pwmh input (single mode). with the spi bits sd (cr 10) and sds (cr 10) four different slow-decay modes (via drivers and via diode) can be selected using the high-side or the low-side tr ansistors. unconnected inputs are defined by internal pull-down current. w , / 2 $ ' 8 q o l p l w h g , q u x v k & x u u h q w / l p l w h g , q u x v k & x u u h q w l q s u r j u d p p d e o h u h f r y h u \ p r g h & x u u h q w / l p l w d w l r q * $ 3 * & ) 7 a. if tccp is programmed to 4 s and frequency to 50 khz, max duty cycle achievable is 92%. application information L99DZ120 86/162 docid029145 rev 4 during watchdog long-open window, the h-bridge drivers are forced off until the first valid watchdog trigger in window mode (setting trig = 0 during safe window). the control registers remain accessible during long open window. 4.24 h-bridge driver slew-rate control the rising and falling sl ope of the drivers for the external high-side power-mos can be slew rate controlled. if this mode is enabled the gate of the external high-side power-mos is driven by a current source instead of a low-impedance output driver switch as long as the drain-source voltage over this power-mos is below the switch threshold. the current is programmed using the bits slew_x<4:0> (cr 10), which represent a binary number. this number is multiplied by the minimum curren t step. this minimum current step is the maximum source-/sink-current (i ghxrmax / i ghxfmax ) divided by 31. programming slew_x <4:0> to 0 disables the slew rate cont rol and the output is driven by the low- impedance output driver switch. table 49. h-bridge control truth table control pins control bits failure bits output pins motor config comment nb dirh pwmh hen sd sds cp_low vs_ov vs_uv ds tsd1 gh1 gl1 gh2 gl2 1x x0xxxxxxxrlrlrlrl h-bridge disabled 2 x x 1 x x 1 0 0 0 0 rl rl rl rl single charge pump voltage too low 3x x1xx0xxx1rlrlrlrl thermal shutdown 4 x x1xx01000 l l l l overvoltage 5 x x1xx00010l (1) l (1) l (1) l (1) short-circuit (1) 6 0 1 1 x x 0 0 0 0 0 l h h l bridge h2/l1 on 7 x 010000000 l h l h slow-decay mode ls1 and ls2 on 8 0 010100000 l h l l slow-decay mode ls1 on 9 1 010100000 l l l h slow-decay mode ls2 on 10 1 1 1 x x 0 0 0 0 0 h l l h bridge h1/l2 on 11x 011000000h l h l slow-decay mode hs1 and hs2 on 120 011100000 l l h l slow-decay mode hs1 on 131 011100000h l l l slow-decay mode hs2 on 1. only the h-bridge leg (low-side and high-s ide), in which one mosfet is in short- circuit condition is switched off. both mosfets of the other h-bridge leg remain active and driven by dirh and pwmh. docid029145 rev 4 87/162 L99DZ120 application information 161 figure 37. h-bridge gshx slope 4.25 resistive low the resistive output mode protec ts the devices and the h-bridge in the standby mode and in some failure modes (thermal sh utdown tsd1 (sr 1), charge pump low cp_low (sr 2) and di pin stuck at ?1? spi_inv_cmd (sr 2)). wh en a gate driver changes into the resistive output mode due to a failure a sequence is started. in this sequence the concerning driver is switched into sink condition for 32 s to 64 s to ensure a fast swit ch-off of the h-bridge transistor. if slew rate control is enabled, the sink condition is slew-rate controlled. afterwards the driver is switch ed into the resistive output mode (resistive path to source). 4.26 short circuit detection / drain source monitoring the drain - source voltage of each activated external mosfet of the h-bridge is monitored by comparators to detect shorts to ground or battery. if the voltage-drop over the external mosfet exceeds the configurable threshold voltage v scd_hb (diag_x (cr 10) for longer t > t scd_hb the corresponding gate driver switches off the external mosfet and the corresponding drain source monitoring flag ds_mon_x (sr 2) is set. the dsmon_x bits have to be cleared through the spi to reactivate the gate drivers. this monitoring is only active while the corresponding gate driver is activated. if a drain-source monitor event is detected, the corresponding gate-driver remain s activated for at maximum the filter time. when the gate driver switc hes on, the drain-source comp arator requires the specified settling time until the drain-source monitoring is valid. during this time, this drain-source 9 * 6 + [ w & x u u h q w & r q w u r o o h g & x u u h q w & r q w u r o o h g / r z 5 h v l v w l y h 6 z l w f k & r q w u r o o h g 9 ' 6 + [ w * $ 3 * & ) 7 application information L99DZ120 88/162 docid029145 rev 4 monitor event may start the filter time. the threshold voltage v scd_hb can be programmed using the spi bits diag_x (cr 10). figure 38. h-bridge diagnosis 4.27 h-bridge monito ring in off-mode the drain source voltages of the h-bridge driver external transistors can be monitored, while the transistors are switched off. if either bit ol_h1l2 (cr 10) or ol_h2l1 (cr 10) is set to 1, while bit hen (cr 1) = 1, the h-drivers enter resistive low mode and the drain-source voltages can be monitored. since the pull-up re sistance is equal to the pull-down resistance on both sides of the bridge a voltage of 2/3 v s on the pull-up highside and 1/3 v s on the low- side is expected, if they driv e a low-resistive inductive load (e.g. motor). if the drain source voltage on each of these power-mos is less than 1/6 v s , the drain-source monitor bit of the associated driver is set. the open-load filter time is t ol_hb . 0 9 v * + 9 6 6 + * / 9 6 * + 6 + * / n n * d w h ' u l y h u + 6 * d w h ' u l y h u / 6 ' 6 0 r q l w r u l q j + 6 ' 6 0 r q l w r u l q j / 6 2 / 0 r q l w r u l q j 9 7 k u h v 9 7 k u h v n n * d w h ' u l y h u + 6 * d w h ' u l y h u / 6 ' 6 0 r q l w r u l q j + 6 ' 6 0 r q l w r u l q j / 6 2 / 0 r q l w r u l q j 9 7 k u h v 9 7 k u h v ( " 1 ( $ ' 5 docid029145 rev 4 89/162 L99DZ120 application information 161 figure 39. h-bridge open-load-detection (no open-load detected) figure 40. h-bridge open-load-detection (open-load detected) 0 p n n n 9 v 9 v 9 7 9 v ' 6 0 ' 6 0 9 7 9 v 9 v * $ 3 * & ) 7 0 p n n n 2 s h q 9 v 9 7 9 v ' 6 0 ' 6 0 9 7 9 v 9 v * $ 3 * & ) 7 application information L99DZ120 90/162 docid029145 rev 4 figure 41. h-bridge open-load-detection (short to ground detected) figure 42. h-bridge open-load detection (short to v s detected) table 50. h-bridge monitoring in off-mode control bits failure bits comments nb ol h1l2 ol h2l1 h olth high dsmon ls1 dsmon ls2 10 0 0 0 0 drain-source monitor disabled 2 1 0 x 0 0 no open-load detected 3 1 0 0 0 1 open-load sh2 4 1 0 0 1 1 short to gnd 5 1 0 1 1 1 short to vs 6 0 1 x 0 0 no open-load detected 7 0 1 0 1 0 open-load sh1 0 p n n n * 1 ' 9 7 9 v ' 6 0 ' 6 0 9 7 9 v * 1 ' 6 k r u w 9 v * $ 3 * & ) 7 0 p n n n ' 6 0 ' 6 0 9 7 9 v 6 k r u w 9 v 9 v 9 v 9 7 9 v * $ 3 * & ) 7 docid029145 rev 4 91/162 L99DZ120 application information 161 4.28 programmable cro ss current protection the external powermosfets transistors in h- bridge (two half-bridges) configuration are switched on with an additional delay time t ccp to prevent cross current in the halfbridge. the cross current protection time t ccp can be programmed with the spi bits copt_x<3:0> (cr 10). the timer is started when the gate driver is switched on in the device. the pwmh module has 2 timers to configure locking time for high-side and freewheeling low-side. the programmable time t ccp-tim1 / t ccp-tim2 is the same. sequence for switching in pwm mode is the following: ? hs switch off after locking t ccp-tim1 ? ls switch on after 2nd locking t ccp-tim1 ? hs switch on after locking t ccp-tim2 which starts with rising edge on pwm input figure 43. pwmh cross current protection time implementation 4.29 power window h-bridge safety switch off block the two ls switches ls1_fso and ls2_fso are intended to be used to switch off the gates of the external high-side mosfets in the power window h-bridge if a fatal error happens. this block must work also in case the mosfet driver and the according control blocks on the chip are destroyed. therefore it is necessary to have a complete separated safety block on the device, which has it?s ow n supply and gnd connection, separated from the other supplies and gnds. in the block is implemented an own voltage regulator and oscillator. 8 0 1 0 1 1 short to gnd 9 0 1 1 1 1 short to vs table 50. h-bridge monitoring in off-mode (continued) control bits failure bits comments nb ol h1l2 ol h2l1 h olth high dsmon ls1 dsmon ls2 w & & 3 7 , 0 w & & 3 7 , 0 w s s ! [ w f f s 3 : 0 , q s x w + 6 / r j l f / 6 / r j l f w & & 3 7 , 0 w & & 3 7 , 0 w s s [ w f f s 3 d v v l y h ) u h h : k h h o l q j $ f w l y h ) u h h : k h h o l q j ( " 1 ( $ ' 5 w s s w f f s w & & 3 7 , 0 w & & 3 7 , 0 w & & 3 7 , 0 3 d v v l y h ) u h h : k h h o l q j w & & 3 7 , 0 w & & 3 7 , 0 application information L99DZ120 92/162 docid029145 rev 4 the safety block is surrounded by a gnd isolat ion ring realized by deep trench isolation. the ls driver must work down to a lower volt age than the other circuits. the block has its own internal supply and an ow n oscillator for monitoring the failure signals (wwd, v1 fail, spi fail & tj) which are manchester encoded and decoupled by high ohmic resistances. in case of fail-safe event, both ls switches ls1_fso and ls2_fso are switched on. in case of entering v1_standby mode or vbat_standby mode both fail safe low-side switches are switched on to mi nimize the current drawn by the fail safe block (e.g. oscillator is switched off and manchester encoding is deactivated). short circuit protection to v s is active in both standby modes limiting the current to i olimit for a filter of t scf . after this filter time the fail-sa fe switches are switched off and lsxfso_oc (sr 3) is set. to reactivate the low-side functionality this bit ha s to be set back by a read and clear command. in case of v s loss the fail safe switches are biased by their own output voltage to turn on the low-side switches down to vout_max. to allow verification of the fail-safe path, the low-side switches ls1_fso and ls2_fso can be turned on by spi (configuration register 0x3f bit 4: fs_forced) figure 44. lsx_fso: low-side driver ?passi vely? turned on, taking supply from output pin (if main supply fails), can guarantee v lsx_fso < v out_max ) l o w h u v 6 w d w h 0 d f k l q h ( q d e o h / 6 b ) 6 2 b 2 & / 6 b ) 6 2 b 2 & & o r f n / 6 b ) 6 2 b 2 & / 6 b ) 6 2 b 2 & : d w f k g r j ) d l o 9 ) d l o x u h v 2 y h u 7 h p s 7 6 ' & / ( $ 5 / 6 [ b ) 6 2 b 2 & 7 [ 0 d q f k h v w h u ( q f r g h g 6 l j q d o v 1 r u p d o o \ 6 z l w f k l q j 5 [ 6 l j q d o 9 5 ( * * 1 ' 6 x s s o \ / r z 6 l g h ' u l y h u / r z 6 l g h ' u l y h u ) d l o 6 d i h % o r f n & r p s o h w h , & / 6 b ) 6 2 / 6 b ) 6 2 7 ; 6 l j q d o v ( " 1 ( $ ' 5 docid029145 rev 4 93/162 L99DZ120 application information 161 figure 45. safety concept 4.30 temperature warn ing and shutdown if any of the cluster (see section 4.31: thermal clusters ) junction temperatures rises above the temperature warning threshold tw, the temperature warning flag tw (sr 2) is set after the temperature warning filter time t jtft and can be read via spi. if the junction temperature increases above the temperature shutdown th reshold (tsd1), the thermal shutdown bit tsd1 (sr 1) is set and the power transistors of all output stages are switched off to protect the device after the thermal shutdown filter ti me. the gates of the h-bridge is discharged by the ?resistive low? mode. after these bits have been cleared, the output stages are reactivated. if the temperatur e is still above the thermal wa rning threshold, the thermal warning bit is set after t jtft . once this bit is set and the temperature is above the temperature shutdown threshold, temperature shutdown is detected after t jtft and the outputs are switched off. therefore the minimum time afte r which the outputs are switched off after the bits have been cleared in case the temperature is still above the thermal shutdown threshold is twice the thermal warning/ th ermal shutdown filter time t jtft . 4.31 thermal clusters in order to provide an advanced on-chip te mperature control, the power outputs are grouped in six clusters with dedicated thermal sensors. the sensors are suitably located on the device (see figure 46: thermal clusters identification ). in case the temperature of an output cluster reaches the thermal shutdown thre shold, the outputs assi gned to this cluster are shut down (all other outputs remain active). each output cluster has a dedicated temperature warning and shutdown flag (sr 6) and the cluster temperature can be read out by spi. hence, the thermal cluster concept allows to identify a group of outputs in which one or more channels are in overload condition. if thermal shutdown has occurred within an output cluster, or if temperature is rising within a cluster, it may be desired to identify which of the output (s) is (are) determining the temperature increase. an additional evaluation , based on current monitoring and cluster temperature read-out, supports identification of the outputs mainly contributing to the temperature increase. the cluster temperatures are available in sr 7, sr 8 and sr 9 and can be calculated from the binary coded register value using the following formula: decimal code = (350 ? temp) / 0.488 7 [ 6 l j q d o 0 d q f k h v w h u ( q f r g h g 6 l j q d o v & o r f n 5 [ 6 l j q d o 1 r u p d o 2 s h u d w l r q ) d l o 6 d i h & o r f n ) d l o x u h ' d w d ) d l o x u h ( " 1 ( $ ' 5 application information L99DZ120 94/162 docid029145 rev 4 example: t = -40 c => decimal code is 799 (0x31f) t = 25 c => decimal code is 666 (0x29a) thermal clusters can be configured using bit tsd_config (config reg): ? standard mode (default): as soon as any cl uster reaches thermal threshold the device is switched off. v1 regulator remains on and is switched off reaching tsd2. ? cluster mode: only the cluster which reache d shutdown temperature is switched off. if cluster th_cl6 (global) or cluster th_cl5 (voltage regulators) reachtsd1, the whole device is off (beside v1). note: clusters related to power outputs (clusters 1 to 4, see figure 46: thermal clusters identification ) will be managed digitally only, by m ean of the adc conversion of related thermal sensors, while clusters 5 and 6 will be managed in an analog way (comparators) since adc can be off, e.g. in v1_standby mo de. temperature reading provided by adc may differ from real junction temperature of a spec ific output due to spatial placement of thermal sensor. such an effect is more visible during fast thermal increases of junction temperature. figure 46. thermal clusters identification * $ 3 * & ) 7 6 + * + * / 6 + * + * / & 3 & 3 3 & 3 3 & 3 0 & 3 0 1 & 1 & 2 8 7 1 & 2 8 7 2 8 7 2 8 7 2 8 7 9 b 9 6 2 8 7 2 8 7 2 8 7 1 & 2 8 7 b + 6 / , 1 7 [ ' b / 5 [ ' b / 1 , 1 7 & 6 1 ' 2 ' , & / . ' , 5 + 1 & 3 : 0 + / , 1 ) / $ 6 + & 0 ' , 5 1 & 1 & 6 * 1 ' 9 b 1 & 2 8 7 9 6 9 6 3 * 1 ' 2 8 7 1 & 2 8 7 2 8 7 2 8 7 2 8 7 ' h e x j ' , 5 / 6 b ) 6 2 / 6 b ) 6 2 1 , 1 7 9 6 5 ( * : 8 1 & 1 5 ( 6 ( 7 7 k h u p d o & o x v w h u 7 k h u p d o & o x v w h u 7 k h u p d o & o x v w h u 7 k h u p d o & o x v w h u 7 k h u p d o & o x v w h u 7 k h u p d o & o x v w h u 2 8 7 docid029145 rev 4 95/162 L99DZ120 application information 161 4.32 v s compensation (duty cy cle adjustment) module all stand-alone hs outputs can be programmed to calculat e some internal duty cycle adjustment to adapt the duty cycle to a changing supply voltage at v s . this feature is aimed to avoid led brightness flickering in case of alternating supply voltage. the correction of the duty cycle is based on the following formula: equation 1: duty cycle correction v th = duty cycle reference voltage: defined as 10 v v bat = reference voltage: defined as voltage at pin vs v led = voltage drop on the external led dc nom = nominal duty cycle programmed by spi< pwmx dcx> to be compatible to different led load characteristics the value for v led can be programmed for each output by a dedicated control register out7_vled ? out_hs_vled (cr 18 to cr 22). auto compensation features can be activated for all hs outputs each by setting outx_autocomp_en (cr 18 to cr 22). the programmed led voltage (outx_v_led (cr18 to cr22)) must be lower than v th (10 v). figure 47. block diagram v s compensation (duty cycle adjustment) module table 51. thermal cluster definition th_cl1 th_cl2 th_cl3 th_cl4 th_cl5 th_cl6 5 w driver + out15 door lock + out_hs out1 + out6 10w driver high ohmic channels vreg 1 vreg 2 global tw & tsd1 both digitally managed tw & tsd1 both digitally managed tw & tsd1 both digitally managed tw & tsd1 both digitally managed tw digitally managed tsd1 & tsd2 both analog managed tw digitally managed tsd1 analog managed dutycycle v th v led ? v bat v led ? --------------------------------- dc nom ? = 5 h j l v w h u ' x w \ & \ f o h + 6 % l w d f f x u d f \ 1 r p l q d o 9 r o w d j h # 9 6 3 , 6 3 , + 6 $ v v l j q p h q w d q g / r d g $ g d s w l r q 9 6 & r p s h q v d w l r q & d o f x o d w l r q 5 h j l v w h u d g m x v w h g ' x w \ & \ f o h + 6 % l w d f f x u d f \ + 6 + 6 + 6 + 6 $ ' & 9 6 , q w h u q d o $ g m x v w p h q w 2 1 2 ) ) % , 7 9 / ( ' y r o w d j h o h y h o 9 9 * $ 3 * & ) 7 application information L99DZ120 96/162 docid029145 rev 4 4.33 analog digital converter voltage signals v s , v sreg , v wu and th_cl1..6 are read out sequentially. the voltage signals are multiplexed to an adc. the adc is realized as a 10 bit sar, that is sampled with the main clock f clk2 / f adc . each channel will be converted with a conversion time tcon, th erefore an upda te of the adc value is available every t con * 9. in case of wu is directly connected to cla mp 30, the input must be protected by a series resistance of typical 1k ? to sustain reverse battery condition. figure 48. sequential adc read out for v sreg , v s , wu and thcl1 ..thcl6 9 l q & k d q q h o 0 x [ : 8 9 6 5 ( * 9 6 7 + & / % l w 6 $ 5 6 3 , 5 h j l v w h u s ) n n 9 5 ( ) 9 9 7 + & / 7 + & / 7 + & / 7 + & / 7 + & / ( " 1 ( $ ' 5 docid029145 rev 4 97/162 L99DZ120 serial periphe ral interface (spi) 161 5 serial peripheral interface (spi) a 32-bit spi is used for bi-directional communication with the microcontroller. the spi is driven by a microcontroller with it s spi peripheral runnin g in the following mode: cpol = 0 and cpha = 0. for this mode input data is sampled by the low to high transition of the clock clk, and output data is changed from the high to low tr ansition of clk. this device is not limited to microcontroller with a built-in spi. only three cmos-compatible output pins and one input pin will be needed to communicate with the device. a fault cond ition can be detected by setting csn to low. if csn = 0, the do-pin will refl ect the global error flag (fault condition) of the device. ? chip select not (csn) the input pin is used to select the serial in terface of this device. when csn is high, the output pin (do) is in high impedance state. a low signal activates the output driver and a serial communication can be started. the state during csn = 0 is called a communication frame. if csn = low for t > t csnfail the do output will be switched to high impedance in order to not block the signal line for other spi nodes. ? serial data in (di) the input pin is used to transfer data serial into the device. the data applied to the di will be sampled at the rising edg e of the clk signal and shift ed into an internal 32-bit shift register. at the rising edge of the csn signal the content of t he shift register will be transferred to data in put register. the writing to the selected data input register is only enabled if exactly 32-bit are transmitte d within one communication frame (i.e. csn low). if more or less clock pulses are co unted within one frame the complete frame will be ignored. this safety function is impl emented to avoid an activation of the output stages by a wrong communication frame. note: due to this safety functionality a daisy c haining of spi is not possible. instead, a parallel operation of the spi bus by controlling t he csn signal of the connected ic's is recommended. ? serial data out (do) the data output driver is activated by a l ogical low level at the csn input and will go from high impedance to a low or high level depending on the global error flag (fault condition). the first rising edge of the clk input after a high to low transition of the csn pin will transfer the content of the selected status register into the data out shift register. each subsequent falling edge of the clk will shift the next bit out. ? serial clock (clk) the clk input is used to synchronize the inpu t and output serial bit streams. the data input (di) is sampled at the rising edge of the cl k and the data output (do) will change with the falling edge of the clk signal. the spi can be driven with a clk frequency up to 4 mhz. 5.1 st spi 4.0 the st-spi is a standard used in st automotive assp devices. serial peripheral interface (spi) L99DZ120 98/162 docid029145 rev 4 this chapter describes the spi protocol standardization. it defines a common structure of the communication frames and defines spec ific addresses for product and status information. the st-spi allows usage of generic software to operate the devices while maintaining the required flexibility to adapt it to the individual functionality of a particular produc t. in addition, failsafe mechanisms are implemented to protect the communication from external influences and wrong or unwanted usage. the devices serial peripheral interface are compliant to the st spi standard rev. 4.0. 5.1.1 physical layer figure 49. spi pin description 5.2 signal description ? chip select not (csn) the communication interface is de -selected, when this input signal is logically high. a falling edge on csn enables an d starts the communication while a rising edge finishes the communication and the sent command is executed when a valid frame was sent. during communication start and stop the serial clock (sck) has to be logically low. the serial data out (sdo) is in high impedance when csn is high or a communication timeout was detected. ? serial clock (sck) this sck provides the clock of the spi. data present at serial data input (sdi) is latched on the rising edge of serial clock (s ck) into the internal shift registers while on the falling edge data from the in ternal shift registers are shif ted out to serial data out (sdo). ? serial data input (sdi) this input is used to transfer data serially into the device. data is latched on the rising edge of serial clock (sck). ? serial data output (sdo) this output signal is used to transfer data se rially out of the device. data is shifted out on the falling edge of serial clock (sck). ? & 6 3 , 0 d v w h u / ' = & 6 1 6 & . 6 ' , 6 ' 2 ( " 1 ( $ ' 5 docid029145 rev 4 99/162 L99DZ120 serial periphe ral interface (spi) 161 figure 50. sdo pin 5.2.1 clock and data characteristics the st-spi can be driven by a microcontroller with its spi peripheral running in the following mode: cpol = 0 cpha = 0 figure 51. spi signal description the communication frame star ts with the falling edge of th e csn (communication start). sck has to be low. the sdi data is then latched at all following risi ng sck edges into the internal shift registers. after communication start the sdo will leave 3-state mode and pres ent the msb of the data shifted out to sdo. at all following falling sck edges da ta is shifted out through the internal shift registers to sdo. ' l j l w d o o r j l f * 1 ' 9 ' d w d 2 x w ' d w d , q ( q d e o h * 1 ' ( 6 ' s u r w ( " 1 ( $ ' 5 & 6 1 6 & . 6 ' , 6 ' 2 0 6 % 0 6 % / 6 % / 6 % ( " 1 ( $ ' 5 serial peripheral interface (spi) L99DZ120 100/162 docid029145 rev 4 the communication frame is finished with the ri sing edge of csn. if a valid communication took place (e.g. correct number of sck cycles, access to a valid address), the requested operation according to the operating code will be perform ed (write or clear operation). 5.2.2 communication protocol sdi frame the devices data-in frame consist of 32-bit (opcode (2 bits) + address (6 bits) + data byte 3 + data byte 2 + data byte 1). the first two transmitted bits (msb, msb-1) contain the operation code which re presents the instruct ion which will be performed. the following 6 bits (msb-2 to msb-7) represen t the address on which the op eration will be performed. the subsequent bytes contain the payload. figure 52. sdi frame operating code the operating code is used to distinguish between different access modes to the registers of the slave device. a write operation will lead to a mo dification of the a ddressed data by the payload if a write access is allowed (e.g. control register, valid data). beside this a shift out of the content (data present at communication start) of the registers is performed. a read operation shifts out the data present in the addressed register at communication start. the payload data will be ignored and internal data will no t be modified. in addition a burst read can be performed. table 52. operation codes oc1 oc0 description 0 0 write operation 0 1 read operation 1 0 read & clear operation 1 1 read device information 2 & 2 & $ $ $ $ $ $ 2 3 & 2 ' ( $ ' ' 5 ( 6 6 ' $ 7 $ % \ w h ' $ 7 $ % \ w h 0 6 % / 6 % w l p h w l p h w l p h ' $ 7 $ % \ w h w l p h ( " 1 ( $ ' 5 docid029145 rev 4 101/162 L99DZ120 serial periphe ral interface (spi) 161 a read & clear operation will lead to a clear of addressed status bits. th e bits to be cleared are defined first by address, second by payload bits set to ?1?. beside th is a shift out of the content (data present at communication start) of the registers is performed. note: status registers which change status during communication could be cleared by the actual read & clear operation and are neither reported in actual communication nor in the following communications. to avoid a loss of any reported status it is recommended just clear status registers which are already report ed in the previous communication (selective bitwise clear). advanced operation codes to provide the separate write of all control registers and the bitwise clear of all status registers, two advanced operat ion codes can be used to set all control registers to the default value and to clear all status registers. a ?set all control registers to default? command is performed when an opcode ?11? at address b?111111 is performed. note: please consider that potenti al device specific write protected registers cannot be cleared with this command in therefore a device power-on-reset is needed. a ?clear all status registers? command is performed when an opcode ?10? at address b?111111 is performed. data-in payload the payload (data byte 1 to data byte 3) is the data transferred to the devices with every spi communication. the payload always follo ws the opcode and the address bits. for write access the payload represents the new data written to the addressed register. for read & clear operations the payl oad defines which bits of the adressed status register will be cleared. in case of a ?1? at the corresponding bit position the bit will be cleared. for a read operation the payload is not used. for functional safety reasons it is recommended to set unused payload to ?0?. sdo frame the data-out frame consists of 32-bit (gsb + data byte 1 to 3). the first eight transmitted bits contain device re lated status information and are latched into the shift register at the time of the communication start. these 8-bit are transmitted at every spi transaction. the subsequent bytes contain the payload data and are latched into the shift register with the eighth positive sck edge. this could lead to an inconsistency in data between the gsb and payload due to different shift register load times. anyhow, no unwanted status register clear should appear, as status information should just be cleared with a dedicated bit clear after. serial peripheral interface (spi) L99DZ120 102/162 docid029145 rev 4 figure 53. sdo frame global status byte (gsb) the bits (bit0 to bit4) represent a logical or combination of bits located in the status registers. therefore no direct read & clear c an be performed on these bits inside the gsb. global status bit not (gsbn) the gsbn is a logical nor combination of bit 24 to bit 30. this bit can also be used as global status flag without starting a complete communication frame as it is present directly after pulling csn low. reset bit (rstb) the rstb indicates a device reset. in case this bit is set, specific in ternal control registers are set to default and kept in that state until th e bit is cleared. the rstb bit is cleared after a read & clear of all the specific bits in the status registers which caused the reset event. spi error (spie) the spie is a logical or combination of errors related to a wrong spi communication. physical layer error (ple) the ple is a logical or combination of errors related to the lin transceiver. functional error (fe) the fe is a logical or combination of errors coming from functional blocks (e.g. high-side overcurrent). device error (de) the de is a logical or combination of errors related to device specific blocks (e.g. vs overvoltage, overtemperature table 53. global status byte bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 gsbn rstb spie ple fe de gw fs ) ( ' ( ) 6 * o r e d o 6 w d w x v % \ w h * 6 % ' $ 7 $ % \ w h ' $ 7 $ % \ w h 5 6 7 % : * 1 % 6 * 6 3 , ( 3 / ( 0 6 % / 6 % w l p h w l p h w l p h ' $ 7 $ % \ w h w l p h ( " 1 ( $ ' 5 docid029145 rev 4 103/162 L99DZ120 serial periphe ral interface (spi) 161 global warning (gw) the gw is a logical or combination of warning flags (e.g . thermal warning). fail safe (fs) the fs bit indicates that the device was forced into a safe state due to mistreatment or fundamental internal errors (e.g. watchdog failure, voltage regulator failure). data-out payload the payload (data bytes 1 to 3) is the data tr ansferred from the slave device with every spi communication to the master device. the payload always follows the opcode and the address bits of the actual shifted in data (in-frame-response). 5.2.3 address definition table 54. device application access operating code oc1 oc0 00 01 10 table 55. device information read access operating code oc1 oc0 11 table 56. ram address range ram address description access 3fh configuration register r/w 3ch status register 12 r/c ?? 32h status register 2 r/c 31h status register 1 r/c ?? 22h control register 34 r/w 1dh control register 29 r/w ?? 02h control register 2 r/w serial peripheral interface (spi) L99DZ120 104/162 docid029145 rev 4 information registers the device information registers can be read by using opcode ?11?. after shifting out the gsb the 8-bit wide payload will be transmitted. by reading device information registers a communication width which is minimum 16-bit plus a multiple by 8 can be used. after shifting out the gsb followed by the 8-bit wide payload a series of ?0? is shifted out at the sdo. 01h control register 1 r/w 00h reserved table 57. rom address range rom address description access 3fh docid029145 rev 4 105/162 L99DZ120 serial periphe ral interface (spi) 161 device identification registers these registers represent a unique signat ure to identify the devi ce and silicon version. serial peripheral interface (spi) L99DZ120 106/162 docid029145 rev 4 docid029145 rev 4 107/162 L99DZ120 serial periphe ral interface (spi) 161 watchdog definition in case a watchdog is implemented the default settings can be read out via the device information registers . serial peripheral interface (spi) L99DZ120 108/162 docid029145 rev 4 figure 54. window watchdog operation the watchdog trigger bit location is defined by the docid029145 rev 4 109/162 L99DZ120 serial periphe ral interface (spi) 161 device application registers (ram) the device application registers are all registers accessible using opcode ?00?, ?01? and ?10?. the functions of these registers are defined in the device specification. 5.2.4 protocol failure detection to realize a protocol which covers certain failsafe requirements a basic set of failure detection mechanisms is implemented. clock monitor during communication (csn low to high phase) a clock monitor counts the valid sck clock edges. if the sck edges do not correlate with the spi data length an spie is reported with the next command and the actual communication is rejected. by accessing the device information registers (opcode = ?11?) the clock monitor is set to a minimum of 16 sck edges plus a multiple by 8 (e.g. 16, 25, 32, ?). providing no sck edge during a csn low to high phase is not recognized as an spie. for a spi burst read also the spi data length plus multiple numbers of payloads sck edges are assumed as a valid communication. sck polarity (cpol) check to detect the wrong polarity access via sck th e internal clock monitor is used. providing first a negative edge on sck during communicatio n (csn low to high phase) or a positive edge at last will lead to an sp i error reported in the next communication and the actual data is rejected. sck phase (cpha) check to verify, that the sck phase of the spi master is set correctly a special device information register is implemented. by reading this register the data must be 55h. in case aah is read the cpha setting of the spi master is wrong and a proper communication cannot be guaranteed. csn timeout by pulling csn low the sdo is set active and leaves its 3-state co ndition. to ensure communication between other spi devices within the same bus even in case of csn stuck at low a csn timeout is implemen ted. by pulling csn low an inte rnal timer is started. after timer end is reached the actual communication is rejected and the sdo is set to 3-state condition. sdi stuck at gnd as a communication with data all-?0? and opcode ?00? on address b?000000 cannot be distinguished between a valid command and a sd i stuck at gnd this communication is not allowed. neverthe less, in case a stuck at gnd is detected the commu nication will be rejected and the spie will be se t with the next communication. sdi stuck at high as a communication with data all-?1? and opcode ?11? on address b?111111 cannot be distinguished between a valid command and a sd i stuck at high this communication is not serial peripheral interface (spi) L99DZ120 110/162 docid029145 rev 4 allowed. in case a stuck at high is detect ed the communication will be rejected and the spie will be set with th e next communication. sdo stuck @ the sdo stuck at gnd and stu ck at high have to be detect ed by the spi master. as the definition of the gsb guarantees at least one to ggle, a gsb with all-?0? or all ??1? reports a stuck at error. docid029145 rev 4 111/162 L99DZ120 application 161 6 application figure 55. typical application diagram * $ 3 * & ) 7 6 3 , , q w h u i d f h : l q g r z : d w f k g r j & 6 1 & / . ' 2 ' , 9 b & 3 2 8 7 & 3 0 & 3 3 & 3 0 & 3 3 9 6 [ * / ' h e x j 3 * 1 ' & 0 * + 6 + 9 5 ( * 9 5 ( * + 6 + 6 + 6 + 6 + 6 + 6 + 6 3 & k d q q h o 9 b 1 5 ( 6 ( 7 / , 1 5 [ ' b / 1 , 1 7 7 [ ' b / / , 1 : 8 ' , 5 ' , 5 + 3 : 0 + + 6 2 8 7 2 8 7 2 8 7 2 8 7 2 8 7 2 8 7 2 8 7 2 8 7 9 6 5 ( * 2 8 7 b + 6 2 8 7 * 1 ' 6 * 1 ' 2 8 7 % x i i h u h g 9 6 ' , 5 2 8 7 1 , 1 7 ) d l o 6 d i h / 6 b ) 6 2 [ % l w $ ' & 6 $ 5 9 6 5 ( * 9 6 [ 7 m & o + 6 3 & k d q q h o & k d u j h 3 x p s [ 7 m & o 0 0 / r f n 6 d i h / r f n + 6 2 8 7 ? & r x w s x w ? & r x w s x w : [ : r u / ( ' & r q w d f w 6 x s s o \ a q ) a q ) a q ) ? & r x w s x w ? & r x w s x w ? & r x w s x w ? & l q s x w ? & l q s x w 0 / 6 b ) 6 2 q ) q ) 9 % $ 7 n ? & r x w s x w ? & l q s x w 7 h v w s r l q w ' h e x j 0 r g h ? & l q s x w / , 1 ? & l q s x w ( 6 ' 3 u r w h f w l r q i r u ( & 8 s l q v q ) q ) i r u 2 8 7 2 8 7 b + 6 9 % $ 7 n 9 3 u r w h f w h g ) d l o 6 d i h 6 z l w f k 2 i i ( [ w / r d g v 9 3 u r w h f w h g ? & 6 x s s o \ & d s d f l w d q f h w r e h g l p h q v l r q h g d f f r u g l q j w r o r d g f x u u h q w u x o h r i w k x p e ? ) h d f k $ & d s d f l w d q f h w r e h g l p h q v l r q h g h j d f f r u g l q j w r y r o w d j h g u r s r x w u h t x l u h p h q w v 2 ( 0 u h t x l u h p h q w v d q g h [ w h u q d o f r p s r q h q w v i r u / , 1 w r e h i x o o i l o o h g ) r u ( 0 & r s w l p l ] d w l r q s x u s r v h v f d s d f l w d q f h v f r x o g e h u h g l p h q v l r q h g ? ) u h f r p p h q g h g ? & r x w s x w ? & r x w s x w / , 1 ) / $ 6 + : r u / ( ' ' u l y h u , q w h u i d f h / r j l f ' l d j q r v w l f spi registers L99DZ120 112/162 docid029145 rev 4 7 spi registers 7.1 global status byte gsb table 65. global status byte (gsb) 31 30 29 28 27 26 25 24 bit name gsbn rstb spie ple fe de gw fs reset 1 0 0 0 0000 access r table 66. gsb signals description bit name description 31 gsbn global status bit inverted the gsbn is a logically nor combination of gsb bits 24 to bit 30 (1) . this bit can also be used as global status flag without starting a complete communication frame as it is present at sdo directly after pulling csn low. 0: error detected (1 or several gsb bits from 24 to 30 are set) 1: no error detected (default after power-on) specific failures may be masked in the configuration register 0x3f. a masked failure will still be reported in the gsb by the related failure flag, however it is not reflected in the gsbn (bit 31). 30 rstb reset the rstb indicates a device reset and it is set in case of the following events: ? vpor (sr1 - 0x31) ? wdfail (sr1 - 0x31) ? v1uv (sr1 - 0x31) ? forced_sleep_tsd2/v 1sc (sr1 - 0x31) 0: no reset signal has been generated (default) 1: reset signal has been generated rstb is cleared by a read & clear command to all bits in status register 1 causing the reset event. 29 spie (2) spi error bit the spie indicates errors related to a wrong spi communication. ? spi_inv_cmd (sr2 - 0x32) ? spi_sck_cnt (sr2 - 0x32) the bit is also set in case of an spi csn time-out detection 0: no error (default) 1: error detected spie is cleared by a valid spi command. docid029145 rev 4 113/162 L99DZ120 spi registers 161 28 ple (2) physical layer error the ple is a logical or combination of errors related to the lin transceiver. ? lin_perm_dom (sr2 - 0x32) ? lin_txd_dom (sr2 - 0x32) ? lin_perm_rec (sr2 - 0x32) 0: no error (default) 1: error detected ple is cleared by a read & clear command to all related bits in status registers 2 and 12 . 27 fe functional error bit the fe is a logical or combination of errors coming from functional blocks. ? v2sc (sr2 - 0x32) ? dsmon_hsx (sr2 - 0x32) ? dsmon_lsx (sr2 - 0x32) ? outxhs_oc th ex (sr3 - 0x33) ? outxls_oc th ex (sr3 - 0x33) ? ouths_oc th ex (sr3 - 0x33) ? outx_oc (sr3 - 0x33) ? lsxfs_oc (sr3 - 0x33) ? outxhs_ol (sr5 - 0x35) (3) ? outxls_ol (sr5 - 0x35) ? outx_ol (sr5 - 0x35) ? ouths_ol (sr5 - 0x35) 0: no error (default) 1: error detected fe is cleared by a read & clear command to all related bits in status registers 2, 3, 4, 5 26 de device error bit de is a logical or combination of global errors related to the device. ? vs_ov (sr2 - 0x32) ? vs_uv (sr2 - 0x32) ? vsreg_ov (sr2 - 0x32) ? vsreg_uv (sr2 - 0x32) ? cp_low (sr2 - 0x32) ? tsd1_clx (sr6 - 0x36) 0: no error (default) 1: error detected de is cleared by a read & clear command to all related bits in status registers 2 and 6 table 66. gsb signals description (continued) bit name description spi registers L99DZ120 114/162 docid029145 rev 4 25 gw (2) global warning bit gw is a logical or combination of warning flags. warning bits do not lead to any device state change or switch off of functions. ? vsreg_ew (sr2 - 0x32) ? v1_fail (sr2 - 0x32) ? v2_fail (sr2 - 0x32) ?tw (3) (sr2 - 0x32) ? spi_inv_cmd (sr2 - 0x32) ? spi_sck_cnt (sr2 - 0x32) 0: no error (default) 1: error detected gw is cleared by a read & clear command to all related bits in status register 2. 24 fs fail safe the fs bit indicates the device was forced into a safe state due to the following failure conditions: ? wdfail (sr1 - 0x31) ? v1uv (sr1 - 0x31) ? tsd2 (sr1 - 0x31) ? forced_sleep_tsd/v1sc (sr1 - 0x31) all control registers are set to default control registers are blocked for write access except the following bits: ? trig (cr1 - 0x01) ? v2_0 (cr1 - 0x01) ? v2_1 (cr1 - 0x01) ? timer settings (bits 8?23) (cr2 - 0x02) ? ouths_x (bits 0?3) (cr5 - 0x05) ? out15_x (bits 0?3) (cr6 - 0x06) ? cr12 (0x0c) to cr17 (0x11); pwm frequency and duty cycles 0: fail safe inactive (default) 1: fail safe active fs is cleared upon exit from fail-s afe mode (refer to chapter ?fail-safe mode?) 1. individual failure flags may be masked in the configuration register (0x3f). 2. bit may be masked in the configuration register (0x3f) , i.e. the bit will not be included in the global status bit (gsbn). 3. open-load status flags may be masked in the configur ation register (0x3f), i.e. the open-load flag will be included in the fe flag, but will not set the gsbn . tw failure status flags may be masked in the configuration register (0x3f), i.e. the tw flag will be included in the gw flag, but will not set the gsbn. table 66. gsb signals description (continued) bit name description docid029145 rev 4 115/162 L99DZ120 spi registers 161 7.2 control register overview table 67. control register overview bit access addr. reg. 2322212019181716151413121110 9 8 7 6 5 4 3 2 1 0 0x00 reserved 0x01 cr1 reserved wu_en reserved wu_pu reserved wu_filt_1 wu_filt_0 timer_nint_wake_sel timer_nint_en reserved hen v2_1 v2_0 parity stby_sel go_stby trig r/w 0x02 cr2 t1_restart t1_dir t1_on_2 t1_on_1 t1_on_0 t1_per_2 t1_per_1 t1_per_0 t2_restart t2_dir t2_on_2 t2_on_1 t2_on_0 t2_per_2 t2_per_1 t2_per_0 lin_rec_only lin_txd_tout_en reserved v1_reset_1 v1_reset_0 wd_time_1 wd_time_0 r/w 0x03 cr3 vsreg_lock_en vs_lock_en vsreg_ov_sd_en vsreg_uv_sd_en vs_ov_sd_en vs_uv_sd_en reserved vsreg_ewth_9 vsreg_ewth_8 vsreg_ewth_7 vsreg_ewth_6 vsreg_ewth_5 vsreg_ewth_4 vsreg_ewth_3 vsreg_ewth_2 vsreg_ewth_1 vsreg_ewth_0 r/w 0x04 cr4 reserved out1_hs out1_ls reserved out4_hs out4_ls reserved out5_hs out5_ls reserved out6_hs out6_ls r/w 0x05 cr5 out7_3 out7_2 out7_1 out7_0 out8_3 out8_2 out8_1 out8_0 reserved out10_3 out10_2 out10_1 out10_0 reserved ouths_3 ouths_2 ouths_1 ouths_0 r/w 0x06 cr6 out9_3 out9_2 out9_1 out9_0 out11_3 out11_2 out11_1 out11_0 out12_3 out12_2 out12_1 out12_0 out13_3 out13_2 out13_1 out13_0 out14_3 out14_2 out14_1 out14_0 out15_3 out15_2 out15_1 out15_0 r/w 0x07 cr7 out1_ocr reserved out4_ocr out5_ocr out6_ocr out7_ocr out8_ocr ouths_ocr reserved ocr_freq out5_oc1 out5_oc0 cm_en reserved cm_sel_3 cm_sel_2 cm_sel_1 cm_sel_0 r/w spi registers L99DZ120 116/162 docid029145 rev 4 0x08 cr8 out1_ocr_thx_en reserved out4_ocr_thx_en out5_ocr_thx_en out6_ocr_thx_en out7_ocr_thx_en out8_ocr_thx_en ouths_ocr_thx_en reserved r/w 0x09 cr9 out7_rdson out8_rdson reserved ouths_ol out15_ol out14_ol out13_ol out12_ol out11_ol out10_ol out9_ol ouths_oc out15_oc out14_oc out13_oc out12_oc out11_oc out10_oc out9_oc r/w 0x0a cr10 diag_2 diag_1 diag_0 reserved sd sds copt_3 copt_2 copt_1 copt_0 h_olth_high ol_h1l2 ol_h2l1 slew_4 slew_3 slew_2 slew_1 slew_0 r/w 0x0b cr11 reserved r/w 0x0c cr12 pmw1_freq_1 pmw1_freq_0 pmw2_freq_1 pmw2_freq_0 pmw3_freq_1 pmw3_freq_0 pmw4_freq_1 pmw4_freq_0 pmw5_freq_1 pmw5_freq_0 pmw6_freq_1 pmw6_freq_0 pmw7_freq_1 pmw7_freq_0 pmw8_freq_1 pmw8_freq_0 pmw9_freq_1 pmw9_freq_0 pmw10_freq_1 pmw10_freq_0 reserved r/w 0x0d cr13 reserved pwm1_dc_9 pwm1_dc_8 pwm1_dc_7 pwm1_dc_6 pwm1_dc_5 pwm1_dc_4 pwm1_dc_3 pwm1_dc_2 pwm1_dc_1 pwm1_dc_0 reserved pwm2_dc_9 pwm2_dc_8 pwm2_dc_7 pwm2_dc_6 pwm2_dc_5 pwm2_dc_4 pwm2_dc_3 pwm2_dc_2 pwm2_dc_1 pwm2_dc_0 r/w 0x0e cr14 reserved pwm3_dc_9 pwm3_dc_8 pwm3_dc_7 pwm3_dc_6 pwm3_dc_5 pwm3_dc_4 pwm3_dc_3 pwm3_dc_2 pwm3_dc_1 pwm3_dc_0 reserved pwm4_dc_9 pwm4_dc_8 pwm4_dc_7 pwm4_dc_6 pwm4_dc_5 pwm4_dc_4 pwm4_dc_3 pwm4_dc_2 pwm4_dc_1 pwm4_dc_0 r/w 0x0f cr15 reserved pwm5_dc_9 pwm5_dc_8 pwm5_dc_7 pwm5_dc_6 pwm5_dc_5 pwm5_dc_4 pwm5_dc_3 pwm5_dc_2 pwm5_dc_1 pwm5_dc_0 reserved pwm6_dc_9 pwm6_dc_8 pwm6_dc_7 pwm6_dc_6 pwm6_dc_5 pwm6_dc_4 pwm6_dc_3 pwm6_dc_2 pwm6_dc_1 pwm6_dc_0 r/w table 67. control register overview (continued) bit access addr. reg. 2322212019181716151413121110 9 8 7 6 5 4 3 2 1 0 docid029145 rev 4 117/162 L99DZ120 spi registers 161 0x10 cr16 reserved pwm7_dc_9 pwm7_dc_8 pwm7_dc_7 pwm7_dc_6 pwm7_dc_5 pwm7_dc_4 pwm7_dc_3 pwm7_dc_2 pwm7_dc_1 pwm7_dc_0 reserved pwm8_dc_9 pwm8_dc_8 pwm8_dc_7 pwm8_dc_6 pwm8_dc_5 pwm8_dc_4 pwm8_dc_3 pwm8_dc_2 pwm8_dc_1 pwm8_dc_0 r/w 0x11 cr17 reserved pwm9_dc_9 pwm9_dc_8 pwm9_dc_7 pwm9_dc_6 pwm9_dc_5 pwm9_dc_4 pwm9_dc_3 pwm9_dc_2 pwm9_dc_1 pwm9_dc_0 reserved pwm10_dc_9 pwm10_dc_8 pwm10_dc_7 pwm10_dc_6 pwm10_dc_5 pwm10_dc_4 pwm10_dc_3 pwm10_dc_2 pwm10_dc_1 pwm10_dc_0 r/w 0x12 cr18 reserved out7_autocomp_en out7_vled_9 out7_vled_8 out7_vled_7 out7_vled_6 out7_ vled_5 out7_vled_4 out7_vled_3 out7_vled_2 out7_vled_1 out7_vled_0 reserved out8_autocomp_en out8_vled_9 out8_vled_8 out8_vled_7 out8_vled_6 out8_vled_5 out8_vled_4 out8_vled_3 out8_vled_2 out8_vled_1 out8_vled_0 r/w 0x13 cr19 reserved out9_autocomp_en out9_vled_9 out9_vled_8 out9_vled_7 out9_vled_6 out9_vled_5 out9_vled_4 out9_vled_3 out9_vled_2 out9_vled_1 out9_vled_0 reserved out10_autocomp_en out10_vled_9 out10_vled_8 out10_vled_7 out10_vled_6 out10_vled_5 out10_vled_4 out10_vled_3 out10_vled_2 out10_vled_1 out10_vled_0 r/w 0x14 cr20 reserved out11_autocomp_en out11_vled_9 out11_vled_8 out11_vled_7 out11_vled_6 out11_vled_5 out11_vled_4 out11_vled_3 out11_vled_2 out11_vled_1 out11_vled_0 reserved out12_autocomp_en out12_vled_9 out12_ vled_8 out12_vled_7 out12_vled_6 out12_vled_5 out12_vled_4 out12_vled_3 out12_vled_2 out12_vled_1 out12_vled_0 r/w table 67. control register overview (continued) bit access addr. reg. 2322212019181716151413121110 9 8 7 6 5 4 3 2 1 0 spi registers L99DZ120 118/162 docid029145 rev 4 note: all reserved bits (res) are read-only (r) and will be read as ?0?. writing ?1? to a reserved bit is ignored and does not cause an spi error. 0x15 cr21 reserved out13_autocomp_en out13_vled_9 out13_vled_8 out13_vled_7 out13_vled_6 out13_vled_5 out13_vled_4 out13_vled_3 out13_vled_2 out13_vled_1 out13_vled_0 reserved out14_autocomp_en out14_vled_9 out14_vled_8 out14_vled_7 out14_vled_6 out14_vled_5 out14_vled_4 out14_vled_3 out14_vled_2 out14_vled_1 out14_vled_0 r/w 0x16 cr22 reserved out15_autocomp_en out15_vled_9 out15_vled_8 out15_vled_7 out15_vled_6 out15_vled_5 out15_vled_4 out15_vled_3 out15_vled_2 out15_vled_1 out15_vled_0 reserved ouths_autocomp_en ouths_vled_9 ouths_vled_8 ouths_vled_7 ouths_vled_6 ouths_vled_5 ouths_vled_4 ouths_vled_3 ouths_vled_2 ouths_vled_1 ouths_vled_0 r/w 0x22 cr34 reserved cp_off icmp wd_en r/w 0x3f conf reg wu_config lin_wu_config lin_hs_en tsd_config reserved dm icmp_config_en wd_config_en mask_ol_hs1 mask_ol_ls1 mask_tw reserved mask_ol mask_spie mask_ple mask_gw cp_off_en cp_low_config cp_dith_dis fs_forced reserved trig r/w table 67. control register overview (continued) bit access addr. reg. 2322212019181716151413121110 9 8 7 6 5 4 3 2 1 0 docid029145 rev 4 119/162 L99DZ120 spi registers 161 7.3 status register overview table 68. status register overview bit access addr.reg.23222120191817161514131211109876543210 0x31 sr1 reserved wu_state reserved wu_wake reserved wake_lin wake_timer debug_active v1uv v1_restart_2 v1_restart_1 v1_restart_0 wdfail_cnt_3 wdfail_cnt_2 wdfail_cnt_1 wdfail_cnt_0 device_state_1 device_state_0 tsd2 tsd1 forced_sleep_tsd2/v1sc forced_sleep_wd wdfail vpor r 0x32 sr2 lin_perm_dom lin_txd_dom lin_perm_rec reserved dsmon_hs2 dsmon_hs1 dsmon_ls2 dsmon_ls1 spi_inv_cmd spi_sck_cnt cp_low tw v2sc v2fail v1fail vsreg_ew vsreg_ov vsreg_uv vs_ov vs_uv r 0x33 sr3 out1_hs_oc_th_ex out1_ls_ oc_th_ex reserved out4_hs_oc_th_ex out4_ls_ oc_th_ex out5_hs_oc_th_ex out5_ls_oc_th_ex out6_hs_oc_th_ex out6_ls_oc_th_ex out7_oc_th_ex out8_oc_th_ex out9_oc out10_oc out11_oc out12_oc out13_oc out14_oc out15_oc ouths_oc_th_ex ls2fso_oc ls1fso_oc r 0x34 sr4 out1_hs_ocr_alert out1_ls_ocr_alert reserved out4_hs_ocr_alert out4_ls_ocr_alert out5_hs_ocr_alert out5_ls_ocr_alert out6_hs_ocr_alert out6_ls_ocr_alert out7_ocr_alert out8_ocr_alert reserved ouths_ocr_alert reserved r 0x35 sr5 out1_hs_ol out1_ls_ol reserved out4_hs_ol out4_ls_ol out5_hs_ol out5_ls_ol out6_hs_ol out6_ls_ol out7_ol out8_ol out9_ol out10_ol out11_ol out12_ol out13_ol out14_ol out15_ol ouths_ol reserved r spi registers L99DZ120 120/162 docid029145 rev 4 0x36 sr6 wd_timer_state_1 wd_timer_state_0 reserved tw_cl6 tw_cl5 tw_cl4 tw_cl3 tw_cl2 tw_cl1 reserved tsd1_cl6 tsd1_cl5 tsd1_cl4 tsd1_cl3 tsd1_cl2 tsd1_cl1 r 0x37 sr7 reserved temp_cl2_9 temp_cl2_8 temp_cl2_7 temp_cl2_6 temp_cl2_5 temp_cl2_4 temp_cl2_3 temp_cl2_2 temp_cl2_1 temp_cl2_0 reserved temp_cl1_9 temp_cl1_8 temp_cl1_7 temp_cl1_6 temp_cl1_5 temp_cl1_4 temp_cl1_3 temp_cl1_2 temp_cl1_1 temp_cl1_0 r 0x38 sr8 reserved temp_cl4_9 temp_cl4_8 temp_cl4_7 temp_cl4_6 temp_cl4_5 temp_cl4_4 temp_cl4_3 temp_cl4_2 temp_cl4_1 temp_cl4_0 reserved temp_cl3_9 temp_cl3_8 temp_cl3_7 temp_cl3_6 temp_cl3_5 temp_cl3_4 temp_cl3_3 temp_cl3_2 temp_cl3_1 temp_cl3_0 r 0x39 sr9 reserved temp_cl6_9 temp_cl6_8 temp_cl6_7 temp_cl6_6 temp_cl6_5 temp_cl6_4 temp_cl6_3 temp_cl6_2 temp_cl6_1 temp_cl6_0 reserved temp_cl5_9 temp_cl5_8 temp_cl5_7 temp_cl5_6 temp_cl5_5 temp_cl5_4 temp_cl5_3 temp_cl5_2 temp_cl5_1 temp_cl5_0 r 0x3a sr10 reserved vsreg_9 vsreg_8 vsreg_7 vsreg_6 vsreg_5 vsreg_4 vsreg_3 vsreg_2 vsreg_1 vsreg_0 reserved r 0x3b sr11 reserved vs_9 vs_8 vs_7 vs_6 vs_5 vs_4 vs_3 vs_2 vs_1 vs_0 reserved vwu_9 vwu_8 vwu_7 vwu_6 vwu_5 vwu_4 vwu_3 vwu_2 vwu_1 vwu_0 r table 68. status register overview (continued) bit access addr.reg.23222120191817161514131211109876543210 docid029145 rev 4 121/162 L99DZ120 spi registers 161 7.4 control registers 7.4.1 control register cr1 (0x01) table 69. control register cr1 23222120191817161514131211109876543210 bit name reserved wu_en reserved wu_pu reserved wu_filt_1 wu_filt_0 timer_ni0nt_wake_sel timer_nint_en reserved hen v2_1 v2_0 parity stby_sel go_stby trig reset 0 1 0 0 00000010000000000000 access r r/w r r/w r r/w table 70. cr1 signals description bit name description 23 reserved ? 22 wu_en wake-up input 1 (wu) enable (1) 0: wu disabled 1: wu enabled (default) 21 reserved ? 20 wu_pu wake-up input1 pull-up/down configuration: configuration of internal current source (1) 0: pull-down (default) 1: pull-up 19 reserved ? 18 17 wu_filt_1 wake-up input1 filter configuration bits: configuratio n of input filter (1) see table 71: wake-up input1 filter configuration 16 wu_filt_0 15 timer_nint_wake_sel select timer for nint / wake: select timer for periodic interrupt in standby modes 0: timer 2 (default) 1: timer 1 spi registers L99DZ120 122/162 docid029145 rev 4 14 timer_nint_en timer nint enable: enable timer interrupt in standby modes 0: timer interrupt disabled (default) 1: timer interrupt enabled v1_standby mode: periodic nint pulse generated by timer (nint pulse at start of timer on-phase) vbat_standby mode: device wakes up after timer expiration and generates nreset 13:7 reserved ? 6hen enable h-bridge 0: h-bridge disabled (default) 1: h-bridge enabled refer to chapter h-bridge control for details 5v2_1 voltage regulator v2 configuration see table 72: voltage regulator v2 configuration 4v2_0 3 parity parity: standby command parity bit stby sel: select standby mode go_stby: execute transition into standby mode the stby_sel and go_stby bits are protected by a parity check. the bits stby_sel, go_stby and parity must represent an even number of '1', otherwise the command is ignored and the spi_inv_cmd bit is set. table 73: standby transition configuration shows the valid settings. all other settings are invalid; comm and will be ignored and spi_inv_cmd will be set. the go_stby bit is not cleared automatically after wake-up. 2 stby_sel 1 go_stby 0 trig watchdog trigger bit 1. setting is only valid if input is configured as wake-up input in configuration register (0x3f). table 70. cr1 signals description (continued) bit name description table 71. wake-up input1 filter configuration wu _ filt_1 wu _ filt_0 0 0 wake-up inputs monitored in static mode (filter time twu_stat) (default) 01 wake- up inputs monitored in cyclic mode with timer2 (filter time: t wu_cyc ; blanking time 80% of timer on time) 10 wake- up inputs monitored in cyclic mode with timer1 (filter time: t wu_cyc ; blanking time 80% of timer on time) 1 1 invalid setting; command will be ignored and spi inv cmd will be set table 72. voltage regulator v2 configuration v2_1 v2_0 0 0 v2 off in all modes (default) 0 1 v2 on in active mode; off in standby modes docid029145 rev 4 123/162 L99DZ120 spi registers 161 7.4.2 control register cr2 (0x02) 1 0 v2 on in active and v1_standby mode; off in vbat_standby mode 1 1 v2 on in all modes table 73. standby transition configuration parity stby_sel go_stby 0 1 1 go to v1 standby 1 0 1 go to vbat_standby 000 no transition to standby 110 table 72. voltage regulator v2 configuration (continued) v2_1 v2_0 table 74. control register cr2 23222120191817161514131211109876543210 bit name t1_restart t1_dir t1_on_2 t1_on_1 t1_on_0 t1_per_2 t1_per_1 t1_per_0 t2_restart t2_dir t2_on_2 t2_on_1 t2_on_0 t2_per_2 t2_per_1 t2_per_0 lin_rec_only lin_txd_tout_en reserved v1_reset_1 v1_reset_0 wd_time_1 wd_time_0 reset 0 0 0 0 00000000000001000000 access r/w table 75. cr2 signals description bit name description 23 t1_restart timer 1 restart: restart of timer 1 0: timer is running with period and on-ti me according to configuration (default) 1: restart of timer at csn low to high transition; starting with on phase (1) bit is automatically reset with next spi frame. 22 t1_dir1 t1_dir1: timer 1 direct drive by dir1 t1_on_x: timer 1 on-time bits configuration of timer 1 on-time, for details see table 76 and figure 56 21 t1_on_2 20 t1_on_1 19 t1_on_0 spi registers L99DZ120 124/162 docid029145 rev 4 18 t1_per_2 configuration of timer 1 period 000: t1 (default) 001: t2 010: t3 011: t4 100: t5 101: t6 110: t7 111: t8 17 t1_per_1 16 t1_per_0 15 t2_restart timer 2 restart: restart of timer 2 0: timer is running with period and on-ti me according to configuration (default) 1: restart of timer at csn low to high transition; starting with on phase (1) bit is automatically reset with next spi frame. 14 t2_dir1 t2_dir1: timer 2 direct drive by dir1 t2_on_x: timer 2 on-time bits configuration of timer 2 on-time, for details see table 76 and figure 56 13 t2_on_2 12 t2_on_1 11 t2_on_0 10 t2_per_2 configuration of timer 2 period 000: t1 (default) 001: t2 010: t3 011: t4 100: t5 101: t6 110: t7 111: t8 9 t2_per_1 8 t2_per_0 7lin_rec_only lin transceiver receive only mode 0: lin receive only mode disabled (default) 1: lin receive only mode enabled 6 lin_txd_tout_en lin txd timeout enable 0: lin txd timeout detection disabled 1: lin txd timeout dete ction enabled (default) 5:4 reserved ? table 75. cr2 signals description (continued) bit name description docid029145 rev 4 125/162 L99DZ120 spi registers 161 3 v1_reset_1 voltage regulator v1 reset threshold 00: vrt4 (default) 01: vrt3 10: vrt2 11: vrt1 thresholds are monitored in active mode and v1_standby mode 2 v1_reset_0 1 wd_time_1 watchdog trigger time 00: tsw1 (default) 01: tsw2 10: tsw3 11: tsw4 writing to wd_time_x is blocked unless wd config en = 1. the modified wd trigger time is valid im mediately after the write command (csn transition low-high). the watchdog timer is reset when the trigger time is modified (restart at csn transition low-high). 0wd_time_0 1. timer restart behavior: ? write to cr2 when tx_on_x and tx_perx remain unchanged: ? tx_restart = 1: timers restart at end of spi frame, starting with on time ? tx_restart = 0: write operation to cr2 has no effect on timers ? write to cr2 when tx_on_x and tx_perx are modified ? tx_restart = 1: timers restart at end of spi frame, star ting with on time and according to new setting (on time and period) ? tx_restart = 0: behavior is not defined; if a predictable behavior is needed, it is recommended to set tx_restart = 1 table 75. cr2 signals description (continued) bit name description table 76. configuration of timer x on-time tx_dir1 tx_on_2 tx_on_1 tx_on_0 0 0 0 0 ton1 (default) 0001ton2 0010ton3 0011ton4 0100ton5 0101 invalid setting; command will be ignored and spi inv cmd will be set 0110 0111 1 (1) 0 0 0 ton1 controlled by dir1 input signal (logical and) 1 (1) 0 0 1 ton2 controlled by dir1 input signal (logical and) 1 (1) 0 1 0 ton3 controlled by dir1 input signal (logical and) 1 (1) 0 1 1 ton4 controlled by dir1 input signal (logical and) 1 (1) 1 0 0 ton5 controlled by dir1 input signal (logical and) spi registers L99DZ120 126/162 docid029145 rev 4 figure 56. timer_x controlled by dir1 7.4.3 control register cr3 (0x03) 1 (1) 101 invalid setting; command will be ignored and spi inv cmd will be set 1 (1) 110 1 (1) 111 1. tx_dir1 = 1 is only valid for out7-out15 and out_hs control; the dir1 signal has no influence for wu monitoring if wu is monitored by timer. table 76. configuration of timer x on-time (continued) tx_dir1 tx_on_2 tx_on_1 tx_on_0 7 [ ' , 5 7 [ w r q [ 7 l p h u ; ' , 5 2 8 7 [ ( " 1 ( $ ' 5 table 77. control register cr3 23222120191817161514131211109876543210 bit name vsreg_lock_en vs_lock_en vsreg_ov_sd_en vsreg_uv_sd_en vs_ov_sd_en vs_uv_sd_en reserved vsreg_ewth_9 vsreg_ewth_8 vsreg_ewth_7 vsreg_ewth_6 vsreg_ewth_5 vsreg_ewth_4 vsreg_ewth_3 vsreg_ewth_2 vsreg_ewth_1 vsreg_ewth_0 reset 1 1 1 1 11000000000000000000 access r/w docid029145 rev 4 127/162 L99DZ120 spi registers 161 table 78. cr3 signals description bit name description 23 vsreg_lock_en v sreg lockout enable: lockout of v sreg related outputs after v sreg overvoltage/ undervoltage shutdown 0: v sreg related outputs are turned on automatically and status bits (vsreg_uv, vsreg_ov) are cleared 1: v sreg related outputs remain turned off until status bits (vsreg_uv, vsreg_ov) are cleared (default) lockout is always disabled in standby modes in order to ensure supply of external contacts and detect wake-up conditions 22 vs_lock_en v s lockout enable: lockout of v s related outputs after v s over/undervoltage shutdown 0: v s related outputs are turned on automatically and status bits (vs_uv, vs_ov) are cleared 1: v s related outputs remain turned off until status bits (vs_uv, vs_ov) are cleared (default) lockout is always disabled in standby modes in order to ensure supply of external contacts and detect wake-up conditions 21 vsreg_ov_sd_en v sreg overvoltage shutdown enable: shutdown of v sreg related outputs in case of v sreg overvoltage 0: no shutdown of v sreg related outputs in case of v sreg overvoltage 1: shutdown of v sreg related outputs in case of v sreg overvoltage (default) 20 vsreg_uv_sd_en v sreg undervoltage shutdown enable: shutdown of v sreg related outputs in case of v sreg undervoltage 0: no shutdown of v sreg related outputs in case of v sreg undervoltage 1: shutdown of v sreg related outputs in case of v sreg undervoltage (default) in case of v1 undervoltage due to vsreg_uv, the device enters fail-safe mode and the outputs are turned off 19 vs_ov_sd_en v s overvoltage shutdown enable: shutdown of v s related outputs in case of v s overvoltage 0: no shutdown of v s related outputs in case of v s overvoltage if charge pump output voltage is still sufficient (until cplow threshold is reached) 1: shutdown of v s related outputs in case of v s overvoltage (default) 18 vs_uv_sd_en v s undervoltage shutdown enable: shutdown of v s related outputs in case of v s undervoltage 0: no shutdown v s related of outputs in case of v s undervoltage 1: shutdown of v s related outputs in case of v s undervoltage (default) in case of v1 undervoltage due to vs_uv, the device enters fail-safe mode and the outputs are turned off 17:10 reserved reserved spi registers L99DZ120 128/162 docid029145 rev 4 7.4.4 control register cr4 (0x04) 9 vsreg_ew_th_9 v sreg early warning threshold. at v sreg < vsreg_ew_th, an interrupt is generated at nint and status bit vsreg_ew in sr2 is set (in active mode) 0000000000: 0 v (default) feature deactivated ... 1111111111: v ainvs 8 vsreg_ew_th_8 7 vsreg_ew_th_7 6 vsreg_ew_th_6 5 vsreg_ew_th_5 4 vsreg_ew_th_4 3 vsreg_ew_th_3 2 vsreg_ew_th_2 1 vsreg_ew_th_1 0 vsreg_ew_th_0 table 78. cr3 signals description (continued) bit name description table 79. control register cr4 23222120191817161514131211109876543210 bit name reserved out1_hs out1_ls reserved out4_hs out4_ls reserved out5_hs out5_ls reserved out6_hs out6_ls reset 0 0 0 0 00000000000000000000 access r/w table 80. cr4 signals description bit name description 23:22 reserved reserved 21 out1_hs out1 high-side driver control 0: out1_hs is turned off (default) 1: out1_hs is turned on an internal cross-current protection pr events, that both the low- and high-side drivers of the half-bridge out1 are switched on simultaneously. 20 out1_ls out1 low-side driver control 0: out1_ls is turned off (default) 1: out1_ls is turned on an internal cross-current protection pr events, that both the low- and high-side drivers of the half-bridge out1 are switched on simultaneously. 19:10 reserved reserved docid029145 rev 4 129/162 L99DZ120 spi registers 161 7.4.5 control register cr5 (0x05) 9 out4_hs out4 high-side driver control 0: out4_hs is turned off (default) 1: out4_hs is turned on an internal cross-current protection pr events, that both the low- and high-side drivers of the half-bridge out4 are switched on simultaneously. 8 out4_ls out4 low-side driver control 0: out4_ls is turned off (default) 1: out4_ls is turned on an internal cross-current protection pr events, that both the low- and high-side drivers of the half-bridge out4 are switched on simultaneously. 7:6 reserved reserved 5 out5_hs out5 high-side driver control 0: out5_hs is turned off (default) 1: out5_hs is turned on an internal cross-current protection pr events, that both the low- and high-side drivers of the half-bridge out5 are switched on simultaneously. 4 out5_ls out5 low-side driver control 0: out5_ls is turned off (default) 1: out5_ls is turned on an internal cross-current protection pr events, that both the low- and high-side drivers of the half-bridge out5 are switched on simultaneously. 3:2 reserved reserved 1 out6_hs out6 high-side driver control 0: out6_hs is turned off (default) 1: out6_hs is turned on an internal cross-current protection prev ents, that both the low-side and high-side drivers of the half-bridge out6 are switched on simultaneously. 0 out6_ls out6 low-side driver control 0: out6_ls is turned off (default) 1: out6_ls is turned on an internal cross-current protection prev ents, that both the low-side and high-side drivers of the half-bridge out6 are switched on simultaneously. table 80. cr4 signals description (continued) bit name description table 81. control register cr5 23222120191817161514131211109876543210 bit name out7_3 out7_2 out7_1 out7_0 out8_3 out8_2 out8_1 out8_0 reserved out10_3 out10_2 out10_1 out10_0 reserved ouths_3 ouths_2 ouths_1 ouths_0 reset 0 0 0 0 00000000000000000000 access r/w spi registers L99DZ120 130/162 docid029145 rev 4 table 82. cr5 signals description bit name description 23 out7_3 out7 configuration bits: high-side driver out7 configuration for out7 bits configuration see table 83: outx configuration bits 22 out7_2 21 out7_1 20 out7_0 19 out8_3 out8 configuration bits: high-side driver out8 configuration for out8 bits configuration see table 83: outx configuration bits 18 out8_2 17 out8_1 16 out8_0 15:12 reserved ? 11 out10_3 out10 configuration bits: high-side driver out10 configuration for out10 bits configuration see table 83: outx configuration bits 10 out10_2 9 out10_1 8 out10_0 7:4 reserved ? 3 ouths_3 ouths configuration bits: high-side driver ouths configuration for ouths bits configuration see table 83: outx configuration bits 2 ouths_2 1 ouths_1 0 ouths_0 table 83. outx c onfiguration bits outx_3 outx_2 outx_1 outx_0 description 0 0 0 0 off (default) 00 01on 0 0 1 0 timer1 0 0 1 1 timer2 01 00pwm1 01 01pwm2 01 10pwm3 01 11pwm4 10 00pwm5 10 01pwm6 10 10pwm7 10 11pwm8 11 00pwm9 docid029145 rev 4 131/162 L99DZ120 spi registers 161 7.4.6 control register cr6 (0x06) 11 01pwm10 1 1 1 0 dir1 1 1 1 1 dir2 table 83. outx configuration bits (continued) outx_3 outx_2 outx_1 outx_0 description table 84. control register cr6 23222120191817161514131211109876543210 bit name out9_3 out9_2 out9_1 out9_0 out11_3 out11_2 out11_1 out11_0 out12_3 out12_2 out12_1 out12_0 out13_3 out13_2 out13_1 out13_0 out14_3 out14_2 out14_1 out14_0 out15_3 out15_2 out15_1 out15_0 reset 0 0 0 0 00000000000000000000 access r/w table 85. cr6 signals description bit name description 23 out9_3 out9 configuration bits: high-side driver out9 configuration for out9 bits configuration see table 83: outx configuration bits 22 out9_2 21 out9_1 20 out9_0 19 out11_3 out11 configuration bits: high-s ide driver out11 configuration for out11 bits configuration see table 83: outx configuration bits 18 out11_2 17 out11_1 16 out11_0 15 out12_3 out12 configuration bits: high-side driver out12 configuration for out12 bits configuration see table 83: outx configuration bits 14 out12_2 13 out12_1 12 out12_0 11 out13_3 out13 configuration bits: high-side driver out13 configuration for out13 bits configuration see table 83: outx configuration bits 10 out13_2 9 out13_1 8 out13_0 spi registers L99DZ120 132/162 docid029145 rev 4 7.4.7 control register cr7 (0x07) 7 out14_3 out14 configuration bits: high-side driver out14 configuration for out14 bits configuration see table 83: outx configuration bits 6 out14_2 5 out14_1 4 out14_0 3 out15_3 out15 configuration bits: high-side driver out15 configuration for out15 bits configuration see table 83: outx configuration bits 2 out15_2 1 out15_1 0 out15_0 table 85. cr6 signals description (continued) bit name description table 86. control register cr7 23222120191817161514131211109876543210 bit name out1_ocr reserved out4_ocr out5_ocr out6_ocr out7_ocr out8_ocr ouths_ocr reserved ocr_freq out5_oc1 out5_oc0 cm_en reserved cm_sel_3 cm_sel_2 cm_sel_1 cm_sel_0 reset 0 0 0 0 00000000000000100000 access r/w table 87. cr7 signals description bit name description 23 out1_ocr overcurrent recovery for out1 0: overcurrent recovery is turned off (default) 1: overcurrent recovery is turned on 22:21 reserved ? 20 out4_ocr overcurrent recovery for outx 0: overcurrent recovery is turned off (default) 1: overcurrent recovery is turned on 19 out5_ocr 18 out6_ocr 17 out7_ocr 16 out8_ocr 15 ouths_ocr overcurrent recovery for ouths 0: overcurrent recovery is turned off (default) 1: overcurrent recovery is turned on 14:9 reserved ? docid029145 rev 4 133/162 L99DZ120 spi registers 161 8ocr_freq overcurrent recovery frequency 0: freq0 (default) 1: freq1 7 out5_oc1 overcurrent threshold for out5 00: ioc5_3 overcurrent threshold 3 (default) 01: ioc5_1 overcurrent threshold 1 10: ioc5_2 overcurrent threshold 2 11: ioc5_3 overcurrent threshold 3 6 out5_oc0 5cm_en current monitor: 0: off (3-state) 1: on (default) 4 reserved ? 3 cm_sel_3 current moni tor select bits. a current image of the selected binary coded output is multiplexed to the cm output. if a corresponding output does not exist, the current monitor is deactivated. 0000: out1 0001: invalid configuration 0010: invalid configuration 0011: out4 0100: out5 0101: out6 0110: out7 0111: out8 1000: out9 1001: out10 1010: out11 1011: out12 1100: out13 1101: out14 1110: out15 1111: out_hs 2 cm_sel_2 1 cm_sel_1 0 cm_sel_0 table 87. cr7 signals description (continued) bit name description spi registers L99DZ120 134/162 docid029145 rev 4 7.4.8 control register cr8 (0x08) table 88. control register cr8 23222120191817161514131211109876543210 bit name out1_ocr_thx_en reserved out4_ocr_thx_en out5_ocr_thx_en out6_ocr_thx_en out7_ocr_thx_en out8_ocr_thx_en ouths_ocr_thx_en resrved reset 1 1 1 1 11111000000000000000 access r/w table 89. cr8 signals description bit name description 23 out1_ocr_thx_en enable overcurrent recovery with thermal expiration for outx. 0: overcurrent recovery with thermal expiration is off 1: overcurrent recovery with the rmal expiration is on (default) the output is turned off after thermal expiration. 22:21 reserved ? 20 out4_ocr_thx_en enable overcurrent recovery with thermal expiration for outx. 0: overcurrent recovery with thermal expiration is off 1: overcurrent recovery with the rmal expiration is on (default) the output is turned off after thermal expiration. 19 out5_ocr_thx_en 18 out6_ocr_thx_en 17 out7_ocr_thx_en 16 out8_ocr_thx_en 15 ouths_ocr_thx_en enable overcurrent recovery with thermal expiration for ouths. 0: overcurrent recovery with thermal expiration is off 1: overcurrent recovery with the rmal expiration is on (default) the output is turned off after thermal expiration. 14:0 reserved ? docid029145 rev 4 135/162 L99DZ120 spi registers 161 7.4.9 control register cr9 (0x09) table 90. control register cr9 23222120191817161514131211109876543210 bit name out7_rdson out8_rdson reserved ouths_ol out15_ol out14_ol out13_ol out12_ol out11_ol out10_ol out9_ol ouths_oc out15_oc out14_oc out13_oc out12_oc out11_oc out10_oc out9_oc reset 0 0 0 0 00000000000000000000 access r/w table 91. cr9 signals description bit name description 23 out7_rdson select rdson for out7 0: r on_low (default) 1: r on_high 22 out8_rdson select rdson for out8 0: r on_low (default) 1: r on_high 21:16 reserved ? 15 ouths_ol open-load threshold for outx 0: i old1 ; high-current mode (default) 1: i old1 ; low-current mode 14 out15_ol 13 out14_ol 12 out13_ol 11 out12_ol 10 out11_ol 9 out10_ol 8out9_ol 7 ouths_oc overcurrent threshold for outx 0: i oc ; high-current mode (default) 1: i oc ; low-current mode 6 out15_oc 5 out14_oc 4 out13_oc 3 out12_oc 2 out11_oc 1 out10_oc 0 out9_oc spi registers L99DZ120 136/162 docid029145 rev 4 7.4.10 control re gister cr10 (0x0a) table 92. control register cr10 23222120191817161514131211109876543210 bit name diag_2 diag_1 diag_0 reserved sd sds copt_3 copt_2 copt_1 copt_0 h_olth_high ol_h1l2 ol_h2l1 slew_4 slew_3 slew_2 slew_1 slew_0 reset 1 1 1 0 01110000111100000000 access r/w table 93. cr10 signals description bit name description 23 diag_2 drain-source monitoring threshold for external h-bridge 000: v scd1_hb 001: v scd2_hb 010: v scd3_hb 011: v scd4_hb 100: v scd5_hb 101: v scd6_hb 110: v scd7_hb 111: v scd7_hb (default) 22 diag_1 21 diag_0 20:14 reserved ? 13 sd slow decay 12 sds slow decay single 11 copt_3 cross current protection time 0000: not allowed 0001: tccp 0001 0010: tccp 0010 0011: tccp 0011 0100: tccp 0100 0101: tccp 0101 0110: tccp 0110 0111: tccp 0111 1000: tccp 1000 1001: tccp 1001 1010: tccp 1010 1011: tccp 1011 1100: tccp 1100 1101: tccp 1101 1110: tccp 1110 1111: tccp 1111 (default) 10 copt_2 9copt_1 8copt_0 7 h_olth_high h-bridge ol high threshold (5/6 * v s ) select docid029145 rev 4 137/162 L99DZ120 spi registers 161 7.4.11 control register cr11 (0x0b) 7.4.12 control re gister cr12 (0x0c) 6 ol_h1l2 test open-load condition between h1 and l2 5 ol_h2l1 test open-load condition between h2 and l1 4slew_4 binary coded slew rate of h-bridge (bit0 = lsb; bit4 = msb) 00000: control disabled (default) 11111: i ghxmax 3slew_3 2slew_2 1slew_1 0slew_0 table 93. cr10 signals description (continued) bit name description table 94. control register cr11 23222120191817161514131211109876543210 bit name reserved reset 0 0 0 0 00000000000000100000 access r/w table 95. cr11 signals description bit name description 23:0 reserved ? table 96. control register cr12 23222120191817161514131211109876543210 bit name pmw1_freq_1 pmw1_freq_0 pmw2_freq_1 pmw2_freq_0 pmw3_freq_1 pmw3_freq_0 pmw4_freq_1 pmw4_freq_0 pmw5_freq_1 pmw5_freq_0 pmw6_freq_1 pmw6_freq_0 pmw7_freq_1 pmw7_freq_0 pmw8_freq_1 pmw8_freq_0 pmw9_freq_1 pmw9_freq_0 pmw10_freq_1 pmw10_freq_0 reserved reset 0 0 0 0 00000000000000000000 access r/w spi registers L99DZ120 138/162 docid029145 rev 4 table 97. cr12 signals description bit name description 23 pmw1_freq_1 frequency of pwm channel pwm1 00: f pwmx (00) (default) 01: f pwmx (01) 10: f pwmx (10) 11: f pwmx (11) 22 pmw1_freq_0 21 pmw2_freq_1 frequency of pwm channel pwm2 00: f pwmx (00) (default) 01: f pwmx (01) 10: f pwmx (10) 11: f pwmx (11) 20 pmw2_freq_0 19 pmw3_freq_1 frequency of pwm channel pwm3 00: f pwmx (00) (default) 01: f pwmx (01) 10: f pwmx (10) 11: f pwmx (11) 18 pmw3_freq_0 17 pmw4_freq_1 frequency of pwm channel pwm4 00: f pwmx (00) (default) 01: f pwmx (01) 10: f pwmx (10) 11: f pwmx (11) 16 pmw4_freq_0 15 pmw5_freq_1 frequency of pwm channel pwm5 00: f pwmx (00) (default) 01: f pwmx (01) 10: f pwmx (10) 11: f pwmx (11) 14 pmw5_freq_0 13 pmw6_freq_1 frequency of pwm channel pwm6 00: f pwmx (00) (default) 01: f pwmx (01) 10: f pwmx (10) 11: f pwmx (11) 12 pmw6_freq_0 11 pmw7_freq_1 frequency of pwm channel pwm7 00: f pwmx (00) (default) 01: f pwmx (01) 10: f pwmx (10) 11: f pwmx (11) 10 pmw7_freq_0 9 pmw8_freq_1 frequency of pwm channel pwm8 00: f pwmx (00) (default) 01: f pwmx (01) 10: f pwmx (10) 11: f pwmx (11) 8 pmw8_freq_0 docid029145 rev 4 139/162 L99DZ120 spi registers 161 7.4.13 control register cr13 (0x0d) to cr17 (0x11) where: x = 1 + (z * 2), z = 0 to 4 y = 2 + (z * 2), z = 0 to 4 7 pmw9_freq_1 frequency of pwm channel pwm9 00: f pwmx (00) (default) 01: f pwmx (01) 10: f pwmx (10) 11: f pwmx (11) 6 pmw9_freq_0 5 pmw10_freq_1 frequency of pwm channel pwm10 00: f pwmx (00) (default) 01: f pwmx (01) 10: f pwmx (10) 11: f pwmx (11) 4 pmw10_freq_0 3:0 reserved ? table 97. cr12 signals description (continued) bit name description table 98. control register cr13 to cr17 23222120191817161514131211109876543210 bit name reserved pwmx_dc_9 pwmx_dc_8 pwmx_dc_7 pwmx_dc_6 pwmx_dc_5 pwmx_dc_4 pwmx_dc_3 pwmx_dc_2 pwmx_dc_1 pwmx_dc_0 reserved pwmy_dc_9 pwmy_dc_8 pwmy_dc_7 pwmy_dc_6 pwmy_dc_5 pwmy_dc_4 pwmy_dc_3 pwmy_dc_2 pwmy_dc_1 pwmy_dc_0 reset 0 0 0 0 00000000000000000000 access r/w table 99. cr13 to cr17 signals description bit name description 23:22 reserved ? spi registers L99DZ120 140/162 docid029145 rev 4 7.4.14 control register cr18 (0x12) to cr22 (0x16) 21 pwmx_dc_9 binary coded on-dutycycle of pwm channel pwmx (bit12 = lsb; bit21 = msb) 00 0000 0000: duty cycle 0% (default) xx xxxx xxxx: duty cycle 100% /1023 x register value 11 1111 1111. duty cycle 100% 20 pwmx_dc_8 19 pwmx_dc_7 18 pwmx_dc_6 17 pwmx_dc_5 16 pwmx_dc_4 15 pwmx_dc_3 14 pwmx_dc_2 13 pwmx_dc_1 12 pwmx_dc_0 11:10 reserved ? 9 pwmy_dc_9 binary coded on-dutycycle of pwm channel pwmy (bit0 = lsb; bit9 = msb) 00 0000 0000: duty cycle 0% (default) xx xxxx xxxx: duty cycle 100% /1023 x register value 11 1111 1111. duty cycle 100% binary coded on-dutycycle of pwm channel pwmy 8 pwmy_dc_8 7 pwmy_dc_7 6 pwmy_dc_6 5 pwmy_dc_5 4 pwmy_dc_4 3 pwmy_dc_3 2 pwmy_dc_2 1 pwmy_dc_1 0 pwmy_dc_0 table 99. cr13 to cr17 signals description (continued) bit name description table 100. control register cr18 23222120191817161514131211109876543210 bit name reserved outx_autocomp_en outx_vled_9 outx_vled_8 outx_vled_7 outx_vled_6 outx_ vled_5 outx_vled_4 outx_vled_3 outx_vled_2 outx_vled_1 outx_vled_0 reserved outy_autocomp_en outy_vled_9 outy_vled_8 outy_vled_7 outy_vled_6 outy_vled_5 outy_vled_4 outy_vled_3 outy_vled_2 outy_vled_1 outy_vled_0 reset 0 0 0 0 00000000000000000000 access r/w docid029145 rev 4 141/162 L99DZ120 spi registers 161 where: x = 7 + (z * 2), z = 0 to 4 y = 8 + (z * 2), z = 0 to 4 table 101. cr18 to cr22 signals description bit name description 23 reserved ? 22 outx_autocomp_en setting this bit to ?1? enables the automatic v s compensation for outx 21 outx_vled_9 binary coded nominal led voltage of outx (bit12 = lsb; bit21 = msb) 00 0000 0000: v led = 0 v (default) xx xxxx xxxx: v led = v ainvs /1023 x register value 01 1101 0000: v led = v ainvs v led is clamped at 10 v (0x1d0h) 20 outx_vled_8 19 outx_vled_7 18 outx_vled_6 17 outx_vled_5 16 outx_vled_4 15 outx_vled_3 14 outx_vled_2 13 outx_vled_1 12 outx_vled_0 11 reserved ? 10 outy_autocomp_en setting this bit to ?1? enables the automatic v s compensation for outy 9 outy_vled_9 binary coded nominal led voltage of outy (bit0 = lsb; bit9 = msb) 00 0000 0000: v led = 0 v (default) xx xxxx xxxx: v led = v ainvs /1023 x register value 01 1101 0000: v led = v ainvs v led is clamped at 10 v (0x1d0h) 8 outy_vled_8 7 outy_vled_7 6 outy_vled_6 5 outy_vled_5 4 outy_vled_4 3 outy_vled_3 2 outy_vled_2 1 outy_vled_1 0 outy_vled_0 spi registers L99DZ120 142/162 docid029145 rev 4 7.4.15 control re gister cr34 (0x22) 7.4.16 configurati on register (0x3f) table 102. control register cr34 23222120191817161514131211109876543210 bit name reserved cp_off icmp wd_en reset 0 0 0 0 00000000000000000001 access r/w table 103. cr34 signals description bit name description 23:3 reserved ? 2cp_off charge pump control 0: enabled; charge pump on in active mode (default) 1: disabled; charge pump off in active mode setting cp_off = 1 is only possible when cp_off_en = 1 1icmp v1 load current supervision 0: enabled; watchdog is disabled in v1 standby when i v1 < i cmp (default) 1: disabled; watchdog is disabled upon transition into v1_standby mode setting icmp = 1 is only possible when icmp_config_en = 1 0wd_en watchdog enable 0: watchdog disabled 1: watchdog enabled (default) table 104. configuration register 23222120191817161514131211109876543210 bit name wu_config lin_wu_config lin_hs_en tsd_config reserved dm icmp_config_en wd_config_en mask_ol_hs1 mask_ol_ls1 mask_tw reserved mask_ol mask_spie mask_ple mask_gw cp_off_en cp_low_config cp_dith_dis fs_forced reserved trig reset 1 0 0 0 00000000000000000001 access r/w docid029145 rev 4 143/162 L99DZ120 spi registers 161 table 105. cr signals description bit name description 23 wu_config configuration of input pin wu input configured as wake-up input 0: wu configured as wake-up input 1: wu configured for input voltage measurement (default) 22 lin_wu_config configuration of lin wake-up behaviour 0: wake up at recessive - dominant - recessive with t dom > t dom_lin (default) (according to lin 2.2a and hardware requirements for transceivers version 1.3) 1: wake up at recessive - dominant transition 21 lin_hs_en configuration of lin transceiver bit rate 0: lin transceiver in normal communication mode (20kbit/s) (default) 1: lin transceiver in high speed mode for fast flashing (115kbit/s) 20 tsd_config configuration of thermal shutdown behaviour 0: in case of tsd1 all power stages are switched off (default) 1: selective shut down of power stage cluster 19 reserved ? 18 dm h-bridge configuration 0: single motor mode (default) 1: reserved 17 icmp_config_en icmp configuration enable 0: writing icmp = 1 is blocked (writing icmp=0 is possible); (default) 1: writing icmp = 1 is possible with next spi command bit is automatically reset to 0 after next spi command 16 wd_config_en watchdog configuration enable 0: writing to wd configuration (cr2 [0:1] is blocked (default) 1: writing to wd configuration bits is possible with next spi command bit is automatically reset to 0 after next spi command 15 mask_ol_hs1 mask open-load hs1 0: open-load condition at hs1 is not masked (default) 1: open-load condition at hs1 is masked i.e. it is reported as a functional error (gsb bit 3) but not as a global error (gsb bit 7) 14 mask_ol_ls1 mask open-load ls1 0: open-load condition at ls 1 is not masked (default) 1: open-load condition at ls1 is masked i.e. it is reported as a functional error (gsb bit 3) but not as a global error (gsb bit 7) 13 mask_tw mask thermal warning 0: thermal warning is not masked (default) 1: thermal warning is masked i.e. it is reported as a global warning (gsb bit 1) but not as a global error (gsb bit 7) spi registers L99DZ120 144/162 docid029145 rev 4 12 reserved ? 11 mask_ol mask open-load 0: open-load condition at all outputs are not masked (default) 1: open-load condition at all outputs are masked i.e. it is reported as a functional error (gsb bit 3) but not as a global error (gsb bit 7) 10 mask_spie mask spi error 0: spi errors are not masked (default) 1: spi errors are masked i.e. reported as am spi error (gsb bit 5) but not as a global error (gsb bit 7) 9 mask_ple mask physical layer error 0: physical layer errors are not masked (default) 1: physical layer errors are masked i.e. reported as a physical layer error (gsb bit 4) but not as a global error (gsb bit 7) 8 mask_gw mask global warning 0: global warning conditions are not masked (default) 1: global warning conditions are masked i.e. reported as a global warning (gsb bit 1) but not as a global error (gsb bit 7) 7 cp_off_en charge pump control enable 0: writing cp_off = 1 is blocked (writing cp off = 0 is possible); (default) 1: writing cp_off = 1 is possible with next spi command bit is automatically reset to 0 after next spi command 6 cp_low_config charge pump low configuration 0: cp_low (sr 2, bit 9) is latched and outputs are off until r&c; (default) 1: cp_low (sr 2, bit 9) is a ?live? bit; outputs are re-act ivated automatically upon recovery of the charge pump output voltage 5cp_dith_dis charge pump clock dithering 0: cp clock dithering is enabled; (default) 1: cp clock dithering is disabled 4 fs_forced force lsx_fso on lsx_fso low-side outputs are forced on (to allow diagnosis of the fail-safe path) 0: lsx_fso outputs are controlled by the fail-safe logic (default) 1: lsx_fso outputs are forced on and the device enters fail-safe mode; no nreset is generated 3:1 reserved ? 0 trig watchdog trigger bit table 105. cr signals description (continued) bit name description docid029145 rev 4 145/162 L99DZ120 spi registers 161 7.5 status registers 7.5.1 status register sr1 (0x31) table 106. status register sr1 (0x31) 23222120191817161514131211109876543210 bit name reserved wu_state reserved wu_wake reserved wake_lin wake_timer debug_active v1uv v1_restart_2 v1_restart_1 v1_restart_0 wdfail_cnt_3 wdfail_cnt_2 wdfail_cnt_1 wdfail_cnt_0 device_state_1 device_state_0 tsd2 tsd1 forced_sleep_tsd2/v1sc forced_sleep_wd wdfail vpor access r/c r r/c r r/c table 107. sr1 signals description bit name description 23 reserved ? 22 wu_state state of wu input 0: input level is low 1: input level is high the bit shows the momentary status of wu and cannot be cleared (?live bit?) note: the status is only valid if wu is configured as wake-up input in configuration register (0x3f). otherwise this bit remains at his previous logic state. 21 reserved ? 20 wu_wake wake-up by wu: shows wake up source 1: wake-up bits are latched until a ?read and clear? command 19 reserved ? 18 wake_lin wake-up by lin: shows wake up source 1: wake-up bits are latched until a ?read and clear? command 17 wake_timer wake-up by timer: shows wake up source 1: wake-up bits are latched until a ?read and clear? command 16 debug_active debug mode active: indicates device is in debug mode 1: debug mode the bit shows the momentary status and cannot be cleared (?live bit?) spi registers L99DZ120 146/162 docid029145 rev 4 15 v1uv indicates undervoltage condition at voltage regulator v1 (v1 < v rtx ) 1: undervoltage bit is latched until a ?read and clear? command 14 v1_restart_2 indicates the number of tsd2 events which caused a restart of voltage regulator v1 bits cannot be cleared; counter will be cleared automatically if no additional tsd2 event occurs within 1 minute. 13 v1_restart_1 12 v1_restart_0 11 wdfail_cnt_3 indicates number of subsequent watchdog failures. bits cannot be cleared; will be cleared with a valid watchdog trigger 10 wdfail_cnt_2 9 wdfail_cnt_1 8 wdfail cnt_0 7 device_state_1 state from which the device woke up 00: active mode after read&clear command or after flash mode state 01: active mode after wake-up from v1_standby mode (before read&clear command) 10: active mode after power-on or after wake-up from vbat_standby mode (before read&clear command) 11: flash mode (lin flash mode) bit is latched until a ?read and clear? command after a ?read and clear access?, the device state will be updated 6 device_state_0 5tsd2 thermal shutdown 2 was reached bit is latched until a "read and clear" command 4tsd1 thermal shutdown 1 was reached (logical or combination of all tsd1_clx; see status register sr6). this bit cannot be cleared directly. it is reset if the corresponding tsd1_clx bits in sr6 are cleared. 3 forced_sleep_ tsd2/v1sc device entered forced vbat_standby mode due to: ? thermal shutdown or ? short circuit on v1 during startup bit is latched until a "read and clear" command 2 forced_sleep_wd device entered forced vbat_standby m ode due to multiple watchdog failures bit is latched until a "read and clear" command 1wdfail watchdog failure bit is latched until a "read and clear" command 0 vpor v s power-on reset thresh old (vpor) reached bit is latched until a "read and clear" command table 107. sr1 signals description (continued) bit name description docid029145 rev 4 147/162 L99DZ120 spi registers 161 7.5.2 status register sr2 (0x32) table 108. status register sr2 (0x32) 23222120191817161514131211109876543210 bit name lin_perm_dom lin_txd_dom lin_perm_rec reserved dsmon_hs2 dsmon_hs1 dsmon_ls2 dsmon_ls1 spi_inv_cmd spi_sck_cnt cp_low tw v2sc v2fail v1fail vsreg_ew vsreg_ov vsreg_uv vs_ov vs_uv access r/c r r/c table 109. sr2 signals description bit name description 23 lin_perm_dom lin bus signal is dominant for t > t dom(bus) bit is latched until a ?read and clear? command 22 lin_txd_dom txdl pin is dominant for t > t dom(txdl) the lin transmitter is disabled until the bit is cleared bit is latched until a ?read and clear? command 21 lin_perm_rec lin bus signal does not follow txdl within t lin the lin transmitter is disabled until the bit is cleared bit is latched until a ?read and clear? command 20:16 reserved ? 15 dsmon_hs2 drain-source monitoring ?1? indicates a short-circuit or open-load condition was detected bit is latched until a ?read and clear? command 14 dsmon_hs1 13 dsmon_ls2 12 dsmon_ls1 11 spi_inv_cmd invalid spi command ?1? indicates one of the following conditions was detected: ? access to undefined address ? write operation to status register ? di stuck at '0' or '1' ? csn timeout ? parity failure ? invalid or undefined setting the spi frame is ignored bit is latched until a ?read and clear? command 10 spi_sck_cnt spi clock counter ?1? indicates an spi frame with wron g number of clk cycles was detected bit is latched until a valid spi frame 9cp_low charge pump voltage low ?1? indicates that the charge pump voltage is too low bit is latched until a ?read and clear? command spi registers L99DZ120 148/162 docid029145 rev 4 8tw thermal warning ?1? indicates the temperature has reached the thermal warning threshold (logical or combination of bits tw_clx in sr6) bit is latched until a ?read and clear? command 7v2sc v2 short circuit detection ?1? indicates a short circuit to gnd condi tion of v2 at turn-on of the regulator (v2 < v2_fail for t > t v2_short ) bit is latched until a ?read and clear? command 6v2fail v2 failure detection ?1? indicates a v2 fail event occurred since last readout (v2 < v2_fail for t > t v2_fail ) bit is latched until a ?read and clear? command 5v1fail v1 failure detection ?1? indicates a v1 fail event occurred since last readout (v1 < v1_fail for t > t v1_fail ) bit is latched until a ?read and clear? command 4 vsreg_ew v sreg early warning ?1? indicates the voltage at v sreg has reached the early warning threshold (configured in cr3) in active mode, an interrupt pulse is generated at nint bit is latched until a ?read and clear? command. bit needs a "read and clear" command after wake-up from standby modes 3 vsreg_ov v sreg overvoltage ?1? indicates the voltage at v sreg has reached the overvoltage threshold bit is latched until a ?read and clear? command 2 vsreg_uv v sreg undervoltage ?1? indicates the voltage at v sreg has reached the undervoltage threshold bit is latched until a ?read and clear? command 1vs_ov v s overvoltage ?1? indicates the voltage at v s has reached the overvoltage threshold bit is latched until a ?read and clear? command 0 vs_uv v s undervoltage ?1? indicates the voltage at v s has reached the undervoltage threshold bit is latched until a ?read and clear? command table 109. sr2 signals description (continued) bit name description docid029145 rev 4 149/162 L99DZ120 spi registers 161 7.5.3 status register sr3 (0x33) table 110. status register sr3 (0x33) 23222120191817161514131211109876543210 bit name out1_hs_oc_th_ex out1_ls_ oc_th_ex reserved out4_hs_oc_th_ex out4_ls_ oc_th_ex out5_hs_oc_th_ex out5_ls_oc_th_ex out6_hs_oc_th_ex out6_ls_oc_th_ex out7_oc_th_ex out8_oc_th_ex out9_oc out10_oc out11_oc out12_oc out13_oc out14_oc out15_oc ouths_oc_th_ex ls2fso_oc ls1fso_oc access r/c table 111. sr3 signals description bit name description 23 out1_hs_oc_th_ex overcurrent shutdown ?1? indicates the output was shut down due to overcurrent condition. if overcurrent recovery is di sabled (cr7: outx_ocr = 0): bit is set upon overcurrent condition and output is turned off. if overcurrent recovery is ena bled (cr7: outx_ocr = 1): in case of overcurrent condition this bit is not set. the output goes into overcurrent recovery mode and outx_ocr_alert in sr4 is set to '1' in case of thermal expiration enabled (cr8: outx_ocr_thx_en = 1): bit is set after thermal expiration and output is turned off bit is latched until a ?read and clear? command 22 out1_ls_oc_th_ex 21:18 reserved ? 17 out4_hs_oc_th_ex overcurrent shutdown ?1? indicates the output was shut down due to overcurrent condition. if overcurrent recovery is di sabled (cr7: outx_ocr = 0): bit is set upon overcurrent condition and output is turned off. if overcurrent recovery is ena bled (cr7: outx_ocr = 1): in case of overcurrent condition this bit is not set. the output goes into overcurrent recovery mode and outx_ocr_alert in sr4 is set to '1' in case of thermal expiration enabled (cr8: outx_ocr_thx_en = 1): bit is set after thermal expiration and output is turned off bit is latched until a ?read and clear? command 16 out4_ls_oc_th_ex 15 out5_hs_oc_th_ex 14 out5_ls_oc_th_ex 13 out6_hs_oc_th_ex 12 out6_ls_oc_th_ex 11 out7_oc_th_ex 10 out8_oc_th_ex spi registers L99DZ120 150/162 docid029145 rev 4 7.5.4 status register sr4 (0x34) 9out9_oc overcurrent shutdown ?1? indicates the output was shut down due to overcurrent condition. bit is latched until a ?read and clear? command 8 out10_oc 7out11_oc 6 out12_oc 5 out13_oc 4 out14_oc 3 out15_oc 2 ouths_oc_th_ex overcurrent shutdown ?1? indicates the output was shut down due to overcurrent condition. if overcurrent recovery is di sabled (cr7: outx_ocr = 0): bit is set upon overcurrent condition and output is turned off. if overcurrent recovery is ena bled (cr7: outx_ocr = 1): in case of overcurrent condition this bit is not set. the output goes into overcurrent recovery mode and outx_ocr_alert in sr4 is set to '1' in case of thermal expiration enabled (cr8: outx_ocr_thx_en = 1): bit is set after thermal expiration and output is turned off bit is latched until a ?read and clear? command 1 ls2fso_oc overcurrent shutdown ?1? indicates the output was shut down due to overcurrent condition. bit is latched until a ?read and clear? command 0 ls1fso_oc table 111. sr3 signals description (continued) bit name description table 112. status register sr4 (0x34) 23222120191817161514131211109876543210 bit name out1_hs_ocr_alert out1_ls_ocr_alert reserved out4_hs_ocr_alert out4_ls_ocr_alert out5_hs_ocr_alert out5_ls_ocr_alert out6_hs_ocr_alert out6_ls_ocr_alert out7_ocr_alert out8_ocr_alert reserved ouths_ocr_alert reserved access r r/c r r/c docid029145 rev 4 151/162 L99DZ120 spi registers 161 7.5.5 status register sr5 (0x35) table 113. sr4 signals description bit name description 23 out1_hs_ocr_alert autorecovery alert ?1? indicates that the out put reached the overcurrent threshold and is in autorecovery mode bit is not latched and cannot be cleared. 22 out1_ls_ocr_alert 21:18 reserved ? 17 out4_hs_ocr_alert autorecovery alert ?1? indicates that the out put reached the overcurrent threshold and is in autorecovery mode bit is not latched and cannot be cleared. 16 out4_ls_ocr_alert 15 out5_hs_ocr_alert 14 out5_ls_ocr_alert 13 out6_hs_ocr_alert 12 out6_ls_ocr_alert 11 out7_ocr_alert 10 out8_ocr_alert 9:3 reserved ? 2 ouths_ocr_alert autorecovery alert ?1? indicates that the out put reached the overcurrent threshold and is in autorecovery mode bit is not latched and cannot be cleared. 1:0 reserved ? table 114. status register sr5 (0x35) 23222120191817161514131211109876543210 bit name out1_hs_ol out1_ls_ol reserved out4_hs_ol out4_ls_ol out5_hs_ol out5_ls_ol out6_hs_ol out6_ls_ol out7_ol out8_ol out9_ol out10_ol out11_ol out12_ol out13_ol out14_ol out15_ol ouths_ol reserved access r/c table 115. sr5 signals description bit name description 23 out1_hs_ol open-load ?1? indicates an open-load condition was detected at the output bit is latched until a ?read and clear? command 22 out1_ls_ol 21:18 reserved ? spi registers L99DZ120 152/162 docid029145 rev 4 7.5.6 status register sr6 (0x36) 17 out4_hs_ol open-load ?1? indicates an open-load condition was detected at the output bit is latched until a ?read and clear? command 16 out4_ls_ol 15 out5_hs_ol 14 out5_ls_ol 13 out6_hs_ol 12 out6_ls_ol 11 out7_ol 10 out8_ol 9out9_ol 8 out10_ol 7out11_ol 6 out12_ol 5 out13_ol 4 out14_ol 3 out15_ol 2 ouths_ol 1:0 reserved ? table 115. sr5 signals description (continued) bit name description table 116. status register sr6 (0x36) 23222120191817161514131211109876543210 bit name wd_timer_state_1 wd_timer_state_0 reserved tw_cl6 tw_cl5 tw_cl4 tw_cl3 tw_cl2 tw_cl1 reserved tsd1_cl6 tsd1_cl5 tsd1_cl4 tsd1_cl3 tsd1_cl2 tsd1_cl1 access r r/c table 117. sr6 signals description bit name description 23 wd_timer_state_1 watchdog timer status 00: 0 - 33% 01: 33 - 66% 11: 66 - 100% 22 wd_timer_state_0 docid029145 rev 4 153/162 L99DZ120 spi registers 161 7.5.7 status register sr7 (0x37) to sr9 (0x39) where: x = 2 + (z * 2), z = 0 to 2 y = 1 + (z * 2), z = 0 to 2 21:14 reserved ? 13 tw_cl6 thermal warning for cluster x ?1? indicates cluster x has reached the thermal warning threshold bit is latched until a ?read and clear? command 12 tw_cl5 11 tw_cl4 10 tw_cl3 9tw_cl2 8tw_cl1 7:6 reserved ? 5tsd1_cl6 thermal shutdown of cluster x ?1? indicates cluster x has reached the thermal shutdown threshold (tsd1) and the output cluster was shut down bit is latched until a ?read and clear? command 4tsd1_cl5 3tsd1_cl4 2tsd1_cl3 1tsd1_cl2 0tsd1_cl1 table 117. sr6 signals description (continued) bit name description table 118. status register sr7 (0x37) to sr9 (0x39) 23222120191817161514131211109876543210 bit name reserved temp_clx_9 temp_clx_8 temp_clx_7 temp_clx_6 temp_clx_5 temp_clx_4 temp_clx_3 temp_clx_2 temp_clx_1 temp_clx_0 reserved temp_cly_9 temp_cly_8 temp_cly_7 temp_cly_6 temp_cly_5 temp_cly_4 temp_cly_3 temp_cly_2 temp_cly_1 temp_cly_0 access r/c r r/c r table 119. sr7 to sr9 signals description bit name description 23:22 reserved ? spi registers L99DZ120 154/162 docid029145 rev 4 7.5.8 status register sr10 (0x3a) 21 temp_clx_9 temperature cluster x: binary coded voltage of temperature diode for cluster x (bit12 = lsb; bit21 = msb) (see section 4.31: thermal clusters ) bits cannot be cleared. 20 temp_clx_8 19 temp_clx_7 18 temp_clx_6 17 temp_clx_5 16 temp_clx_4 15 temp_clx_3 14 temp_clx_2 13 temp_clx_1 12 temp_clx_0 11:10 reserved ? 9 temp_cly_9 temperature cluster y: binary coded volt age of temperature diode for cluster y (bit0 = lsb; bit9 = msb) (see section 4.31: thermal clusters ) bits cannot be cleared. 8 temp_cly_8 7 temp_cly_7 6 temp_cly_6 5 temp_cly_5 4 temp_cly_4 3 temp_cly_3 2 temp_cly_2 1 temp_cly_1 0 temp_cly_0 table 119. sr7 to sr9 signals description (continued) bit name description table 120. status register sr10 (0x3a) 23222120191817161514131211109876543210 bit name reserved vsreg_9 vsreg_8 vsreg_7 vsreg_6 vsreg_5 vsreg_4 vsreg_3 vsreg_2 vsreg_1 vsreg_0 reserved access r/c r r/c table 121. sr10 signals description bit name description 23:22 reserved ? docid029145 rev 4 155/162 L99DZ120 spi registers 161 7.5.9 status register sr11 (0x3b) 21 vsreg_9 binary coded voltage at v sreg pin (bit12 = lsb; bit21 = msb) 00 0000 0000: 0v xx xxxx xxxx: v ainvs /1023 x register value 11 1111 1111: v ainvs bits cannot be cleared. 20 vsreg_8 19 vsreg_7 18 vsreg_6 17 vsreg_5 16 vsreg_4 15 vsreg_3 14 vsreg_2 13 vsreg_1 12 vsreg_0 11:0 reserved ? table 121. sr10 signals description (continued) bit name description table 122. status register sr11 (0x3b) 23222120191817161514131211109876543210 bit name reserved vs_9 vs_8 vs_7 vs_6 vs_5 vs_4 vs_3 vs_2 vs_1 vs_0 reserved vwu_9 vwu_8 vwu_7 vwu_6 vwu_5 vwu_4 vwu_3 vwu_2 vwu_1 vwu_0 access r/c r r/c r table 123. sr11 signals description bit name description 23:22 reserved ? 21 vs_9 binary coded voltage at v s pin (bit12 = lsb; bit21 = msb) 00 0000 0000: 0v xx xxxx xxxx: v ainvs /1023 x register value 11 1111 1111: v ainvs bits cannot be cleared. 20 vs_8 19 vs_7 18 vs_6 17 vs_5 16 vs_4 15 vs_3 14 vs_2 13 vs_1 12 vs_0 11:10 reserved ? spi registers L99DZ120 156/162 docid029145 rev 4 9vwu_9 binary coded voltage at wu pin (bit0 = lsb; bit9 = msb) 00 0000 0000: 0v xx xxxx xxxx: v ainvs /1023 x register value 11 1111 1111: v ainvs bits cannot be cleared. 8vwu_8 7vwu_7 6vwu_6 5vwu_5 4vwu_4 3vwu_3 2vwu_2 1vwu_1 0vwu_0 table 123. sr11 signals description (continued) bit name description docid029145 rev 4 157/162 L99DZ120 package information 161 8 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions a nd product status are available at: www.st.com . ecopack ? is an st trademark. 8.1 lqfp-64 package information figure 57. lqfp-64 package dimension table 124. lqfp-64 mechanical data symbol millimeters min. typ. max. 0o 3.5 6 1 0o 9 12 2 11o 12 13 3 11o 12 13 ( " 1 ( $ ' 5 package information L99DZ120 158/162 docid029145 rev 4 a 1.60 a1 0.05 0.15 a2 1.35 1.40 1.45 b 0.27 b1 0.17 0.20 0.23 c 0.09 0.20 c1 0.09 0.127 0.16 d 12.00 bsc d1 10.00 bsc d2 6.85 d3 5.7 e 0.50 bsc e 12.00 bsc e1 10.00 bsc e2 4.79 e3 3.3 l 0.45 0.60 0.75 l1 1.00 n64 r1 0.08 r2 0.08 0.20 s0.20 tolerance of form and position aaa 0.20 bbb 0.20 ccc 0.08 ddd 0.08 table 124. lqfp-64 mechanical data (continued) symbol millimeters min. typ. max. docid029145 rev 4 159/162 L99DZ120 package information 161 figure 58. lqfp-64 footprint 8.2 lqfp-64 marking information figure 59. lqfp-64 marking information parts marked as es are not yet qualified and therefore not approved for use in production. st is not responsible for any consequences resultin g from such use. in no event will st be liable for the customer using any of these engi neering samples in production. st?s quality department must be contacted to run a qualification activity prior to any decision to use these engineering samples. ( " 1 ( $ ' 5 4 q f d j b m g v o d u j p o e j h j u t & 4 & o h j o f f s j o h t b n q m f c m b o l $ p n n f s d j b m t b n q m f - 2 ' 1 5 0 1 7 * & 8 o p u j o t d b m f . b s l j o h b s f b . b s l j o h b s f b ( " % ( . " ( p s order code L99DZ120 160/162 docid029145 rev 4 9 order code table 125. device summary package order codes tray tape and reel lqfp-64 epad L99DZ120 L99DZ120-tr docid029145 rev 4 161/162 L99DZ120 revision history 161 10 revision history table 126. document revision history date revision changes 27-apr-2016 1 initial release. 11-may-2016 2 updated section 3.3.1: lqfp64 thermal data updated table 19 updated table 21 updated table 39 updated figure 59 updated section 4.14: auto-recovery alert and thermal expiration updated section 4.22: programmable soft-start function to drive loads with higher inrush current updated figure 43 updated table 113 12-sep-2016 3 updated table 28 22-nov-2016 4 added aec-q100 qualified in features . updated table 3: esd protection , added section 3.4.12: over current recovery settings updated section 4.22: programmable soft-start function to drive loads with higher inrush current added table 17: half bridges (out1, out4, out5 and out6) ocr timing parameters and table 18: high-side (out7, out8 and out_hs ) ocr timing parameters updated table 19: current monitoring updated table 109: sr2 signals description updated table 123: sr11 signals description L99DZ120 162/162 docid029145 rev 4 important notice ? please read carefully stmicroelectronics nv and its subsidiaries (?st?) reserve the right to make changes, corrections, enhancements, modifications, and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant in formation on st products before placing orders. st products are sold pursuant to st?s terms and conditions of sale in place at the time of o rder acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and st assumes no liability for application assistance or the design of purchasers? products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information set forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2016 stmicroelectronics ? all rights reserved |
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