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d a t a sh eet product speci?cation file under integrated circuits, ic02 2001 oct 19 integrated circuits TDA4887PS 160 mhz bus-controlled monitor video preamplifier
2001 oct 19 2 philips semiconductors product speci?cation 160 mhz bus-controlled monitor video preampli?er TDA4887PS contents 1 features 2 general description 3 ordering information 4 quick reference data 5 block diagram 6 pinning 7 functional description 7.1 signal input stage 7.2 electronic potentiometer stages 7.3 output stage 7.4 pedestal blanking 7.5 output clamping and feedback references 7.6 clamping and blanking pulses 7.7 on screen display insertion and osd contrast 7.8 subcontrast adjustment, contrast modulation and beam current limiting 7.9 i 2 c-bus control 7.10 i 2 c-bus data buffer 8 limiting values 9 thermal characteristics 10 characteristics 11 i 2 c-bus protocol 12 test and application information 12.1 test board 12.2 application board with monolithic post amplifier 12.3 building the application board 12.4 application hints 13 internal circuitry 14 package outline 15 soldering 15.1 introduction to soldering through-hole mount packages 15.2 soldering by dipping or by solder wave 15.3 manual soldering 15.4 suitability of through-hole mount ic packages for dipping and wave soldering methods 16 data sheet status 17 definitions 18 disclaimers 19 purchase of philips i 2 c components
2001 oct 19 3 philips semiconductors product speci?cation 160 mhz bus-controlled monitor video preampli?er TDA4887PS 1 features 160 mhz pixel rate 2.7 ns rise time, 3.6 ns fall time i 2 c-bus control i 2 c-bus data buffer for synchronization of adjustments 8-bit digital-to-analog converters (dacs) 200 ns input clamping pulse 4.6 v (p-p) output signal brightness control with grey scale tracking for user-friendly performance (4 db more than tda4885 and tda4886) brightness control without grey scale tracking for easy alignment on screen display (osd) mixing with 50 mhz pixel rate osd contrast negative feedback for dc-coupled cathodes especially for ac-coupled cathodes C bus controlled black level adaptable to post amplifier type C internal positive feedback C dac outputs for black level restoration integrated black level storage capacitors beam current limiting subcontrast/contrast modulation adjustable pedestal blanking sync clipping. 2 general description the TDA4887PS is a monolithic integrated rgb preamplifier for colour monitor systems (e.g. 15" and 17") with i 2 c-bus control and osd. in addition to bus control, beam current limiting and contrast modulation are possible. the ic offers brightness control with or without grey scale tracking for easy alignment. the signals are amplified to drive commonly used video modules or discrete solutions. a choice can be made between individual black level control with negative feedback from the cathode (dc coupling), or black level control with positive feedback and three dac outputs for external cut-off control (ac coupling). the circuit can be used with special advantages in conjunction with the tda485x monitor deflection ic family. 3 ordering information type number package name description version TDA4887PS sdip24 plastic shrink dual in-line package; 24 leads (400 mil) sot234-1
2001 oct 19 4 philips semiconductors product speci?cation 160 mhz bus-controlled monitor video preampli?er TDA4887PS 4 quick reference data symbol parameter conditions min. typ. max. unit v p supply voltage (pin 7) 7.6 8.0 8.8 v i p supply current (pin 7) - 25 30 ma v p(n) supply voltage; channels 1, 2 and 3 (pins 21, 18 and 15) 7.6 8.0 8.8 v i p(n) supply current; channels 1, 2 and 3 (pins 21, 18 and 15) - 20 25 ma v i(n)(b-w) input voltage; channels 1, 2 and 3 (pins 6, 8 and 10) (black-to-white value) - 0.7 1.0 v v o(n)(b-w)(max) maximum output voltage swing (black-to-white value); channels 1, 2 and 3 (pins 22, 19 and 16) maximum contrast; maximum gain; v i(n)(b-w) = 0.7 v; r l =2k w 4.2 4.6 4.9 v v o(n) output voltage level (pins 22, 19 and 16) 0.1 - v p(n) - 1v i o(n)(source)(m) peak output source current (pins 22, 19 and 16) during fast positive signal transients - 40 -- ma i o(n)(sink)(m) peak output sink current (pins 22, 19 and 16) during fast negative signal transients -- 20 ma v bl(n)(ref) black level reference voltage (pins 22, 19 and 16) typical values dc coupling control bit fpol = 0 0.5 - 2.0 v ac coupling control bit fpol = 1; no pedestal blanking 0.53 - 1.89 v t r(n) rise time of fast transients at signal outputs (pins 22, 19 and 16) - 2.7 - ns t f(n) fall time of fast transients at signal outputs (pins 22, 19 and 16) - 3.6 - ns d v o(n) overshoot/undershoot at signal outputs (pins 22, 19 and 16) input rise/fall times = 1 ns; maximum colour signal -- 10 % a ct(f) crosstalk suppression by frequency f = 50 mhz 25 -- db d c contrast control: colour signal related to maximum colour signal - 45 - 0db d g track tracking of output colour signals of channels 1, 2 and 3 contrast control from maximum to minimum - 0 0.5 db d g gain control related to maximum gain - 13.5 - 0db d v bl(n) brightness control (difference between video black level and reference black level at signal outputs related to maximum colour signal) control bit bri = 0 - 10 - +33 % d v da(n) brightness control range (dac output voltages for ac coupling or internal feedback reference voltage for dc coupling) from maximum to minimum; control bit bri=1 - 1.4 - 0v
2001 oct 19 5 philips semiconductors product speci?cation 160 mhz bus-controlled monitor video preampli?er TDA4887PS v fb/rn dac output voltage range without brightness control (for black level restoration) (pins 23, 20 and 17) control bit fpol = 1; control bit bri = 0 3.95 - 5.75 v v osdn(max) maximum osd colour signal related to maximum colour signal (pins 22, 19 and 16) maximum osd contrast; maximum gain - 96 - % d oc osd colour signal related to maximum osd colour signal osd contrast control from maximum to minimum - 12 - 0db symbol parameter conditions min. typ. max. unit
2001 oct 19 6 philips semiconductors product speci?cation 160 mhz bus-controlled monitor video preampli?er TDA4887PS this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... 5 block diagram b ook, full pagewidth mhb943 input clamping blanking input clamping blanking input clamping blanking contrast lim v i2 v i3 diso disv fpol bri contrast contrast register i 2 c-bus 12 13 sda scl 24 v i1 6 8 10 subcontrast contrast modulation limiting osd contrast osd contrast osd contrast 4 8-bit dac 4-bit dac 8 4 8 8 8 8 diso 1234 fbl osd 1 osd 2 osd 3 fast blanking osd input input clamping channel 1 reference brightness switch ac black level brightness gain gain gain brightness brightness brightness blanking 8-bit dac 8-bit dac 8-bit dac 8-bit dac 2 2-bit dac 3 8 8 3-bit dac 8-bit dac 8-bit dac 8 8-bit dac 79 gnd supply v p 511 input clamping vertical blanking blanking output clamping pedestal blanking pedestal blanking pedestal blanking hfb cli disv fb/r 3 v p3 v o3 gndx 15 16 14 17 fb/r 2 v p2 v o2 18 19 20 fpol bri fpol fb/r 1 v p1 v o1 21 22 23 blanking blanking output clamping TDA4887PS channel 2 reference fpol fpol channel 3 reference fpol fpol fig.1 block diagram.
2001 oct 19 7 philips semiconductors product speci?cation 160 mhz bus-controlled monitor video preampli?er TDA4887PS 6 pinning symbol pin description fbl 1 fast blanking input for osd insertion osd 1 2 osd input, channel 1 osd 2 3 osd input, channel 2 osd 3 4 osd input, channel 3 cli 5 input clamping and vertical blanking input v i1 6 signal input, channel 1 v p 7 supply voltage v i2 8 signal input, channel 2 gnd 9 ground v i3 10 signal input, channel 3 hfb 11 output clamping and blanking input sda 12 i 2 c-bus serial data input/output scl 13 i 2 c-bus clock input gndx 14 ground signal, channels 1, 2 and 3 v p3 15 supply voltage, channel 3 v o3 16 signal output, channel 3 fb/r 3 17 feedback input/reference voltage output channel 3 v p2 18 supply voltage, channel 2 v o2 19 signal output, channel 2 fb/r 2 20 feedback input/reference voltage output, channel 2 v p1 21 supply voltage, channel 1 v o1 22 signal output, channel 1 fb/r 1 23 feedback input/reference voltage output, channel 1 lim 24 subcontrast adjustment, contrast modulation and beam current limiting input handbook, halfpage fbl osd 1 osd 2 osd 3 cli v i1 v p v i2 gnd v i3 hfb sda lim fb/r 1 v o1 v p1 v o2 v p2 fb/r 2 fb/r 3 v o3 v p3 gndx scl mhb919 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 TDA4887PS fig.2 pin configuration.
2001 oct 19 8 philips semiconductors product speci?cation 160 mhz bus-controlled monitor video preampli?er TDA4887PS 7 functional description refer also to block diagram (fig.1) and definitions of levels and signals (chapter 10). 7.1 signal input stage the rgb input signals are capacitively coupled into the TDA4887PS from a low-ohmic source (75 w recommended) and actively clamped to the internal reference black level during signal black level. the signal amplitude is 0.7v i(b-w) and should not exceed 1 v. the high-ohmic input impedance of the TDA4887PS allows the coupling capacitor to be relatively small (10 nf recommended). the coupling capacitor also functions as a storage capacitor between clamping pulses. very small input currents will discharge the coupling capacitor resulting in black output signals for missing input clamping pulses. composite signals will not disturb normal operation because a clipping circuit cuts all signal parts below black level. a fast signal blanking circuit included in the input stage is driven by several blanking pulses (see section 7.6) and control bit disv = 1. during the off condition the internal reference black level is inserted instead of the input signals. 7.2 electronic potentiometer stages 7.2.1 c ontrast control the contrast control is driven by an 8-bit dac via the i 2 c-bus. the input signals related to the internal reference black level can be adjusted simultaneously by contrast control with a control range of 32 db (typical). the nominal setting is for maximum contrast. 7.2.2 b rightness control 7.2.2.1 brightness control with grey scale tracking the brightness control is driven by an 8-bit dac via the i 2 c-bus; brightness control with grey scale tracking is selected when control bit bri = 0. with brightness control, the video black level is shifted in relation to the reference black level simultaneously for all three channels. with a negative setting (up to 10% of the maximum signal amplitude) dark signal parts will be lost in ultra black; for positive settings (up to 33% of the maximum signal amplitude) the background will alter from black to grey. at nominal brightness setting (40h) there is no shift. the brightness setting is also valid for osd signals. during blanking and output clamping the video black level will be blanked to the reference black level (brightness blanking). the brightness information is inserted before the gain potentiometers, background colour temperature will not change with brightness setting (grey scale tracking). 7.2.2.2 brightness control without grey scale tracking brightness control without grey scale tracking is selected when control bit bri = 1. the brightness information will be mixed with the dac outputs for external black level restoration (fpol = 1, ac-coupled cathodes) or internal feedback reference voltages (fpol = 0, dc-coupled cathodes). this allows a simple bus-controlled brightness setting without grey scale tracking. with ac-coupled cathodes this is equivalent to brightness control via grid g1. 7.2.3 g ain control and grey scale tracking the gain control is driven by an 8-bit dac via the i 2 c-bus. gain control is used for white point adjustment (correction for different voltage-to-light amplification of the three colour channels) and therefore individually for r, g and b. the video signals related to the reference black level can be gain-controlled within a range of 14 db (typical). this range is large enough to accommodate the maximum output amplitude for different applications. the nominal setting is maximum gain. the gain setting is also valid for osd signals and brightness shift (bri = 0), therefore the complete grey scale is effected by gain control. 7.3 output stage in the output stage the nominal input signal will be amplified to provide a 4.6 v (typical) output colour signal at maximum contrast and maximum gain settings. reference or pedestal black levels are adjusted by output clamping. in order to achieve fast rise and fall times of the output signals with minimum crosstalk between the channels, each signal stage has its own supply voltage pin.
2001 oct 19 9 philips semiconductors product speci?cation 160 mhz bus-controlled monitor video preampli?er TDA4887PS 7.4 pedestal blanking the pedestal blanking is driven by a 2-bit dac via the i 2 c-bus. pedestal blanking inserts a negative output level related to the reference black level (should always correspond to the extended cut-off voltage at the cathode) during blanking and output clamping. in this way retrace lines during vertical flyback are suppressed (blanking to spot cut-off). the depth of pedestal blanking (voltage difference between reference black level and pedestal black level) is bus-controlled (2 bits, 0 to 13.5% of the maximum colour signal) and does not change with any other control or adjustment. the pedestal blanking level is used for output clamping instead of the reference black level (see section 7.5). if the pedestal blanking level is the most negative output signal and if the application is for ac-coupled cathodes, a very simple black level restoration with a dc diode clamp can be used. 7.5 output clamping and feedback references the aim of the output clamping is to set the reference black level of the signal outputs to a value which corresponds to the extended cut-off voltage of the crt cathodes. with missing output clamping pulses the integrated storage capacitors will be discharged resulting in output signals going to switch-off voltage. if using pedestal blanking, the pedestal black level will be controlled by output clamping (see fig.5). it is therefore not allowed to change the pedestal depth after black level adjustment of the monitor. feedback references are driven via the i 2 c-bus and controlled by an 8-bit dac for dc feedback references or by a 3-bit dac for ac feedback references: 1. dc-coupled cathodes (control bit fpol = 0) the cathode voltage is divided by a voltage divider and fed back to the ic (pins fb/r 1 , fb/r 2 and fb/r 3 ). during the output clamping pulse it is compared with a bus-controlled feedback reference voltage with a range of approximately 5.75 to 3.95 v. any difference will lead to a reference black level correction (subaddress 0bh = 00h) or pedestal black level correction (subaddress 0bh 1 00h) by charging or discharging the integrated capacitors that store the black level information between the output clamping pulses. the dc voltages of the output stages should be designed in such a way that the reference black level/pedestal black level is within the range of 0.5 to 2.4 v at the preamplifier output. for correct operation it is necessary that there is enough headroom for ultra black signals (negative brightness setting and pedestal blanking). any clipping with the video supply voltage at the cathode can disturb the signal rise/fall times or the black level stabilization. after power-on, the control bit fpol is set to logic 1 and all alignment registers are set to logic 0 resulting in the reference black level at its lowest level (0.53 v) with no output signal. normal operation starts after all data registers have been refreshed via the i 2 c-bus. brightness control with grey scale tracking (control bit bri = 0) can be used as well as brightness control without grey scale tracking (control bit bri = 1) using the mixing function of bus-controlled brightness offset (0 to - 1.4 v) to feedback reference voltages (see section 7.2). 2. ac-coupled cathodes (control bit fpol = 1) for applications with ac-coupled cathodes the signal outputs are fed back internally. during the output clamping pulse they are compared with a bus controlled feedback reference voltage (0.5 to 1.9 v). these values ensure a good adaptability to both discrete and integrated post amplifiers. for black level restoration, the dac outputs (fb/r 1 , fb/r 2 and fb/r 3 ) with a range of approximately 3.95 to 5.75 v can be used. pedestal blanking is recommended because it allows use of a simple restoration circuit. after power-on, the dac outputs will be at maximum output voltage (register value logic 0), so when using a non-inverting amplifier for the reference voltages the monitor will start with black. brightness control with grey scale tracking (control bit bri = 0) can be used as well as simple brightness control without grey scale tracking (control bit bri = 1) using the mixing function of bus controlled brightness offset (0 to - 1.4 v) to dac output voltages (see section 7.2).
2001 oct 19 10 philips semiconductors product speci?cation 160 mhz bus-controlled monitor video preampli?er TDA4887PS 7.6 clamping and blanking pulses there are two pins for clamping and blanking purposes (pins cli and hfb): 1. pin cli (input clamping, vertical blanking) the pin cli of TDA4887PS can be connected directly to pin clbl of e.g. tda4855 sync processor for input clamping pulses and vertical blanking pulses. input clamping pulses and blanking pulses are completely separated from the sandcastle input, that means there is normally (outside detected vertical blanking) no blanking during input clamping and the clamping pulse is not suppressed during vertical blanking. the input pulse is scanned with two thresholds: a) 1.4 v (typical) for vertical blanking b) 3 v (typical) for input clamping. in order to separate the vertical blanking pulse from the sandcastle pulse it is necessary that the input clamping pulse has rise/fall times faster than 75 ns/v during the transition from 1.2 to 3.5 v and vice versa. the leading edge of the internal vertical blanking pulse is delayed by typically 270 ns (after the end of an input clamping pulse or the beginning of a separate blanking pulse), the trailing edge is delayed by typically 115 ns. during the vertical blanking pulse signal blanking, brightness blanking and pedestal blanking will be activated. in buffered mode, the leading edge of the internal vertical blanking pulse is used to synchronize data transmitted via the i 2 c-bus (see section 7.10.1). for correct input clamping the input signals have to be at black level during the input clamping pulse. 2. pin hfb (output clamping and blanking) the input pulse (e.g. horizontal flyback pulse) is scanned with two thresholds. if the input pulse exceeds the first threshold (typically 1.4 v) signal blanking, brightness blanking and pedestal blanking will be activated. if the input pulse exceeds the second threshold (typically 3 v) output clamping will be activated additionally. especially for applications with dc-coupled cathodes (fpol = 0), it is useful that the leading edge of the (internal) clamping pulse is slightly delayed with respect to the leading edge of the (internal) blanking pulse in order to avoid initial misclamping due to the delay of the feedback signal from the cathodes. 7.7 on screen display insertion and osd contrast on screen display (osd) insertion and osd contrast are controlled by a 4-bit dac driven via the i 2 c-bus. if the fast blanking input signal at pin fbl exceeds the threshold (typically 1.4 v) the input signals are blanked (signal blanking) and osd signals are enabled. then, any signal at pins osd 1 , osd 2 or osd 3 exceeding the same threshold will create an insertion signal with an amplitude of 100% of the maximum colour signal. the amplitude can be controlled by osd contrast (driven via the i 2 c-bus) with a range of 12 db. the osd signals are inserted at the same point as the contrast-controlled input signals and will be treated with brightness and gain control as with normal input signals. identical pulses at osd signal input pins and fbl have to be handled very carefully. each difference in pulse delay at the inputs will produce glitches at pulse edges at signal outputs. when control bit diso = 1 the osd signal insertion and fast blanking (pin fbl) are disabled. 7.8 subcontrast adjustment, contrast modulation and beam current limiting the pin lim is a linear contrast control pin which allows subcontrast setting, contrast modulation and beam current limiting. the maximum contrast is defined by the actual i 2 c-bus setting. input signals at pin lim act on video and osd signals and do not affect the contrast bit resolution. if the pin is not used it should be decoupled with a capacitor or tied to the supply voltage. 7.8.1 b eam current limiting the open-circuit voltage is approximately 5 v, contrast reduction starts at input voltages <4.4 v (typical) and signal amplification will be reduced with descending input voltages. the input resistance of pin lim is very high to make it possible to choose a time constant sufficient for the open-circuit voltage to recover through the application. 7.8.2 s ubcontrast in order to fit the maximum signal amplification to the post amplifier gain, an input voltage of <4.4 v can be used. 7.8.3 c ontrast modulation to achieve brightness uniformity over the screen, scan dependent contrast modulation is possible. the nominal input voltage should be <4.4 v having enough margin for positive and negative modulation.
2001 oct 19 11 philips semiconductors product speci?cation 160 mhz bus-controlled monitor video preampli?er TDA4887PS 7.9 i 2 c-bus control the TDA4887PS contains an i 2 c-bus receiver for several control functions: contrast register with control bits bri, fpol, disv and diso brightness control with 8-bit dac contrast control with 8-bit dac osd contrast control with 4-bit dac gain control for each channel with 8-bit dac internal feedback reference and external reference voltage control for each channel with 8-bit dac black level for ac coupling with 3-bit dac depth of pedestal blanking with 2-bit dac. after power-up and after internal power-on reset of the i 2 c-bus, the registers are set to the following values (for most applications these settings guarantee a black screen after power-up): control bit fpol set to logic 1 control bits bri, disv and diso set to logic 0 all other alignment registers set to logic 0 (minimum value for control registers). after an intermediate power dip, all registers are set to their initial values and an internal power-on reset bit will be set with the consequence that the device will give no acknowledge on the data byte after being first addressed. the power-on reset bit will be reset if the control register is addressed. it is recommended to then refresh all registers by using the auto-increment function. 7.10 i 2 c-bus data buffer 7.10.1 b uffered mode adjustments via the i 2 c-bus are synchronized with vertical blanking pulse at cli: most significant bit (msb) of subaddress is set to logic 1 only one i 2 c-bus transmission in buffered mode is accepted before the start of the vertical blanking pulse; following transmissions receive no acknowledge received data is stored in one internal 8-bit buffer adjustments will take effect with detection of the first vertical blanking pulse after the end of the acknowledged i 2 c-bus transmission waiting for vertical blanking pulse in buffered mode can be interrupted by power-on reset auto-increment is not possible buffered mode should be used for user adjustments such as contrast, osd contrast and brightness when a picture is visible on the monitor. 7.10.2 d irect mode adjustments via the i 2 c-bus take effect immediately: most significant bit (msb) of subaddress is set to logic 0 number of i 2 c-bus transmissions in direct mode is unlimited adjustments take effect directly at the end of each i 2 c-bus transmission direct mode can be used for all adjustments but large changes of control values may appear as visual disturbances in the picture on the monitor auto-increment is possible vertical blanking pulse is not necessary.
2001 oct 19 12 philips semiconductors product speci?cation 160 mhz bus-controlled monitor video preampli?er TDA4887PS 8 limiting values in accordance with the absolute maximum rating system (iec 60134). notes 1. no external voltages. 2. equivalent to discharging a 200 pf capacitor via a 0.75 m h inductance ( snw-fq-302b ). 3. equivalent to discharging a 100 pf capacitor via a 1500 w series resistor ( snw-fq-302a ). 9 thermal characteristics symbol parameter conditions min. max. unit v p supply voltage (pin 7) 0 8.8 v v p(n) supply voltage; channels 1, 2 and 3 (pins 21, 18 and 15) 0 8.8 v v i(n) input voltage; channels 1, 2 and 3 (pins 6, 8 and 10) - 0.1 v p v v ext external dc voltage applied to pins 1 to 4 - 0.1 v p v pins 5 and 11 - 0.1 v p + 0.7 v pins 12 and 13 - 0.1 v p v pins 23, 20 and 17 - 0.1 v p + 0.7 v pins 22, 19 and 16 note 1 note 1 pin 24 - 0.1 v p v i o(n)(av) average output current; channels 1, 2 and 3 (pins 22, 19 and 16) - 20 ma i o(n)(m) peak output current channels 1, 2 and 3 (pins 22, 19 and 16) - 50 ma p tot total power dissipation - 1400 mw t stg storage temperature - 25 +150 c t amb ambient temperature - 20 +70 c t j junction temperature - 25 +150 c v esd electrostatic handling voltage for all pins machine model note 2 - 250 +250 v human body model note 3 - 3000 +3000 v symbol parameter conditions value unit r th(j-a) thermal resistance from junction to ambient in free air 55 k/w r th(j-c) thermal resistance from junction to case 5 k/w
2001 oct 19 13 philips semiconductors product speci?cation 160 mhz bus-controlled monitor video preampli?er TDA4887PS 10 characteristics all voltages and currents are measured in a dedicated test circuit (see fig.17) optimized for best high frequency performance; all voltages are measured with respect to gnd (pins 9 and 14); v p =v p1,2,3 = 8 v (pins 7, 21, 18 and 15); t amb =25 c; nominal input signals [0.7 v (p-p) at pins 6, 8 and 10]; maximum colour signals at signal outputs (pins 22, 19 and 16); reference black level (v bl(ref) ) approximately 0.7 v; nominal setting for brightness; maximum settings for osd contrast, contrast and gain; no subcontrast, modulation of contrast or limiting (v lim 3 5 v); no osd fast blanking (pin 1 connected to ground); notes 1 to 3; unless otherwise speci?ed. symbol parameter conditions min. typ. max. unit supplies v p supply voltage (pin 7) 7.6 8.0 8.8 v v p(so) supply voltage threshold at pin 7 at which signal outputs are switched off note 1 6.8 7.0 7.2 v i p supply current (pin 7) note 4 - 25 30 ma v p(n) supply voltage; channels 1, 2 and 3 (pins 21, 18 and 15) 7.6 8.0 8.8 v i p(n) supply current; channels 1, 2 and 3 (pins 21, 18 and 15) pins 22, 19 and 16 open-circuit; v bl(n)(ref) = 0.7 v; notes 4 and 5 - 20 25 ma input clamping and vertical blanking input, validation of buffered i 2 c-bus data (cli; pin 5) v cli input clamping and vertical blanking input signal notes 6 and 7 no vertical blanking, no input clamping - 0.1 - +1.2 v vertical blanking, no input clamping 1.6 - 2.6 v input clamping, no vertical blanking 3.5 - v p v i cli input current v cli =1v -- 0.2 -m a pin 5 connected to ground; note 8 - 80 - 45 - 30 m a v cli = - 0.1 v; note 8 - 250 - 135 - 100 m a t r/f5 rise/fall time for input clamping pulse; disable for vertical blanking note 6; see fig.7 -- 75 ns/v t w(cli) width of input clamping pulse 200 -- ns t w(i2c)(valid) width of vertical blanking pulse for validation of buffered i 2 c-bus data leading and trailing edge threshold v cli = 1.4 v; note 7 10 -- m s t d(i2c)(valid) delay between leading edge of vertical blanking pulse and validation of buffered i 2 c-bus data i 2 c-bus buffered mode transmission completed; leading edge threshold v cli = 1.4 v; note 7; see fig.7 -- 2 m s
2001 oct 19 14 philips semiconductors product speci?cation 160 mhz bus-controlled monitor video preampli?er TDA4887PS t dead(i2c) i 2 c-bus receiver dead time after synchronizing vertical blanking pulse following a completed i 2 c-bus buffered mode transmission leading edge threshold v cli = 1.4 v; note 7 15 -- m s t dl5 delay between leading edges of vertical blanking input pulse and signal blanking at signal outputs v hfb < 0.8 v; input pulse rising and falling edges = 50 ns/v; threshold for vertical blanking with rising edge v cli = 1.4 v; threshold for vertical blanking with falling edge v cli =3v; see fig.7 - 270 - ns t dt5 delay between trailing edges of vertical blanking input pulse and signal blanking at signal outputs v hfb < 0.8 v; input pulse falling edge = 50 ns/v; threshold v cli = 1.4 v; see fig.7 - 115 - ns output clamping and blanking input (hfb; pin 11) v hfb output clamping and blanking input signal note 9 no blanking, no output clamping - 0.1 - +0.8 v blanking, no output clamping 2 - 2.6 v blanking, output clamping 3.5 - v p v i hfb input current v hfb = 0.8 v -- 0.4 -m a pin 11 connected to ground; note 8 - 80 - 45 - 30 m a v hfb = - 0.1 v; note 8 - 250 - 135 - 100 m a t w(hfb) width of output clamping pulse v hfb =3v 1 -- m s video signal inputs; channels 1, 2 and 3 (pins 6, 8 and 10) v i(n)(b-w) input voltage; black-to-white value (pins 6, 8 and 10) - 0.7 1.0 v i i(n) dc input current (pins 6, 8 and 10) no input clamping; v i(n) =v i(n)(clamp) ; t amb = - 20 to +70 c 0.02 0.20 0.35 m a during input clamping; v i(n) =v i(n)(clamp) 0.7 v 350 420 500 m a signal blanking a ct(blank) crosstalk suppression from input to output during blanking control bit disv = 1; f = 80 mhz 20 -- db control bit disv = 1; f = 120 mhz 10 -- db symbol parameter conditions min. typ. max. unit
2001 oct 19 15 philips semiconductors product speci?cation 160 mhz bus-controlled monitor video preampli?er TDA4887PS clipping of negative input signals (measured at signal outputs) d v clipp offset during sync clipping related to maximum colour signal v i(n) =v i(n)(clamp) ; sync amplitude = 0.3 v; note 10; see fig.3 - 0.6 1.2 % contrast control; see fig.8 and note 11 d c colour signal related to maximum colour signal ffh (maximum) - 0 - db 00h (minimum) -- 45 - db d g track tracking of output colour signals of channels 1, 2 and 3 ffh to 40h; note 12 - 0 0.5 db fast blanking (pin 1) and osd signal insertion; channels 1, 2 and 3 (pins 2, 3 and 4); note 13 v fbl fast blanking input signal (pin 1) no video signal blanking; osd signal insertion disabled 0 - 1.1 v video signal blanking; osd signal insertion enabled 1.7 - v p v v osdn osd input signal (pins 2, 3 and 4) v fbl > 1.7 v no internal osd signal insertion 0 - 1.1 v internal osd signal insertion 1.7 - v p v t r(osdn) rise time of osd colour signals (pins 22, 19 and 16) 10 to 90% amplitude; pulse leading edge = 1.2 ns/v - 34 ns t f(osdn) fall time of osd colour signals (pins 22, 19 and 16) 90 to 10% amplitude; pulse falling edge = 1.2 ns/v - 47 ns t g(n)(co) width of (negative going) osd signal insertion glitch, leading edge (pins 22, 19 and 16) identical pulses at fast blanking input (pin 1) and osd signal inputs (pins 2, 3 and 4) 046ns t g(n)(oc) width of (negative going) osd signal insertion glitch, trailing edge (pins 22, 19 and 16) identical pulses at fast blanking input (pin 1) and osd signal inputs (pins 2, 3 and 4) 056ns d v osdn overshoot/undershoot of osd colour signal related to actual osd output pulse amplitude (pins 22, 19 and 16) pulse with 1.2 ns/v at osd signal inputs (pins 2, 3 and 4) - 610 % v osdn(max) maximum osd colour signal related to maximum colour signal (pins 22, 19 and 16) maximum osd contrast; maximum gain 90 96 110 % symbol parameter conditions min. typ. max. unit
2001 oct 19 16 philips semiconductors product speci?cation 160 mhz bus-controlled monitor video preampli?er TDA4887PS osd contrast control; see fig.9 and note 14 d oc osd colour signal related to maximum osd colour signal 0fh (maximum) - 0 - db 00h (minimum) - 14 - 12 - 10 db subcontrast adjustment, contrast modulation and beam current limiting (pin 24); see fig.8 and note 15 v lim(nom) nominal input voltage pin 24 open-circuit 4.7 5.0 5.3 v v lim(start) starting voltage for linear contrast and osd contrast reduction 4.2 4.4 4.8 v v lim(stop) stop voltage for linear contrast and osd contrast reduction - 40 db below maximum colour signal (contrast setting ffh) 1.5 2.0 2.5 v b lim bandwidth of contrast modulation - 3db 4 -- mhz i lim(max) maximum input current v lim =0v - 1 - +1 m a brightness control; see figs 10, 12 and 14 and notes 16 and 17 d v bl(n) difference between video black level and reference black level at signal outputs related to maximum colour signal ffh (maximum); bri = 0 28 33 38 % 40h (nominal); bri = 0 - 2 0 +2 % 00h (minimum); bri = 0 - 12 - 10 - 8% d v da(n) dac output voltage shift (pins 23, 20 and 17) fpol = 1, see dac output voltages for ac coupling or feedback reference voltage shift; fpol = 0, see internal feedback reference voltage for dc coupling ffh (maximum); bri = 1 -- 1.4 - v 00h (minimum); bri = 1 - 0 - v gain control; see fig.11 and note 18 d g video signal related to video signal at maximum gain ffh (maximum) - 0 - db 00h (minimum) - 15 - 13.5 - 12.5 db pedestal blanking; see fig.5 and note 19 d v bl(n)(ped-vid) difference between pedestal black level and video black level at nominal brightness, measured at signal outputs (pins 22, 19 and 16) related to maximum colour signal 03h (maximum) - 12 - 13.5 - % 02h - 8 - 9 - % 01h - 4 - 4.5 - % 00h (minimum) - 0 - % symbol parameter conditions min. typ. max. unit
2001 oct 19 17 philips semiconductors product speci?cation 160 mhz bus-controlled monitor video preampli?er TDA4887PS signal outputs; channels 1, 2 and 3 (pins 22; 19 and 16) v o(n)(min) minimum output voltage level (pins 22, 19 and 16) 0.01 0.05 0.1 v v o(n)(max) maximum output voltage level (pins 22, 19 and 16) arbitrary input signals, contrast, brightness and gain adjustments; without load v p(n) - 2 - v p(n) - 1v i o(n)(source)(max) maximum output source current (pins 22, 19 and 16) - 15 -- ma r o(n) output resistance (pins 22, 19 and 16) 65 75 90 w v o(n)(b-w)(max) maximum output voltage swing (black-to-white value); channels 1, 2 and 3 (pins 22, 19 and 16) maximum contrast; maximum gain; v i(n)(b-w) = 0.7 v; r l =2k w 4.2 4.6 4.9 v i o(n)(source)(m) peak output source current (pins 22, 19 and 16) during fast positive signal transients - 40 -- ma i o(n)(sink)(m) peak output sink current (pins 22, 19 and 16) during fast negative signal transients -- 20 ma s/n signal-to-noise ratio note 20 48 -- db frequency response at signal outputs; channels 1, 2 and 3 (pins 22, 19 and 16) t r(n) rise time of fast transients (pins 22, 19 and 16) input rise tim e=1ns; 10 to 90% amplitude; r l =10k w ; notes 21, 22 and 23; 2.8 v (p-p) signal amplitude; c l =5pf - 2.7 3.8 ns 4.5 v (p-p) signal amplitude; c l =5pf - 3.2 4.2 ns 4.5 v (p-p) signal amplitude; c l =11pf - 3.8 4.5 ns t f(n) fall time of fast transients (pins 22, 19 and 16) input fall time = 1 ns; 90 to 10% amplitude; r l =10k w ; notes 21, 22 and 23; 2.8 v (p-p) signal amplitude; c l =5pf - 3.6 4.5 ns 4.5 v (p-p) signal amplitude; c l =5pf - 3.6 4.5 ns 4.5 v (p-p) signal amplitude; c l =11pf - 56 ns symbol parameter conditions min. typ. max. unit
2001 oct 19 18 philips semiconductors product speci?cation 160 mhz bus-controlled monitor video preampli?er TDA4887PS d v o(n) overshoot of output signal pulse related to actual output pulse amplitude (pins 22, 19 and 16) input rise tim e=1ns; maximum colour signal -- 10 % undershoot of output signal pulse related to actual output pulse amplitude (pins 22, 19 and 16) input fall time = 1 ns; maximum colour signal -- 10 % crosstalk at signal outputs; channels 1, 2 and 3 (pins 22, 19 and 16) a ct(tr)(n) transient crosstalk suppression (pins 22, 19 and 16) input rise/fall time = 1 ns; note 24 10 -- db a ct(f) crosstalk suppression by frequency f = 50 mhz; note 25 25 -- db f = 100 mhz; note 25 10 -- db internal feedback reference voltage for dc coupling; see fig.12 and note 26 v ref(dc) internal reference voltage for negative feedback polarity (without brightness control) ffh; fpol = 0; bri = 0 3.7 3.95 4.1 v 00h; fpol = 0; bri = 0 5.6 5.75 5.9 v internal reference voltage for negative feedback polarity (with brightness control, see also brightness control d v da(n) ) ffh; fpol = 0; bri = 1; maximum brightness 2.3 2.55 2.7 v 00h; fpol = 0; bri = 1; minimum brightness 5.6 5.75 5.9 v output clamping, feedback inputs for dc coupling; fb/r 1 , fb/r 2 and fb/r 3 (pins 23, 20 and 17) i fb/rn(max) maximum input current (pins 23, 20 and 17) during output clamping; v hfb > 3.5 v; v fb/rn = 0.5 v; fpol = 0 - 500 - 200 - 60 na v bl(n)(ref)(min) minimum reference black level/minimum pedestal black level (pins 22, 19 and 16) v hfb > 3.5 v; fpol = 0 0.01 0.1 0.5 v v bl(n)(ref)(max) maximum reference black level/maximum pedestal black level (pins 22, 19 and 16) v hfb > 3.5 v; fpol = 0 2.0 2.8 4.0 v d v bl(crt) black level variation at crt fpol = 0; note 27 -- 200 mv d v bl(n)(lf) black level decrease between clamping pulses related to maximum colour signal (pins 22, 19 and 16) fpol = 0; f line = 60 khz; d = 10% - 0.1 - % symbol parameter conditions min. typ. max. unit
2001 oct 19 19 philips semiconductors product speci?cation 160 mhz bus-controlled monitor video preampli?er TDA4887PS output clamping; internal feedback (of signal outputs) reference voltage for ac coupling; see fig.13 and note 28 v bl(n)(ref) reference black level voltage/pedestal black level voltage (pins 22, 19 and 16) v hfb > 3.5 v; fpol = 1 00h (minimum) 0.47 0.53 0.59 v 0fh (maximum) 1.83 1.89 1.95 v dac output voltages for ac coupling; fb/r 1 , fb/r 2 and fb/r 3 (pins 23, 20 and 17); see fig.14 and note 29 v fb/rn dac output voltage (without brightness control) ffh; fpol = 1; bri = 0 3.7 3.95 4.1 v 00h; fpol = 1; bri = 0 5.6 5.75 5.9 v dac output voltage (with brightness control, see also brightness control d v da(n) ) ffh; fpol = 1; bri = 1; maximum brightness 2.3 2.55 2.7 v 00h; fpol = 1; bri = 1; minimum brightness 5.6 5.75 5.9 v r fb/rn output resistance fpol = 1 - 100 -w i fb/rn(sink)(max) maximum sink current fpol = 1 -- 400 m a i fb/rn(source)(max) maximum source current fpol = 1 -- 200 -m a i 2 c-bus inputs; sda (pin 12), scl (pin 13); note 30 f scl scl clock frequency -- 100 khz v il low-level input voltage 0 - 1.5 v v ih high-level input voltage 3 - 5v i il low-level input current v il =0v - 10 -- m a i ih high-level input current v ih =5v - 10 -- m a v ol low-level output voltage during acknowledge 0 - 0.4 v i sda(ack) sda output current (pin 12) during acknowledge v ol = 0.4 v 3 -- ma v ol = 0.6 v 6 -- ma t o(f) output fall time v sda = 3 to 1.5 v; bus capacitance c sda = 400 pf -- 250 ns v th(por)(r) threshold for power-on reset on rising supply voltage - 1.5 2.0 v falling supply voltage - 3.5 - v v th(por)(f) threshold for power-on reset off rising supply voltage -- 7v falling supply voltage - 1.5 - v symbol parameter conditions min. typ. max. unit
2001 oct 19 20 philips semiconductors product speci?cation 160 mhz bus-controlled monitor video preampli?er TDA4887PS notes to the characteristics 1. definition of levels (see figs 3 to 5) reference black level : this is the level to which the input level is clamped during the input clamping pulse (v cli > 3.5 v). it is used internally as a reference for the gain settings. it can be observed on the outputs: a) when the input is at black and the brightness setting is nominal (subaddress 01h = 40h) or control bit bri = 1 b) during output blanking and clamping (v hfb > 3.5 v) if the pedestal blanking depth is set to zero (subaddress 0bh = 00h). video black level : this is the black level of the actual video. at the input it is still equal to the reference black level. at the output it may deviate from it according to the brightness setting. contrast setting leaves the video black level unaltered . gain setting biases the video black level due to its influence on brightness. this is important for correct grey scale tracking. it can be observed at the outputs when the input is at black outside output blanking and clamping pulses (v hfb < 0.8 v). pedestal black level : this is an ultra black level which deviates from the reference black level by a bus controlled amount. it can be observed at the output during output blanking and clamping (v hfb > 3.5 v; subaddress 0bh 1 00h). switch-off voltage : this is the lowest signal voltage at outputs. the signals will be switched off by discharging the internal black level storage capacitors if the supply voltage is less than v p(so) . it can be observed at the outputs when the input is at black, the brightness setting is nominal and v p < 6.8 v (subaddress 01h = 40h). blanking level : this level equals reference black (subaddress 0bh 1= 00h) or pedestal black. it can be observed at the outputs during output blanking and clamping (v hfb > 3.5 v). 2. explanation to black level adjustment: the three reference black levels are aligned correctly when they are made equal to the extended cut-off levels of the three cathodes. full raster and spot cut-off can only be achieved by enabling the pedestal blanking or by applying a negative pulse to the grid g1. negative feedback for dc-coupled cathodes (control bit fpol = 0): the actual blanking level on the outputs depends on the external feedback application for output clamping. the loop will function correctly only if it is within the control range of v bl(n)(ref)(min) to v bl(n)(ref)(max) at pins 22, 19 and 16. it should be noted that changing pedestal blanking in a given application will not affect the blanking level, but instead shifts the video (and needs re-alignment of the three black levels). positive feedback for ac-coupled cathodes (control bit fpol = 1): the feedback loop for output clamping is closed internally. the actual blanking level is bus controlled between 0.53 and 1.89 v (subaddress 0ah). it should be noted that changing pedestal blanking will not affect the blanking level, but instead shifts the video (and re-alignment of the three black levels is needed). 3. definition of output signals (see fig.6): colour signal : all positive voltages are referenced to black level at signal outputs. maximum colour signal : colour signal with nominal input signal 0.7v i(b-w) , maximum contrast setting and maximum gain setting. video signal : all positive voltages referred to reference black level at signal outputs. the video signal is the superimposing of the brightness information ( d v bl ) and the colour signal. 4. the total supply current i p(tot) =i p +i p1 +i p2 +i p3 depends on the supply voltage with a factor of approximately 4.4 ma/v and varies in the temperature range from - 20 to +70 c by approximately 5% (v o(n) = 0.7 v). 5. the channel supply current i p1 ,i p2 ,i p3 depends on the signal output current i o1 ,i o2 ,i o3 , the channel supply voltage v p1 ,v p2 ,v p3 and the signal output voltage v o1 ,v o2 ,v o3 . with i px =i p(n) at i o(n) = 0, v p(n) = 8 v and v o(n) = 0.7 v: i p(n) i px i o(n) 4.4 ma/v v p(n) 8v C () 1 ma/v v o(n) 0.7 v C () C ++ ?
2001 oct 19 21 philips semiconductors product speci?cation 160 mhz bus-controlled monitor video preampli?er TDA4887PS 6. pin 5 should be used for input clamping and blanking during vertical retrace (signal blanking, brightness blanking and pedestal blanking). with a fast clamping pulse (transition between v cli = 1.2 to 3.5 v and 3.5 to 1.2 v in less than 75 ns/v) no blanking will occur during input clamping. for 75 ns/v < t r/f5 280 ns/v the generation of the internal blanking pulse is uncertain. for t r/f5 > 280 ns/v the internal blanking pulse will be generated. if pin 5 is open-circuit, it will activate permanent input clamping and undefined blanking. 7. pin 5 can be used to synchronize all adjustments via the i 2 c-bus (one by one). with a completed i 2 c-bus transmission in buffered mode, only the leading edge of a vertical blanking pulse activates an adjustment (see also section 7.10). after the adjustment has been activated (validation of buffered i 2 c-bus data) the i 2 c-bus will be reset and further transmissions in direct or buffered mode are enabled. i 2 c-bus transmissions in direct mode need no synchronization pulses. 8. input voltages less than - 0.1 v can produce internal substrate currents which disturb the leakage currents at the signal inputs. an internal protection circuit creates a current for pin voltages of approximately 0 v or with negative voltage. feeding clamping and blanking pulses via a resistor (several k w) protects the pin from negative voltages. 9. pin 11 should be used for output clamping and/or blanking. if pin 11 is open-circuit, it will activate permanent blanking and output clamping. 10. composite signals will not disturb normal operations because an internal clipping circuit cuts all signal parts below input reference black level (see fig.3). 11. contrast control acts on internal colour signals under i 2 c-bus control; subaddress 02h (bit resolution 0.4% of contrast range). 12. a n : colour signal output amplitude in channel n = 1, 2 or 3 at any contrast setting. a n0 : colour signal output amplitude in channel n = 1, 2 or 3 at maximum contrast setting and same gain setting. 13. when osd fast blanking is active and osd inputs osd 1 , osd 2 and osd 3 are high (v fbl > 1.7 v, v osd(n) > 1.7 v) the osd colour signals will be inserted in front of the gain potentiometers. this ensures a correct grey scale of all video signals. the amplitudes of the inserted osd signals can be controlled simultaneously by osd contrast via the i 2 c-bus. the inserted black level change ( d v bl ) due to brightness control is not affected by osd fast blanking. 14. osd contrast control acts on inserted osd colour signals under i 2 c-bus control; subaddress 03h (bit resolution 6.7% of osd contrast range). 15. this pin can be used for subcontrast adjustment, beam current limiting and contrast modulation. both the video and osd contrast are reduced simultaneously (see figs 8 and 9). because of the high-ohmic input impedance the pin should be tied to a voltage of more than 5 v or decoupled with a capacitor (several nf) if not used. 16. brightness control adds an i 2 c-bus controlled dc offset to the internal colour signal; subaddress 01h (bit resolution 0.4% of brightness range). when control bit bri = 1 the internal gain dependent brightness control is switched off and the feedback reference voltages (control bit fpol = 0) or dac output voltages for dc restoration (control bit fpol = 1) at the cathodes are shifted with brightness control. 17. the voltage difference between video black level and reference black level is related to the colour signal (see note 3) with nominal 0.7 v (p-p) input signal, at maximum contrast (subaddress 02h = ffh) and for any gain setting. this voltage difference (in volts) is proportional to the gain setting (grey scale tracking). therefore d v bl (in percent) is constant for any gain setting. the given values of d v bl are valid only for video black levels higher than the minimum output voltage level v o(n)(min) . d g track 20 maximum of a 1 a 10 -------- - a 20 a 2 -------- - ? ?? log a 1 a 10 -------- - a 30 a 3 -------- - ? ?? log a 2 a 20 -------- - a 30 a 3 -------- - ? ?? log ?t y db =
2001 oct 19 22 philips semiconductors product speci?cation 160 mhz bus-controlled monitor video preampli?er TDA4887PS 18. gain control acts on video signals and inserted osd video signals under i 2 c-bus control; subaddress 04h (channel 1), 05h (channel 2) and 06h (channel 3; bit resolution 0.4% of gain range respectively). 19. pedestal blanking produces an ultra black level during blanking and output clamping which is the most negative signal at the signal output pins. the pedestal depth can be selected by bus control, subaddress 0bh. the reference black level which should correspond to the extended cut-off voltage at the cathodes is approximately d v bl(n)(ped-vid) higher (see fig.5). the use of pedestal blanking with ac-coupled cathodes (control bit fpol = 1) allows a very simple black level restoration with a dc diode clamp instead of a complicated pulse restoration circuit. 20. the signal-to-noise ratio is calculated using the formula (range 1 to 120 mhz): 21. the following formula can be used to approximately determine the output rise/fall time for any input rise/fall time other than 1 ns: 22. the relationship between pixel rate and signal bandwidth is f - 3db = 0.75 f pixel , which is a compromise between excellent and acceptable video performance. the calculation of the pixel-related rise and fall times can be done using the formula . although this formula is valid for low-pass filters of first order only it is used in most cases for simplified estimations. the pixel rate is a good approximation for many filter types. 23. rise and fall times depend on signal amplitude, temperature, external load, black level and supply voltage. the rise time is affected if the top level of the signal pulse approaches the maximum output voltage level (high black level, large signal amplitude or low supply voltage). the fall time depends on the black level (increase with decreasing black level) and on large capacitive loads. low-ohmic pull-down loads at the outputs helps towards smaller fall times. rise and fall times increase with increasing ambient (or crystal) temperature. at maximum operating temperature, rise and fall times are approximately 0.4 ns longer than at t amb =25 c. 24. transient crosstalk between any two output pins: a) input conditions : any channel (channel a) with nominal input signal and 1 ns rise time. the inputs of the other two channels (channels b) are capacitively coupled to ground. gain setting at maximum (ffh). contrast setting at maximum (ffh). no limiting/modulation of contrast (v lim 3 4.8 v) b) output conditions : black level set to approximately 0.7 v for each channel at signal outputs. output signals are v a and v b respectively c) transient crosstalk suppression : 25. crosstalk by frequency between any two output pins: a) input conditions : any channel (channel a) with 0.2 v (p-p) sinusoidal input signal, dc-coupled to approximately 4.3 v, no input clamping. the inputs of the other two channels (channels b) are capacitively coupled to ground. gain setting at maximum (ffh). contrast setting at maximum (ffh). no limiting/modulation of contrast (v lim 3 4.8 v) b) output conditions : control bit fpol = 1, subaddress 0ah set to 01h, no pedestal blanking, nominal brightness setting. output signals are v a and v b respectively c) crosstalk suppression : s n --- - 20 peak-to-peak value of the maximum signal output voltage rms value of the noise output voltage ------------------------------------------------------------------------------------------------------------------------------- ------------------------ - db log = t r/f, measured 2 t r/f (22,19,16) 2 t r/f, input 2 1 ns [] 2 C () + = t r/f 0.35 f 3db C ----------- - 0.35 0.75 f pixel ---------------------------- - == f pixel 0.35 0.75 t r -------------------- - = a ct(tr) 20 v a v b ------ - db log = a ct(f) 20 v a v b ------ - db log =
2001 oct 19 23 philips semiconductors product speci?cation 160 mhz bus-controlled monitor video preampli?er TDA4887PS 26. control bit fpol = 0 : the internal feedback reference voltages for dc control act under i 2 c-bus control; subaddress 07h (channel 1), 08h (channel 2) and 09h (channel 3); bit resolution 0.4% of voltage range. rising values of the data bytes, e.g. 00h to ffh, correspond to rising values of the resulting reference black levels at signal outputs (pins 22, 19 and 16). the internal feedback reference voltages can be measured at feedback inputs (pins 23, 20 and 17) during output clamping (v hfb > 3.5 v) in closed feedback loop. the feedback loop remains operative at reference black levels between the specified values of v o(n)bl(ref)(min) and v o(n)bl(ref)(max) . control bit bri = 1 : the internal feedback reference voltages can be shifted under i 2 c-bus control which allows easy brightness control without grey scale tracking (see section 7.2.2.2); subaddress 01h (bit resolution 0.4% of voltage shift range). the superimposition of internal feedback reference and brightness control leads to a voltage output range of 5.8 to 2.5 v. 27. slow variations of video supply voltage v crt will be suppressed at the crt cathode by the clamping feedback loop. a change of v crt with 5 v leads to a specified change of the cathode voltage. 28. to adapt to different types of post amplifier, the internal feedback reference voltage for ac coupling (control bit fpol = 1) acts under i 2 c-bus control; subaddress 0ah (bit resolution 14.29%). the internal feedback reference voltage can be measured at signal outputs (pins 22, 19 and 16) during output clamping (v hfb > 3.5 v); reference black level or pedestal black level. 29. the dac output voltages act under i 2 c-bus control for control bit fpol = 1; subaddress 07h (fb/r 1 ), 08h (fb/r 2 ) and 09h (fb/r 3 ); bit resolution 0.4% of voltage range respectively. using an inverting amplifier for dc restoration, rising values of the data bytes, e.g. 00h to ffh, correspond to changing the light output from dark to bright. with control bit bri = 1 the dac output voltages can be shifted under i 2 c-bus control which allows easy brightness control without grey scale tracking (see section 7.2.2.2); subaddress 01h (bit resolution 0.4% of voltage shift range). the superimposition of black level control and brightness control leads to a voltage output range of 5.8 to 2.5 v. 30. all adjustments via the i 2 c-bus can be synchronized with vertical blanking pulse at pin cli. this is called i 2 c-bus transmission in buffered mode. conversely the adjustments via the i 2 c-bus will take effect immediately in direct mode. the timing of i 2 c-bus transmissions in buffered mode is related to the vertical blanking. see section 7.6 and note 7 for specification of vertical blanking input (pin 5).
2001 oct 19 24 philips semiconductors product speci?cation 160 mhz bus-controlled monitor video preampli?er TDA4887PS handbook, full pagewidth mha344 input video signal with sync pulses at pins 6, 8 and 10 input clamping pulses at pin 5 output clamping and blanking input pulses at pin 11 input reference black level the sync pulses are clipped to reference black level internally fig.3 definition of input signals. the input video signals have to be at black level during input clamping.
2001 oct 19 25 philips semiconductors product speci?cation 160 mhz bus-controlled monitor video preampli?er TDA4887PS handbook, full pagewidth signal outputs at pins 22, 19 and 16 maximum gain setting, maximum contrast setting, maximum/nominal/minimum brightness setting maximum gain setting, maximum brightness setting, maximum/minimum contrast setting maximum brightness setting, maximum contrast setting, maximum/minimum gain setting video black levels (maximum brightness) video black level (maximum brightness) reference black level mhb920 reference black level reference black level video black levels at maximum brightness nominal brightness minimum brightness output clamping and blanking input pulses at pin 11 switch-off voltage ground (1) (2) (3) (1) (3) (1) (3) switch-off voltage ground switch-off voltage ground fig.4 definition of levels and functions of brightness, contrast and gain with no pedestal blanking. (1) maximum. (2) nominal. (3) minimum.
2001 oct 19 26 philips semiconductors product speci?cation 160 mhz bus-controlled monitor video preampli?er TDA4887PS handbook, full pagewidth no pedestal blanking maximum gain setting, maximum contrast setting, maximum/minimum brightness setting reference black level video black levels at maximum brightness minimum brightness (1) (2) switch-off voltage ground pedestal blanking maximum gain setting, maximum contrast setting, maximum/minimum brightness setting reference black level pedestal black level mhb921 video black levels at maximum brightness minimum brightness (1) (2) switch-off voltage ground signal outputs at pins 22, 19 and 16 output clamping and blanking input pulses at pin 11 fig.5 output signals with and without pedestal blanking. (1) maximum. (2) minimum.
2001 oct 19 27 philips semiconductors product speci?cation 160 mhz bus-controlled monitor video preampli?er TDA4887PS handbook, full pagewidth reference black level colour signals (1) (2) video signals mhb922 video black levels at maximum brightness minimum brightness fig.6 definition of output signals at pins 22, 19 and 16: maximum gain setting, maximum contrast setting and no pedestal blanking. (1) maximum brightness setting. (2) minimum brightness setting. handbook, full pagewidth mhb944 vertical blanking pulses at signal outputs (brightness blanking at maximum brightness setting) 3 v 1.4 v t r/f5 75 ns/v t dl5 t dl5 video black level reference black level t dl5 internal pulse for input clamping input pulses at pin 5 fig.7 timing of pulses at pin 5 and derived pulses at maximum brightness setting.
2001 oct 19 28 philips semiconductors product speci?cation 160 mhz bus-controlled monitor video preampli?er TDA4887PS handbook, full pagewidth mhb945 contrast control data byte colour signal amplitude with respect to maximum colour signal amplitude (db) (1) (2) (3) 0 - 45 00h 20h 40h 60h 80h a0h c0h e0h ffh - 6 - 12 - 3 contrast modulation range fig.8 contrast control characteristic with subcontrast, limiting or contrast modulation. (1) no contrast reduction. (2) partial contrast reduction by subcontrast, limiting or contrast modulation. (3) full contrast reduction by subcontrast, limiting or contrast modulation. handbook, full pagewidth mhb946 osd contrast control data byte osd signal amplitude with respect to maximum colour signal amplitude (%) 00h 0fh (1) (2) (3) maximum colour signal amplitude maximum osd signal amplitude 96 24 fig.9 osd contrast control characteristic with subcontrast, limiting or contrast modulation. (1) no osd contrast reduction. (2) partial osd contrast reduction by subcontrast, limiting or contrast modulation. (3) full osd contrast reduction by subcontrast, limiting or contrast modulation.
2001 oct 19 29 philips semiconductors product speci?cation 160 mhz bus-controlled monitor video preampli?er TDA4887PS handbook, full pagewidth mhb947 brightness control data byte 00h 20h 40h 60h 80h a0h c0h e0h ffh difference of video black level and reference black level with respect to maximum colour signal amplitude (%) (1) (2) 33 - 10 0 fig.10 brightness control characteristic; control bit bri = 0. (1) nominal adjustment. (2) nominal brightness reference black level. handbook, full pagewidth mhb948 00h 20h 40h 60h 80h a0h c0h e0h ffh 100 20 gain control data byte video signal gain with respect to maximum video signal gain (%) fig.11 gain control characteristic.
2001 oct 19 30 philips semiconductors product speci?cation 160 mhz bus-controlled monitor video preampli?er TDA4887PS handbook, full pagewidth 00h 20h 40h 60h 80h a0h c0h e0h ffh 3.95 5.75 (1) 4.35 2.55 0 (2) internal feedback reference voltage (v) negative feedback reference data byte mhb949 brightness control; 8-bit dac subaddress 01h fig.12 internal feedback reference voltages for negative feedback (fpol = 0). (1) control bit bri = 0 or control bit bri = 1 and minimum brightness setting (subaddress 01h at 00h). (2) control bit bri = 1 and maximum brightness setting (subaddress 01h at ffh). handbook, full pagewidth mhb950 0 internal feedback reference voltage (v) positive feedback reference data byte 0.53 01h 02h 04h 05h 06h 07h 03h 1.70 1.50 1.31 1.11 0.92 0.72 1.89 fig.13 internal feedback reference voltages for positive feedback (fpol = 1).
2001 oct 19 31 philips semiconductors product speci?cation 160 mhz bus-controlled monitor video preampli?er TDA4887PS handbook, full pagewidth mhb951 00h 20h 40h 60h 80h a0h c0h e0h ffh 0 dac output voltage pins 23, 20, 17 (v) feedback reference data byte; subaddresses 07h, 08h and 09h 2.55 5.75 3.95 4.35 (1) (2) brightness control; 8-bit dac subaddress 01h fig.14 dac output voltages (control bit fpol = 1). (1) control bit bri = 0 or control bit bri = 1 and minimum brightness setting (subaddress 01h at 00h). (2) control bit bri = 1 and maximum brightness setting (subaddress 01h at ffh).
2001 oct 19 32 philips semiconductors product speci?cation 160 mhz bus-controlled monitor video preampli?er TDA4887PS 11 i 2 c-bus protocol table 1 slave address notes 1. address bit. 2. write bit. table 2 slave receiver format notes 1. start condition. 2. a = acknowledge. after an intermediate power dip all registers are set to their initial values (see note 3 at table 4) and an internal power-on reset bit will be set with the consequence that the device will give no acknowledge on the data byte after a first addressing. the power-on reset bit will be reset if the control register is addressed. it is recommended to then refresh all registers by using the auto-increment function. 3. all subaddresses within the range 00h to 0bh are automatically incremented. the subaddress counter wraps around from 0bh to 00h. for subaddresses within the range 80h to 8fh no auto-increment takes place. subaddresses outside the ranges 00h to 0bh and 80h to 8bh are acknowledged by the device but no auto-increment or any other internal operation takes place. 4. single data byte in case of no auto-increment of subaddresses. more than one data byte with auto-increment of subaddresses. 5. stop condition. a6 (1) a5 (1) a4 (1) a3 (1) a2 (1) a1 (1) a0 (1) w (2) 10001000 s (1) slave address a (2) subaddress (3) a data byte (4) ap (5)
2001 oct 19 33 philips semiconductors product speci?cation 160 mhz bus-controlled monitor video preampli?er TDA4887PS table 3 subaddress byte format notes 1. the most significant bit (msb) of the subaddress enables an i 2 c-bus transmission in direct or in buffered mode (see note 3). subaddresses outside the ranges 00h to 0fh and 80h to 8fh are not used. 2. subaddress bit. 3. most significant bit of subaddress byte. i 2 c-bus transmission in direct mode: b = 0 . i 2 c-bus transmission in buffered mode: b = 1 . function subaddress (1) subaddress byte direct mode buffered mode s7 (2) s6 (2) s5 (2) s4 (2) s3 (2) s2 (2) s1 (2) s0 (2) control register 00h 80h b (3) 0000000 brightness control 01h 81h b (3) 0000001 contrast control 02h 82h b (3) 0000010 osd contrast control 03h 83h b (3) 0000011 gain control channel 1 04h 84h b (3) 0000100 gain control channel 2 05h 85h b (3) 0000101 gain control channel 3 06h 86h b (3) 0000110 black level reference channel 1 07h 87h b (3) 0000111 black level reference channel 2 08h 88h b (3) 0001000 black level reference channel 3 09h 89h b (3) 0001001 black level for ac coupling 0ah 8ah b (3) 0001010 depth of pedestal blanking 0bh 8bh b (3) 0001011 0ch to 0fh 8ch to 8fh not used
2001 oct 19 34 philips semiconductors product speci?cation 160 mhz bus-controlled monitor video preampli?er TDA4887PS table 4 subaddress and data byte format notes 1. see table 3 (subaddress byte format). 2. the least significant bit (lsb) of an analog alignment register is defined as ax0 (data bit d0). 3. under certain conditions the nominal values lead to nominal colour signals, etc. (see notes 1 and 3 of chapter characteristics and figs 4 to 6). after power-up and after internal power-on reset of the i 2 c-bus the registers are set to the following values: a) control bit fpol to logic 1. b) control bits disv, diso and bri to logic 0. c) all other alignment registers to logic 0 (minimum value for control registers). 4. data bit. 5. x means dont care but the bits are preferably set to logic 0 for software compatibility with other video ics that have the same slave address. function subaddress (1) data byte (2) nominal value (3) direct mode buffered mode d7 (4) d6 (4) d5 (4) d4 (4) d3 (4) d2 (4) d1 (4) d0 (4) control register 00h 80h x (5) bri x (5) x (5) fpol disv diso x (5) 08h brightness control 01h 81h a17 a16 a15 a14 a13 a12 a11 a10 40h contrast control 02h 82h a27 a26 a25 a24 a23 a22 a21 a20 ffh osd contrast control 03h 83h x (5) x (5) x (5) x (5) a33 a32 a31 a30 0fh gain control channel 1 04h 84h a47 a46 a45 a44 a43 a42 a41 a40 ffh gain control channel 2 05h 85h a57 a56 a55 a54 a53 a52 a51 a50 ffh gain control channel 3 06h 86h a67 a66 a65 a64 a63 a62 a61 a60 ffh black level reference channel 1 07h 87h a77 a76 a75 a74 a73 a72 a71 a70 - black level reference channel 2 08h 88h a87 a86 a85 a84 a83 a82 a81 a80 - black level reference channel 3 09h 89h a97 a96 a95 a94 a93 a92 a91 a90 - black level for ac coupling 0ah 8ah x (5) x (5) x (5) x (5) x (5) aa2 aa1 aa0 - depth of pedestal blanking 0bh 8bh x (5) x (5) x (5) x (5) x (5) x (5) ab1 ab0 00
2001 oct 19 35 philips semiconductors product speci?cation 160 mhz bus-controlled monitor video preampli?er TDA4887PS table 5 control register bit function diso = 0 osd signals enabled diso = 1 osd signals disabled disv = 0 video signals enabled disv = 1 video signals disabled fpol = 0 negative feedback polarity; pins 23, 20 and 17 as feedback inputs; no external dac voltage outputs fpol = 1 positive feedback polarity; pins 23, 20 and 17 as external dac voltage outputs; internal feedback of signal outputs bri = 0 internal brightness control with grey scale tracking bri = 1 brightness control without grey scale tracking. with fpol = 0 the brightness information is combined with the internal feedback reference voltages. with fpol = 1 the brightness information is combined with the dac output voltages for dc restoration at the cathodes.
2001 oct 19 36 philips semiconductors product speci?cation 160 mhz bus-controlled monitor video preampli?er TDA4887PS handbook, full pagewidth start load preset control bits fpol, bri disv = 1 diso = 1 load factory settings gain (channel 1, 2, 3) black level references (channel 1, 2, 3) or external dac voltages ac black level pedestal depth load user preset values contrast brightness osd contrast deflection control ic locked yes yes load from eeprom load from eeprom load from program rom code or eeprom no disv = 0 diso = 0 display new mode (1) diso = 1 diso = 0 response to user inputs (2) (contrast, brightness, osd contrast) diso = 1 disv = 1 deflection control ic locked yes no user input no mhb932 fig.15 i 2 c-bus control flow chart. (1) only synchronized video should be displayed. each new mode can be displayed by osd. (2) data transmission should be synchronized with vertical blanking of the monitor.
2001 oct 19 37 philips semiconductors product speci?cation 160 mhz bus-controlled monitor video preampli?er TDA4887PS 12 test and application information handbook, full pagewidth to cathode 70 v application with integrated post amplifier, ac-coupled cathode and black level restoration cicuit. application with integrated post amplifier, dc-coupled cathode and negative feedback. 24 TDA4887PS i 2 c-bus black level restoration 1 23 2 22 3 21 4 20 5 19 6 18 7 17 8 16 9 15 10 14 11 13 12 output clamping blanking pull-up resistors to cathode subcontrast setting contrast modulation input 90 v 90 v application with discrete post amplifier, dc-coupled cathode and negative feedback. to cathode limiting input input clamping vertical blanking osd inputs signal inputs channel 1 channel 2 channel 3 fast blanking 5 v 8 v mhb933 fig.16 basic applications for different kinds of post amplifiers with dc or ac coupling. 12.1 test board for high frequency measurements, a special test board with only a few external components can be built. it utilizes the internal positive feedback of the output signals during output clamping with control bit fpol = 1. figure 17 shows the test circuit and figs 18 and 19 show the layout and mounting of the double-sided printed-circuit board. most components are smd-type. short hf loops and minimum crosstalk between channels and between signal inputs and outputs are achieved by using properly shaped ground areas.
2001 oct 19 38 philips semiconductors product speci?cation 160 mhz bus-controlled monitor video preampli?er TDA4887PS handbook, full pagewidth 50 w 5 k w 0.47 m f (63 v) 100 pf 100 nf cli v p v i2 v i1 cli 50 w 5.6 w 1 k w fbl fbl v i2 v i3 v i3 sda scl hfb gnd v o3 fb/r 3 fb/r 1 fb/r 2 50 w osd 3 osd 3 50 w osd 2 osd 2 50 w osd 1 osd 1 150 pf 10 nf 10 nf 0.47 m f (63 v) 150 pf 100 nf 5.6 w 0.47 m f (63 v) 150 pf 100 nf 5.6 w 0.47 m f (63 v) 150 pf 100 nf 5.6 w 1 k w j2 5 k w 10 k w 10 k w 10 k w j3 5 k w j1 50 w 150 pf 10 nf v i1 50 w 150 pf 10 nf 10 nf 50 w hfb limac sda 5 v scl 50 w 50 w 150 pf 10 nf 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 gndx v p3 v p1 v p2 v o1 v o2 fb/r 1 solder pin fb/r 2 solder pin fb/r 3 solder pin lim TDA4887PS channel 3 channel 2 channel 1 vpx 3.3 pf 10 k w v o3 3.3 pf 10 k w v o2 3.3 pf 10 k w v o1 v p1 sense v p sense v p gnd vindc lim 5 v mhb934 fig.17 test board utilizing internal positive feedback only (fpol = 1).
2001 oct 19 39 philips semiconductors product speci?cation 160 mhz bus-controlled monitor video preampli?er TDA4887PS handbook, full pagewidth cli j1 j2 j3 TDA4887PS limac mhb935 scl sda osd 3 osd 2 osd 1 v o1 v o2 v o3 v i1 v i2 v i3 fbl hfb 1 k w 1 k w 5 k w 5 k w 0.47 m f 0.47 m f 0.47 m f 0.47 m f 5 k w 10 k w 10 k w 10 k w 10 k w 10 k w 50 w + + + + - - - - 50 w 50 w 50 w 50 w 50 w 50 w 50 w 50 w 5.6 w 5.6 w 5.6 w 50 w 5.6 w 10 nf 100 nf 100 nf 100 nf 10 nf 150 pf 3.3 pf 3.3 pf 3.3 pf 150 pf 150 pf 150 pf 150 pf 150 pf 10 k w 10 nf 10 nf 10 nf u19 81 103 fig.18 printed-circuit top view shown with and without components mounted (for bottom view, see fig.19). dimensions are in mm.
2001 oct 19 40 philips semiconductors product speci?cation 160 mhz bus-controlled monitor video preampli?er TDA4887PS mhb217 handbook, full pagewidth 100 nf 100 pf 100 pf 100 nf 81 103 fig.19 printed-circuit bottom view shown with and without components mounted (for top view, see fig.18). dimensions are in mm.
2001 oct 19 41 philips semiconductors product speci?cation 160 mhz bus-controlled monitor video preampli?er TDA4887PS 12.2 application board with monolithic post ampli?er figure 20 shows the application circuit of TDA4887PS with a modern monolithic video post amplifier and ac-coupled crt. the black level restoration circuit is designed for 80 v supply and use of i 2 c-bus controlled external brightness setting. the 8 v supply voltage of the preamplifier is made from 12 v on this board. connectors for video, sync, i 2 c-bus, osd, clamping pulses, beam current limiting and supply voltages are provided.
2001 oct 19 42 philips semiconductors product speci?cation 160 mhz bus-controlled monitor video preampli?er TDA4887PS handbook, full pagewidth mhb966 r15/h 8 v 2.7 k w r16/h 2.7 k w r1 1 w 7808 l2 10 m h l1 10 m h r103 c101 ch 1 video input 22 nf 33 w r7 10 k w r8 10 k w r14 2.2 w r104 5.6 w r106 10 w r10 100 w r11 100 w c102 100 nf r204 5.6 w r12 100 w r5 1 k w r4 1 k w c9 22 nf c6 100 m f c3 100 nf c2 330 nf r206 10 w c202 100 nf r304 5.6 w r306 10 w c302 100 nf r3 5.6 w r2 1 w c7 22 nf c1 100 nf r101 75 w r6 1 k w r302 1 k w r202 1 k w r102 1 k w r9 100 w d1 5.1 v 1.5 nf c12 TDA4887PS 24 23 22 21 20 19 18 17 16 15 14 r203 c201 ch 2 22 nf 33 w r201 75 w r303 c301 ch 3 22 nf 33 w r301 75 w vert sync hor sync 13 n m l k j i h g f e d c b a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 9 10 11 12 5 6 7 8 1 2 3 4 n.c. n.c. ground hor sync vert sync aquadag blanking v ff v ff gnd v g1 v g2 beam cur lim v2 80 v v1 12 v clamping 4 3 2 1 ch 1 ch 2 osd ch 3 fbl 4 3 2 1 sda + 5 v 8 v i 2 c-bus gnd scl fig.20 application board with lm2435 (drawing is continued in fig. 20).
2001 oct 19 43 philips semiconductors product speci?cation 160 mhz bus-controlled monitor video preampli?er TDA4887PS handbook, full pagewidth mhb967 r305 10 w r307 c306 l308 0.22 m h 22 w r319 1 m w 10 k w r317 r313 270 w r218/h 68 w r118/h 68 w r318/h 68 w c304 2.2 nf c15 100 nf tr302 tr301 8 v r315 150 k w d303 baw62 d310 bav103 d309 bav103 r316 68 k w r314 12 k w 2 bc546 c10 1.5 nf c5 1 nf (2 kv) c305 1 m f (100 v) r205 10 w 10 k w r217 r213 270 w c204 2.2 nf tr202 tr201 8 v r215 150 k w d203 baw62 r216 68 k w r214 12 k w 2 bc546 c205 1 m f (100 v) r105 10 w r13 4.7 w 10 k w r117 r113 270 w c104 2.2 nf tr102 tr101 8 v r115 150 k w d103 baw62 r116 68 k w r114 12 k w 2 bc546 c105 1 m f (100 v) 1 m f (63 v) r207 c206 l208 0.22 m h 22 w r219 1 m w d210 bav103 d209 bav103 1 2 3 1 m f (63 v) c106 1 m f (63 v) r107 c14 l108 0.22 m h 22 w r119 1 m w d110 bav103 d109 bav103 2 100 nf c4 47 m f c8 47 m f c11 1 nf (2 kv) 10 9571 lm2435 6 8 11 eht v foc n m l k j i h g f e d c b a 9 5 6 7 8 4 fig.21 application board with lm2435 (drawing continued from fig. 20).
2001 oct 19 44 philips semiconductors product speci?cation 160 mhz bus-controlled monitor video preampli?er TDA4887PS 12.3 building the application board 12.3.1 g eneral double-sided board short hf loops by large ground plane on the rear smd components with minimum parasitics. 12.3.2 v oltage outputs capacitive loads as small as possible be aware of internal output resistance (typically 75 w ). 12.3.3 s upply voltages capacitors as near as possible to the pins use electrolytic capacitors with small serial resistance and inductance. 12.3.4 f lashover high electric field strength is present between the gun electrodes of picture tubes. in case of a flashover large transient currents and voltages may damage electronic components. it is therefore important to provide protective circuits with spark gaps, series resistors and protection diodes. be aware that not only electronic components that are directly connected to the tube socket are endangered if interconnection lines on the application board are unfavourably routed. 12.4 application hints 12.4.1 a lignment recommendations using brightness control with grey scale tracking 12.4.1.1 introduction (philosophy of TDA4887PS) with the TDA4887PS the user may change contrast, brightness and even colour temperature (r, g, b gains) or any combination at will. the x,y colour point will remain stable for the full grey scale. this feature is achieved in the following way: a change of brightness will cause a change of black level which is proportional to the actual gain setting conversely, a change of gain setting will cause a change of black level that is proportional to the deviation of brightness from its nominal setting. to benefit fully from this colour tracking feature, the reference black levels of the video amplifiers must match exactly to the cut-off points of the cathodes. re-adjustments of black level settings by the end user should be avoided, because this will upset the tracking feature. 12.4.1.2 dif?culty during monitor production the factory cut-off alignment is done at a quite high level (e.g. 2.4 cd/m 2 ). as a consequence it is not certain that the reference black level will match the cut-off exactly after a first black level adjustment. if then the r, g, b gains are adjusted for the (x, y) white point at e.g. 102.8 cd/m 2 , the white balance at 2.4 cd/m 2 will have changed. so two or more alignment cycles may be needed to achieve good results. 12.4.1.3 considerations for a single-pass factory alignment the nominal brightness setting is 40h. in this condition the black level equals reference black level and must match to the crt cut-off. for a better understanding, discrete values for luminance, video and feedback gain have been taken (these values should be regarded as examples). for special applications actual values have to be taken instead. white point must be aligned at maximum luminance (e.g. at 102.8 cd/m 2 ) with maximum contrast and nominal brightness. it is recommended to use only a small white square for white point alignment, to prevent variations of the voltage at grid g1 (v g1 ) and grid g2 (v g2 ) and to prevent unwanted activation of the automatic beam limiter (abl). for practical reasons, alignment of the r, g, b reference black levels must be done with a small amount of drive for obtaining a luminance level of approximately 2.4 cd/m 2 . this drive can be simulated by setting the brightness to a certain value. assuming 102.8 cd/m 2 luminance with full white video (100% drive) and a cathode characteristic with gamma = 2.25, the drive for black level adjustment can be shown as: which corresponds to a brightness setting of b8h. after black level adjustment for l = 2.4 cd/m 2 , the cathode voltages are fixed and the cut-off voltages are set with equal gain condition in all channels. during white point adjustment the gains will be changed. in the factory procedure for single pass adjustment, the luminance level for black level alignment (2.4 cd/m 2 ) is kept constant while adjusting the gain settings. to achieve this, the black level references are compensated by software and an alignment computer (this compensation is for factory alignment only and is not needed for any user change of r, g, b gain). 2.4 102.8 1/2.25 --------------------------- 100 = 18.8% drive
2001 oct 19 45 philips semiconductors product speci?cation 160 mhz bus-controlled monitor video preampli?er TDA4887PS calculation of compensation (see fig.22): 1. gain adjustment is in 255 steps from 20 to 100% which equates to 4.6 v per step at maximum contrast. one step = which is equal to 187 mv at the cathode with video gain = 13 for the white area. 2. for 18.8% drive (used for black level adjustment) the output changes only 2.7 mv (35 mv at the cathode) per gain step. 3. the black level adjustment range (at feedback inputs) is 1.9 v in 255 steps, which is 7.45 mv per step ( d black level of 97 mv at the cathode with feedback gain = 1 13 ). it follows that the optimum compensation is one step black level for or approximately three steps of gain. 0.8 4.6 v 255 ---------------------------- 14.4 mv = 97 35 ------ 2.8 = handbook, full pagewidth mhb953 fixed maximum gain 4.6 / 0.7 v preamplifier contrast - 40 db (0.5 / 100%) 255 steps brightness - 10 / 30% of 4.6 v 255 steps 3 gain 20 /100% 255 steps video gain 13 crt signal amplitude 60 v (max.) 25 v cut-off level variation 4.6 v (max.) 0.7 v (nom.) 5.75 to 3.95 v 3 black references range 1.9 v 255 steps feedback gain 1/13 fig.22 signal amplification and feedback references. 12.4.1.4 example of automatic factory alignment this procedure shows a realization of the alignment description, it depends on disposable equipment. gamma = 2.25, maximum luminance = 102.8 cd/m 2 , video gain = 13, feedback gain = 1 13 , white d; see fig.23. 1. initialization a) set grid 2 voltage to minimum b) set r, g, b gains to the centre values (80h, subaddresses 04h, 05h, 06h) c) set r, g, b black references to centre values (80h, subaddresses 07h, 08h, 09h) d) set contrast to maximum (ffh, subaddress 02h). 2. v g2 and black levels a) set brightness to 18.8% drive (b8h, subaddress 01h, control bit bri=0) b) apply black video c) increase v g2 manually until one colour appears d) activate the alignment computer e) the computer will continuously adjust the r, g, b black levels to meet the following three conditions: x = 0.131 y = 0.329 the centre of the min/max setting remains at 80h (this will leave some margin for the compensation steps that follow) f) fine tuning of v g2 (or v g1 ) until y = 2.4 cd/m 2 with the computer still active.
2001 oct 19 46 philips semiconductors product speci?cation 160 mhz bus-controlled monitor video preampli?er TDA4887PS 3. r, g, b gains (white point) a) set brightness at nominal (40h) b) apply full video white area (700 mv) c) activate the computer d) the computer will adjust the r, g, b gains to meet the following three conditions: x = 0.313 y = 0.329 y = 102.8 cd/m 2 for each 3 (2.8) gain increments, the computer will decrement the black references by one step. the effect on cathode voltages is demonstrated in fig.23. after step 2 the voltages at 18.8% drive are correct but not those at 100% drive (white) and 0% (black). after step 3 the voltages at 18.8% drive have not changed but white as well as black voltages are correct now. any brightness setting ( - 10 to +30%) relates to the individual maximum video amplitude (black-to-white). this alignment procedure is adaptable to dc-coupled as well as ac-coupled cathodes. handbook, full pagewidth mhb954 step 2: black level references adjusted with 18.8% drive and gain set to 80h. step 1: black level references and gain set to 80h. 10 0 20 30 40 50 60 70 80 cut-off voltage range from black level references (13 5.75 to 13 3.95) black white 18.8% step 3: gain adjustment at 100% white with automatic black level reference correction. cathode voltages for 18.8% drive left unchanged. cathode voltage (v) fig.23 automatic factory alignment.
2001 oct 19 47 philips semiconductors product speci?cation 160 mhz bus-controlled monitor video preampli?er TDA4887PS 12.4.2 b lack level restoration figure 24 shows two simple circuits for black level restoration for applications with ac-coupled cathodes. the output signal of the post amplifier is coupled via a 1 m f capacitor and a 68 w resistor to the cathode. the cathode voltage is clamped (peak responding) to the dc voltage v cl =v b +v be via diode d1. the voltage v b is derived from the bus controlled reference voltage v ref (pin fb/r (n) of TDA4887PS) by resistor network r1 to r2. for the upper circuit. for the lower circuit. the upper circuit has much less temperature dependence on clamp voltage and, in the event of an i 2 c-bus power-on reset in TDA4887PS, all clamp voltages go to black. for correct clamping, a well-defined top level of v sig is necessary (pedestal black level has to be the most positive voltage). when using internal brightness control, pedestal blanking (subaddress 0bh) has to be larger than minimum possible brightness setting (10% of maximum signal swing if the complete range is used). with 40 v maximum signal swing and 15% pedestal blanking, the clamping voltage v cl has to be 6 v higher than the extended cut-off voltage. without using internal brightness control, at least 5% pedestal blanking is recommended. v b v a r1 r2 + r1 --------------------- = v b v p1 v a1 v be C () r2 r1 ------- C = handbook, full pagewidth mhb955 1 m f 1 m f video booster amplification 13 68 w 100 v v p1 v sig v ref r2 150 k w d1 baw62 bav21 r1 10 k w 1 m w cathode amplification - 15 bc546 TDA4887PS 1 m f 1 m f video booster amplification 13 68 w r e 560 w 8 v 90 v v p2 v p1 v sig v cl v cl v b v a1 v a v b v ref r2 150 k w r c 22 k w d1 baw62 bav21 r1 12 k w 1 m w cathode amplification 13.5 2 bc546 TDA4887PS fig.24 black level restoration circuits.
2001 oct 19 48 philips semiconductors product speci?cation 160 mhz bus-controlled monitor video preampli?er TDA4887PS 12.4.3 a voiding negative input voltages at blanking and clamping input pins negative voltages on any input pin causes esd protection diodes and other internal junctions will become open-circuit resulting in substrate current injection. substrate currents can generate parasitic effects that are not completely predictable. signal inputs (pins 6 and 10) are neighbouring clamping inputs (pins 5 and 11) and can therefore suffer from larger leakage currents during negative clamping pulse glitches. an internal circuit in combination with an external resistor protects the pins from negative voltages (see fig.25). at pin voltages near to ground level, the voltage difference between the internal reference voltage v ref and the base voltage of tr1, which is 2v be higher than the pin voltage, generates a current through r1 which is amplified to the output by transistor tr1. the voltage drop at the external resistor r ext stabilizes voltage v pin near ground. the recommended value for r ext is1k w . handbook, full pagewidth mhb956 r1 6 k w tr1 8 v v p v pin v i r ext v ref = 2v be tr2 tr3 junctions from pin to substrate clamping pulse TDA4887PS ground fig.25 protection circuit at pins cli and hfb.
this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... 2001 oct 19 49 philips semiconductors product speci?cation 160 mhz bus-controlled monitor video preampli?er TDA4887PS 13 internal circuitry pin symbol and description characteristic waveform equivalent circuit 1 fbl; fast blanking input for osd insertion open-circuit base 2 osd 1 ; osd input channel 1 open-circuit base 3 osd 2 ; osd input channel 2 open-circuit base mha653 0 v 5 v mha928 1 50 m a 50 m a 50 m a 50 m a signal blanking osd1 blanking osd2 blanking osd3 blanking v p 1 k w mha653 0 v 5 v mhb197 50 m a 2 v p v p signal blanking fbl disable osd 1 k w 1 k w mha653 0 v 5 v mhb198 50 m a 3 v p v p signal blanking fbl disable osd 1 k w 1 k w
this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... 2001 oct 19 50 philips semiconductors product speci?cation 160 mhz bus-controlled monitor video preampli?er TDA4887PS 4 osd 3 ; osd input channel 3 open-circuit base 5 cli; vertical blanking input, input clamping input v cli > 0.2 v: open-circuit base v cli 0.2 v: source current rising with decreasing voltage pin symbol and description characteristic waveform equivalent circuit mha653 0 v 5 v mhb199 50 m a 4 v p v p signal blanking fbl disable osd 1 k w 1 k w mha651 5 v 0 v 2.5 v mha619 26 m a 5 v p v p power on/down 1 k w 10 k w 10 k w 6 k w 2v be 3 v + v be
this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... 2001 oct 19 51 philips semiconductors product speci?cation 160 mhz bus-controlled monitor video preampli?er TDA4887PS 6v i1 ; signal input channel 1 outside clamping pulse: open-circuit base with base current compensation i i1 during clamping: - 420 to +420 m a 7v p ; supply voltage i p = 25 ma (typical) pin symbol and description characteristic waveform equivalent circuit mha652 sync video signal input clamping (pin 5) black shoulder 4.7 v 4 v 3.7 v d book, halfpage 240 m a 420 m a 0 m a 220 m a signal 700 w mirror 1 : 1 6 v p v p 1.8 v + v be mhb926 mha621 7
this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... 2001 oct 19 52 philips semiconductors product speci?cation 160 mhz bus-controlled monitor video preampli?er TDA4887PS 8v i2 ; signal input channel 2 outside clamping pulse: open-circuit base with base current compensation i i2 during clamping: - 420 to +420 m a 9 gnd; ground 10 v i3 ; signal input channel 3 outside clamping pulse: open-circuit base with base current compensation i i3 during clamping: - 420 to +420 m a pin symbol and description characteristic waveform equivalent circuit mha652 sync video signal input clamping (pin 5) black shoulder 4.7 v 4 v 3.7 v b ook, halfpage 240 m a 420 m a 0 m a 220 m a signal 700 w mirror 1 : 1 8 v p v p 1.8 v + v be mhb927 mha623 9 mha652 sync video signal input clamping (pin 5) black shoulder 4.7 v 4 v 3.7 v b ook, halfpage 240 m a 420 m a 0 m a 220 m a signal mhb923 700 w mirror 1 : 1 10 v p v p 1.8 v + v be
this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... 2001 oct 19 53 philips semiconductors product speci?cation 160 mhz bus-controlled monitor video preampli?er TDA4887PS 11 hfb; output clamping input, blanking input v hfb > 0.2 v: open-circuit base v hfb 0.2 v: source current rising with decreasing voltage 12 sda; i 2 c-bus serial data input/output no acknowledge: open-circuit base during acknowledge: i sda >3ma 13 scl; i 2 c-bus clock input open-circuit base pin symbol and description characteristic waveform equivalent circuit mha649 5 v 0 v mha625 27 m a blanking 1.7 v clamping 11 v p v p 1 k w 10 k w 12 k w 10 k w 6 k w 2v be 3 v + v be power on/down 27 m a mha647 5 v 0 v halfpage 12 acknowledge 10 k w 6 m a 70 m a 19 m a 2.46 v + v be mhb924 mha648 5 v 0 v a lfpage 19 m a 1 k w 2.46 v + v be 13 mhb925
this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... 2001 oct 19 54 philips semiconductors product speci?cation 160 mhz bus-controlled monitor video preampli?er TDA4887PS 14 gndx; ground signal channels 1, 2 and 3 15 v p3 ; supply voltage channel 3 i p3 = 20 ma (typical) 16 v o3 ; signal output channel 3 reference black level voltage 0.1 to 2.8 v control bit pedst = 0 pedestal black level voltage 0.1 to 2.8 v control bit pedst = 1 pin symbol and description characteristic waveform equivalent circuit mhb205 14 mhb206 15 mha655 brightness reference black level during output clamping 16 v p v p 75 w 1.5 k w 1 k w 2 k w 8 k w mhb957 3.5 pf 60 ff 1 k w 10 m a mha656 brightness pedestal black level during output clamping
this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... 2001 oct 19 55 philips semiconductors product speci?cation 160 mhz bus-controlled monitor video preampli?er TDA4887PS 17 fb/r 3 ; feedback input/ reference voltage output channel 3 open-circuit base control bit fpol = 0 i fb/r3 : - 200 to +200 m a v fb/r3 : 5.75 to 2.55 v control bit fpol = 1 18 v p2 ; supply voltage channel 2 i 18 = 20 ma (typical) pin symbol and description characteristic waveform equivalent circuit ag e feedback reference 5.75 to 2.55 v pedst = 0 pedst = 1 mhb931 2 i i 27 i 100 w 17 v p 1 k w 5.75 to 2.55 v 5.75 to 2.55 v v s1 v s2 1 k w 1.7 k w 15 k w 15 k w 10 m a 10 m a mhb928 dc coupling (control bit fpol = 0): v s1 =0v; v s2 =1v; i=0 ac coupling (control bit fpol = 1): v s1 =1v; v s2 =0v; i=7.5 m a mhb218 18
this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... 2001 oct 19 56 philips semiconductors product speci?cation 160 mhz bus-controlled monitor video preampli?er TDA4887PS 19 v o2 ; signal output channel 2 reference black level voltage 0.1 to 2.8 v control bit pedst = 0 pedestal black level voltage 0.1 to 2.8 v control bit pedst = 1 pin symbol and description characteristic waveform equivalent circuit mha655 brightness reference black level during output clamping 19 v p v p 75 w 1.5 k w 1 k w 2 k w 8 k w mhb958 3.5 pf 60 ff 1 k w 10 m a mha656 brightness pedestal black level during output clamping
this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... 2001 oct 19 57 philips semiconductors product speci?cation 160 mhz bus-controlled monitor video preampli?er TDA4887PS 20 fb/r 2 ; feedback input/reference voltage output channel 2 open-circuit base control bit fpol = 0 i fb/r2 : - 200 to +200 m a v fb/r2 : 5.75 to 2.55 v control bit fpol = 1 21 v p1 ; supply voltage channel 1 i p1 = 20 ma (typical) pin symbol and description characteristic waveform equivalent circuit ag e feedback reference 5.75 to 2.55 v pedst = 0 pedst = 1 mhb931 2 i i 27 i 100 w 20 v p 1 k w 5.75 to 2.55 v 5.75 to 2.55 v v s1 v s2 1 k w 1.7 k w 15 k w 15 k w 10 m a 10 m a mhb929 dc coupling (control bit fpol = 0): v s1 = 0; v s2 =1v; i=0 ac coupling (control bit fpol = 1): v s1 =1v; v s2 = 0; i = 7.5 m a mhb211 21
this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... 2001 oct 19 58 philips semiconductors product speci?cation 160 mhz bus-controlled monitor video preampli?er TDA4887PS 22 v o1 ; signal output channel 1 reference black level voltage 0.1 to 2.8 v control bit pedst = 0 pedestal black level voltage 0.1 to 2.8 v control bit pedst = 1 pin symbol and description characteristic waveform equivalent circuit mha655 brightness reference black level during output clamping 22 v p v p 75 w 1.5 k w 1 k w 2 k w 8 k w mhb959 3.5 pf 60 ff 1 k w 10 m a mha656 brightness pedestal black level during output clamping
this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... 2001 oct 19 59 philips semiconductors product speci?cation 160 mhz bus-controlled monitor video preampli?er TDA4887PS 23 fb/r 1 ; feedback input/reference voltage output channel 1 open-circuit base control bit fpol = 0 i fb/r1 : - 200 to +200 m a v fb/r1 : 5.75 to 2.55 v control bit fpol = 1 pin symbol and description characteristic waveform equivalent circuit ag e feedback reference 5.75 to 2.55 v pedst = 0 pedst = 1 mhb931 2 i i 27 i 100 w 23 v p 1 k w 5.75 to 2.55 v 5.75 to 2.55 v v s1 v s2 1 k w 1.7 k w 15 k w 15 k w 10 m a 10 m a mhb930 dc coupling (control bit fpol = 0): v s1 = 0; v s2 =1v; i=0 ac coupling (control bit fpol = 1): v s1 =1v; v s2 = 0; i = 7.5 m a
this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... 2001 oct 19 60 philips semiconductors product speci?cation 160 mhz bus-controlled monitor video preampli?er TDA4887PS 24 lim; subcontrast adjustment, contrast modulation, beam current limiting input open-circuit voltage v lim =5v v lim < 4.4 v: open-circuit base pin symbol and description characteristic waveform equivalent circuit mhb214 24 v p 5.0 v 1 k w 21 m a 10 k w
2001 oct 19 61 philips semiconductors product speci?cation 160 mhz bus-controlled monitor video preampli?er TDA4887PS 14 package outline unit b 1 cee m h l references outline version european projection issue date iec jedec eiaj mm dimensions (mm are the original dimensions) sot234-1 92-11-17 95-02-04 b max. w m e e 1 1.3 0.8 0.53 0.40 0.32 0.23 22.3 21.4 9.1 8.7 3.2 2.8 0.18 1.778 10.16 10.7 10.2 12.2 10.5 1.6 4.7 0.51 3.8 m h c (e ) 1 m e a l seating plane a 1 w m b 1 e d a 2 z 24 1 13 12 b e pin 1 index 0 5 10 mm scale note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. (1) (1) d (1) z a max. 12 a min. a max. sdip24: plastic shrink dual in-line package; 24 leads (400 mil) sot234-1
2001 oct 19 62 philips semiconductors product speci?cation 160 mhz bus-controlled monitor video preampli?er TDA4887PS 15 soldering 15.1 introduction to soldering through-hole mount packages this text gives a brief insight to wave, dip and manual soldering. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (document order number 9398 652 90011). wave soldering is the preferred method for mounting of through-hole mount ic packages on a printed-circuit board. 15.2 soldering by dipping or by solder wave the maximum permissible temperature of the solder is 260 c; solder at this temperature must not be in contact with the joints for more than 5 seconds. the total contact time of successive solder waves must not exceed 5 seconds. the device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (t stg(max) ). if the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. 15.3 manual soldering apply the soldering iron (24 v or less) to the lead(s) of the package, either below the seating plane or not more than 2 mm above it. if the temperature of the soldering iron bit is less than 300 c it may remain in contact for up to 10 seconds. if the bit temperature is between 300 and 400 c, contact may be up to 5 seconds. 15.4 suitability of through-hole mount ic packages for dipping and wave soldering methods note 1. for sdip packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board. package soldering method dipping wave dbs, dip, hdip, sdip, sil suitable suitable (1)
2001 oct 19 63 philips semiconductors product speci?cation 160 mhz bus-controlled monitor video preampli?er TDA4887PS 16 data sheet status notes 1. please consult the most recently issued data sheet before initiating or completing a design. 2. the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the latest information is available on the internet at url http://www.semiconductors.philips.com. data sheet status (1) product status (2) definitions objective speci?cation development this data sheet contains data from the objective specification for product development. philips semiconductors reserves the right to change the speci?cation in any manner without notice. preliminary speci?cation quali?cation this data sheet contains data from the preliminary specification. supplementary data will be published at a later date. philips semiconductors reserves the right to change the speci?cation without notice, in order to improve the design and supply the best possible product. product speci?cation production this data sheet contains data from the product specification. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. changes will be communicated according to the customer product/process change noti?cation (cpcn) procedure snw-sq-650a. 17 definitions short-form specification ? the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values definition ? limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the specification is not implied. exposure to limiting values for extended periods may affect device reliability. application information ? applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 18 disclaimers life support applications ? these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes ? philips semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
2001 oct 19 64 philips semiconductors product speci?cation 160 mhz bus-controlled monitor video preampli?er TDA4887PS 19 purchase of philips i 2 c components purchase of philips i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specification defined by philips. this specification can be ordered using the code 9398 393 40011.
2001 oct 19 65 philips semiconductors product speci?cation 160 mhz bus-controlled monitor video preampli?er TDA4887PS notes
2001 oct 19 66 philips semiconductors product speci?cation 160 mhz bus-controlled monitor video preampli?er TDA4887PS notes
2001 oct 19 67 philips semiconductors product speci?cation 160 mhz bus-controlled monitor video preampli?er TDA4887PS notes
? koninklijke philips electronics n.v. 2001 sca73 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owne r. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not con vey nor imply any license under patent- or other industrial or intellectual property rights. philips semiconductors C a worldwide company contact information for additional information please visit http://www.semiconductors.philips.com . fax: +31 40 27 24825 for sales of?ces addresses send e-mail to: sales.addresses@www.semiconductors.philips.com . printed in the netherlands 753504/01/pp 68 date of release: 2001 oct 19 document order number: 9397 750 08393

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