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cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 002-08369 rev. *b revised july 24, 2017 mb39c011a 2ch dc/dc converter ic with synchronous rectification datasheet the mb39c011a is a two-channel dc/dc converte r ic suitable for down-conve rsion that utilizes synchr onous rectification and puls e width modulation (pwm). the mb39 c011a can operate over a wide range of power supp ly voltages (4.5 v to 17 v), making it optimal as a built-in power supply in di gital audio visual equipment and various other electronic devices. features wide range of power supply voltages: 4.5 v to 17 v supports high frequency operation: 2.0 mhz (max) supports synchronous rectif ication method (ch1, ch2) an arbitrary output voltage can be conf igured using an external resistance. built-in standb y function: 0 a (typ) low current consumption: 2.2 ma (typ, at quiescence) built-in soft-start circuit that can control ea ch channel separately independent of the load built-in timer latch type short-circuit protec tion circuit (shares the soft-start capacitor) built-in totem pole type output stage for external p-ch/n-ch mos fet devices package : tssop-16-pin applications ? digital tv ? photocopiers ? surveillance cameras ? set-top boxes (stb) ? dvd players, dvd recorders ? projectors ? ip phones ? vending machines ? consoles and other non-portable devices
document number: 002-08369 rev. *b page 2 of 53 mb39c011a contents 1. pin assignment ........................ ........................ ............. 3 2. pin description ....................... ........................ ............. 4 3. block diagram ...................... ......................... ................ 5 4. absolute maximum ratings ......................... ................ 6 5. recommended operating conditions ........................ 7 6. electrical characteristics ......................... .................... 8 7. typical characteristics .......................... ..................... 10 8. functional description .......................... ..................... 12 8.1 dc/dc converter block ...... ........................ .................. 12 8.2 protection function ............. ........................ .................. 13 9. switching scheme selection ....................... .............. 20 10. setting the output voltage ...................... .................. 21 11. setting the triangular oscillation frequency ......... 22 11.1 power dissipation and the rmal design........................ 22 12. setting the soft-start a nd short-circuit detection times ........................... ............................ ..................... 24 13. vb pin and vh pin connections in condition of vcc voltage ...................... ......................... .............. 24 14. design of phase compensation circuit ................... 26 14.1 phase compensation circuit when low esr capacitor is used as output capacitor..... ........................ .................. 26 14.2 notes on phase compensatio n circuit constants........ 27 15. handling the unused channel pins when using a single channel ...................... ..................... .............. 29 16. i/o equivalent circuit ............................ ..................... 31 17. example application circuit ........................ .............. 33 18. parts list ........................... ........................ .................. 34 19. part selection ....................... ......................... .............. 35 19.1 coil selection ...................... ........................ .................. 35 19.2 sw fet selection ............... ........................ .................. 36 19.3 fly-back diode selection .... ........................ .................. 38 19.4 output capacitor selection . ......................... .................. 39 19.5 input capacitor selection . ............................ .................. 39 19.6 vb pin capacitor.................. ........................ .................. 40 19.7 vh pin capacitor ................. ........................ .................. 40 20. pcb layout ...................... ........................ .................. 41 21. reference data ......................... ..................... .............. 43 22. usage precaution .............................. ......................... 45 22.1 do not configure the ic over the maximum ratings ...... 45 22.2 use the device within the recommended operating conditions.............. ............................... ......................... 45 22.3 printed circuit board ground lines should be set up with consideration for common im pedance.......................... 45 22.4 take appropriate measures a gainst static electricity .... 45 22.5 do not apply negative volt ages................... .................. 45 23. ordering information ............................. ..................... 46 24. ev board ordering information ................... .............. 46 25. rohs compliance information of lead (pb) free version ........................... ............................ .................. 47 26. marking format (lead-free version) ........................ 47 27. labeling sample (lead-free version) ....................... 48 28. mb39c011apft- ??? e1 recommended mounting conditions ......................... ........................ .................. 49 28.1 recommended mounting cond itions.............. .............. 49 28.2 parameters for each moun ting method ........................ 50 29. package dimensions ............................. ..................... 51
document number: 002-08369 rev. *b page 3 of 53 mb39c011a 1. pin assignment (top view) (fpt-16p-m07) vcc out1-1 out1-2 vb rt fb1 -ine1 cscp1 vh out2-1 out2-2 ctl gnd fb2 -ine2 cscp2 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9
document number: 002-08369 rev. *b page 4 of 53 mb39c011a 2. pin description pin no. pin name i/o description 1vcc - power supply pin for the reference voltage circuit and control circuit. 2 out1-1 o output pin for p-ch drive (drives the gate of the external high side fet). 3 out1-2 o output pin for n-ch drive (drives the gate of the external low side fet). 4 vb i/o power supply pin for the n-ch fet drive circuit (vb = 5 v). 5rt - triangular-wave oscillation frequen cy setting resistor connection pin. 6 fb1 o error amplifier (error amp1) output pin. 7 -ine1 i error amplifier (error amp1) inverted input pin. 8 cscp1 - timer-latch short-circuit protection circuit 1 capacitor connection pin. 9 cscp2 - timer-latch short-circuit protection circuit 2 capacitor connection pin. 10 -ine2 i error amplifier (error amp2) inverted input pin. 11 fb2 o error amplifier (error amp2) output pin. 12 gnd - ground pin for the reference voltage circ uit, control circuit, and output circuit. 13 ctl i power supply control pin. ic becomes a stand-by mode by setting ctl pin ?l? level. 14 out2-2 o output pin for n-ch drive (drive s the gate of the external low side fet). 15 out2-1 o output pin for p-ch drive (drives the gate of the external high side fet). 16 vh o power supply pin for the n-ch fet drive circuit (vh = vcc ? 5 v).
document number: 002-08369 rev. *b page 5 of 53 mb39c011a 3. block diagram rt ct bi as vb 7 a 6 2 a 10 b 11 b 1 13 12 5 8 16 vh vh vb 3 15 14 4 vb vb vb 9 v in (6 v to 17 v) -ine2 cscp2 cscp1 uvlo reset sr latch osc bias voltage bias voltage vr1 power on/off ctl h:on (power on) l:off(standbymode) vth=1.4 v gnd (2.0 v) (2.0 v) 2.5 v 2.5 v (1.9 v) scp comp.1 scp comp.2 error amp2 pwm comp.2 error amp1 pwm comp.1 ast ast (1.9 v) (0.7 v) (1.7 v) (0.7 v) (1.7 v) (1.0 v) (1.0 v) (2.3u) (1.0u) (1.0u) (2.3u) erroramp ref. (1.0 v) vb (5 v) fb1 fb2 -ine1 p-ch vcc drive1-1 drive1-2 drive2-1 out2-1 step-down vo2 (3.3 v) step-down vo1 (1.8 v) out2-2 out1-1 out1-2 drive2-2 n-ch p-ch n-ch << ch1 >> << ch2 >> ctl vcc (vcc-5 v)
document number: 002-08369 rev. *b page 6 of 53 mb39c011a 4. absolute maximum ratings [1] : when mounted on a 10 cm squar e double-sided epoxy circuit board. warning: semiconductor devices can be permanently damaged by application of stress (v oltage, current, temperature, etc.) in excess of absolute maximum rati ngs. do not exceed these ratings. parameter symbol condition rating unit min max power supply voltage v cc vcc pin - 18 v input voltage v b vb pin (when vcc pin connected to vb pin) - 7v v ine -ine1, -ine2 pins ? 0.3 v b v v ctl ctl pin - 18 v output current i o out1-1, out1-2, out2-1, out2-2 pins - 60 ma peak output current i op duty 5 % (t = 1/fosc duty) - 700 ma power dissipation p d ta + 25 ? c - 1060 [1] mw storage temperature t stg - ? 55 + 125 ? c
document number: 002-08369 rev. *b page 7 of 53 mb39c011a 5. recommended operating conditions warning: the recommended operating cond itions are required in order to ensure the normal operation of the semiconductor device. all of the device's electrical characteristics are warranted when the device is operat ed within these ranges. always use semiconductor devi ces within their recommended operating co ndition ranges. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinati ons not represented on the data sheet. users considering application outside the listed co nditions are advised to contact their representatives beforehand. parameter symbol condition value unit min typ max power supply voltage v cc vcc pin 4.5 12 17 v vh pin output current i vh vh pin 0 - 40 ma vb pin output current i vb vb pin ? 40 - 0ma vb pin input voltage v b vb pin(when vcc pin connected to vb pin) 4.5 5 6 v input voltage v ine -ine1, -ine2 pins 0 - v b ? 0.9 v ctl pin input voltage v ctl ctl pin 0 - 17 v output current i out out1-1, out1-2, out2-1, out2-2 pins ? 45 - + 45 ma oscillation frequency f osc tj + 85 ? c 100 500 2000 khz timing resistor r t rt pin 3.6 16 100 k vh pin capacitor c vh vh pin - 1.0 4.7 f vb pin capacitor c vb vb pin - 1.0 4.7 f cscp1, cscp2 pin capacitor cscp1, cscp2 cscp1, cscp2 pins - 0.047 1.0 f operating ambient temperature ta - ? 30 + 25 + 85 ? c
document number: 002-08369 rev. *b page 8 of 53 mb39c011a 6. electrical characteristics ( ta = + 25 ? c , v cc = 12 v ) (continued) parameter symbol pin no. condition value unit min typ max under voltage lockout protection circuit block [uvlo] threshold voltage v tlh 4 vb 3.8 4.0 4.2 v v thl 4 vb 3.6 3.8 4.0 v hysteresis width v h 4 -- 0.2 [1] - v short-circuit protection circuit block [scp] threshold voltage v th 8, 9 - 1.9 2.0 2.1 v input source current i cscp 8, 9 rt = 16 k ? 3.2 ? 2.3 ? 1.4 a reset voltage v rst 4vb = 3.6 3.8 4.0 v triangular wave oscil- lator block [osc] oscillation frequency fosc 2, 15 rt = 16 k 450 500 550 khz soft-start block [cs] charge current i cs 8, 9 cscp1, 2 = 0 v, rt = 16 k ? 4.6 ? 3.3 ? 2.0 a error amp block [error amp1, error amp2] threshold voltage v th 6, 11 fb1 = 1 v, fb2 = 1 v 0.99 1.00 1.01 v input bias current i b 7, 10 -ine1 = 0 v, -ine2 = 0 v ? 100 0 + 100 na voltage gain a v 6, 11 dc - 80 [1] - db frequency band- width bw 6, 11 a v = 0 db - 5.0[ 1] - mhz output voltage v oh 6, 11 - v b ? 0.3 v b ? 0.1 - v v ol 6, 11 -- 40 200 mv output source current i source 6, 11 fb1 = 1 v, fb2 = 1 v -- 400 ? 300 a output sink current i sink 6, 11 fb1 = 1 v, fb2 = 1 v 4.0 8.0 - ma pwm comparator block [pwm comp.1, pwm comp.2] threshold voltage v t0 6, 11 duty cycle = 0 % 0.6 0.7 - v v t100 6, 11 duty cycle = 100 % - 1.7 1.8 v vh bias voltage block [vh] output voltage v h 16 vcc = 6 v to 17 v vh = 0 to 40 ma v cc ? 5.5 v cc ? 5.0 v cc ? 4.5 v vb bias voltage block [vb] output voltage v b 4 vcc = 6 v to 17 v vb = 0 to ? 40 ma 4.5 5.0 5.5 v
document number: 002-08369 rev. *b page 9 of 53 mb39c011a (continued) ( ta = + 25 ? c , v cc = 12 v ) [1] : standard design value parameter symbol pin no. condition value unit min typ max output block[drive1 to 2] output source current i source 2, 15 out1-1 = 7 v out2-1 = 7 v duty 5 % - ? 500 [1] - ma 3, 14 vb = vcc = 5 v out1-2 = 0 v out2-2 = 0 v duty 5 % output sink current i sink 2, 15 vcc = 5 v, at connect vh-gnd out1-1 = 5 v out2-1 = 5 v duty 5 % - 500 [1] - ma 3, 14 out1-2 = 5 v out2-2 = 5 v duty 5 % output on resistor r oh 2, 3, 14, 15 out1-1, out1-2, out2-1, out2-2 = ? 45 ma - 4.0 6.0 r ol 2, 15 out1-1, out2-1 = 45 ma - 4.0 6.0 3, 14 out1-2, out2-2 = 45 ma - 2.6 3.9 dead time td 2, 3, 14, 15 out1-1, out2-1 : h l out1-2, out2-2 : h l 20 40 80 ns out1-1, out2-1 : l h out1-2, out2-2: l h control block ctl input voltage v ih 13 ic active mode 2 - 17 v v il 13 ic standby mode 0 - 0.8 v input current i ctlh 13 ctl = 5 v - 50 100 a i ctll 13 ctl = 0 v -- 1 a general standby current i ccs 1ctl = 0 v - 010 a power supply current i cc 1ctl = 5 v - 2.2 3.3 ma
document number: 002-08369 rev. *b page 10 of 53 mb39c011a 7. typical characteristics (continued) power supply current vs.power supply voltage vb bias volt age vs.power supply voltage power supply current i cc (ma) vb bias voltage v b (v) power supply voltage v cc (v) power supply voltage v cc (v) vb bias voltage vs.vb bias output current vb bias voltage vs .operating ambient temperature vb bias voltage v b (v) vb bias voltage v b (v) vb bias output current i vb (ma) operating ambient temperature ta ( ? c) voltage between vcc and vh vs.power supply voltage voltage between vcc and vh vs.vh bias output current voltage between vcc and vh (v) voltage between vcc and vh (v) power supply voltage v cc (v) vh bias output current i vh (ma) 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 4 6 8 1012141618 ta = + 25 ? c 5.5 5.4 5.3 5.2 5.1 5.0 4.9 4.8 4.7 4.6 4.5 4 6 8 10 12 14 16 18 ta = + 25 ? c vb = 0 a 5.5 5.4 5.3 5.2 5.1 5.0 4.9 4.8 4.7 4.6 4.5 -100 -80 -60 -40 -20 0 ta = + 25 ? c vcc = 12 v 5.5 5.4 5.3 5.2 5.1 5.0 4.9 4.8 4.7 4.6 4.5 -40 -20 0 +20 +40 +60 +80 +100 vcc = 12 v vb = 0 a 5.5 5.4 5.3 5.2 5.1 5.0 4.9 4.8 4.7 4.6 4.5 4681012141618 ta = + 25 ? c vh = 0 a 5.5 5.4 5.3 5.2 5.1 5.0 4.9 4.8 4.7 4.6 4.5 0 20406080100 ta = + 25 ? c vcc = 12 v
document number: 002-08369 rev. *b page 11 of 53 mb39c011a (continued) voltage between vcc and vh vs. operating ambient temperature triangular-wave generator frequency vs. timing resistance voltage between vcc and vh (v) triangular-wave g enerator frequency fosc (khz) operating ambient te mperature ta ( ? c) timing resistance r t (k ) triangular-wave generator frequency vs. power supply voltage triangular-wave generator frequency vs. operating ambient temperature triangular-wave generator frequency fosc (khz) triangular-wave generator frequency fosc (khz) power supply voltage v cc (v) operating ambient temperature ta ( ? c) error amp threshold voltage vs. operating ambient temperature power dissipation vs. operating ambient temperature error amp threshold voltage v th (v) power dissipation p d (mw) operating ambient te mperature ta ( ? c) operating ambient temperature ta ( ? c) 5.5 5.4 5.3 5.2 5.1 5.0 4.9 4.8 4.7 4.6 4.5 -40 -20 0 +20 +40 +60 +80 +100 vcc = 12 v vh = 0 a 10000 1000 100 110100 ta = + 25 ? c vcc = vb = 5 v 650 600 550 500 450 400 350 4.5 5.0 5.0 6.0 6.5 7.0 ta = + 25 ? c vcc = vb fosc = 500 khz 650 600 550 500 450 400 350 -40 -20 0 +20 +40 +60 +80 +100 vcc = vb = 5 v fosc = 500 khz 1.05 1.04 1.03 1.02 1.01 1.00 0.99 0.98 0.97 0.96 0.95 -40 -20 0 +20 +40 +60 +80 +100 vcc = vb = 5 v 1200 1000 800 600 400 200 0 1060 -50 -25 0 +25 +50 +75 +100 +125
document number: 002-08369 rev. *b page 12 of 53 mb39c011a 8. functional description 8.1 dc/dc converter block 8.1.1 triangular wave oscillator block (osc) the triangular wave oscillator block has a built-in capacitor for setting the oscill ator frequency. the triangular wave is generated by connecting a resistor for se lecting the frequency of the triangular wave to the rt pin (pin 5).the triangular wave is input internally to the pwm comparator in the ic. 8.1.2 error amplifier block (error amp1, error amp2) the error amplifiers (error amp1, error amp2) detect t he dc/dc converter output voltages and output the pwm control signals. the output voltages can be set to an arbitrary level by externally con necting output voltage se tting resistors to the error amplifier inverted input pins. in addition, an arbitrary loop gain can be set by connecting a feedbac k resistor and capacitor from the error amplifier output (fb1 pin (pin 6), fb2 pin (pin 11)) to in verted input terminal (-ine1 pin (pin 7), -ine2 pin (pin 10)), enabling stable phase compensation of the system.connecting a soft-start capacitor to the cscp1 and cs cp2 pins (pins 8 and 9) prevents rush currents when the ic is turned on. using an error amplifier for soft-start detect ion makes the soft-start time constant, independent of the output load of dc/dc converter. 8.1.3 pwm comparator block (pwm comp.) the pwm comparator circuit is a voltage-pu lse width converter for controlling the outp ut duty of the error amplifiers (error amp1, error amp2) depending on their output voltage. the pwm comparator circuit compar es the triangular wave generate d by the triangular wave osci llator to the error amplifier output voltage and turns on the external out put transistor during the interval in wh ich the triangular wave voltage is lower than the error amplifier output voltage. 8.1.4 output block (drive1-1, 1-2, drive 2-1, 2-2) the output circuit consists of cmos driv ers on both the high side and the low si de, and is capable of driving an external p-ch mos fet on the high side and an external n-ch mos fet on the low side. 8.1.5 power supply control block (ctl) the dc/dc converter can be put into stan dby mode by setting the ctl pin (pin 13 ) to the ?l? level (the maximum power supply current in standby mode is 10 a), and put into operating mo de by setting the ctl pin (pin 13) to the ?h? level. control function table ctl ic l off (standby) h on (operating)
document number: 002-08369 rev. *b page 13 of 53 mb39c011a 8.2 protection function 8.2.1 soft-start circuit to prevent rush currents when the ic is turned on, soft-start can be performed by connecting soft-star t capacitors (cscp1 and cscp2) to the cscp1 and cscp2 pins (pins 8 and 9). when ctl pi n (pin 13) is driven to the ?h? level and the ic begins operation (vcc uvlo threshold voltage), the external soft-start capacitors (cscp1 and cs cp2) connected to the cscp1 and cscp2 pins (pins 8 and 9) are charged by the chargi ng current obtained from the following formula. i cs ? 5.4 10 ? 5 / r t the error amplifier output (fb1 pin (pin 6), fb2 pin (pin 11)) is dete rmined by comparing the voltag es of the two non-inverted input pins (whichever of the in ternal 1.0 v reference voltage and the cscp1 and cscp2 pins (p in 8 and pin 9) has the lowest voltage) against the inverted in put pin voltages (-ine1 pin (pin 7) voltage, -ine2 pin (pin 10) voltage). during the soft-start period, fb1 and fb2 are determined by co mparing the internal 1.0 v reference volt age against the voltages of the cscp1 and cscp2 pins (pins 8 and 9), and the dc/ dc converter output voltages rise in pr oportion to voltages of the cscp1 and cscp2 pins (pins 8 and 9) as the soft-st art capacitors (cscp1 and cscp2) connec ted to the cscp1 and cscp2 pins (pins 8 and 9) are charged. the soft-start time can be foun d from the following formula. ts ? 0.019 cscp r t i cs :charge current [a] r t :timing resistance [k ] ts :soft-start time (time to output voltage 100 % ) [s] cscp :capacitance of cscp pin [ f] r t :timing resistance [k ] t ? reference voltage 1.0 v error amp block -ine1 (-ine2) voltage cscp pin voltage soft start time, ts ? 1.3 v ? 0 v
document number: 002-08369 rev. *b page 14 of 53 mb39c011a 8.2.2 timer-latch short-circuit protection circuit each channel has a short-circuit detection comparator (scp comp1 and comp2) that co nstantly compares the output level of the error amplifier against the reference voltag e. while the dc/dc converter load conditio ns remain stable, the error amplifier out put does not change and the short-ci rcuit protection comparator rema ins in an equilibrium state. at this time, the cscp1 and cscp2 pins (pins 8 and 9) maintain the voltage fr om when the soft-start finished (about 1. 3 v). if the output voltage of the dc/dc co nverter falls drastically due to a short-circuit or other load cond itions, the output voltage of the error amplifier rises 1.9 v or mor e, and the external cscp1 and cscp2 capacitors are further charged. when the cscp1 or cscp2 capacitors are charged to about 2.0 v, a latch is set that turns off the external p-ch/n-ch mosfets (dead time is set to 100% ). at this time, the latch input is close d and the cscp1 and cscp2 pins (pins 8 and 9) are held at the ?l? leve l. once the protection circuit has been activated, it can be re set by allowing the vb pin (pin 4) volt age to 3.8 v (minimum) or loss by turning the power off and on again. t cscp ? 0.019 cscp r t t cscp :short-circuit detection time [s] cscp :capacitance of cscp pin [ f] r t :timing resistance [k ] soft-start circuit error amp (1.0 v) -ine1 cscp1 r1 r2 vb ic1 ic2 vo fb1 uvlo 7 8 6 cscp 10 (-ine2) (fb2) 11 9 (cscp2) ics r t : timing resistor ic1[a] ? 3.7 10 ? 5 /r t [k ] ic2[a] ? 1.7 10 ? 5 /r t [k ] l priority
document number: 002-08369 rev. *b page 15 of 53 mb39c011a timer-latch short-circuit protection circuit (1.9 v) ic1 ic2 uvlo cscp1 s r latch scp comp. vb vo r1 r2 error amp1 (1.0 v) -ine1 fb1 to drive (2.0 v) 2.5 v (-ine2) 6 7 10 (fb2) 11 8 9 (cscp2) ics
document number: 002-08369 rev. *b page 16 of 53 mb39c011a soft-start and short-circuit protection timing chart (1) (2) (3) (4) (5) (6) (7) t ts 2.0 v 1.3 v 1.0 v tcscp cscp voltage soft-start time short-circuit detection time output short output short 1. when the ctl pin (pin 13) is set to the ?h? level and the ic becomes active, the voltages of the cscp1 and cscp2 pins (pins 8 and 9) rise due to the capacitors atta ched externally to the cscp1 and cscp2 pi ns (pins 8 and 9) being charged. during this time, error amp1 and error amp2 ar e controlled by the cscp1 and cscp2 pins (pins 8 and 9) and the -ine1 and -ine2 pins (pins 7 and 10) inputs, thus performing a soft-start. 2. when the cscp1 and cscp2 pins (pins 8 and 9) reach 1 v or more, error amp1 an d error amp2 become controlled by the internal reference voltage (1 v) and the -ine1 and -ine2 pin (pin s 7 and 10) inputs, and the output voltage is held at a consta nt level. 3. the cscp1 and cscp2 pins (pins 8 and 9) are clampe d to about 1.3 v. 4. when there is a short circuit in the lo ad and the error amplifier outpu t becomes 1.9 v or more, th e short-circuit protection comparator (scp comp.) is activated and the cscp1 and cscp2 capacitors are charged further. 5. if the short-circuit in the load is cleared within th e short-circuit detection time t cscp , the cscp1 and cscp2 pins (pins 8 and 9) return to the clamping voltage of about 1.3 v. 6. when there is a short-circuit in the load and the error amplifier output becomes 1. 9 v or more, the short-circuit protection comparator (scp comp.) is activated and the cscp1 and cscp2 capacitors are charged further. 7. the latch is set when the load sh ort-circuit is not released even if short-circuit detection time t cscp passes, external mos fet p-ch/n-ch are turned off, and the cscp1,cscp2 pins (pins 8 and 9) ar e hold at ?l? level.
document number: 002-08369 rev. *b page 17 of 53 mb39c011a notes : the output is stopped by the sh ort-circuit protection (s cp) function when the dc/dc output is short-circuited to gnd etc. however, care needs to be taken because the short-circuit prot ection (scp) function will no t stop the output when a half short-circuit occurs. measures such as plac ing a fuse in the input can be used for th is situation. [ half short-circuit refers to a short-circuit condition where an overcu rrent flows, but it is not sufficie nt to reduce the output voltage.] in the event that an output short curren t flows that exceeds the capac ity of the input power supply , the power supply voltage may drop. if the power supply voltage at th is time drops below 3.8 v, the output is stopped by the under voltage lockout protection circuit (uvlo). however, once the input power supp ly voltage recovers after the output has been stopped, the output will begin again. care needs to be taken because this situat ion may result in a repeat ing cycle of ?short-circuit power-supply voltage drop output stop power-supply voltage recovery output start short-circuit?. there are putting a fuse in the input etc. as measures. notes the short-circuit protection (scp) fu nction when the dc/dc converter is starte d/stopped. the output may also be stopped by the short-circuit protection (scp) function under the fo llowing conditions. ? operations that act on the input power supply and the ctl pin (f or example, shorting the input power supply to the ctl pin). ? during the transition period when the input power supply voltage (v in ) is changing (such as when the input power supply is turned on or turned off), the condition is met that input power supply voltage (v in ) < output setting voltage (v o ). although this is normal ic operation, as an example of startup of the ic, the output may be st opped due to the following process. (1) dc/dc converter outp ut begins when v in ( = vb) > uvlo threshold voltage. (2) a period of time occurs where the input power supply voltage (v in ) < the output voltage setting (v o ), and the duty cycle becomes 100% on. the error ampl ifier output rises ab ove 1.9 v due to the feedback control. (3) the output is stopped after the shor t-circuit detection time has elapsed.
document number: 002-08369 rev. *b page 18 of 53 mb39c011a furthermore, when turning off the input power supply, set the ctl pin to ?l? befo re turning off the input power supply. 8.2.3 under voltage lockout protection circuit (uvlo) a drop in the power supply vo ltage may cause the ic to malfunction, result ing in breakdown or degradation of the system. to prevent such malfunctions, the under voltage lockout protec tion circuit detects decreases in vb voltage due to the power supply voltage, and locks, the out1-1 pin (pin 2) and out2-1 pin (pin 15) at the ?h? level and the out1-2 pin (pin 3) and out2-2 pin (pin 14) at the ?l? level. th e system is restored if the vb voltage rises above the threshold voltage of the under voltage lockout protection circuit. function table when the protection circuit (uvlo) is operating when the uvlo circuit is operating (the vb voltage is below the uvlo threshold voltage), the following pins are fixed at the following logic levels. out1-1 out1-2 out2-1 out2-2 cscp1 cscp2 hlhlll example where the output stops when the dc/dc converter is activated by the input power supply (example of output stopped by scp during startup) in this case, the output can be pr evented from being stopped by the scp function during startup by controlling the ctl pin independently. example of the dc/dc converter being started by the ctl pin (1) (2) (3) output voltage setting time [s] output voltage (v o ) input power supply voltage v in ( = ctl) voltage [v] ctl output voltage setting time [s] output voltage (v o ) input power supply voltage v in voltage [v]
document number: 002-08369 rev. *b page 19 of 53 mb39c011a 8.2.4 operation when ctl is turned on and off when ctl is turned on, the internal refe rence voltages vr1 and vb begi n to rise. when vb exce eds the threshold voltage (vth) of uvlo (under voltage lockout prot ection circuit), uvlo is released, and the output drive circuits of each channel are allowed to operate.when ctl is off, th e output drive circuit of each channel is locked in the full off state and the cscp1 and cscp2 pins (pins 8 and 9) ar e fixed at the ?l? level, even if the uvlo circuit is in the clear state. when the internal reference voltages vr1 and vb begin to fall and when vb falls below the threshol d voltage of the uvlo (under voltage lockout protection circuit), th e uvlo circuit is activated. 8.2.5 independent control of each channel the on/off state of each output voltage can be controlled independently by externally connecting the cscp1 and cscp2 pins (pins 8 and 9) to the drain pin of an nmos transistor or to an nmos open dr ain pin of a microcontroller, etc. when the cscp1 or cscp2 pins (pins 8 and 9) is se t to the ?l? level by turning on the exte rnal nmos transistor , the output voltage turns off. furthermore, when the external nmos transistor is turned off, the soft-st art function begins and the output voltage turns on. note that the internal operatio n of the ic continues when the output voltages are turn ed off using the cscp1 and cscp2 pins (pins 8 and 9). set the ctl pin (pin 13) to the ?l? level to ente r standby mode (the maximum power supply current in standby mode is 10 a). ctl v t vo1 vo2 ctl1 ctl2 mb39c011a ctl cs ctl1 cs ctl2 cscp1 ctl cscp2
document number: 002-08369 rev. *b page 20 of 53 mb39c011a 9. switching scheme selection this device can operate even by a sync hronous rectification and an asynchronous rectification. there is superiority or inferiority respectively. select the switchin g type considering the features as a guide. switching type parts feature asynchronous rectification p-ch fet + fly-back diode superior cost advantages under large load currents and low output voltages, it is inefficient because generation of heat of the fly-back diode (sbd) is large. synchronous rectification p-ch fet + n-ch fet offers a balance between cost and efficiency. supports large load current s and low output voltages p-ch fet + n-ch fet + fly-back diode emphasis on efficiency (particularl y effective at high oscillator frequencies) supports large load current s and low output voltages because of the increased number of parts, the cost is a disadvantage.
document number: 002-08369 rev. *b page 21 of 53 mb39c011a 10. setting the output voltage t he output voltage can be set to an arbitrary value by the ratio of the feedback resistance to -ine1 (-ine2). set the output voltage to a valu e higher than the reference vo ltage (1 v) of the error amp. under usage conditions wh ere the duty cycle is 30 % or less, set v o 1 < v o 2 as much as possible. d = v o 100 v in d :duty cycle [ % ] v in :power supply voltage of switching system [v] v o :output setting voltage [v] r1, r2 :output voltage setting resistors [ ] r1 r2 vo (r1+r2) = r2 1.0 vo1,2 cscp1 (cscp2) -ine1 (-ine2) 10 7 9 8 1.0 v error amp
document number: 002-08369 rev. *b page 22 of 53 mb39c011a 11. setting the triangular oscillation frequency the triangular oscillation frequency is determined by the timing resistor (r t ) connected to the rt pin (pin 5). fosc : triangular osci llation frequency [khz] r t : timing resistance [k ] the upper limit on the oscillation frequency that can be set dep ends on the junction temperature and duty cycle. it is recommen ded that the device is used within the range shown in the following graph. note : refer to ? power dissipation and thermal design ? for details on calculatin g the junction temperature. 11.1 power dissipation and thermal design i t is necessary to examine it for the use at a high power-supply voltage, a high osci llation frequency, and the high temperature . also use within the range of ? oscillation frequency vs. junction temperature ? . the junction temperature can be investigated from the internal power dissipation of the ic. the internal power dissipation of the ic (p ic ) is given by the following formula. p ic = v cc (i cc + qg fosc) the junction temperature is gi ven by the following formula. fosc ? 0.001 122.4 10 ? 12 r t 10 3 + 96 10 ? 9 p ic : internal ic power dissipation [w] v cc : power supply voltage (vin : [v]) i cc : power supply current (3.3 ma max) qg : total electric charge (vgs = 5 v) of all sw fet for 2ch [c] fosc : oscillation frequency [hz] 2100 1900 1700 1500 1300 1100 900 700 500 300 100 -30 0 +30 +60 +90 +120 oscillation frequency fosc (khz) oscillation frequency vs. junction temperature junction temperature tj ( ? c )
document number: 002-08369 rev. *b page 23 of 53 mb39c011a tj = ta + ja p ic tj :junction temperature ( + 125 ? c max) ta :ambient temperature [ ? c] ja :tssop-16 package thermal resistance (94 ? c/w) p ic :internal ic power dissipation [w] notes : ? refer to ? setting the output voltage ? for details on calc ulating the duty cycle. ? when using the ic outside of the ranges shown in the above graphs, check for jitter and other adverse effects on the output voltage before use. synchronous rectification, at 4.5 v v in 6 v (vcc = vb) synchronous rectification, at v in > 6 v(vb = 5 v) duty cycle vs. oscillation frequency d uty cycle vs. oscillation frequency duty cycle d( % ) duty cycle d( % ) oscillation frequency fosc(khz) o scillation frequency fosc(khz) asynchronous rectification, at 4.5 v v in 6 v(vcc = vb) asynchronous rectification, at v in > 6 v(vb = 5 v) duty cycle vs. oscillation frequency d uty cycle vs. oscillation frequency duty cycle d( % ) duty cycle d( % ) oscillation frequency fosc(khz) o scillation frequency fosc(khz) 100 80 60 40 20 0 0 500 1000 1500 2000 applicability 100 80 60 40 20 0 0 500 1000 1500 2000 applicability 100 80 60 40 20 0 0 500 1000 1500 2000 applicability 100 80 60 40 20 0 0 500 1000 1500 2000 applicability
document number: 002-08369 rev. *b page 24 of 53 mb39c011a 12. setting the soft-start and short-circuit detection times set the soft-start time and the short- circuit detection time using the cscp pins. both become the same time. ts = t cscp ? 0.019 cscp r t 13. vb pin and vh pin connections in condition of vcc voltage in the range of 4.5 v vcc 6.0 v, there is a chance that the vb voltage [1] and vh voltage [2] may drop due to the internal ic regulator saturating. as a resul t, there are drive voltage shortage and a bird cl apper of sw fet. it is therefore recommended t hat the vb pin (pin 4) and vh pin (pin 16) are connected as show n in the ?vb pin and vh pin connection table?. [1]: voltage between vb pin (pin 4) and gnd pin (pin 12) : 5 v [2] : voltage between vcc pin (pin 1) and vh pin (pin 16) : 5 v vb pin and vh pin connection table [3]: check that the switching oper ation is functioning normally. [4]: refer to the connection of the vb pin (p in 4) and the vh pi n (pin 16) in the ? block diagram ?. ts :soft-start time (time to output voltage 100 % ) [s] t cscp :short-circuit detection time [s] cscp :cscp pin capacitor [ f] r t :timing resistance [k ] vcc condition vb pin vh pin 4.5 vcc 6 v connected to vcc connected to gnd 6 v vcc 17 v vb capacitor connection [4] vh capacitor connection [4] used with vcc crossing 6 v [3] (ex. 5 v vcc 7 v) vb capacitor connection [4] vh capacitor connection [4]
document number: 002-08369 rev. *b page 25 of 53 mb39c011a transition diagram of the vb voltage and vh voltage (vb pin: vb capacitor connection , vh pin: vh capacitor connection) 5 v vcc voltage vb voltage vb pin voltage vh pin voltage vh voltage power supply voltage vcc vcc ? 6 v
document number: 002-08369 rev. *b page 26 of 53 mb39c011a 14. design of phase compensation circuit 14.1 phase compensation circuit when low esr capacitor is used as output capacitor when a low-esr capacitor such as a cerami c capacitor is used as the output capacito r, it becomes easy to vibrate for a phase delay of the 180 to be generated due to th e resonant frequency of the lc. in this ca se, it is common to use a phase compensati on circuit that can advance the phase, such as a 2-pole/2-zero circuit. set the r3, rc, c1, and cc constants in th e phase compensation circuit by using the following formula as a guide. as for freque ncy (f co ) of crossover, in which the band width of the control loop of dc/dc is shown, height is excellent in the rapid response. howev er, vibration may be generated due to an in sufficient phase margin. although the crossover frequency (f co ) can be set to any value, the maximum value must be 1/2 of the oscillation frequency (f osc ), or 1/5 of the oscillation frequency (f osc ) as preferable. furthermore , the crossover frequency (f co ) should be set such that the phase margin is a minimum of 30, or mo re than 45 as preferable. 2-pole/2-zero phase compensation circuit v o 1,v o 2 fb1,fb2 error amp1,amp2 vref - + r2 -ine1,-ine2 r3 rc cc r1 c1 to pwm comp.1,2
document number: 002-08369 rev. *b page 27 of 53 mb39c011a 14.2 notes on phase compensation circuit constants select the constants of the following three points and select the consta nt for the design of the phas e compensation circuit whe n the large load sudden change, or the capacito r is connected to dc/d c converter operating. in particular, if a capacitance much larg er than the output capacitance of the dc/ dc converter is connected by hard-switching while the dc/dc converter is operating, the output voltage may begin vibrating or the protection function may be activated, due to the sudden response. note the following points. 14.2.1 error amp output (fb1 and fb2 pins) current capacity the resistance constants of the phase compen sation circuit need to be designed by c onsidering the current ca pacities of the err or amp outputs (fb1 and fb2 pins (pins 6 a nd 11)). take the outp ut source current ( ? 300 a max) of the error amp an d the threshold voltage v t100 (1.7 v typ) of the pwm comp into consideration, select the resistance values such that th e following formula is satisfied. although low resistance values may be desi red to improve the noise immunity, the abov e formula may not be satisfied as a result . while it is ideal for each of the resistance values to satisfy the above formula, in this situation the values may be used afte r confirming that there are no problems when us ed under the rapidly varying load conditions. 14.2.2 phase margin at the output load changes select phase compensation constants that en sure the phase margin when the output load (resistive load, capacitative load, inductive load) is connected. r3 ? f lc r1 r3, rc : [ ] 2 f esr ? f lc c1, cc : [f] f lc : resonant frequency [hz] of the coil l [h] and output capacitor c [f] c1 ? 1 f esr : resonant frequency [hz] of th e output capacitor c [f] and esr [ ] f lc (r1 + r3) rc ? (r1//r3) f esr f co v in f lc 2 f co : crossover frequency (arbitrary setting) [hz] cc ? 1 r1//r3 : resistance of r1 a nd r3 connected in parallel [ ] 2 r c f lc v in : switching system power supply voltage [v] 300 [ a] > 1.7 [v] r1//r2//r3 = resistance of r1, r2 and r3 connected in parallel [ ] r1//r2//r3 + r c r c : [ ] f lc = 1 2 l c f esr = 1 2 esr c
document number: 002-08369 rev. *b page 28 of 53 mb39c011a 14.2.3 phase margin at the reverse current flow from the output pin under usage conditions where current from the dc/dc converter output (vo) pin flows by the load sudden change, select phase compensation constants that ensure the phas e margin even when reverse current flow occurs. example of measuring the phase margin during reverse current flow r dc/dc v in v o
document number: 002-08369 rev. *b page 29 of 53 mb39c011a 15. handling the unused channel pins when using a single channel although this device is a 2-channel dc/dc co nverter control ic, it is also able to be used as a 1-channel dc/dc converter by handling the pins of the unused channe l as shown in the following diagram. 1. connection when ch 1 is not used out1-2 cscp1 8 3 fb1 -ine1 6 7 2 out1-1 ?open? ?open? ?open?
document number: 002-08369 rev. *b page 30 of 53 mb39c011a 2. connection when ch 2 is not used -ine2 cscp2 15 out2-1 fb2 out2-2 14 11 10 9 ?open? ?open? ?open?
document number: 002-08369 rev. *b page 31 of 53 mb39c011a 16. i/o equivalent circuit (continued) gnd ctl vcc vb gnd vcc rt vb gnd vb fbx gnd 4 13 5 x : each channel no.
document number: 002-08369 rev. *b page 32 of 53 mb39c011a (continued) vb cscpx gnd -inex vh gnd vcc vh outx-1 vcc gnd outx-2 vb gnd gnd 1 16 12 x : each channel no.

document number: 002-08369 rev. *b page 33 of 53 mb39c011a 17. example application circuit r9 c5 r12 r13 c6 r10 r7 c4 r3 c3 r6 r4 gnd v in v o1 gnd1 vcc out1-1 out1-2 vh vb cscp1 cscp2 out2-1 out2-2 v o2 gnd2 fb2 fb1 -ine2 -ine1 ctl rt r1 q1 q2 q3 q4 l1 l2 c11 c13 c2 c1 c7 c8 c9 gnd c10 c12 2 3 4 9 8 14 15 7 6 10 11 13 5 16 1 mb39c011a ctl 1.8 v 3.3 v 12
document number: 002-08369 rev. *b page 34 of 53 mb39c011a 18. parts list component item specification component item specification q1 p-ch fet vds = ? 30 v, id = ? 4 a (max) c1 ceramic condenser 0.015 f (50 v) q2 n-ch fet vds = 30 v, id = 5 a (max) c2 ceramic condenser 0.015 f (50 v) q3 p-ch fet vds = ? 30 v, id = ? 4 a (max) c3 ceramic condenser 100 pf (50 v) q4 n-ch fet vds = 30 v, id = 5 a (max) c4 ceramic condenser 470 pf (50 v) r1 resistor 16 k c5 ceramic condenser 220 pf (50 v) r3 resistor 2 k c6 ceramic condenser 2200 pf (50 v) r4 resistor 5.1 k + 75 k c7 ceramic condenser 0.1 f (50 v) r6 resistor 100 k c8 ceramic condenser 1 f (16 v) r7 resistor 10 k c9 ceramic condenser 1 f (16 v) r9 resistor 1 k c10 ceramic condenser 22 f (25 v) r10 resistor 1.5 k + 33 k c11 ceramic condenser 33 f (6.3 v) r12 resistor 15 k c12 ceramic condenser 22 f (25 v) r13 resistor 5.6 k c13 ceramic condenser 33 f (6.3 v) l1 inductor 3.3 h (idc = 6.7 a) --- l2 inductor 4.7 h (idc = 6 a) ---
document number: 002-08369 rev. *b page 35 of 53 mb39c011a 19. part selection 19.1 coil selection as a rough guide, choose the inductance of the coil such that the peak-to-peak ripple current of the coil is less than 50 % of the maximum load current. the inductance in th is case is given by the following formula. when the ic is used with asynchronous rect ification, it is recommended that the ic be used in the load current range where the coil current is continuous in order to ensure responsiveness to the load. for a synchronous rectification it is therefore recomm ended that the minimum value of the lo ad current is used as the basis for setting the inductance value. the maximum value of the current flowing th rough the coil needs to be found in order to determine whether the current flowing through the coil is with in the rated value. the maximum cu rrent flowing through the coil is given by the following formula. l v in ? v o v o lor i omax v in fosc l : coil inductance [h] i omax : maximum load current [a] lor : 0.5 v in : switching system powe r-supply voltage [v] v o : output voltage setting [v] fosc : oscillation frequency [hz] l v in ? v o v o 2 i omin v in fosc l : coil inductance [h] i omin : minimum load current [a] v in : switching system powe r-supply voltage [v] v o : output voltage setting [v] fosc : oscillation frequency [hz] il max = i omax + il 2 il v in ? v o v o lv in fosc il il max i omax i omin 0 the coil current changes according to the load current. time coil current
document number: 002-08369 rev. *b page 36 of 53 mb39c011a 19.2 sw fet selection the maximum value of the current flowing through the sw fet needs to be found in order to determine whether the current flowing through the sw fet is within the rated valu e. the maximum current flowing through the sw fet is given by the following formula. furthermore, the power diss ipation of the sw fet needs to be found in order to det ermine whether the powe r dissipation of the sw fet is within the rated value. the power dissipation of the sw fet is given by the following formula. high side fet (p-ch mos fet) power dissipation p hisidefet = p ron + p sw il max : maximum coil current [a] i omax : maximum load current [a] il : coil ripple current peak to peak value [a] l : coil inductance [h] v in : switching system powe r-supply voltage [v] v o : output setting voltage [v] fosc : oscillation frequency [hz] i dmax i omax + il 2 i dmax : maximum sw fet drain current [a] i omax : maximum load current [a] il : coil ripple current peak to peak value [a] p r on : high side fet (p-ch mos fet) conduction loss p ron = i omax 2 v o ron v in i omax : maximum load current [a] v in : switching system power supply voltage [v] v o : output voltage [v] ron : high side fet on resistance [ ] p sw : high side fet (p-ch mo s fet) switching loss p sw = v in f osc (ibtm tr itop tf) 2 v in : switching system power supply voltage [v] fosc : oscillation frequency [hz] ibtm : bottom value of ripple current of coil [a] ibtm = i omax ? il 2 itop :top value of ripple current of coil [a] itop = i omax + il 2
document number: 002-08369 rev. *b page 37 of 53 mb39c011a tr and tf are simply obtain ed by the following formula. to select sw fets that offer good conversion efficiency, the high side fet in particular should select such that the switching loss is small (the power dissipated wh en the sw fet changes between on and off). however, beca use there is generally a trade-off between switching loss and conduction loss, this balance needs to be cons idered when making the selection. as a guide, select fets such that the total qg of the sw fets is as follows. the sw fets used with this device typicall y have a drive voltage of 4 v. although ther e are fets that support a drive voltage o f less than 4 v, low drive voltage fets genera lly have a larger qg even at equal value of ron, the efficiency lowers. if a fet wi th a low drive voltage is used, check that the low side fet does not self turn-on and t hat the dead-time is secured under the usag e conditions. il : coil ripple current peak to peak value [a] tr : turn-on time of high side fet [s] tf : turn-off time of high side fet [s] tr = qgd 4 tf = qgd 4 5 ? vgs (on) vgs (on) qgd : quantity of charge between the gate and drain of high side fet [c] vgs(on) : absolute value of voltage diffe rence between the gate and source of the high side fet at qgd [v] low side fet(n-ch mos fet) conduction loss p losidefet = p ron = i omax 2 (1 ? v o ) ron v in p ron : low side fet conduction loss [w] i omax : maximum load current [a] v in : switching system power supply voltage [v] v o : output voltage [v] ron : low side fet on resistance [ ] qghisidefet< 0.04 qglosidefet< 0.04 fosc fosc qghisidefet : sum total electric charge of the ch1 and ch2 high side fets [c] qglosidefet : sum total electric charge of the ch1 and ch2 low side fets [c] fosc : oscillation frequency [hz]
document number: 002-08369 rev. *b page 38 of 53 mb39c011a 19.3 fly-back diode selection select a schottky barrier diode (sbd) th at has a small forward voltage drop. the peak current flowing through the fly-back diode needs to be found in order to determine whether the current flowing through the fly-back diode is within the rated value. when the dc/dc converter ic is used with asynchronous rectification, the maximum current through the fly-back diode is given by the fo llowing formula. furthermore, the power dissipation of the fly-back diode needs to be found in order to determine whether the power dissipation of the fly-back diode is within the rated value. the power dissipation of the fly-ba ck diode is given by the following formula. when the dc/dc converter is used with sync hronous rectification, the le ngth of time that the current flows through the fly-back diode is limited to the synchronous rectific ation period (dead time). for example, at an oscillating frequency of 500 khz, the proportion of time that current flows is less than 5 % . therefore, select that fly-back diode current does not exc eed the peak forward surge current (ifsm) rated value. the pe ak forward surge current va lue of the sbd is given by the following formula. i f i omax il 2 i f : forward current [a] i omax : maximum load current [a] il : coil ripple current peak to peak value [a] p sbd = i omax (1 ? v o ) vf v in p sbd : fly-back diode power dissipation [w] i omax : maximum load current [a] v in : switching system power supply voltage [v] v o : output voltage [v] vf :forward voltage [v] i fsm i omax + il 2 i fsm : peak forward surge current value of fly-back diode [a] i omax : maximum load current [a] il : coil ripple current peak to peak value [a]
document number: 002-08369 rev. *b page 39 of 53 mb39c011a 19.4 output capacitor selection because the ripple voltage increases if the esr is large, a low esr capacitor needs to be used in order to reduce the ripple vo ltage. however, using a capacitor with a low esr has a large effect on th e phase characteristics of the lo op, and care needs to be tak en to prevent the system from losi ng stability. furthermore, the capacitor that is us ed should have sufficient tolerance for the r ipple current. if taking into account the switching ripp le voltage, the minimum nec essary capacitance is giv en by the following formula. when a capacitive load is connected, it is recommended that the dc/dc converter output capa citor have the same capacitance as the load capacitance. the allowable ripple current of the output capacitor is given by the following formula. 19.5 input capacitor selection select an input capacitor that has as small an esr as possible. ceramic capacitors are ideal. if a large capacitance is require d that cannot be provided by a ceramic capa citor, use a polymer capacitor or a tantalum capacitor with a low esr. furthermore, th e capacitor that is used should have suff icient tolerance for the ripple current. the allowable ripple current is given by the following formula. c o 1 2 fosc ( v o / il ? esr) esr : series resistance elemen t of output capacitance [ ] v o : switching ripple voltage [v] il : coil ripple current peak to peak value [a] c o : output capacitance [f] fosc : oscillation frequency [hz] irms il 2 3 irms : allowable rippl e current (root-mean-square value) [a] il : coil ripple current peak to peak value [a] irms i omax v o (v in ? v o ) v in irms : allowable ripple current (root-mean- square value) [a] i omax : maximum load current [a] v in : switching system power supply voltage [v] v o : output voltage [v]
document number: 002-08369 rev. *b page 40 of 53 mb39c011a 19.6 vb pin capacitor although the vb pin capa citor typically has a capacitance of 1 f, this needs to be adjusted if the sw fet being used has a large qg. the following formula provides a guide to the lower limit of the vb pin capa citor. if this lower limit exceeds 1 f, use the formula as a guide to set the capacitance. cvbmin 0.1 qglosidefet 19.7 vh pin capacitor the vh pin capacitor typically has a capacitance of 1 f (when the vb pin capacitor 1 f). however, this needs to be adjusted, if the vb pin capacitor exceeds 1 f or if the sw fet being used has a large qg. the following formula provides a guide to the lower limit of the vh pin capacitor. if th is lower limit exceeds 1 f, use the formula as a guide to set the capacitance. large one either of cvhmin 0.01 qghisidefet or cvhmin cvb cvbmin : lower limit of vb pin capacitor [ f] qglosidefet : sum total electric charge of ch1 and ch2 low side fets [nc] cvhmin : lower limit of vh pin capacitor [ f] qghisidefet : sum total electric charge of ch1 and ch2 high side fets [nc] cvb : capacitance of vb pin capacitor [ f]
document number: 002-08369 rev. *b page 41 of 53 mb39c011a 20. pcb layout consider the following points wh en designing the pcb layout : ? make the input capacitor (cin), sw fet, fl y-back diode (sbd), coil (l), and output ca pacitor (cout) connec tions on the surface as much as possible, and avoid making the connections with the through-holes. ? take the most care with the loop consisting of the input capa citor (cin), sw fet, and fly-back diode (sbd), and make the current loop as small as possible. ? create through-hole directly ne xt to the gnd pins of the i nput capacitor (cin), sw fet, fly-back diode (sbd), and output capacitor (cout), and connect these to the sw system gnd inner layer. ? large currents flow momentarily through the wiring of the outx-x pins that ar e connected to the sw fet gates. use a wiring width of about 0.8 mm as a guide, and make the wiring as short as possible. ? arrange the bypass capacitors that are connect ed to the vcc, vb, and vh pins (pins 1, 4, and 16) near the pins as possible. furthermore, connect the gnd pin of th e vcc and vb by-pass capacitor with a nearest gnd pin of the ic. (create a through-hole directly next to the gnd pi n of the ic (pin 12) and the gnd pins of the bypass capacitors to reinforce the connection to the inner ground layer). ? the wiring for the -ine1, -ine2, fb1, fb2, and rt pins (pins 7, 10, 6, 11, and 5) is sensitive to noi se and should be made as short as possible. furthermore, th e feedback line from the output (v o ) should be kept as far aw ay from sw system components as possible. ? create as much ground plane on the side wher e the ic is mounted as possible. to prev ent creating a large current path to the control system gnd, connect this to the pgnd (sw system gnd) at a single point.
document number: 002-08369 rev. *b page 42 of 53 mb39c011a (layer1) (layer2) vcc vh vb rt cin swfet swfet cout l v in sbd v o surface gnd layer control system gnd control system gnd and sw system gnd are connected by one point. through-hole control system gnd sw system gnd sw system gnd feedback line to -ine example of arranging sw system parts gnd wiring example sw system gnd
document number: 002-08369 rev. *b page 43 of 53 mb39c011a 21. reference data (continued) ch1 ch2 conversion efficiency vs. load current c onversion efficiency vs. load current conversion efficiency ( % ) conversion efficiency ( % ) load current i o1 (a) load current i o2 (a) output voltage vs. load current output voltage vs. load current output voltage v o1 (v) output voltage v o2 (v) load current i o1 (a) load current i o2 (a) 100 95 90 85 80 75 70 65 60 0.0 0.5 1.0 1.5 2.0 2.5 3.0 ta = + 25 ? c v in = 12 v v o1 = 1.8 v fosc = 500 khz 0.0 0.5 1.0 1.5 2.0 2.5 3.0 100 95 90 85 80 75 70 65 60 ta = + 25 ? c v in = 12 v v o2 = 3.3 v fosc = 500 khz 1.84 1.83 1.82 1.81 1.80 1.79 1.78 1.77 1.76 0.0 0.5 1.0 1.5 2.0 2.5 3.0 ta = + 25 ? c v in = 12 v v o1 =1.8 v setting fosc = 500 khz 3.34 3.33 3.32 3.31 3.30 3.29 3.28 3.27 3.26 0.0 0.5 1.0 1.5 2.0 2.5 3.0 ta = + 25 ? c v in = 12 v v o2 = 3.3 v setting fosc = 500 khz
document number: 002-08369 rev. *b page 44 of 53 mb39c011a (continued) out-1 out-2 ta = + 25 ? c v in = 12 v v o1 = 1.8 v fosc = 500 khz out-1 out-2 ta = + 25 ? c v in = 12 v v o2 = 3.3 v fosc = 500 khz i o 1 2 a/div v o 1 500 mv/div i o 2 2 a/div v o 2 500 mv/div ctl 5 v/div v o 2 1 v/div v o 1 1 v/div ch1 switching wave form ch2 switching wave form 5 v/div, 80 ns/div 5 v/div, 200 ns/div ch1 sudden load variation waveform ch2 sudden load variation waveform 40 s/div 40 s/div ctl startup waveform 1 ms/div ta = + 25 ? c v in = 12 v, v o 1=1.8 v, i o1 = 3 a, v o 2 = 3.3 v, i o2 = 3 a, fosc = 500 khz soft start setting time = 4.5 ms ta = + 25 ? c v in = 12 v v o1 = 1.8 v i o1 = 0 ? 3 a fosc = 500 khz ta = + 25 ? c v in = 12 v v o2 = 3.3 v i o2 = 0 ? 3 a fosc = 500 khz
document number: 002-08369 rev. *b page 45 of 53 mb39c011a 22. usage precaution 22.1 do not configure the ic over the maximum ratings if the ic is used over the maximum ra tings, the lsi may be permanently damaged. it is preferable for the device to normal ly operate within the recommended usage co nditions. usage outside of these conditions can have a bad effect on the reliability of the lsi. 22.2 use the device within the recommended operating conditions the recommended operating conditions are under which the ls i is guaranteed to ope rate. the electrical ratings are guaranteed when the device is used within the re commended operating conditio ns and under the condition s stated for each item. 22.3 printed circuit board ground lines sh ould be set up with consideration for common impedance 22.4 take appropriate measures against static electricity ? containers for semiconductor materials should have anti-static protection or be made of cond uctive material. ? after mounting, printed circuit boards should be stor ed and shipped in conducti ve bags or containers. ? work platforms, tools, and instru ments should be properly grounded. ? working personnel should be gro unded with resistance of 250 k to 1 m between body and ground. 22.5 do not apply negative voltages the use of negative voltages below ? 0.3 v may create parasitic transistors on lsi lines, wh ich can cause malfunctions.
document number: 002-08369 rev. *b page 46 of 53 mb39c011a 23. ordering information 24. ev board ordering information part number package remarks mb39c011apft- ??? e1 16-pin plastic tssop (fpt-16p-m07) lead-free version part number ev board version no. remarks MB39C011AEVB-01 board rev.1.0 tssop-16-pin
document number: 002-08369 rev. *b page 47 of 53 mb39c011a 25. rohs compliance information of lead (pb) free version the lsi products with ?e1? are compliant with rohs directive, and has observed the standard of lead, cadmium, mercury, hexavalent chromium, polybrominated biphen yls (pbb), and polybrominated diphenyl et hers (pbde). products that are complied with this standard have ?e1? appended to the part number. 26. marking format (lead-free version) xxxx xxx index lead-free version
document number: 002-08369 rev. *b page 48 of 53 mb39c011a 27. labeling sample (lead-free version) 2006/03/01 assembled in japan g qc pass (3n) 1mb123456p-789-ge1 1000 (3n)2 1561190005 107210 1,000 pcs 0605 - z01a 1000 1/1 1561190005 mb123456p - 789 - ge1 mb123456p - 789 - ge1 mb123456p - 789 - ge1 pb the part number of a lead-free product has the trailing characters "e1". lead-free mark jeita logo jedec logo
document number: 002-08369 rev. *b page 49 of 53 mb39c011a 28. mb39c011apft- ??? e1 recommended mounting conditions 28.1 recommended mounting conditions item condition mounting method ir (infrared reflow), manual so ldering (partial heating method) mounting times 2 times storage period before opening please use it within two years after manufacture. from opening to the 2nd reflow less than 8 days when the storage period after opening was exceeded please processes within 8 days after baking (125 ? c , 24h) storage conditions 5 ? c to 30 ? c , 70 % rh or less (the lowest possible humidity)
document number: 002-08369 rev. *b page 50 of 53 mb39c011a 28.2 parameters for each mounting method 28.2.1 ir (infrared reflow) 28.2.2 manual soldering (partial heating method) conditions : temperature 400 ? c max times : 5 s max/pin 260 c (e) (d') (d) 255 c 170 c 190 c rt (b) (a) (c) to note : temperature : the top of the package body (a) temperature increase gradient : average 1 ? c/s to 4 ? c/s (b) preliminary heating : temperature 170 ? c to 190 ? c, 60s to 180s (c) temperature increase gradient : average 1 ? c/s to 4 ? c/s (d) actual heating : temperature 260 ? c max; 255 ? c or more, 10s or less (d?) : temperature 230 ? c or more, 40s or less or temperature 225 ? c or more, 60s or less or temperature 220 ? c or more, 80s or less (e) cooling : natural co oling or forced cooling h rank : 260 ? c max
document number: 002-08369 rev. *b page 51 of 53 mb39c011a 29. package dimensions 16-pin plastic tssop lead pitch 0.65 mm package width package length 4.40 5.00 mm lead shape gullwing sealing method plastic mold mounting height 1.10mm max weight 0.06g code (reference) p-tssop16-4.4 5.0-0.65 16-pin plastic tssop (fpt-16p-m07) (fpt-16p-m07) c 2003 fujitsu limited f16020s-c-3-3 5.00?.10(.197?004) 4.40?.10 6.40?.20 (.252?008) (.173?004) 0.10(.004) 0.65(.026) 0.24?.08 (.009?003) 1 8 16 9 "a" 0.17?.05 (.007?002) m 0.13(.005) details of "a" part 0~8 ? (.024?006) 0.60?.15 (0.50(.020)) 0.25(.010) (.041?002) 1.05?.05 (mounting height) 0.07 +0.03 ?.07 +.001 ?003 .003 (stand off) lead no. index * 1 * 2 dimensions in mm (inches). note: the values in parentheses are reference values. ?003-2008 fujitsu microelectronics limited f16020s-c-3-4 note 1) * 1 : resin protrusion. (each side : +0.15 (.006) max). note 2) * 2 : these dimensions do not include resin protrusion. note 3) pins width and pins thickness include plating thickness. note 4) pins width do not include tie bar cutting remainder.
document number: 002-08369 rev. *b page 52 of 53 mb39c011a document history spansion publication number: ds04-27260-2e document title: mb39c011a 2ch dc/dc converte r ic with synchronous r ectification datasheet document number: 002-08369 revision ecn orig. of change submission date description of change ** ? taoa 08/07/2008 migrated to cypress and assigned document number 002-08369. no change to document contents or format. *a 5187215 taoa 03/19/2016 updated to cypress template *b 5830510 masg 07/24/2017 adapted cypress new logo.
document number: 002-08369 rev. *b revi sed july 24, 2017 page 53 of 53 ? cypress semiconductor corporat ion, 2007-2017. this document is the property of cypr ess semiconductor corporation and its subs idiaries, including spansion llc ("cypress"). this document, including any software or firmware included or referenced in this document ("software") , is owned by cypress under the intellec tual property laws and treaties of th e united states and other countries worldwide. cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragr aph, grant any license under its patent s, copyrights, trad emarks, or other intellectual property right s. if the software is not accomp anied by a license agreement and yo u do not otherwise have a writte n agreement with cypress governing the use of the software, then cypress hereby grants you a personal, non-exclusive, nontransferable license (witho ut the right to sublicense) (1) under its copyright rights in the software (a) for softwa re provided in source code form, to modify and reproduce the software solely for use with cypress hardware products, only internally within your organization, and (b) to distribute the software in bi nary code form externally to end users (either directly or indi rectly through resellers and distributors), solely for use on cypre ss hardware product units, and (2) u nder those claims of cypress's patents that are infringed by the software (as provided by cypress, unmodified) to make, use, distribute, and import t he software solely for use with cypress hardware product s. any other use, reproduction, modi fication, translati on, or compilation of the software is prohibited. to the extent permitted by applicab le law, cypress makes no warrant y of any kind, express or implie d, with regard to this docum ent or any software or accompanying hardware, includ ing, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. to the extent permitted by applicable law, cypr ess reserves the right to make changes to this document without further notice. cypress does n ot assume any liability arising out of the applicati on or use of any product or circuit described in this document. any informati on provided in this document, incl uding any sample design informat ion or programming code, is provided only for reference purposes. it is the responsibility of the user of this docum ent to properly design, prog ram, and test the functional ity and safety of any appli cation made of this information and any resulting product. cypress products are not designed, inte nded, or authorized for use as critical components in systems designe d or intended for the operation of w eapons, weapons systems, nuclear instal lations, life-support devices or systems, other medical devices or systems (inc luding resuscitation equipment and surgical implants), pollution control or hazar dous substances management , or other uses wher e the failure of the device or system could cause per sonal injury, death, or property damage ("unintend ed uses"). a cr itical component is any compon ent of a device or system whose fa ilure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. cypress is not liable, in whol e or in part, and you s hall and hereby do release cypress from any claim, damage, or other liability ar ising from or related to all unin tended uses of cypress products. you shall indemnify and hold cyp ress harmless from and against all cl aims, costs, damages, and other liabilities, including claims for pe rsonal injury or death, arising from or related to any un intended uses of cypress products. cypress, the cypress logo, spansion, the spansion l ogo, and combinations thereof, wiced, psoc, capsense, ez-usb, f-ram, and tra veo are trademarks or regist ered trademarks of cypress in the united states and other countri es. for a more complete list of cypress trademarks, visit cyp ress.com. other names and brand s may be claimed as property of their respective owners. 53 mb39c011a sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representative s, and distributors. to find t he office closest to you, visit us at cypress locations . products arm ? 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