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preliminary rev. 0.5 8/15 copyright ? 2015 by silicon laboratories SI8920 this information applies to a product under development. its characteristics and specifications are subject to change without n otice. SI8920 i solated a mplifier for c urrent s hunt m easurement features applications safety approvals (pending) description the SI8920 is a galvanically isolated analog amplifier. the low-voltage differential input is ideal for meas uring voltage across a current shunt resistor or for any place where a sens or must be isolated from the control system. the output is a differential analog signal amplified by either 8.1x or 16.2x. the very low signal delay of the SI8920 allows control systems to respond quickly to fault conditions or changes in load. low offset and gain drift ensure that accuracy is maintained over the entire operating temperature range. exceptionally high common- mode transient immunity means that the SI8920 delivers accurate measurements even in the presence of high- power switching as is found in motor drive systems and inverters. the SI8920 isolated amplif ier utilizes silicon labs ? proprietary isolation technology. it supports up to 5.0 kvrms withstand voltage per ul1577. this technology enables higher performance, reduced variation with temperature and age, tighter part-to- part matching, and longer lifetimes compared to other isolation technologies. ? low voltage differential input ?? 100 mv and 200 mv options ? low signal delay: 0.75 s ? input offset: 0.2 mv ? gain error: <0.5% ? excellent drift specifications ?? 1 v/c offset drift ?? 60 ppm/c gain drift ? nonlinearity: 0.1% full-scale ? low noise: 0.10 mvrms over 100 khz bandwidth ? high common-mode transient immunity: 75 kv/s ? compact packages ?? 16-pin wide body soic ?? 8-pin surface mount dip ? ?40 to 125 c ? aec-q100 ? industrial, hev and renewable energy inverters ? ac, brushless, and dc motor controls and drives ? variable speed motor control in consumer white goods ? isolated switch mode and ups power supplies ? ul 1577 recognized ?? up to 5000 vrms for 1 minute ? csa component notice 5a approval ? vde certification conformity ?? vde0884 part 10 (basic/reinforced insulation) ? cqc certification approval ?? gb4943.1 patents pending ordering information: see page 14. pin assignments SI8920 vdda aip ain gnda vddb aop aon gndb 1 2 3 4 8 7 6 5 SI8920 vdda nc gnda nc vddb aip ain nc nc gnda gndb aop nc aon nc gndb 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9
SI8920 2 preliminary rev. 0.5
SI8920 preliminary rev. 0.5 3 t able of c ontents section page 1. functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2. electrical specificat ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 2.1. regulatory information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 3. typical operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4. functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 5. current sense application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 6. pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7. ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 8. package outline: dip8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 9. land pattern: dip8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 10. package outline: 16-pi n wide body soic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 11. land pattern: 16-pin wide body soic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 12. top markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 12.1. SI8920 top marking (dip8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 12.2. top marking explana tion (dip8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 12.3. SI8920 top marking (soic-16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 12.4. top marking explana tion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 contact information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
SI8920 4 preliminary rev. 0.5 1. functional block diagram figure 1. SI8920 block diagram cmos isolation mod uvlo vdda aip ain gnda aop gndb demod + _ uvlo + _ aon vddb
SI8920 preliminary rev. 0.5 5 2. electrical specifications table 1. electrical specifications v dda , v ddb =5v, t a = ?40 to +125 c; typical specs at 25 c parameter symbol test condition min typ max units input side supply voltage vdda 3.0 5.5 v input supply current ivdda v aip =v ain @ 3.3 v 3.2 4.2 5.5 ma output side supply voltage vddb 3.0 5.5 v output supply current ivddb v aip =v ain @ 3.3 v 2.3 3.2 4.1 ma vdd undervoltage threshold vdduv+ vdda, vddb rising 2.7 v vdd undervoltage threshold v dduv? vdda, vddb falling 2.6 v vdd undervoltage hysteresis vdd hys 100 mv amplifier bandwidth 750 khz amplifier input specified full scale input amplitude SI8920a vaip ? vain ?100 100 mv SI8920b ?200 200 mv maximum input volt- age before clipping SI8920a vaip ? vain 125 mv SI8920b 250 mv common-mode operating range vcm ?0.2 1 v input referred of fset vos 0.2 1.5 mv input offset drift vos t 1.0 v/c differential input impedance SI8920a rin 20 k ? SI8920b 37.2 k ? amplifier output full-scale output vaop ? vaon 1.58 1.62 1.65 vpk gain SI8920a 16.2 SI8920b 8.1 gain error t a =25c ?0.5 0.5 % gain error drift 60 ppm/c output common mode voltage (vaop + vaon)/2 1.02 1.1 1.17 v output noise SI8920a 100 khz bandwidth 0.14 0.28 mvrms SI8920b 100 khz bandwidth 0.10 0.20 mvrms nonlinearity SI8920a 0.15 0.50 % SI8920b 0.10 0.30 % output resistive load rload 5 k ? output capacitive load cload 100 pf timing signal delay tpd 50% to 50% 50% to 99% 10% to 90% 0.75 1.85 0.42 s common-mode transient immunity* cmti aip = ain = agnd, vcm = 1500 v 50 75 kv/s *note: an analog cmti failure is defined as an output erro r of more than 100 mv persisting for at least 1 s.
SI8920 6 preliminary rev. 0.5 figure 2. common mode transient immunity characterization circuit vddb SI8920 vdda aip gnda aop 7 gndb 5 vddb 8 ain aon 6 isolated supply + - differential probe 1 2 3 4 high ? voltage ? transient ? generator high voltage differential probe oscilloscope
SI8920 preliminary rev. 0.5 7 2.1. regulatory information table 2. regulatory information 1,2,3 csa the si892x is certified under csa component acceptance notice 5a. for more details, see file 232873. vde the si892x is certified according to vde 0884-10. for more details, see file 5006301-4880-0001. vde 0884-10: up to 1200 v peak for reinforced insulation working voltage. ul the si892x is certified under ul1577 component rec ognition program. for more details, see file e257455. rated up to 5000 v rms isolation voltage for basic protection. cqc the si892x is certified under gb4943.1-2011. rated up to 600 v rms reinforced insulation working voltage; up to 1000 v rms basic insulation working voltage. notes: 1. regulatory certifications apply to 5 kv rms rated devices which are production tested to 6.0 kvrms for 1 sec. 2. regulatory certifications apply to 3.75 kv rms rated devices which are production tested to 4.5 kvrms for 1 sec. 3. all certifications are pending. table 3. insulation and safety-related specifications parameter symbol test condition value unit gw dip-8 wb soic-16 nominal air gap (clearance) l(io1) 7.2 8.0 1 mm nominal external tracking (creepage) l(io2) 7.0 8.0 1 mm minimum internal gap (internal clearance) 0.016 0.016 mm tracking resistance (proof tracking index) pti iec60112 600 600 v erosion depth ed 0.031 0.019 mm resistance (input-output) 2 r io 10 12 10 12 ? capacitance (input-output) 2 c io f=1mhz 1 1 pf notes: 1. the values in this table correspond to the nominal creep age and clearance values. vde certifies the clearance and creepage limits as 8.5 mm minimum for the wb soic-16 package. ul does not impose a clearance and creepage minimum for component-level certifications. csa certifies t he clearance and creepage limits as 7.6 mm minimum for the wb soic-16 package. 2. to determine resistance and capacitance, the SI8920 is c onverted into a 2-terminal device. pins 1?8 (1?4 dip8) are shorted together to form the first terminal, and pins 9?16 (5?8 dip8) are shorted together to form the second terminal. the parameters are then measured between these two terminals.
SI8920 8 preliminary rev. 0.5 table 4. iec 60664-1 (vde 0884) ratings parameter test conditions specification gw dip-8 wb soic-16 basic isolation group material group i i installation classification rated mains voltages < 150 v rms i-iv i-iv rated mains voltages < 300 v rms i-iv i-iv rated mains voltages < 450 v rms i-iii i-iii rated mains voltages < 600 v rms i-iii i-iii table 5. vde 0884-10 insulation characteristics* parameter symbol test condition characteristic unit gw dip-8 wb soic-16 maximum working insulation voltage v iorm 891 1200 v peak input to output test voltage v pr method b1 (v iorm x1.875=v pr , 100% production test, t m = 1 sec, partial discharge < 5 pc) 1671 2250 v peak transient overvoltage v iotm t = 60 sec 6000 8000 v peak pollution degree (din vde 0110, table 1) 22 insulation resistance at t s , v io =500v r s >10 9 >10 9 ? *note: this isolator is suitable for reinforced electrical isolation only within the safety limit dat a. maintenance of the safety data is ensured by protective circuits. the SI8920 provides a climate classification of 40/125/21.
SI8920 preliminary rev. 0.5 9 table 6. absolute maximum ratings* parameter symbol min max unit storage temperature t stg -65 150 c ambient temperature under bias t a -40 125 c junction temperature t j ?1 5 0 c supply voltage vdda, vddb ?0.5 6.0 v input voltage respect to gnda vaip, vain ?0.5 vdd x +0.5 v output sink or source current |i o |? 5 m a total power dissipation p t ?2 1 2m w lead solder termperature (10 s) ? 260 c human body model esd rating 4000 ? v capacitive discharge model esd rating pdip 2000 ? v capacitive discharge mo del esd rating soic 2000 ? v maximum isolation (input to output) (1 s) pdip ? 6500 v rms maximum isolation (input to output) (1 s) soic ? 6500 v rms *note: permanent device damage may occur if the absolute maximu m ratings are exceeded. functional operation should be restricted to conditions as specified in the operational sections of the data sheet.
SI8920 10 preliminary rev. 0.5 3. typical operat ing characteristics figure 3. amplifier bandwidth figure 5. iddb vs. temperature figure 7. cmrr vs. frequency figure 9. step response low to high figure 4. gain error vs. temperature figure 6. idda vs. temperature figure 8. step response high to low -40 -30 -20 -10 0 10 20 30 1.e+02 1.e+03 1.e+04 1.e+05 1.e+06 1.e+07 gain (db) frequency (hz) 3.3 3.4 3.5 3.6 3.7 3.8 -50 -25 0 25 50 75 100 125 iddb (ma) temperature ( o c) 3.3v 5.5v 50 55 60 65 70 75 80 85 90 1.e-01 1.e+00 1.e+01 1.e+02 1.e+03 1.e+04 1.e+05 common mode rejection ratio (db) frequency (hz) -2.50 -1.50 -0.50 0.50 1.50 2.50 -0.15 -0.10 -0.05 0.00 0.05 0.10 0.15 -10-8-6-4-20246810 output (v) input (v) time ( s) input output -0.25 -0.15 -0.05 0.05 0.15 0.25 -50 -25 0 25 50 75 100 125 gain error (%) temperature ( o c) SI8920a SI8920b 3.9 4 4.1 4.2 4.3 4.4 4.5 4.6 4.7 -50 -25 0 25 50 75 100 125 idda (ma) temperature ( o c) 3.3v 5.0v -2.50 -1.50 -0.50 0.50 1.50 2.50 -0.15 -0.10 -0.05 0.00 0.05 0.10 0.15 -10-8-6-4-20246810 output (v) input (v) time ( s) input output
SI8920 preliminary rev. 0.5 11 4. functional description the input to the SI8920 is tuned for low-voltage, differenti al signals. this is ideal fo r connection to low resistance current shunt measurement resistors. the SI8920a has a full scale input of 100 mv, and the SI8920b has a full scale input of 200 mv. in both case s, the internal gain is set so th at the full scale output is 1.6 v. the SI8920 modulates the analog signal in a unique way for transmission across the semiconductor based isolation barrier. the input signal is first converted to a pulse-width modu lated digital signal. for transmission across the isolation barrier, the signal is further modulat ed with a high frequency carrier. on the other side of the isolation barrier, the signal is demodulated and the carrier portion is removed. the re sulting pwm signal is then used to faithfully reproduce the analog signal. this so lution provides exceptional signal bandwidth and accuracy. 5. current sense application figure 9. current sense application in the driver circuit presented in figure 9, the SI8920 is used to amplify the voltage across the sense resistor, rsense, and transmit the analog signal to the low voltag e domain across an isolation barrier. isolation is needed as the voltage of rsense with respec t to ground will swing between 0 v and the high voltage rail connected to the drain of q1. the load in this application can be a motor winding or a similar inductive winding. in a three phase motor drive application, this circuit would be re peated three times, one for each phas e. rsense should be a small resistor value to reduce power loss . however, too low a resistance will reduce the signal-to-noise of the measurement. SI8920 offers two specified full scale input options, 1 00 mv (SI8920a) and 200 mv (SI8920b) for optimizing the value of rsense. aip and ain connections to the rsense resistor should be made as cl ose as possible to each end of the rsense resistor as trace resistance will add error to the measurement. the inpu t to the SI8920 is differential, and the pcb traces back to the input pins should run in paralle l. this ensures that any large noise transients that occur on the high voltage side are coupled equally to the aip and ai n pins and will be rejected by the SI8920 as a common-mode signal. c4 0.1uf c2 0.1uf c3 0.1uf r3 1.82k si8234 pwm gndi disable vob vddi gndb vddb vddi dt gnda voa vdda SI8920 vdda aip gnda aop 7 gndb 5 vddb 8 ain aon 6 q1 q2 c5 0.1uf r6 c6 r4 r5 c1 10nf r1 20 r2 20 rsense d1 5.6v q3 load adc + \ to controller 3.3 to 5v supply low side gate driver supply floating gate driver 24v supply high voltage bus 1 2 3 4
SI8920 12 preliminary rev. 0.5 the amplifier bandwidth of the SI8920 is approximately 750 khz. if further input filter ing is required, a passive, differential rc low pass filter can be placed between rsense and the inputs pins. values of r1 = r2 = 20 ? and c1 = 10 nf, as shown in figure 9, provides a cutoff at approximately 400 khz. for best gain error, r1 and r2 should always be less than 33 ? to keep the source impedance sufficiently low compared to the SI8920 input impedance. the common mode voltage of ain and aip must be greate r than ?0.2 v but less than 1 v with respect to gnda. to meet this requirement, connect gnda of the SI8920 to one side rsense resistor. in this example gnda, rsense, the source of q1 and drain of q2 are co nnected together. the ground of the gate driver, silicon labs? si8234 in this circuit, is also commonly connected to the same node. the q1 gate driver has a floating supply, 24 v in this example. since the input and output of the SI8920 are galvanically isolated from each other, separate power supplies are necessary on each side. q3, r3, c3, and d1 make a regulator circuit for powering the input side of the SI8920 from this floating supply. d1 establishes a voltage of 5.6 v at the base of q3. r3 is selected to provide a ze ner current of 10 ma for d1. c3 provides filtering at the base of q3 and the emitter output of q3 provides appro ximately 5 v to vdda. c2 is a bypass capacitor for the supply and should be placed at the vdda pin with its re turn trace connecting to the gnda connection at rsense. c4, the local bypass capacitor for the b-side of SI8920, should be placed closed to vddb supply pin with its return close to gndb. the output signal at aop and aon is differential with a nominal gai n of 8.1 (SI8920b) or 16.2 (SI8920a) and common mode of 1.1 v. the outputs are sa mpled by a differential input adc. depending on the sample rate of the adc, an anti-aliasing filter may be r equired. r4, c6, and r5 make a simple anti-aliasing filter from passive components. the characte ristics of this filter will be dict ated by the input to pology and sampling frequency of the adc. however, to ensure the SI8920 outputs are not overloaded, r4 = r5 > 5k ? , and c6 can be calculated by the following equation: c6 1 2 ?? r4 ? r5 ? f 3db ? ------------------------------------------ --------------- - =
SI8920 preliminary rev. 0.5 13 6. pin descriptions figure 10. SI8920 pin configurations table 7. SI8920 pin descriptions name wb soic-16 pin # gw dip-8 pin # description vdda 1 1 input side power supply aip 2 2 analog input high ain 3 3 analog input low gnda 4, 8 4 input side ground gndb 9, 16 5 output side ground aon 11 6 analog output low aop 13 7 analog output high vddb 14 8 output power supply nc 5, 6, 7, 10, 12, 15 ? no connect *note: no connect. these pins are not internally connected. to maximize cmti performance, these pins should be connected to the ground plane. SI8920 vdda nc gnda nc vddb aip ain nc nc gnda gndb aop nc aon nc gndb 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 SI8920 vdda aip ain gnda vddb aop aon gndb 1 2 3 4 8 7 6 5
SI8920 14 preliminary rev. 0.5 7. ordering guide table 8. SI8920 ordering guide 1,2,3 new ordering part number (opn) ordering options specified input range isolation rating package type SI8920ac-ip 100 mv 3.75 kvrms gull-wing dip-8 SI8920bc-ip 200 mv 3.75 kvrms gull-wing dip-8 SI8920ad-is 100 mv 5.0 kvrms wb soic-16 SI8920bd-is 200 mv 5.0 kvrms wb soic-16 notes: 1. all packages are rohs-compliant. moisture sensitivity level is msl3 with peak reflow temperature of 260 c according to the jedec industry standard classifications and peak solder temperature. 2. ?si? and ?si? are used interchangeably. 3. aec-q100 qualified.
SI8920 preliminary rev. 0.5 15 8. package outline: dip8 figure 11 illustrates the package details for the SI8920 in a dip8 package. table 9 lists the values for the dimensions shown in the illustration. figure 11. dip8 package table 9. dip8 package diagram dimensions dimension min max a ? 4.19 a1 0.55 0.75 a2 3.17 3.43 b 0.35 0.55 b2 1.14 1.78 b3 0.76 1.14 c 0.20 0.33 d 9.40 9.90 e 7.37 7.87 e1 6.10 6.60 e2 9.40 9.90 e 2.54 bsc. l 0.38 0.89 aaa ? 0.25 notes: 1. all dimensions shown are in mill imeters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994.
SI8920 16 preliminary rev. 0.5 9. land pattern: dip8 figure 12 illustrates the reco mmended land pattern details for the SI8920 in a dip8 package. table 10 lists the values for the di mensions shown in the illustration. figure 12. dip8 land pattern table 10. dip8 land pattern dimensions* dimension min max c8 . 8 58 . 9 0 e2 . 5 4 b s c x0 . 6 00 . 6 5 y1 . 6 51 . 7 0 *note: this land pattern design is ba sed on the ipc-7351 specification. ?
SI8920 preliminary rev. 0.5 17 10. package outline: 16-pin wide body soic figure 13 illustrates the package details for the SI8920 in a 16-pin wide body soic. table 11 lists the values for the dimensions shown in the illustration. figure 13. 16-pin wide body soic
SI8920 18 preliminary rev. 0.5 table 11. package diagram dimensions symbol millimeters min max a ? 2.65 a1 0.10 0.30 a2 2.05 ? b 0.31 0.51 c 0.20 0.33 d 10.30 bsc e 10.30 bsc e1 7.50 bsc e1 . 2 7 b s c l 0.40 1.27 h 0.25 0.75 0 8 aaa ? 0.10 bbb ? 0.33 ccc ? 0.10 ddd ? 0.25 eee ? 0.10 fff ? 0.20 notes: 1. all dimensions shown are in mi llimeters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this drawing conforms to jedec outline ms-013, variation aa. 4. recommended reflow profile per jedec j-std-020c specification for small body, lead-free components.
SI8920 preliminary rev. 0.5 19 11. land pattern: 1 6-pin wide body soic figure 14 illustrates th e recommended land pattern de tails for the SI8920 in a 16-p in wide-body soic. table 12 lists the values for the dimens ions shown in the illustration. figure 14. 16-pin soic land pattern table 12. 16-pin wide body soic land pattern dimensions dimension feature (mm) c1 pad column spacing 9.40 e pad row pitch 1.27 x1 pad width 0.60 y1 pad length 1.90 notes: 1. this land pattern design is based on ipc-7351 pattern soic127p1032x265-16an for density level b (median land protrusion). 2. all feature sizes shown are at maximum material condition (mmc) and a card fabrication tolerance of 0.05 mm is assumed.
SI8920 20 preliminary rev. 0.5 12. top markings 12.1. SI8920 top marking (dip8) 12.2. top marking explanation (dip8) line 1 marking: customer part number SI8920 = isolator amplifier series s = input range: a=100mv b=200mv v = insulation rating c = 3.75 kv d=5.0,kv line 2 marking: yy = year ww = work week assigned by the assembly house. corresponds to the year and work week of the mold date. rttttt = mfg code manufacturing code from the assembly purchase order form. ?r? indicates revision. line 3 marking: circle = 51 mils diameter center-justified ?e4? pb-free symbol country of origin (iso-code abbreviation) cc ?
SI8920 preliminary rev. 0.5 21 12.3. SI8920 top marking (soic-16) 12.4. top marking explanation line 1 marking: customer part number SI8920 = isolator amplifier series s = input range: a = 100 mv b = 200 mv v = insulation rating c = 3.75 kv d=5.0,kv line 2 marking: yy = year ww = work week assigned by the assembly house. corresponds to the year and work week of the mold date. rttttt = mfg code manufacturing code from the assembly purchase order form. ?r? indicates revision. line 3 marking: circle = 43 mils diameter left-justified ?e4? pb-free symbol si892xsv yywwrttttt tw e4
SI8920 22 preliminary rev. 0.5 c ontact i nformation silicon laboratories inc. 400 west cesar chavez austin, tx 78701 tel: 1+(512) 416-8500 fax: 1+(512) 416-9669 toll free: 1+(877) 444-3032 please visit the silicon labs technical support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. patent notice silicon labs invests in research and development to help our customers differentiate in the market with innovative low-power, s mall size, analog- intensive mixed-signal solutions. silicon labs' extensive pat ent portfolio is a testament to our unique approach and world-clas s engineering team. silicon laboratories and silicon labs are trademarks of silicon laboratories inc. other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. the information in this document is believed to be accurate in all respects at the time of publ ication but is subject to change without notice. silicon laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resu lting from the use of information included herein. additionally, silicon la boratories assumes no responsibility for the functioning of und escribed fea- tures or parameters. silicon laboratories reserves the right to make changes without further notice. silicon laboratories makes no warran- ty, representation or guarantee regarding the suitability of it s products for any particular purpose, nor does silicon laborato ries assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, in cluding without limitation consequential or incidental damages. silicon laboratories products are not designed, intended, or authorized for use in applica tions intend- ed to support or sustain life, or for any other application in which the failure of the silicon laboratories product could crea te a situation where personal injury or death may occur. should buyer purchase or us e silicon laboratories products for any such unintended or unaut horized application, buyer shall indemnify and hold silicon laboratories harmless against all claims and damages.

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