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integrated circuit systems, inc. general description features ics9250-11 third party brands and names are the property of their respective owners. block diagram

9250-11 rev c 3/20/00 pin configuration 56-pin ssop
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(+@(+ ('@# ; "(' ?7# sel 133/100# sel(0:1) spread# x1 x2 osc pll spread spectrum pll2 cpu/2 (0:1) ref (0:1) 2 6 4 2 2 cpuclk (0:5) 3v66 (0:3) 48mhz / 2 / 3 / 2 3v33 (0:1) c o n t r o l / 2 / 2 / 4 / 3 / 2 ioapic(0:5) 6 power groups: %??7895c?789d7895e5e" %??5c?d% %??5c?d% %??)65c?)6d)6 %??/75c?/7d22 %??25c?2d23 %??2"5c?2"d" %??20.5c?0.d./0. ics reserves the right to make changes in the device data identified in this publication without further notice. ics advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
ics9250-11 pin descriptions pin number pin name type description 1, 52, 53 gndlapic pwr ground pin for the ioapic outputs. 2, 3, 50, 51, 54, 55 ioapic (0:5) out 2.5v clock outputs running divide synchronous with the cpu (host bus) clock frequency. the default apic is running at ? of cpuclk frequency. when freq_apic is strapped low, the apic is running at fixed 16.67 mhz. if cpu = 133 mhz, apic = cpu/8 if cpu = 100 mhz, apic = cpu/6 4, 49, 56 vddlapic pwr power pin for the ioapic outputs. 2.5v. 5, 11 vddref pwr power pin for ref clocks 6 x1 in xtal_in 14.318mhz crystal input 7 x2 out xtal_out crystal output ref0 out 3.3v 14.318 mhz clock output. apic clock strapping option for fixed 16.67 mhz apic clock outputs. freq_apic# out if freq_apic# = 0, apic clock = 16.67 mhz if freq_apic# = open, apic clock = cpu/4 ref1 out 3.3v 14.318mhz clock output. test# out test# is sampled low (external with 10k pulldown). all clock outputs are tri-state. 12, 19 vdd66 pwr power pin for the 3v66 clocks. 13, 14, 17, 18 3v66[0:3] out 66mhz outputs at 3.3v. these outputs are stopped when cpu_stop# is driven active.. 8, 15, 16, 23, 24 gnd pwr ground pin for 3v outputs. 21, 22 3v33mhz out 3.3v fixed 33mhz clock output. 25 vddcor pwr 3.3v power for pll core. 26 gnd48 pwr ground pin for the 48mhz output 27 48mhz out fixed 48mhz clock output. 3.3v 28 vdd48 pwr power pin for the 48mhz output. 29 sel 133/100# in this selects the frequency for the cpu and cpu/2 outputs. high = 133mhz, low=100mhz 30, 31 sel[0:1] in function select pins. see truth table for details. 32 spread# in enables spread spectrum when active(low). modulates all the cpu, pci, ioapic, 3v66 and cpu/2 clocks. does not affect the ref and 48mhz clocks. 0.5% down spread modulation. 33 vddlcpu/2 pwr power pin for the cpu/2 clocks. 2.5v 34, 35 cpu/2[0:1] out 2.5v clock outputs at 1/2 cpu frequency. 66mhz or50mhz depending on the state of the sel 133/100# input pin. 36 gndlcpu/2 pwr gro und pin for the cpu/2 clocks. 37, 44, 45 gndlcpu pwr ground pin for the cpuclks 38, 39, 42, 43, 46, 47 cpuclk[0:5] out host bus clock output at 2.5v. 133mhz or 100mhz depending on the state of the sel 133/100mhz. 40, 41, 48 vddlcpu pwr power pin for the cpuclks. 2.5v 9 10
ics9250-11 frequency select: power management features: l e s # 0 0 1 / 3 3 1 1 l e s0 l e s u p c z h m 2 / u p c z h m 6 6 v 3 z h m 3 3 v 3 z h m 8 4 z h m f e r z h m z h m c i p a o i 000 e t a t s i r te t a t s i r te t a t s i r te t a t s i r te t a t s i r te t a t s i r te t a t s i r t 001 a / na / na / na / na / na / na / n 010 0 0 10 0 . 0 56 . 6 63 . 3 3f f o8 1 3 . 4 17 6 . 6 1 / k l c u p c ? 011 0 0 10 0 . 0 56 . 6 63 . 3 38 48 1 3 . 4 17 6 . 6 1 / k l c u p c ? 100 2 / k l c t4 / k l c t4 / k l c t8 / k l c t2 / k l c tk l c t6 1 / k l c t 101 a / na / na / na / na na / na / n 110 3 . 3 3 16 . 6 66 . 6 63 . 3 3f f o8 1 3 . 4 17 6 . 6 1 / k l c u p c ? 111 3 . 3 3 16 . 6 66 . 6 63 . 3 38 48 1 3 . 4 17 6 . 6 1 / k l c u p c ?

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(+'># electrical characteristics - input/supply/common output parameters t a = 0 - 70c; supply voltage v dd = 3.3 v +/-5%, v ddl = 2.5 v +/-5% (unless otherwise stated) parameter symbol conditions min typ max units input high voltage v ih 2v dd +0.3 v input low voltage v il v ss -0.3 0.8 v input high current i ih v in = v dd 5 a i il1 v in = 0 v; inputs with no pull-up resistors -5 i il2 v in = 0 v; inputs with pull-up resistors 200 c l = max loads; select @ 100 mhz 160 c l = max loads; select @ 133 mhz 160 c l = max loads; select @ 100 mhz 75 c l = max loads; select @ 133 mhz 90 i dd3.3pd c l = max loads 200 i dd.25pd input address vdd or gnd 100 input frequency f i v dd = 3.3 v 14.318 mhz pin inductance 1 l pin 7nh c in logic inputs 5 pf c out output pin capacitance 6 pf c inx x1 & x2 pins 13.5 18 22.5 pf transition time 1 t trans to 1st crossing of target frequency 3 ms clk stabilization 1 t stab from v dd = 3.3 v to 1% target frequency 3 ms t pzh ,t pzl output enable delay (all outputs) 1 8 ns t phz ,t plz output disable delay (all outputs) 1 8 ns t cpu-3v66 cpu @ 1.25v, 3v66 @ 1.5v 0 1.5 ns t 3v66-3v33 3v66 @ 1.5v, 3v33 @ 1.5v 1.5 3.5 ns t cpu-ioapic cpu @ 1.25v, ioapic @ 1.25v 1.0 3.0 ns 1 guaranteed by design, not 100% tested in production. input low current a i dd3.3op delay 1 ma input capacitance 1 i dd.2 5 op a powerdown current operating supply current ma skew 1
ics9250-11 electrical characteristics - cpu t a = 0 - 70c; v ddl = 2.5 v +/-5%; c l = 10-20 pf (unless otherwise specified) parameter symbol conditions min typ max units output high voltage v oh2b i oh = -12 ma 2 v output low voltage v ol2b i ol = 12 ma 0.4 v v oh @ min = 1.0 v -27 v oh @ max = 2.375 v -27 v ol @ min = 1.2 v 27 v ol @ max = 0.3 v 30 ris e time 1 t r2b v ol = 0.4 v, v oh = 2.0 v 0.4 1.6 ns fall time 1 t f2 b v oh = 2.0 v, v ol = 0.4 v 0.4 1.6 ns duty cycle 1 d t2b v t = 1.25 v 45 55 % skew window 1 t sk2b v t = 1.25 v 175 ps jitter, cycle-to-cycle 1 t jcyc-cyc2b v t = 1.25 v 150 ps 1 guaranteed by design, not 100% tested in production. ma ma output high current output low current i oh2b i ol2b electrical characteristics - cpu/2 t a = 0 - 70c; v ddl = 2.5 v +/-5%; c l = 10-20 pf (unless otherwise specified) parameter symbol conditions min typ max units output high voltage v oh2b i oh = -12 ma 2 v output low voltage v ol2b i ol = 12 ma 0.4 v v oh @ min = 1.0 v -27 v oh @ max = 2.375 v -27 v ol @ min = 1.2 v 27 v ol @ max = 0.3 v 30 ris e time 1 t r2b v ol = 0.4 v, v oh = 2.0 v 0.4 1.6 ns fall time 1 t f2 b v oh = 2.0 v, v ol = 0.4 v 0.4 1.6 ns duty cycle 1 d t2b v t = 1.25 v 45 55 % skew window 1 t sk2b v t = 1.25 v 175 ps jitter, cycle-to-cycle 1 t jcyc-cyc2b v t = 1.25 v 250 ps 1 guaranteed by design, not 100% tested in production. ma ma output high current output low current i oh2b i ol2b
ics9250-11 electrical characteristics - 3v33 t a = 0 - 70c; v dd = 3.3 v +/-5%; c l = 10-30 pf (unless otherwise specified) parameter symbol conditions min typ max units output high voltage v oh1 i oh = -14.5 ma 2.4 v output low voltage v ol1 i ol = 9.4 ma 0.4 v v oh @ min = 1.0 v -33 v oh @ max = 3.135 v -33 v ol @ min = 1.95 v 30 v ol @ max = 0.4 v 38 ris e time 1 t r1 v ol = 0.4 v, v oh = 2.4 v 0.5 2.0 ns fall time 1 t f1 v oh = 2.4 v, v ol = 0.4 v 0.5 2.0 ns duty cycle 1 d t1 v t = 1.5 v 45 55 % skew window 1 t sk1 v t = 1.5 v 250 ps jitter, cycle-to-cycle 1 t jcyc-cyc1 v t = 1.5 v 250 ps 1 guaranteed by design, not 100% tested in production. output high current output low current ma ma i oh1 i ol1 electrical characteristics - 3v66 t a = 0 - 70c; v dd = 3.3 v +/-5%; c l = 10-30 pf (unless otherwise specified) parameter symbol conditions min typ max units output high voltage v oh1 i oh = -14.5 ma 2.4 v output low voltage v ol1 i ol =9 ma 0.4 v v oh @ min = 1.0 v -33 v oh @ max = 3.135 v -33 v ol @ min = 1.95 v 30 v ol @ max = 0.4 v 38 ris e time 1 t r1 v ol = 0.4 v, v oh = 2.4 v 0.5 2.0 ns fall time 1 t f1 v oh = 2.4 v, v ol = 0.4 v 0.5 2.0 ns duty cycle 1 d t1 v t = 1.5 v 45 55 % skew window 1 t sk1 v t = 1.5 v 250 ps jitter, cycle-to-cycle 1 t jcyc-cyc1 v t = 1.5 v 500 ps 1 guaranteed by design, not 100% tested in production. output high current output low current ma ma i oh1 i ol1
ics9250-11 electrical characteristics - ref, 48mhz t a = 0 - 70c; v dd = 3.3 v +/-5%; c l = 10-20 pf (unless otherwise specified) parameter symbol conditions min typ max units output high voltage v oh5 i oh = -16 ma 2.4 v output low voltage v ol5 i ol = 9 ma 0.4 v v oh @ min = 1.0 v -29 v oh @ max = 3.135 v -23 v ol @ min = 1.95 v 29 v ol @ max = 0.4 v 27 ris e time 1 t r5 v ol = 0.4 v, v oh = 2.4 v 1.0 4.0 ns fall time 1 t f5 v oh = 2.4 v, v ol = 0.4 v 1.0 4.0 ns duty cycle 1 d t5 v t = 1.5 v 45 55 % jitter, cycle-to-cycle 1 t jcyc-cyc5 v t = 1.5 v, fixed clocks 500 ps jitter, cycle-to-cycle 1 t jcyc-cyc5 v t = 1.5 v, ref clocks 1000 ps 1 guaranteed by design, not 100% tested in production. output high current i oh5 ma output low current i ol5 ma electrical characteristics - ioapic t a = 0 - 70c; v ddl = 2.5 v +/-5%; c l = 10-20 pf (unless otherwise specified) parameter symbol conditions min typ max units output high voltage v oh2b i oh = -12 ma 2 v output low voltage v ol2b i ol = 12 ma 0.4 v v oh @ min = 1.0 v -27 v oh @ max = 2.375 v -27 v ol @ min = 1.2 v 27 v ol @ max = 0.3 v 30 ris e time 1 t r2b v ol = 0.4 v, v oh = 2.0 v 0.4 1.6 ns fall time 1 t f2 b v oh = 2.0 v, v ol = 0.4 v 0.4 1.6 ns duty cycle 1 d t2b v t = 1.25 v 45 55 % skew window 1 t sk2b v t = 1.25 v 250 ps jitter, cycle-to-cycle 1 t jcyc-cyc2b v t = 1.25 v 250 ps 1 guaranteed by design, not 100% tested in production. ma ma output high current output low current i oh2b i ol2b
ics9250-11 ics reserves the right to make changes in the device data identified in this publication without further notice. ics advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. l o b m y ss n o i s n e m i d n o m m o cs n o i t a i r a vdn . n i m. m o n. x a m. n i m. m o n. x a m a5 9 0 .2 0 1 .0 1 1 .d a0 2 7 .5 2 7 .0 3 7 .6 5 1 a8 0 0 .2 1 0 .6 1 0 . 2 a7 8 0 .0 9 0 .4 9 0 . b8 0 0 .- 5 3 1 0 . c5 0 0 .-0 1 0 . ds n o i t a i r a v e e s e1 9 2 .5 9 2 .9 9 2 . ec s b 5 2 0 . 0 h5 9 3 .-0 2 4 . h0 1 0 .3 1 0 .6 1 0 . l0 2 0 .-0 4 0 . ns n o i t a i r a v e e s 0- 8 56 pin 300 mil ssop package ?for current dimensional specifications, see jedec 95.? .093 dia. pin (optional) d/2 e/2 bottom view a 2 see detail ?a? -e- c end view h pin 1 top view index area parting line l detail ?a? a 1 -e- b a side view -c- -d- seating plane .004 c ordering information ics9250 y f-11-t

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