rev. information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a adg781/adg782/adg783 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: ? analog devices, inc., 2.5 quad spst switches in chip scale package functional block diagrams in1 in2 in3 in4 s1 d1 s2 d2 s3 d3 s4 d4 adg781 switches shown for a logic 1 input in1 in2 in3 in4 s1 d1 s2 d2 s3 d3 s4 d4 adg782 in1 in2 in3 in4 s1 d1 s2 d2 s3 d3 s4 d4 adg783 features 1.8 v to 5.5 v single supply low on resistance (2.5 typ) low on-resistance flatness (0.5 ) C3 db bandwidth > 200 mhz rail-to-rail operation 20-lead 4 mm 4 mm chip scale package fast switching times t on = 16 ns t off = 10 ns typical power consumption (< 0.01 w) ttl/cmos compatible for functionally equivalent devices in 16-lead tssop and soic packages, see adg711/adg712/adg713 applications battery powered systems communication systems sample hold systems audio signal routing video switching mechanical reed relay replacement general description the adg781, adg782, and adg783 are monolithic cmos devices containing four independently selectable switches. these switches are designed on an advanced submicron process that provides low power dissipation and high switching speed, low on resistance, low leakage currents and high bandwidth. they are designed to operate from a single 1.8 v to 5.5 v sup- ply, making them ideal for use in battery powered instruments and with the new generation of dacs and adcs from analog devices. fast switching times and high bandwidth make the part suitable for video signal switching. the adg781, adg782, and adg783 contain four independent single-pole/single throw (spst) switches. the adg781 and adg782 differ only in that the digital control logic is inverted. the adg781 switches are turned on with a logic low on the appropriate control input, while a logic high is required to turn on the switches of the adg782. the adg783 contains two switches whose digital control logic is similar to the adg781, while the logic is inverted on the other two switches. each switch conducts equally well in both directions when on. the adg783 exhibits break-before-make switching action. the adg781/adg782/adg783 are available in 20-lead chip scale packages. product highlights 1. 20-lead 4 mm 4 mm chip scale package (csp). 2. 1.8 v to 5.5 v single supply operation. the adg781, adg782, and adg783 offer high performance and are fully specified and guaranteed with 3 v and 5 v supply rails. 3. very low r on (4.5 max at 5 v, 8 max at 3 v). at su pply voltage of 1.8 v, r on is typically 35 over the temperature range. 4. low on-resistance flatness. 5. C3 db bandwidth >200 mhz. 6. low power dissipation. cmos construction ensures low power dissipation. 7. fast t on /t off. 8. break-before-make switching. this prevents channel shorting when the switches are configured as a multiplexer (adg783 only). 781/461-3113 2013 c
rev. C2C adg781/adg782/adg783Cspecifications (v dd = 5 v 10%, gnd = 0 v. all specifications C40 c to +85 c unless otherwise noted.) b version C40 c to parameter +25 c +85 c unit test conditions/comments analog switch analog signal range 0 v to v dd v on resistance (r on ) 2.5 typ v s = 0 v to v dd , i s = C10 ma; 4 4.5 max test circuit 1 on-resistance match between 0.05 typ v s = 0 v to v dd , i s = C10 ma channels ( r on ) 0.4 max on-resistance flatness (r flat(on) ) 0.5 typ v s = 0 v to v dd , i s = C10 ma 1.0 max leakage currents v dd = 5.5 v; source off leakage i s (off) 0.01 na typ v s = 4.5 v/1 v, v d = 1 v/4.5 v; 0.1 0.2 na max test circuit 2 drain off leakage i d (off) 0.01 na typ v s = 4.5 v/1 v, v d = 1 v/4.5 v; 0.1 0.2 na max test circuit 2 channel on leakage i d , i s (on) 0.01 na typ v s = v d = 1 v, or 4.5 v; 0.1 0.2 na max test circuit 3 digital inputs input high voltage, v inh 2.4 v min input low voltage, v inl 0.8 v max input current i inl or i inh 0.005 a typ v in = v inl or v inh 0.1 a max dynamic characteristics 2 t on 11 ns typ r l = 300 , c l = 35 pf, 16 ns max v s = 3 v; test circuit 4 t off 6 ns typ r l = 300 , c l = 35 pf, 10 ns max v s = 3 v; test circuit 4 break-before-make time delay, t d 6 ns typ r l = 300 , c l = 35 pf, (adg783 only) 1 ns min v s1 = v s2 = 3 v; test circuit 5 charge injection 3 pc typ v s = 2 v; r s = 0 , c l = 1 nf; test circuit 6 off isolation C58 db typ r l = 50 , c l = 5 pf, f = 10 mhz C78 db typ r l = 50 , c l = 5 pf, f = 1 mhz; test circuit 7 channel-to-channel crosstalk C90 db typ r l = 50 , c l = 5 pf, f = 10 mhz; test circuit 8 bandwidth C3 db 200 mhz typ r l = 50 , c l = 5 pf; test circuit 9 c s (off) 10 pf typ f = 1 mhz c d (off) 10 pf typ f = 1 mhz c d , c s (on) 22 pf typ f = 1 mhz power requirements v dd = 5.5 v i dd 0.001 a typ digital inputs = 0 v or 5.5 v 1.0 a max notes 1 temperature ranges are as follows: b version: C40 c to +85 c. 2 guaranteed by design, not subject to production test. specifications subject to change without notice. c
rev. C3C adg781/adg782/adg783 b version C40 c to parameter +25 c +85 c unit test conditions/comments analog switch analog signal range 0 v to v dd v on resistance (r on ) 5 5.5 typ v s = 0 v to v dd , i s = C10 ma; 10 max test circuit 1 on-resistance match between 0.1 typ v s = 0 v to v dd , i s = C10 ma channels ( r on ) 0.5 max on-resistance flatness (r flat(on) ) 2.5 typ v s = 0 v to v dd , i s = C10 ma leakage currents v dd = 3.3 v; source off leakage i s (off) 0.01 na typ v s = 3 v/1 v, v d = 1 v/3 v; 0.1 0.2 na max test circuit 2 drain off leakage i d (off) 0.01 na typ v s = 3 v/1 v, v d = 1 v/3 v; 0.1 0.2 na max test circuit 2 channel on leakage i d , i s (on) 0.01 na typ v s = v d = 1 v, or 3 v; 0.1 0.2 na max test circuit 3 digital inputs input high voltage, v inh 2.0 v min input low voltage, v inl 0.8 v max input current i inl or i inh 0.005 a typ v in = v inl or v inh 0.1 a max dynamic characteristics 2 t on 13 ns typ r l = 300 , c l = 35 pf, 20 ns max v s = 2 v; test circuit 4 t off 7 ns typ r l = 300 , c l = 35 pf, 12 ns max v s = 2 v; test circuit 4 break-before-make time delay, t d 7 ns typ r l = 300 , c l = 35 pf, (adg783 only) 1 ns min v s1 = v s2 = 2 v; test circuit 5 charge injection 3 pc typ v s = 1.5 v; r s = 0 , c l = 1 nf; test circuit 6 off isolation C58 db typ r l = 50 , c l = 5 pf, f = 10 mhz C78 db typ r l = 50 , c l = 5 pf, f = 1 mhz; test circuit 7 channel-to-channel crosstalk C90 db typ r l = 50 , c l = 5 pf, f = 10 mhz; test circuit 8 bandwidth C3 db 200 mhz typ r l = 50 , c l = 5 pf; test circuit 9 c s (off) 10 pf typ f = 1 mhz c d (off) 10 pf typ f = 1 mhz c d , c s (on) 22 pf typ f = 1 mhz power requirements v dd = 3.3 v i dd 0.001 a typ digital inputs = 0 v or 3.3 v 1.0 a max notes 1 temperature ranges are as follows: b version: C40 c to +85 c. 2 guaranteed by design, not subject to production test. specifications subject to change without notice. specifications 1 (v dd = 3 v 10%, gnd = 0 v. all specifications C40 c to +85 c unless otherwise noted.) c
rev. adg781/adg782/adg783 C4C absolute maximum ratings 1 (t a = 25 c unless otherwise noted.) v dd to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . C0.3 v to +6 v analog, digital inputs 2 . . . . . . . . . . C0.3 v to v dd + 0.3 v or 30 ma, whichever occurs first continuous current, s or d . . . . . . . . . . . . . . . . . . . . . 30 ma peak current, s or d . . . . . . . . . . . . . . . . . . . . . . . . . 100 ma (pulsed at 1 ms, 10% duty cycle max) operating temperature range industrial (b version) . . . . . . . . . . . . . . . . C40 c to +85 c storage temperature range . . . . . . . . . . . . C65 c to +150 c junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150 c chip scale package ja thermal impedance . . . . . . . . . . . . . . . . . . . . . 32 c/w lead temperature, soldering (10 sec) . . . . . . . . . . . . 300 c ir reflow (<20 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 235 c notes 1 stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. only one absolute maximum rating may be applied at any one time. 2 overvoltages at in, s, or d will be clamped by internal diodes. current should be limited to the maximum ratings given. pin configuration table i. truth table (adg781/adg782) adg781 in adg782 in switch condition 01on 1 0 off table ii. truth table (adg783) logic switch 1, 4 switch 2, 3 0 off on 1 on off caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the adg781/adg782/adg783 feature proprietary esd protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device (lfcsp) c 14 13 12 1 3 4 s2 15 d2 v dd s3 11 d3 d1 gnd 2 s1 s4 5 d4 7 in4 6 nc 8 nc 9 in3 10 nc 19 in1 20 nc 18 nc 17 in2 16 nc adg781/ adg782/ adg783 top view (not to scale) notes 1. nc = no connect. 2. exposed pad tied to substrate, gnd.
rev. adg781/adg782/adg783 C5C v dd most positive power supply potential. gnd ground (0 v) reference. s source terminal. may be an input or output. d drain terminal. may be an input or output. in logic control input. r on ohmic resistance between d and s. r on on-resistance match between any two chan- nels (i.e., r on max and r on min). r flat(on) flatness is defined as the difference between the maximum and minimum value of on resistance as measured over the specified analog signal range. i s (off) source leakage current with the switch off. i d (off) drain leakage current with the switch off. i d , i s (on) channel leakage current with the switch on. v d (v s ) analog voltage on terminals d, s. c s (off) off switch source capacitance. c d (off) off switch drain capacitance. c d , c s (on) on switch capacitance. t on delay between applying the digital control input and the output switching on. t off delay between applying the digital control input and the output switching off. t d off time or on time measured between the 90% points of both switches, when switching from one address state to another (adg783 only). crosstalk a measure of unwanted signal that is coupled through from one channel to another as a result of parasitic capacitance. off isolation a measure of unwanted signal coupling through an off switch. charge a measure of the glitch impulse transferred injection from the digital input to the analog output during switching. on response the frequency response of the on switch. on loss the loss due to the on resistance of the switch. terminology typical performance characteristics v d or v s C drain or source voltage C v 6 r on C 0 0 0.5 v dd = 2.7v 0.5 1 5.5 5 4.5 4 3.5 3 2.5 2 1.5 1 1.5 2 2.5 3 3.5 4 4.5 v dd = 3v v dd = 4.5v v dd = 5v t a = 25 c 5 tpc 1. on resistance as a function of v d (v s ) v d or v s C drain or source voltage C v 6 r on C 0 0 +85c 0.5 1 5.5 5 4.5 4 3.5 3 2.5 2 1.5 13 v dd = 3v C40 c 0.5 1.5 2 2.5 +25c tpc 2. on resistance as a function of v d (v s ) for different temperatures v dd = 3 v v d or v s C drain or source voltage C v 6 r on C 0 0 0.5 0.5 1 5.5 5 4.5 4 3.5 3 2.5 2 1.5 1 1.5 2 2.5 3 3.5 4 4.5 5 v dd = 5v +85c C40 c +25c tpc 3. on resistance as a function of v d (v s ) for different temperatures v dd = 5 v v dd = 5v 4 sw 1 sw frequency C hz 10m 1m 1n 100 10m 1k i supply C amps 10k 100k 1m 100 10 1 100n 10n tpc 4. supply current vs. input switching frequency c
rev. adg781/adg782/adg783 C6C frequency C hz C30 off isolation C db C40 C110 C120 C130 10k 100k 1m 10m 100m C100 C90 C80 C70 C60 C50 v dd = 5v, 3v tpc 5. off isolation vs. frequency frequency C hz C30 crosstalk C db C40 C110 C120 C130 10k 100k 1m 10m v dd = 5v, 3v 100m C100 C90 C80 C70 C60 C50 tpc 6. crosstalk vs. frequency frequency C hz 0 on response C db C6 10k 100k 1m 10m v dd = 5v 100m C4 C2 tpc 7. on response vs. frequency source voltage C v 25 q inj C pc C10 0 0.5 C5 0 20 15 10 5 1 1.5 2 2.5 3 3.5 4 4.5 5 v dd = 5v v dd = 3v t a = 25c tpc 8. charge injection vs. source voltage applications figure 1 illustrates a photodetector circuit with programmable gain. an ad820 is used as the output operational amplifier. with the resistor values shown in the circuit, and using different combinations of the switches, gain in the range of 2 to 16 can be achieved. 5v 2.5v r3 510k c1 v out gnd d1 s1 d1 gain range 2 to 16 5v ad820 s2 d2 s3 d3 s4 d4 (lsb) in1 in2 in3 (msb) in4 r4 240k r5 240k r6 120k r7 120k r8 120k r9 120k r10 120k r1 33k r2 510k 2.5v figure 1. photodetector circuit with programmable gain c
rev. adg781/adg782/adg783 C7C test circuits test circuit 1. on resistance v d i s (off) i d (off) sd v s a a test circuit 2. off leakage 0.1f v s in s d v dd gnd r l 300 c l 35pf v out v dd adg781 adg782 v in v in v out t on t off 50% 50% 90% 90% 50% 50% v s test circuit 4. switching times s1 d1 0.1f v dd in1, in2 v s1 gnd r l1 300 c l1 35pf v out1 v s2 v out2 r l2 300 c l2 35pf s2 v in d2 v dd adg783 t d t d 50% 50% 90% v in v out1 v out2 90% 90% 90% 0v 0v 0v test circuit 5. break-before-make time delay, t d i d (on) sd a v d nc nc = no connect test circuit 3. on leakage v out v out q inj = c l v out sw on v in sw off s d v dd in r s gnd v s v out c l 1nf v dd test circuit 6. charge injection v s v out 50 network analyzer r l 50 gnd s d v s off isolation = 20 log v out 0.1f v dd v dd 50 v in in test circuit 7. off isolation channel-to-channel crosstalk = 20 log v out v s gnd s1 d2 s2 network analyzer in d1 nc v out r l 50 0.1f v dd v dd 50 r l 50 v s test circuit 8. channel-to-channel crosstalk c i ds sd v s v r on = v/i ds
rev. C8C adg781/adg782/adg783 v s v out 50 network analyzer r l 50 gnd s d 0.1f v dd v dd v in in v out with switch v out without switch insertion loss = 20 log test circuit 9. bandwidth c
adg781/adg782/adg783 rev. c C9C outline dimensions figure 2. 20-lead lead frame chip scale package [lfcsp_wq] 4 mm 4 mm body, very very thin quad (cp-20-6) dimensions shown in millimeters ordering guide model 1 temperature range package description package option adg781bcpz ?40c to +85c 20-lead lead frame chip scale package [lfcsp_wq] cp-20-6 adg781bcpz-reel7 ?40c to +85c 20-lead lead frame chip scale package [lfcsp_wq] cp-20-6 adg782bcpz ?40c to +85c 20-lead lead frame chip scale package [lfcsp_wq] cp-20-6 adg782bcpz-reel7 ?40c to +85c 20-lead lead frame chip scale package [lfcsp_wq] cp-20-6 adg783bcpz ?40c to +85c 20-lead lead frame chip scale package [lfcsp_wq] cp-20-6 adg783bcpz-reel ?40c to +85c 20-lead lead frame chip scale package [lfcsp_wq] cp-20-6 adg783bcpz-reel7 ?40c to +85c 20-lead lead frame chip scale package [lfcsp_wq] cp-20-6 1 z = rohs compliant part. revision history 2/13rev. b to rev. c changed pin 4 from s3 to s4 ........................................................... 4 changes to test circuit 1 ................................................................. 7 changes to ordering guide ............................................................. 9 8/12rev. a to rev. b updated outline dimensions .......................................................... 9 changes to ordering guide ............................................................. 9 3/02rev. 0 to rev. a edits to typical performance characteristics ........................... 5-6 changes to outline dimensions drawing ........................... 8 0.50 bsc 0.65 0.60 0.55 0.30 0.25 0.18 compliant to jedec standards mo-220-wggd-1. bottom view top view exposed pad p i n 1 i n d i c a t o r 4.10 4.00 sq 3.90 seating plane 0.80 0.75 0.70 0.05 max 0.02 nom 0.20 ref 0.20 min coplanarity 0.08 pin 1 indicator 2.30 2.10 sq 2.00 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 1 20 6 10 11 15 16 5 08-16-2010-b ?2013 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d02372-0-2/13(c)
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