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? 2014 exar corporation XR81112 universal clock - high frequency lvcmos/lvds/lvpecl clock synthesizer exar.com/XR81112 rev 1a 1 / 12 general description the XR81112 is a family of universal clock synthesize r devices in a com- pact qfn-12 package. the devices generate any frequ ency in the range of 10 mhz to 1.5ghz by utilizing a highly flexible delta sigma modulator and a wide ranging vco. the outputs are configurable for single ended lvcmos or differential lvds or lvpecl. the clock outputs h ave very low phase noise jitter of sub 0.6ps while consuming extremely low power. these devices can be used with standard crystals or an ext ernal system clock and can be configured to select from four different fre quency multiplier settings to support a wide variety of applications. this family of products have an extremely low power pll block with core power consu mption less than 40% of equivalent devices in the market. the XR81112 is a clock synthesizer with integer/fra ctional divider, lvcmos/ lvds/lvpecl driver, 3.3v/2.5v supply, taking a xtal input and providing one of four selectable output frequencies. the devi ce is optimized for use with a fundamental mode 10mhz to 60mhz crystal (or s ystem clock) and generates a selection of output frequencies from 10 mhz to 1.5ghz in either integer or fractional mode. in fractional mode, freq uency resolution of less than 1hz steps can be achieved. the application diagram below shows a typical synthes izer configuration with any standard crystal oscillating in fundamental mode. internal load capacitors are optionally available to minimize/elim inate external crystal loads. a system clock can also be used to overdrive the oscillator for a syn- chronous timing system. the typical phase noise plot below shows the jitter integrated over the 12khz to 20mhz range that is widely used in wan sys tems. the typical noise for the integration range of 1.875mhz to 20mh z is sub 200fs which is important for lan applications. these clock devices show a very good high frequency noise floor below -150db. features ? small footprint 3mm x 3mm qfn package ? configurable - as one differential lvpecl/lvds output pair or as a single ended lvcmos output ? crystal oscillator interface which can also be overdriven using a single-ended reference clock ? output frequency range: 10mhz - 1500mhz ? crystal/input frequency: 10mhz to 60mhz, paral- lel resonant crystal ? vco range: 2ghz - 3ghz ? rms phase jitter @ 156.25mhz, 12khz - 20mhz: <0.60ps ? full 3.3v or 2.5v operating supply ? -40c to 85c ambient operating temperature ? lead-free (rohs 6) package applications ? 10ge, ge lan/wan ? 2.5g/10g sonet/sdh/otn ? xdsl, pcie ? low-jitter clock generation ? synchronized clock systems ordering information C back page typical application XR81112 phase noise (dbc/hz) @ 156.25mhz 100hz 1khz 10khz 100khz 1mhz 10mhz -120db -160db -140db -100db -80db -60db -180db -40db rms jitter = 542.0 fs int range 12khz to 20mhz v cc 2.5v or 3.3v q 10mhz to 1.5ghz v e e q oe xtal_in xtal_out fsel1 fsel0 10mhz to 60mhz enable freq select XR81112
? 2014 exar corporation XR81112 2 / 12 exar.com/XR81112 rev 1a absolute maximum ratings stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any maximum rating condition for extende d periods may affect device reliability and lifetime. power supply voltage (vcc)......................... ...........+4.2v input voltage...................................... -0.5v to vcc + 0.5v output voltage...................................-0 .5v to vcc + 0.5v reference frequency/input crystal........10mhz to 60mh z storage temperature...............................- 55c to +125c lead temperature (soldering, 10 sec)............... ......300c esd rating (hbm - human body model)................. 2.0kv operating conditions operating temperature range.....................-40 c to +85c
? 2014 exar corporation XR81112 3 / 12 exar.com/XR81112 rev 1a electrical characteristics unless otherwise noted: t a = -40c to +85c, v cc = 3.3v5% or 2.5v5%, v ee = 0v symbol parameter conditions * min typ max units 3.3v power supply dc characteristics v cc power supply voltage ? 3.135 3.3 3.465 v i ee power supply current pecl lvds cmos includes output loading measured at 1500mhz measured at 1500mhz measured at 200mhz ? ? ? 86 34 48 120 50 65 ma ma ma 2.5v power supply dc characteristics v cc power supply voltage ? 2.375 2.5 2.625 v i ee power supply current pecl lvds cmos includes output loading measured at 1500mhz measured at 1500mhz measured at 200mhz ? ? ? 69 25 37 95 35 50 ma ma ma lvcmos/lvttl dc input characteristics v ih input high voltage (oe, fsel[1:0]) v cc = 3.465v ? 2.42 v cc + 0.3 v v cc = 2.625v ? 1.83 v cc + 0.3 v v il input low voltage(oe, fsel[1:0]) v cc = 3.465v ? -0.3 1.03 v v cc = 2.625v ? -0.3 0.785 v i ih input high current (oe, fsel[1:0]) v in = v cc = 3.465v or 2.625v ? 15 a i il input low current (oe, fsel[1:0]) v in = 0v, v cc = 3.465v or 2.625v ? -10 a lvcmos dc output characteristics (vcc = 3.3 +/- 5% or vcc = 2.5 +/- 5%) v oh output high voltage output unloaded ? 0.8 * v cc v v ol output low voltage output unloaded ? 0.1 * v cc v lvpecl dc output characteristics (vcc = 3.3 +/- 5% or vcc = 2.5 +/- 5%) v oh output high voltage ? v cc - 1.3 v cc - 0.4 v v ol output low voltage ? v cc - 2.0 v cc - 1.6 v v swing peak-to-peak output voltage swing ? 0.6 1.2 v lvds dc output characteristics (vcc = 3.3 +/- 5% or vcc =2.5 +/- 5%) v od differential output voltage output < 1ghz ? 200 550 mv v oc common mode voltage ? 1.25 v
? 2014 exar corporation XR81112 4 / 12 exar.com/XR81112 rev 1a * limits applying over the full operating temperatu re range are denoted by a ?. crystal characteristics x mode mode of oscillations fundamental x f frequency 10 60 mhz esr equivalent series resistance 50 c s shunt capacitance 7 pf ac characteristics f out output frequency 10 1500 mhz t jit ( i ) rms phase jitter 156.25mhz (w/25mhz ref) integration range 12khz-20mhz 0.6 ps 150mhz (w/25mhz ref) integration range 12khz-20mhz 0.6 ps 125mhz (w/25mhz ref) integration range 12khz-20mhz 0.6 ps 100mhz (w/25mhz ref) integration range 12khz-20mhz 0.6 ps t jit ( i )i integer rms phase jitter ? 1.0 ps t jit ( i )f fractional rms phase jitter with ref input >25mhz ? 1.5 ps t r /t f output rise/fall time 20% to 80%, see figure 10 ? 100 50 0 ps odc output duty cycle see figure 11 ? 45 55 % symbol parameter conditions * min typ max units
? 2014 exar corporation XR81112 5 / 12 exar.com/XR81112 rev 1a pin configuration pin assignments pin no. pin name type description 1 xtal_in input crystal oscillator input. 2 xtal_out output crystal oscillator output. 3 fsel1 input (900k : pull-dwn) output frequency select pin, msb (lvcmos/lvttl input). 4 fsel0 input (900k : pull-dwn) output frequency select pin, lsb (lvcmos/lvttl inpu t). 5 v ee supply negative supply pin. 6 nc no connect unused, do not connect. 7 oe input (900k : pull-up) output enable pin - lvcmos/lvttl active high input. outputs are enabled when oe = high. outputs are disabled when oe = low. 8 v ee supply negative supply pin. 9 v cc supply power supply pin. 10 q output positive output. 11 q output inverted output. 12 v cc supply power supply pin. 12 3 4 5 6 7 8 10 oe v ee q q v cc fsel1 fsel0 xtal_in xtal_out 9 nc v ee v cc 11 12
? 2014 exar corporation XR81112 6 / 12 exar.com/XR81112 rev 1a functional block diagram osc pdf & lpf vco divide by n divide by m qq fsel0 fsel1 xtal_in xtal_out oe control logic freq #1 freq #2 freq #3 freq #4
? 2014 exar corporation XR81112 7 / 12 exar.com/XR81112 rev 1a typical performance characteristics figures 1, 2, 3 and 4 show typical phase noise perfo rmance plots for 156.25 mhz, 150mhz, 125m, and 100m hz clock out- puts respectively. the data was taken using the ind ustry standard agilent e5052b instrument. the integ ration range is the widely referenced 12khz to 20mhz range most often u sed in wan applications. figure 1: 156.25mhz operation, phase noise at 3.3v figure 2: 150mhz operation, phase noise at 3.3v)
? 2014 exar corporation XR81112 8 / 12 exar.com/XR81112 rev 1a figure 3: 125mhz operation, phase noise at 3.3v figure 4: 100mhz operation, phase noise at 3.3v
? 2014 exar corporation XR81112 9 / 12 exar.com/XR81112 rev 1a application information functional truth table the XR81112 universal clock can support up to 4 indi vidual output frequency configurations. once configured, t he two frequency select pins, fslel[1:0], will determine th e output frequency from the device. this allows the XR81112 t o sup- port a variety of applications. if the fsel pins ar e left float- ing, the XR81112 will default (with internal pull-d own resistors on the fsel inputs) to the frequency #1 ou tput. termination for lvpecl outputs the termination schemes shown in figure 5 and figure 6 are typical for lvpecl outputs. matched impedance l ayout techniques should be used for the lvpecl output pai rs to minimize any distortion that could impact your maxi mum operating frequency. figure 7 is an alternate termin ation scheme that uses a y-termination approach. figure 5: XR81112 3.3v lvpecl output termination figure 6: XR81112 2.5v lvpecl output termination figure 7: XR81112 alternate lvpecl output terminati on using y-termination termination for lvds outputs the termination schemes shown in figure 8 and figure 9 are typical for lvds outputs. lvds swing is a small , typi- cally 350mv, on 1.2v of common mode. the lvds outpu t pair needs a 100 : resistor across the differential pair as close to the destination as possible. figure 8: XR81112 3.3v lvds output termination table 1: output frequency selection fsel[1:0] output frequency (mhz) 00 frequency #1 01 frequency #2 10 frequency #3 11 frequency #4 3.3v 3.3v 3.3v 50 : 50 : 130 : 130 : 82 : 82 : lvpecl output lvpecl input 2.5v 2.5v 2.5v 50 : 50 : : : : : lvpecl output lvpecl input vcc vcc 50 : 50 : 50 : 50 : lvpecl output lvpecl input rtt for 3.3v systems rtt = 50 : for 2.5v systems rtt = 19 : 3.3v 3.3v 50 : 50 : 100 : lvds output lvds input
? 2014 exar corporation XR81112 10 / 12 exar.com/XR81112 rev 1a figure 9: XR81112 2.5v lvds output termination output signal timing definitions the following diagrams clarify the common definitio ns of the ac timing measurements. figure 10: output rise/fall time and swing figure 11: output period and duty cycle 2.5v 2.5v 50 : 50 : 100 : lvds output lvds input 20% 80% t r t f 80% 20% v swing q nq q nq t pw t period odc = x 100% t pw t period
? 2014 exar corporation XR81112 11 / 12 exar.com/XR81112 rev 1a mechanical dimensions 12-pin qfn t t
? 2014 exar corporation XR81112 12 / 12 exar.com/XR81112 rev 1a for further assistance: email: commtechsupport@exar.com exar technical documentation: http://www.exar.com/techdoc/ exar corporation headquarters and sales offices 48720 kato road tel: +1 (5 10) 668-7000 fremont, ca 95438 - usa fax: +1 (510) 66 8-7001 notice exar corporation reserves the right to make changes to the products contained in this publication in o rder to improve design, performance or reliability. exar corporation assumes no responsibility for the use of any circuit s described herein, conveys no license under any pat ent or other right, and makes no representation tha t the circuits are free of patent infringement. charts and schedules contai ned herein are only for illustration purposes and m ay vary depending upon a users specific application. while the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracie s. exar corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reaso nably be expected to cause failure of the life support system or to signi ficantly affect its safety or effectiveness. products are not authorized for use in such applications un less exar corporation receives, in writing, assurances to its satisfactio n that: (a) the risk of injury or damage has been mi nimized; (b) the user assumes all such risks; (c) p otential liability of exar cor- poration is adequately protected under the circumsta nces. reproduction, in part or whole, without the prior w ritten consent of exar corporation is prohibited. ordering information revision history part number package green operating temperature range shipping packaging marking XR81112-f 12-pin qfn yes -40c to +85c tube/tray t112 XR81112evb eval board n/a n/a n/a n/a revision date description 1a june 2014 initial release. [ecn1426-29_6/28/2014]

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