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rev ab january 16, 2011 document number: sp - ap - 0826 page 1 of 16 2 400 west cesar chavez, austin, tx 78701 1+(512) 416 - 8500 1+(512) 416 - 9669 www.silabs.com sl38160 - 17ah sl38160 - 23ah key features ? audio + video clock generation ? programmable on chip analog vcxo with typical pull range of +/ -1 5 0ppm ? vcxo control voltage, 0v to 3 v ? u se s 27 mhz pullable crystal ? 3.3v +/ - 10% power supply range ? available in both commercial (0 to 70c)and industrial ( - 40 to 85c) temperature grades ? low power dissipation and low jitter ? integrated internal voltage regulator applications ? hdtv & sdtv ? wireless hdmi ? set top box ? media center ? dvr description the sl38160 azc - 17ah and sl38160 azc -23ah are programmable low power vcxo clock generator s designed to enable clock recovery and to synthesize the audio and video clocks required for advanced multimedia applications. the product is designed using spectralinear proprietary programmable eproclock? technology to generate the output clock s . the pr oduct is offered in a space saving 16- pin tssop package . the two parts are identical except for iic address, where the sl38160 azc -17a h uses d2(hex) while the sl38160 azc -23ah uses da(hex). block diagram programmable audio/video cg with vcxo
rev ab january 16, 2011 document number: sp - ap- 0198 page 2 of 16 sl38160 - 17ah sl38160 - 23ah pin configuration 16- pin tssop package pin description pin number pin name pin type pin description 1 xin input crystal oscillator input. use fundamental parallel mode 27mhz crystal. 2 27m_ref1 output 27 mhz reference clock output 1 . (default on) (can be cha nged to off/synchronous stop, pulled low to vss, through i2c) 3 vin input vcxo frequency control voltage 4, 5, 13, 15 vdd power 3.3v +/ - 10% positive power supply. 6, 10,12 vss power power supply ground for vdd. 7 sdata i/o i2c serial data 8 sclk input i2c clock 9 vclk output video clock output. (default on) (can be changed to off/high impedance state through i2c) 11 aclk output audio clock output . (default on) (can be cha nged to off/synchronous stop, pulled low to vss, through i2c) 14 27m_ref2 output 27 mhz reference clock output 2 . (default on) (can be cha nged to off/synchronous stop, pulled low to vss, through i2c) 16 xout output crystal oscillator output. use fundamental parallel mode 27mhz crystal.
rev ab january 16, 2011 document number: sp - ap- 0198 page 3 of 1 6 sl38160 - 17ah sl38160 - 23ah absolute ma ximum ratings description condition min max unit supply voltage, vdd - 0.5 4. 2 v all inputs and outputs - 0.5 vdd+0.5 v ambient operating temperature in operation 0 70 c ambient operating temperature industrial grade, in operation -40 85 c storage temperature no power is applied -65 150 c junction temperature in operation, power is applied - 125 c soldering temperature - 260 c esd rating (human body model) jedec22 - a114d -4 ,000 4 ,000 v esd rating (charge device model) jedec22 - c101c - 1,500 1,500 v esd rating (machine model) jedec22 - a115d -250 250 v moisture sensitivity level jedec (j - std -020) 1 stresses beyond those listed under ? absolute maximum ratings ? may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or other conditions beyond those indicated in the operational sections of the specification is not im p lied. exposure to absolute maximum rating conditions for extended perio ds may affect device reliability. dc electrical characteristics unless otherwise stated vdd = 3.3 v+/ -10%, vin=1.65v, output load =15pf and am bient temperature range 0 to + 70c for commercial or - 40 to +85c for i ndustrial temperature option. description symbol condition min typ max unit operating voltage vdd 3.3v +/ - 10% 2. 97 3.3 3.63 v input h igh voltage vih 0.7xvdd - - v input low voltage vil - - 0.3xvdd v output high voltage voh ioh= - 6ma vdd - 0.5 - - v output low voltage vol iol=6ma - - 0.5 v operating supply current idd o utput load = 0pf - 20 25 ma vin input i mpedance vin r 1 - - m input pull - down/up resist o r - 250 - k
rev ab january 16, 2011 document number: sp - ap- 0198 page 4 of 16 sl38160 - 17ah sl38160 - 23ah ac electrical characteristics unless otherwise stated vdd = 3.3v+/ - 10 %, vin=1.65v, output load =15pf for f<200mhz, 5pf for f>200mhz and am bient temperature range 0 to + 70c for commercial or - 40 to +85c for industrial temperature option. parameter symbol condition min typ max unit input frequency range fin c rystal input - 27 - mhz output rise time tr vclk and aclk, all frequencies - - 1.5 ns output rise time tr 27m_ref1,27m_ ref2 clocks - - 2.0 ns output fall time tf vclk and aclk, all frequencies - - 1.5 ns output fall time tf 27m_ref1,27m_ ref2 clocks - - 2.0 ns output duty cycle - a ll outputs , f 1 00mhz 45 50 55 % output duty cycle - all outputs , f> 1 00mhz 40 50 60 % output frequency synthesis error fout all frequencies except 193.16mhz, which has a +15ppm error - - 0 ppm cycle to cycle jitter - 27m_ref1, 27m _ ref2 outputs - 160 250 ps cycle to cycle jitter - vclk output - 1 75 350 ps cycle to cycle jitter - aclk output - 150 250 ps long term jitter 1 - 27m_ref1, 27m _ ref2 outputs - 85 120 ps - rms long term jitter - 1 vclk output - 250 700 ps - rms long term jitter - 1 aclk output - 550 950 ps - rms frequency settling time - time before valid clock output after programming frequency via iic - - 0.5 ms power - up time t pup time from vdd minimum to valid frequency output - - 5.5 ms vcxo pull range 2 f vcxo monotonic vcxo crystal pull range - +/ -150 - ppm recommend ed c rystal specifications (for vcxo applications) 2 symbol description c omments min typ max unit f nom nominal frequency f undamental mode - 27 - mhz f delta25 frequency tolerance at 25 c -20 - 20 ppm f deltat t emperature tolerance 0 to 70 c (reference to 25c ) -20 - 20 ppm cl nom nominal load capacitance - 14 - pf r1 equivalent series resistance f undamental mode (cl=series) - 20 50 dl d rive level nominal vdd @25 c over +/ -1 5 0ppm pull range - - 500 uw c0 s hunt capacitance - 3 .0 7.0 pf 1 measured with 1000 samples at 10us delay on oscilloscope 2 kds 1c727000cc1k crystal
rev ab january 16, 2011 document number: sp - ap- 0198 page 5 of 16 sl38160 - 17ah sl38160 - 23ah c1 m otional capacitance - 11.8 - ff c0/c1 ratio of shunt to motional capacitance 250 f 3 sephi third overtone separation, high side m echanical third (high side of 3xfnom) 240 - - ppm f3 seplo third overtone separation, low side m echanical third (low side of 3xfnom) - - -240 ppm serial data interface to enhance the flexibility and function of the device , an i2c compatible interface is provided. t hrough the serial data interface, various device functions, such as aclk and vclk frequency setting and ind ividual clock output buffers can be individually en abled or disabled. t he registers associated with the serial data interface initialize to their default setting at power - up. c lock device reg ister changes can be made after the device power up initialization process has completed . data protocol the clock driver serial protocol accept s byte write, byte read, block write, and block read operations from the controller. f or block write/read operation, access the bytes in sequential order from lowest to highest (most significant bit first) with the ability to stop after any complete byte is transferred. f or byte write and byte read operations, the system controller can acce ss individually indexed bytes. t he offset of the indexed byte is encoded in the command code descried in the command code definition section . t he block write and block read protocol is outlined in the block read and block write protocol section, while the byte read and byte write protocol section outlines b yte read and byte write information . the slave receiver address is 11010010 (d2h) for the sl38160azc - 17ah. the sl ave receiver address is 11011010 (d a h) for the sl38160azc - 23ah.
rev ab january 16, 2011 document number: sp - ap- 0198 page 6 of 16 sl38160 - 17ah sl38160 - 23ah command code definition bit description 7 0 = block read or block write operation, 1 = byte read or byte write operation (6:0) byte offset for byte read or byte write operation. for block read or block operations, these bits should be ? 0000000 ? block read and block write protocol block write protocol block read protocol bit description bit description 1 start 1 start 8:2 slave address - 7bits 8:2 slave address - 7bits 9 write 9 write 10 acknowledge from slave 10 acknowledge from slave 18:11 command code - 8bits 18:11 command code - 8bits 19 acknowledge from slave 19 acknowledge from slave 27:20 byte count - 8bits 20 repeat start 28 acknowledge from slave 27:21 slave address - 7bits 36:29 data byte 1 - 8bits 28 read = 1 37 acknowledge from slave 29 acknowledge from slave 45:38 data byte 2 - 8bits 37:30 byte count from slave 8bits 46 acknowledge from slave 38 acknowledge ? data byte/slave acknowledges 46:39 data byte 1 from slave - 8bits ? data byte n - 8bits 47 acknowledge ? acknowledge from slave 55:48 data byte 2 from slave - 8bits ? stop 56 acknowledge ? data bytes from slave/acknowledge ? data byte n from slave - 8bits ? not acknowledge ? stop
rev ab january 16, 2011 document number: sp - ap- 0198 page 7 of 16 sl38160 - 17ah sl38160 - 23ah byte read and byte write protocol byte write protocol byte read protocol bit description bit description 1 start 1 start 8:2 slave address - 7bits 8:2 slave address - 7bits 9 write 9 write 10 acknowledge from slave 10 acknowledge from slave 18:11 command code - 8bits 18:11 command code - 8bits 19 acknowledge from slave 19 acknowledge from slave 27:20 data byte - 8bits 20 repeat start 28 acknowledge from slave 27:21 slave address - 7bits 29 stop 28 read 29 acknowledge from slave 37:30 byte count from slave 8bits 38 not acknowledge 39 stop note: when writing to any register bytes between 32d to 63d (20h to 40h), an additional byte outside this range must be written to immediately afterward for proper loading to the register bytes within this range. i2c - bus timing specification parameter symbol standard - mode fast - mode unit min. max. min. max. scl cloc k fr equency f scl 0 100 0 400 khz start hold time t hd;sta 4.0 - 0.6 - us sclk low period t low 4.7 - 1.3 - us sclk high period t high 4.0 - 0.6 - us start set - up time t su;dat 4.7 - 0.6 - us
rev ab january 16, 2011 document number: sp - ap- 0198 page 8 of 16 sl38160 - 17ah sl38160 - 23ah parameter symbol standard - mode fast - mode unit min. max. min. max. sda set - up time t su;dat 250 - 100 - ns sda/sclk rise time t r - 1000 - 300 ns sda/sclk fall time t f - 300 - 300 ns stop set - up time t su;sto 4.0 - 0.6 - ns bus free time t buf 4.7 - 1.3 - us t low t f t hd;sta t r t hd;dat t su ;dat t high t f t su;sta t hd ;sta t su;sto t buf sdata sclk t r s sr p s
rev ab january 16, 2011 document number: sp - ap- 0198 page 9 of 16 sl38160 - 17ah sl38160 - 23ah table 1 . audio clock frequency settings (pin 11) audio clk (mhz) register byte# dec and bit [7:0] hex setting byte 40 byte 41 byte 42 byte 43 byte129 8.192 0 0 4 0 2 1f 18 81 11.2896 0c 45 de 78 81 12.288 0 0 4 0 1 f6 38 81 24.576 0 3 0 4 0 1 f5 18 81 16.9344 0 9 33 e9 d8 81 18.432 0 0 4 0 1 f5 78 81 36.864 0 0 4 0 1 f4 b8 81 16.384 0 0 8 0 3 85 d8 81 22.5792 0c 45 dd 38 81 49.152 0 0 8 0 3 84 98 81 33.8688 0 6 21 f5 38 81 73.728 0 0 4 0 1 f4 58 81 table 2 . digital television video clock frequency settings (pin 9 ) video clk (mhz) register byte# (dec ) and bit [7:0] hex, setting byte17 byte18 byte19 byte22 byte48 byte49 byte 50 byte51 byte128 13.5 0000 07 80 ab c6 04 00 7e c7 34 27 .00000 07 80 ab c6 04 00 5e c7 34 54 .00000 07 80 ab c6 04 00 4e c7 34 74.17582 3 05 80 ab de 1f 6d 86 c7 36 74.25 000 07 00 ab c6 05 80 86 c7 34 148.3517 0 05 8 0 ab de 1f 6d 82 c7 36 148.5 0000 07 80 ab c6 05 80 82 c7 34 3 default output frequency on power up
rev ab january 16, 2011 document number: sp - ap- 0198 page 10 of 16 sl38160 - 17ah sl38160 - 23ah table 3 . vga video clock settings (pin 9 ) 4 screen resolution refresh rate (hz) video clock (mhz) register byte# ( dec ) and bit [7:0] hex, setting byte 17 byte 18 byte 19 byte 22 byte 48 byte 49 byte 50 byte 51 byte 68 byte 69 byte 114 byte 128 640 x 350 85 31.5 00 07 00 ab c6 08 c0 d2 c7 03 83 3e 34 640 x 400 85 31.5 00 07 00 ab c6 08 c0 d2 c7 03 83 3e 34 720 x 400 85 35.5 00 07 00 ab c6 11 c1 90 c7 03 83 3e 34 85.04 35.000 06 80 ab c6 08 c0 d0 c7 0 3 83 3e 34 640 x 480 60 25.175 09 00 6 b 86 fb cf 22 c7 03 83 3e 34 72 31.5 00 07 00 ab c6 08 c0 d2 c7 03 83 3e 34 75 31.5 00 07 00 ab c6 08 c0 d2 c7 03 83 3e 34 85 36 .000 07 80 ab 66 03 00 50 c7 03 83 3e 34 800 x 600 56 38.1 00 05 80 ab c6 1f c2 52 c7 03 83 3e 34 60 40 .000 07 00 ab c6 0a 00 d0 c7 03 83 3e 34 72 50 .000 05 80 ab c6 19 02 4a c7 03 83 3e 34 75 49.5 00 07 00 ab c6 05 80 8a c7 03 83 3e 34 85 56.25 0 07 80 ab c6 06 40 8a c7 03 83 3e 34 1024 x 768 43 44.9 00 05 00 ab c6 70 46 d2 c7 03 83 3e 34 60 65 .000 05 80 ab c6 20 82 4a c7 03 83 3e 34 70 75 .000 07 00 ab c6 0c 80 ca c7 03 83 3e 34 75 78.75 0 07 00 ab c6 08 c0 c6 c7 03 83 3e 34 85 94.5 00 0b 80 ab c6 03 80 46 c7 03 83 3e 34 1152 x 864 75 108 .000 0b 80 ab c6 03 00 44 c7 03 83 3e 34 1280x768 60 68.25 0 06 80 6b c6 16 c1 8a c7 0 3 83 3e 34 60 79.5 00 06 80 6b c6 1a 82 46 c7 0 3 83 3e 34 75 102.2 00 05 00 ab c6 7f cb 44 c7 0 3 83 3e 34 85 117.5 00 06 00 6b c6 3a c4 84 c7 0 3 83 3e 34 1360 x 768 60 85.500 06 80 ab c6 09 80 c6 c7 03 83 3e 34 1280 x 960 60 108 .000 0b 80 ab c6 03 00 44 c7 03 83 3e 34 85 148.5 00 07 00 ab c6 05 80 82 c7 03 83 3e 34 1280x1024 60 108 .000 0b 80 ab c6 03 00 44 c7 03 83 3e 34 75 135 .000 07 80 ab c6 03 c0 44 c7 03 83 3e 34 85 157.5 00 06 80 ab c6 08 c0 c2 c7 03 83 3e 34 1400x1050 60 101.000 06 80 6b c6 19 42 44 c7 03 83 3e 34 60 121.750 05 00 6b c6 79 c6 c6 c7 03 83 3e 34 75 156.000 07 00 6b c6 0d 00 c4 c7 03 83 3e 34 85 179.500 06 00 6b c6 59 c6 c2 c7 03 83 3e 34 1600x1 200 60 162 .000 07 80 ab c6 03 00 42 c7 03 83 3e 34 65 175.5 00 07 80 ab c6 03 40 42 c7 03 83 3e 34 70 189 .000 07 80 ab c6 03 80 42 c7 03 83 3e 34 75 202.5 00 07 80 ab c6 03 c0 42 c7 03 83 3e 34 85 229.5 00 07 80 ab c6 04 40 42 c7 03 83 3e 34 4 pin 9 is the video output clock used for both the digital television and vga video frequency settings
rev ab january 16, 2011 document number: sp - ap- 0198 page 11 of 16 sl38160 - 17ah sl38160 - 23ah screen resolution refresh rate (hz) video clock (mhz) register byte# ( dec ) and bit [7:0] hex, setting byte 17 byte 18 byte 19 byte 22 byte 48 byte 49 byte 50 byte 51 byte 68 byte 69 byte 114 byte 128 1920x1080i 50 72.000 07 80 ab c6 04 00 4a c7 03 83 3e 34 1920x1200 5 60 154.000 06 00 6b c6 26 82 44 c7 03 83 3e 34 60 193.160 05 80 ab de 32 f8 c2 c7 03 83 3e 36 60 193.250 05 00 ab c6 c1 4d 82 c7 03 83 3e 34 75 245.250 06 80 6b c6 1b 41 82 c7 03 83 3e 34 85 281.250 06 80 6b c6 1f 43 00 c7 0f c3 be 34 1792x 1344 60 204.75 0 31 00 ab c6 16 c1 82 c7 03 83 3e 34 75 261.000 07 00 ab c6 07 40 c0 c7 0f c3 be 34 1856x1392 60 218.25 0 31 00 ab c6 18 41 82 c7 03 83 3e 34 75 288.000 07 00 ab c6 08 00 c0 c7 0f c3 be 34 1920x 1440 60 234 .000 31 80 ab c6 0d 00 c2 c7 03 83 3e 34 75 297.000 07 00 ab c6 05 80 80 c7 0f c3 be 34 5 15ppm synthesis error
rev ab january 16, 2011 document number: sp - ap- 0198 page 12 of 16 sl38160 - 17ah sl38160 - 23ah table 4 . output control output byte to change enable disable ref - 1 64d 04h 6 08 h vclk 117 d 00h 6 04h aclk 86d 04h 6 08 h ref - 2 96d 04h 6 08h table 5 . power down control byte to change active mode powerdown mode 29d 16h 6 36h table 6. additional bytes to program byte to change value 126d 26 h 130d 53 h note: these bytes should be programmed once after device power up. 6 default condition
rev ab january 16, 2011 document number: sp - ap- 0198 page 13 of 16 sl38160 - 17ah sl38160 - 23ah
rev ab january 16, 2011 document number: sp - ap- 0198 page 14 of 16 sl38160 - 17ah sl38160 - 23ah typical application circuit 27m_ref1 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 xout vdd 27m_ref2 vdd vss aclk vss vclk xin vin vdd vss sdata sclk vdd kds1c727000cc1k 3.3v 0.01uf 3.3v 0.01uf 3.3v 0.01uf gnd 3.3v 0.01uf gnd gnd gnd 3.3v 10uf gnd pad via legend 22 ohm 22 ohm 22 ohm 22 ohm general guidelines: 1. place crystal on same s ide of the board. 2. place 0.01 f capacitors as close as possible to the power pin . 3. install one bulk capacitor (10 f). note that this filtered power should connect to the 0.01 f capacitor pads first. this is known as pin - cap - via. 4. the 22 ohm series resistors placed on clock outputs are board dependent. this is a nominal value for 50 ohm impedance boards. never share ground vias . 5. it is preferable to have a ground flood directly underneath the part . 6. if pcb process takes advantage of via - in - pad technology, then it is recommended that the ground side of all bypass capacitors have the gnd via placed inside the pad to lower inductance to ground.
rev ab january 16, 2011 document number: sp - ap- 0198 page 15 of 16 sl38160 - 17ah sl38160 - 23ah package outline and package dimensions 16- pin tssop package (4.4mm)
rev ab january 16, 2011 document number: sp - ap- 0198 page 16 of 16 sl38160 - 17ah sl38160 - 23ah thermal characteristics parameter symbol condition min typ max unit thermal resistance junction to ambient ja still air - 80 - c/w ja 1m/s air flow - 70 - c/w ja 3m/s air flow - 68 - c/w thermal resistance junction to case jc independent of air flow - 36 - c/w ordering information ordering number marking shipping package package temperature sl38160azc - 17ah sl38160azc - 17ah tube 16 - pin tssop 0 to 70 c sl38160azc - 17ah t sl38160azc - 17ah tape and reel 16 - pin tssop 0 to 70 c sl38160azc - 23 ah sl38160azc - 23ah tube 16 - pin tssop 0 to 70 c sl38160azc - 23 ah t sl38160azc - 23ah tape and reel 16 - pin tssop 0 to 70 c sl38160az i - 1 7 ah sl38160azi - 17 ah tube 16 - pin tssop - 4 0 to 85 c sl38160az i - 1 7 ah t sl38160azi - 17 ah tape and reel 16 - pin tssop - 4 0 to 85 c sl38160az i - 23 ah sl38160azi - 23 ah tube 16 - pin tssop - 4 0 to 85 c sl38160az i - 23 ah t sl38160azi - 23 ah tape and reel 16 - pin tssop - 4 0 to 85 c notes: 1. all sli products are rohs compliant. document history page rev. issue date orig inator description of change a.1 . 0 7/8/10 d. christenberry create initial datasheet as advance information. b.1.0 9 / 2/ 10 d. christenberry final datasheet b. 1.1 10/5 /10 d. christenberry new frequency support added per customer , also updated package drawing b.1.2 10/14/10 d. christenberry updated cy - cy jitter specifications aa 10/28 /10 d. christenberry release version . added additional bytes, 5pf load condition for f>200mz ab 1/16/11 d. christenberry added industrial temperature operation the information in this document is believed to be accurate in all respects at the time of publication but is subject to chan ge without notice. silicon laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. additionally, silicon laboratories assumes no responsibility for the f unctioning of undescribed features or pa rameters. silicon laboratories reserves the right to make changes without further notice. silicon laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purp ose, nor does silicon laboratorie s assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. silicon laboratories products are no t designed, inte nded, or authorized for use in applications intended to support or sustain life, or for any other application in which the fa ilure of the silicon laboratories product could create a situation where personal injury or death may occur. should buyer purchase or use silicon laboratories products for any such unintended or unauthorized application, buyer shall indemnify and hold silicon laboratorie s harmless against all claims and damages

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