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fn6091 rev 2.00 page 1 of 11 jun 23, 2006 fn6091 rev 2.00 jun 23, 2006 ISL43L120, isl4 3l121, isl43l122 ultra low on-resistance, singl e supply, dual spst analog switch es datasheet the intersil ISL43L120, is l43l121, isl43l122 devices are low on-resistance, low voltage, bidirectional, precision, dual single-pole/single-throw (sps t) analog switches designed to operate from a single +1.65v to +3.6v supply. targeted applications include battery pow ered equipment that benefit from low r on (0.16 ? ), low power consumption (0.12 ? w) and fast switching speeds (t on = 13ns, t off = 13ns). cell phones, for example, often face asic functionality limitations. the number of analog input or gpio pins may be limited and digital geometries are not well suited to analog switch performance. this fam ily of parts may be used to switch in additional functionalit y while reducing asic design risk. the isl43l12x are offered in an 8 ld msop package, alleviating board space limitations. the ISL43L120, isl43l121, i sl43l122 are dual single- pole/single-throw (spst) devi ces. the ISL43L120 has two normally open (no) switches; the isl43l121 has two normally closed (nc) switch es; the isl43l122 has one normally open (no) and one n ormally closed (nc) switch and can be used as an spdt. table 1 summarizes the perf ormance of this family. related literature technical brief tb363 guidelines for handling and processing moisture sensit ive surface mount devices (smds). application note an557 re commended test procedures for analog switches. features ? low on resistance (r on ) - v+ = 3.0v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.16 ? - v+ = 1.8v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.26 ? ?r on matching between channel s . . . . . . . . . . . . 0.005 ? ?r on flatness over signal range . . . . . . . . . . . . . . 0.008 ? ? single supply operation. . . . . . . . . . . . . . . . +1.65v to +3.6v ? low power consumption (p d ) . . . . . . . . . . . . . . . . . <0.12 ? w ? fast switching action (v+ = 3.0v) -t on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13ns -t off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13ns ? esd hbm rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >8kv ? 1.8v logic compatible (+3v supply) ? available in 8-ld thin dfn and 8-ld msop packages ? pb-free plus anneal available (rohs compliant) applications ? battery powered, handheld, and portable equipment - cellular/mobile phones - pagers - laptops, notebooks, palmtops ? portable test and measurement ? medical equipment ? audio and video switching table 1. features at a glance ISL43L120 isl43l121 isl43l122 number of switches 222 sw 1/sw 2 no/no nc/nc no/nc 1.8v r on 0.26 ? 0.26 ? 0.26 ? 1.8v t on /t off 30ns/25ns 30ns/25ns 30ns/25ns 3v r on 0.16 ? 0.16 ? 0.16 ? 3v t on /t off 13ns/13ns 13ns/13ns 13ns/13ns packages 8ld 3x3 tdfn, 8ld msop n o t r e c o m m e n d e d f o r n e w d e s i g n s r e c o m m e n d e d r e p l a c e m e n t : i s l 4 3 l 2 1 0
ISL43L120, isl43l121, isl43l122 fn6091 rev 2.00 page 2 of 11 jun 23, 2006 pinouts (note 1) ISL43L120 (msop, tdfn) top view isl43l122 (msop, tdfn) top view isl43l121 (msop, tdfn) top view note: 1. switches shown for logic 0 input. no 1 com 1 in 2 gnd v+ com 2 no 2 in 1 6 7 8 5 1 2 3 4 no 1 com 1 in 2 gnd v+ com 2 nc 2 in 1 6 7 8 5 1 2 3 4 nc 1 com 1 in 2 gnd v+ com 2 nc 2 in 1 6 7 8 5 1 2 3 4 ordering information part number* part marking temp. range (c) package pkg. dwg. # ISL43L120iu l120 -40 to 85 8 ld msop m8.118 ISL43L120ir l10 -40 to 85 8 ld 3x3 tdfn l8.3x3a isl43l121iu l121 -40 to 85 8 ld msop m8.118 isl43l121ir l11 -40 to 85 8 ld 3x3 tdfn l8.3x3a isl43l122iu l122 -40 to 85 8 ld msop m8.118 isl43l122ir l12 -40 to 85 8 ld 3x3 tdfn l8.3x3a ISL43L120iuz (note) l120z -40 to 85 8 ld msop (pb-free) m8.118 ISL43L120irz (note) l10z -40 to 85 8 ld 3x3 tdfn (pb-free) l8.3x3a isl43l121iuz (note) l121z -40 to 85 8 ld msop (pb-free) m8.118 isl43l121irz (note) l11z -40 to 85 8 ld 3x3 tdfn (pb-free) l8.3x3a isl43l122iuz (note) l122z -40 to 85 8 ld msop (pb-free) m8.118 isl43l122irz (note) l12z -40 to 85 8 ld 3x3 tdfn (pb-free) l8.3x3a *add -t suffix for tape and reel note: intersil pb-free plus anneal products employ special pb-fr ee material sets; molding compounds/ die attach materials and 100% matte tin plate termination finish , which are rohs compliant an d compatible with both snpb and pb-free soldering operations. int ersil pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. truth table logic ISL43L120 isl43l121 isl43l122 sw 1, 2 sw 1, 2 sw 1 sw 2 0off onoffon 1 on off on off note: logic 0 ? 0.5v. logic 1 ?? 1.4v with a 3v supply. pin descriptions pin function v+ system power supply input (+1.65v to +3.6v) gnd ground connection in digital control input com analog switch common pin no analog switch normally open pin nc analog switch normally closed pin
ISL43L120, isl43l121, isl43l122 fn6091 rev 2.00 page 3 of 11 jun 23, 2006 absolute maximum ratings thermal information v+ to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to 4.7v input voltages in (note 2). . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to ((v+) + 0.3v) no, nc (note 2) . . . . . . . . . . . . . . . . . . . . . . -0 .3 to ((v+) + 0.3v) output voltages com (note 2) . . . . . . . . . . . . . . . . . . . . . . . . -0 .3 to ((v+) + 0.3v) continuous current (an y terminal) . . . . . . . . . . . . . . . . . . . . 300ma peak current, in, no, nc, or com (pulsed 1ms, 10% duty cycle, max) . . . . . . . . . . . . . . . . . 500ma esd rating (per mil-std-883 method 3015). . . . . . . . . . . . . .>8kv operating conditions temperature range isl43l12xiu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40c to 85c thermal resistance (typical, note 3) ? ja (c/w) 8 ld 3x3 tdfn package . . . . . . . . . . . . . . . . . . . . . 110 8 ld msop package . . . . . . . . . . . . . . . . . . . . . . . . 190 maximum junction temperat ure (plastic package). . . . . . . . 150c maximum storage temperature range . . . . . . . . . . . . . -65 c to 150c maximum lead temperature (soldering 10s) . . . . . . . . . . . . 300c (lead tips only) caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. notes: 2. signals on nc, no, com, or in exceeding v+ or gnd are clamped by internal diodes. limit forward diode current to maximum cur rent ratings. 3. ? ja is measured with the component mounted on a low effective ther mal conductivity test board in fr ee air. see tech brief tb379 f or details. electrical specifications - 3v supply test conditions: v+ = +2.7v to +3.3v, gnd = 0v, v inh = 1.4v, v inl = 0.5v (note 4, 6), unless otherwise specified parameter test conditions temp (c) min (note 5) typ max (note 5) units analog switch characteristics analog signal range, v analog full 0 - v+ v on resistance, r on v+ = 2.7v, i com = 100ma, v no or v nc = 0v to v+ see figure 4 25 - 0.17 0.25 ? full - - 0.3 ? r on matching between channels, ? r on v+ = 2.7v, i com = 100ma, v no or v nc = voltage at max r on, note 8 25 - 0.005 0.02 ? full - - 0.04 ? r on flatness, r flat(on) v+ = 2.7v, i com = 100ma, v no or v nc = 0v to v+, note 9 25 - 0.008 0.06 ? full - - 0.07 ? no or nc off leakage current, i no(off) or i nc(off) v+ = 3.3v, v com = 0.3, 3v, v no or v nc = 3v, 0.3v 25 -3 - 3 na full -60 - 60 na com on leakage current, i com(on) v ? = 3.3v, v com = 0.3v, 3v, or v no or v nc = 0.3v, 3v 25 -3 - 3 na full -80 - 80 na dynamic characteristics turn-on time, t on v+ = 2.7v, v no or v nc = 1.5v, r l = 50 ? , c l = 35pf, v in = 0 to 2.7v, see figure 1, note 7 25 - 15 25 ns full - - 30 ns turn-off time, t off v+ = 2.7v, v no or v nc = 1.5v, r l = 50 ? , c l = 35pf, v in = 0 to 2.7v, see figure 1, note 7 25 - 15 25 ns full - - 30 ns charge injection, q c l = 1.0nf, v g = 0v, r g = 0 ? , see figure 2 25 - -125 - pc off isolation r l = 50 ? , c l = 5pf, f = 100khz, v com = 1 v rms, see figure 3 25 - 62 - db crosstalk (channel-to-channel) r l = 50 ? , c l = 5pf, f = 100khz, v com = 1 v rms, see figure 5 25 - -94 - db no or nc off capacitance, c off f = 1mhz, v no or v nc = v com = 0v, see figure 6 25 - 182 - pf
ISL43L120, isl43l121, isl43l122 fn6091 rev 2.00 page 4 of 11 jun 23, 2006 com off capacitance, c com(off) f = 1mhz, v no or v nc = v com = 0v, see figure 6 25 - 182 - pf com on capacitance, c com(on) f = 1mhz, v no or v nc = v com = 0v, see figure 6 25 - 290 - pf power supply characteristics power supply range full 1.65 - 3.6 v positive supply current, i+ v+ = 1.65v to 3.6v, v in = 0v or v+, all channels on or off 25 - - 30 na full - - 750 na digital input characteristics input voltage low, v inl full - - 0.5 v input voltage high, v inh full 1.4 - - v input current, i inh , i inl v+ = 3.3v, v in = 0v or v+ (note 7) full -0.5 - 0.5 ? a notes: 4. v in = input voltage to perform proper function. 5. the algebraic convention, wher eby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. 6. parts are 100% tested at +25c . limits across the full temperature range are guaranteed by desi gn and correlation. 7. guaranteed but not tested. 8. r on matching between channels is calculated by subtracting the cha nnel with the highest max ron va lue from the channel with lowes t max ron value. 9. flatness is defined as the difference between maximum and min imum value of on-resistance over the specified analog signal ra nge. electrical specifications - 1.8v supply test conditions: v+ = +1.65v to +2.0v, gnd = 0v, v inh = 1.0v, v inl = 0.4v (note 4, 6), unless otherwise specified parameter test conditions temp (c) min (note 5) typ max (note 5 )units analog switch characteristics analog signal range, v analog full 0 - v+ v on resistance, r on v+ = 1.8v, i com = 100ma, v no or v nc = 0v to v+, see figure 4, note 7 25 - 0.26 0.35 ? full - - 0.4 ? r on matching between channels, ? r on v+ = 1.8v, i com = 100ma, v no or v nc = voltage at max r on, note 8 25 - 0.005 - ? full - 0.005 - ? r on flatness, r flat(on) v+ = 1.8v, i com = 100ma, v no or v nc = 0v to v+, note 9 25 - 0.074 - ? full - 0.082 - ? no or nc off leakage current, i no(off) or i nc(off) v+ = 2.0v, v com = 0.3v, 1.8v, v no or v nc = 1.8v, 0.3v 25 -3 - 3 na full -60 - 60 na com on leakage current, i com(on) v ? = 2.0v, v com = 0.3v, 1.8v, or v no or v nc = 0.3v, 1.8v 25 -3 - 3 na full -80 - 80 na dynamic characteristics turn-on time, t on v ? = 1.65v, v no or v nc = 1.0v, r l =50 ? , c l = 35pf, v in = 0 to 1.65v, see figure 1, note 7 25 - 30 40 ns full - - 45 ns turn-off time, t off v ? = 1.65v, v no or v nc = 1.0v, r l =50 ? , c l = 35pf, v in = 0 to 1.65v, see figure 1, note 7 25 - 25 35 ns full - - 40 ns charge injection, q c l = 1.0nf, v g = 0v, r g = 0 ??? see figure 2 25 - -80 - pc electrical specifications - 3v supply test conditions: v+ = +2.7v to +3.3v, gnd = 0v, v inh = 1.4v, v inl = 0.5v (note 4, 6), unless otherwise specified (continued) parameter test conditions temp (c) min (note 5) typ max (note 5) units
ISL43L120, isl43l121, isl43l122 fn6091 rev 2.00 page 5 of 11 jun 23, 2006 off isolation r l = 50 ? , c l = 5pf, f = 100khz, v com = 1 v rms, see figure 3 and figure 5 25 - 62 - db crosstalk (channel-to-channel) 25 - -94 - db no or nc off capacitance, c off f = 1mhz, v no or v nc = v com = 0v, see figure 6 25 - 182 - pf com off capacitance, c com(off) f = 1mhz, v no or v nc = v com = 0v, see figure 6 25 - 182 - pf com on capacitance, c com(on) f = 1mhz, v no or v nc = v com = 0v, see figure 6 25 - 290 - pf power supply characteristics positive supply current, i+ v+ = 1.65v to 3.6v, v in = 0v or v+, all channels on or off 25 - - 30 na full - - 750 na digital input characteristics input voltage low, v inl full - - 0.4 v input voltage high, v inh full 1.0 - - v input current, i inh , i inl v+ = 2.0v, v in = 0v or v+ (note 7) full -0.5 - 0.5 ? a test circuits and waveforms logic input waveform is inverted for switches that have the opp osite logic sense. figure 1a. measurement points repeat test for all switches. c l includes fixture and stray capacitance. figure 1b. test circuit figure 1. switching times figure 2a. measurement points figure 2b. test circuit figure 2. charge injection electrical specifications - 1.8v supply test conditions: v+ = +1.65v to +2.0v, gnd = 0v, v inh = 1.0v, v inl = 0.4v (note 4, 6), unless otherwise specified (continued) parameter test conditions temp (c) min (note 5) typ max (note 5 )units 50% t r < 5ns t f < 5ns t off 90% v+ 0v v no 0v t on logic input switch input switch output 90% v out v out v (no or nc) r l r l r on ?? + ------------------------------ = ? 35pf gnd v+ c v out ? v out on off on q = ? v out x c l switch output logic input v+ 0v c l v out r g v g gnd com no or nc v+ c logic input in
ISL43L120, isl43l121, isl43l122 fn6091 rev 2.00 page 6 of 11 jun 23, 2006 detailed description the isl43l12x family of devices are bidirectional, single pole/single throw (spst ) analog switches th at offer precise switching capability from a single 1.65v to 3.6v supply with low on-resistance (0.16 ? ) and high speed operation (t on = 13ns, t off = 13ns). the device is especially well suited for portable battery powered equipment due to its low operating supply voltage (1. 65v), low power consumption (2.7 ? w max), low leakage currents (80na max), and the tiny tdfn and msop packaging. the ultra low on-resistance and r on flatness provide very low insertion loss and distortion to application that require signal reproduction. supply sequencing and overvoltage protection with any cmos device, proper power supply sequencing is required to protect the device f rom excessive input currents which might permanently damage the ic. all i/o pins contain esd protection diodes from the pin to v+ and to gnd (see figure 7). to prevent forward b iasing these diodes, v+ must be applied before any input si gnals, and the input signal voltages must remain between v+ and gnd. if these conditions cannot be guarant eed, then one of the following two protection methods should be employed. logic inputs can easily be protected by adding a 1k ? resistor in series with the inpu t (see figure 7). the resistor limits the input current below the threshold that produces permanent damage, and the s ub-microamp input current produces an insignificant v oltage drop during normal operation. figure 3. off isolation test circuit figure 4. r on test circuit figure 5. crosstalk test circuit figure 6. capacitance test circui t test circuits and waveforms (continued) analyzer r l signal generator v+ c 0v or v+ no or nc com in x gnd v+ c 0v or v+ no or nc com in gnd v nx v 1 r on = v 1 /100ma 1ma 0v or v+ analyzer v+ c no1 or nc1 signal generator r l gnd in 1 com1 in 2 50 ? 0v or v+ nc com2 no2 or nc2 v+ c gnd no or nc com in x impedance analyzer 0v or v+
ISL43L120, isl43l121, isl43l122 fn6091 rev 2.00 page 7 of 11 jun 23, 2006 this method is not a cceptable for the signal path inputs. adding a series resistor to t he switch input defeats the purpose of using a low r on switch, so two small signal diodes can be added in series with the supply pins to provide overvoltage protection for all pins (see figure 7). these additional diodes limit the analog signal from 1v below v+ to 1v above gnd. the low leaka ge current performance is unaffected by this approach, but the switch signal range is reduced and the resistance may increase, especially at low supply voltages. power-supply considerations the isl43l12x constru ction is typical of most single supply cmos analog switches, in that they have two supply pins: v+ and gnd. v+ and gnd dr ive the internal cmos switches and set their analog vo ltage limits. unlike switches with a 4v maximum supply vo ltage, the isl43l12x 4.7v maximum supply voltage provid es plenty of room for the 10% tolerance of 3.6v suppli es, as well as room for overshoot and noise spikes. the minimum recommended supply voltage is 1.65v but the part will operate with a supply below 1.5v. it is important to note that the input s ignal range, switch ing times, and on- resistance degrade at lower supply voltages. refer to the electrical specification tables and typical performance curves for details. v+ and gnd also power the inter nal logic and level shifters. the level shifters convert the i nput logic levels to switched v+ and gnd signals to dri ve the analog switch gate terminals. this family of switches canno t be operated with bipolar supplies, because the inpu t switching point becomes negative in this configuration. logic-level thresholds this switch family is 1.8v cmos compatible (0.5v and 1.4v) over a supply range of 2v to 3 .6v (see figure 14). at 3.6v the v ih level is about 1.27v. this is still bel ow the 1.8v cmos guaranteed high output minimum level of 1.4v, but noise margin is reduced. the digital input stages dra w supply current whenever the digital input voltage is not at one of the supply rails. drivin g the digital input signals from gnd to v+ with a fast transition time minimizes power dissipation. high-frequency performance in 50 ? systems, signal response is r easonably flat even past 20mhz with a -3db bandwidth o f 175mhz (see figure 15). the frequency response is ver y consistent over a wide v+ range, and for varying analog signal levels. an off switch acts like a c apacitor and passes higher frequencies with less attenua tion, resulting in signal feedthrough from a switchs input to its output. off isolation is the resistance to this feedthr ough, while crosstalk indicates the amount of feedthrough fr om one switch to another. figure 16 details the high off isolation and crosstalk rejection provided by this fami ly. at 100khz, off isolation is about 62db in 50 ? systems, decreasing approximately 20db per decade as frequency increases. higher load impedances decrease off isolation and crosstalk rejection due to the voltage divider a ction of the switch off impedance and the load impedance. leakage considerations reverse esd protection diodes are internally connected between each analog-signal pin and both v+ and gnd. one of these diodes conducts if any analog signal exceeds v+ or gnd. virtually all the analog leaka ge current comes from the esd diodes to v+ or gnd. although t he esd diodes on a given signal pin are identical and ther efore fairly well balanced, they are reverse biased differen tly. each is biased by either v+ or gnd and the analog signal. this means their leakages will vary as the signal varies. the difference in the two diode leakages to the v+ and gnd pi ns constitutes the analog- signal-path leakage current. all analog leakage current flows between each pin and one of the supply terminals, not to the other switch terminal. this is why both sides of a given switch can show leakage curre nts of the same or opposite polarity. there is no connection between the analog signal paths and v+ or gnd. figure 7. overvoltage protection gnd v com v no or nc optional protection v+ in x diode optional protection diode optional protection resistor
ISL43L120, isl43l121, isl43l122 fn6091 rev 2.00 page 8 of 11 jun 23, 2006 typical performance curves t a = 25c, unless otherwise specified figure 8. on resistance vs supply voltage vs switch voltage figure 9. on resistance vs switch voltage figure 10. on resistance vs switch voltage figure 11. charge injec tion vs switch voltage figure 12. turn - on time vs suppl y voltage figure 13. turn - off time vs supply voltage 0.12 0.14 0.16 0.18 0.2 0.22 0.24 0.26 r on ( ? ) v com (v) 01234 i com = 100ma v+ = 2.7v v+ = 1.8v v+ = 3.6v v+ = 3v v+ = 3v r on ( ? ) v com (v) 00.511.522.53 0.11 0.12 0.13 0.14 0.15 0.16 0.17 0.18 0.19 25c 85c -40c i com = 100ma 0 0.5 1 1.5 2 r on ( ? ) v com (v) 85c -40c v+ = 1.8v i com = 100ma 25c 0.1 0.15 0.2 0.25 0.3 -250 -200 -150 -100 -50 0 50 00.511.522.53 q (pc) v com (v) v+ = 1.8v v+ = 3v 0 10 20 30 40 50 60 70 80 t on (ns) v+ (v) 11.522.533.544.5 85c -40c 25c 0 10 20 30 40 50 t off (ns) v+ (v) 1 1.5 2 2.5 3 3.5 4 4.5 85c -40c 25c
fn6091 rev 2.00 page 9 of 11 jun 23, 2006 ISL43L120, isl43l121, isl43l122 intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description on ly. intersil may modify the circuit design an d/or specifications of products at any time without notice, provided that such modification does not, in intersil's sole judgment, affect the form, fit or function of the product. accordingly, the reader is cautioned to verify that datasheets are current before placing orders. information fu rnished by intersil is believed to be accu rate and reliable. however, no responsib ility is assumed by intersil or its subsidiaries for its use; nor for any infrin gements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com for additional products, see www.intersil.com/en/products.html ? copyright intersil americas ll c 2004-2006. all rights reserved. all trademarks and registered trademarks are the property of their respective owners. figure 14. digital switching point vs supply voltage figure 15. frequency response figure 16. crosstalk and off isolation die characteristics substrate potential (powered up): gnd transistor count: 114 process: submicron cmos typical performance curves t a = 25c, unless otherwise specified (continued) 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 v+ (v) v inh and v inl (v) 11.522.533.544.5 v inh v inl frequency (hz) 0 -20 normalized gain (db) gain phase v+ = 3v 0 20 40 60 80 100 phase (degrees) 1m 10m 100m 600m v in = 0.2v p-p to 2v p-p r l = 50 ? ??? ??? ???? ???
ISL43L120, isl43l121, isl43l122 fn6091 rev 2.00 page 10 of 11 jun 23, 2006 thin dual flat no-lea d plastic package (tdfn) // nx (b) section "c-c" 5 (a1) bottom view a 6 area index c c 0.10 0.08 side view 0.15 2x e a b c 0.15 d top view cb 2x 6 8 area index nx l e2 e2/2 ref. e n (nd-1)xe (datum a) (datum b) 5 0.10 8 7 d2 b a m c n-1 12 plane seating c a a3 nx b d2/2 nx k for even terminal/side e c l terminal tip l1 10 l l8.3x3a 8 lead thin dual flat no-lead plastic package symbol millimeters notes min nominal max a 0.70 0.75 0.80 - a1 - 0.02 0.05 - a3 0.20 ref - b 0.25 0.30 0.35 5, 8 d 3.00 bsc - d2 2.20 2.30 2.40 7, 8, 9 e 3.00 bsc - e2 1.40 1.50 1.60 7, 8, 9 e 0.65 bsc - k0.25 - - - l 0.20 0.30 0.40 8 n82 nd 4 3 rev. 3 11/04 notes: 1. dimensioning and tolerancing conform to asme y14.5-1994. 2. n is the number of terminals. 3. nd refers to the number of terminals on d. 4. all dimensions are in mill imeters. angles are in degrees. 5. dimension b applies to the meta llized terminal and is measure d between 0.15mm and 0.30mm from the terminal tip. 6. the configuration of the pin #1 identifier is optional, but m ust be located within the zone indicated. the pin #1 identifier may be either a mold or mark feature. 7. dimensions d2 and e2 are for the exposed pads which provide improved electrical and thermal performance. 8. nominal dimensions are provided to assist with pcb land pattern design efforts, see in tersil technical brief tb389. 9. compliant to jedec mo-weec-2 except for the l min dimension.
ISL43L120, isl43l121, isl43l122 fn6091 rev 2.00 page 11 of 11 jun 23, 2006 mini small outline pl astic packages (msop) notes: 1. these package dimensions are w ithin allowable dimensions of jedec mo-187ba. 2. dimensioning and tolerancing per ansi y14.5m - 1994. 3. dimension d does not include mold flash, protrusions or gat e burrs and are measured at datum plane. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension e1 does not include interlead flash or protrusion s and are measured at datum plane. interlead flash and protrusions shall not exceed 0. 15mm (0.006 inch) per side. 5. formed leads shall be planar with respect to one another with in 0.10mm (0.004) at seating plane. 6. l is the length of terminal for soldering to a substrate. 7. n is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. dimension b does not include dambar protrusion. allowable dambar protrusion shall be 0.08 mm (0.003 inch) total in excess of b dimension at maximum material condition. minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. datums and to be determined at datum plane . 11. controlling dimension: millimeter. converted inch dimen- sions are for reference only. l 0.25 (0.010) l1 r1 r 4x ? 4x ? gauge plane seating plane e e1 n 12 top view index area -c- -b- 0.20 (0.008) a b c seating plane 0.20 (0.008) c 0.10 (0.004) c -a- -h- side view b e d a a1 a2 -b- end view 0.20 (0.008) c d e 1 c l c a - h - -a - - b - - h - m8.118 (jedec mo-187aa) 8 lead mini small outline plastic package symbol inches millimeters notes min max min max a 0.037 0.043 0.94 1.10 - a1 0.002 0.006 0.05 0.15 - a2 0.030 0.037 0.75 0.95 - b 0.010 0.014 0.25 0.36 9 c 0.004 0.008 0.09 0.20 - d 0.116 0.120 2.95 3.05 3 e1 0.116 0.120 2.95 3.05 4 e 0.026 bsc 0.65 bsc - e 0.187 0.199 4.75 5.05 - l 0.016 0.028 0.40 0.70 6 l1 0.037 ref 0.95 ref - n8 87 r 0.003 - 0.07 - - r1 0.003 - 0.07 - - 05 o 15 o 5 o 15 o - ? 0 o 6 o 0 o 6 o - rev. 2 01/03

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