View TMP86FH12MG_8971893.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

8 bit microcontroller tlcs-870/c series TMP86FH12MG
page 2 TMP86FH12MG the information contained herein is su bject to change without notice. 021023 _ d toshiba is continually working to improve the qual ity and reliability of its products. nevertheless, semiconductor devices in general can malfunction or fa il due to their inherent electrical sensitivity and vulnerability to physical stress. it is the responsibility of the buyer, when utilizing toshiba products , to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such toshiba products could cause loss of human life, bodily injury or damage to property. in developing your designs, please ensure that to shiba products are used within specified operating ranges as set forth in the most re cent toshiba products specifications. also, please keep in mind the precautions and conditions set forth in the ? handling guide for semiconductor devices, ? or ? toshiba semiconductor reliability handbook ? etc. 021023_a the toshiba products listed in this document are inte nded for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). these toshiba products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ( ? unintended usage ? ). unintended usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instrument s, all types of safety devices, etc. unintended usage of toshiba products listed in this document shall be made at the customer's own risk. 021023_b the products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohibited under any applicable laws and regulations. 060106_q the information contained he rein is presented only as a guide for the applications of our products. no responsibility is assumed by tosh iba for any infringements of patents or other rights of the third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of toshiba or others. 021023_c the products described in this document may include products subject to the foreign exchange and foreign trade laws. 021023_f for a discussion of how the reliability of microcontro llers can be predicted, please refer to section 1.3 of the chapter entitled quality and reli ability assurance/hand ling precautions. 030619_s ? 2006 toshiba corporation all rights reserved
revision history date revision 2005/10/26 1 first release 2006/4/21 2 contents revised 2006/6/29 3 periodical updating. no change in contents. 2006/10/17 4 contents revised 2008/8/29 5 contents revised
caution in setting the ua rt noise rejection time when uart is used, settings of rxdnc are limited depend ing on the transfer clock specified by brg. the com- bination "o" is available but please do not select the combination "?". the transfer clock generated by timer/counter in terrupt is calculated by the following equation : transfer clock [hz] = time r/counter source clock [hz] brg setting transfer clock [hz] rxdnc setting 00 (no noise rejection) 01 (reject pulses shorter than 31/fc[s] as noise) 10 (reject pulses shorter than 63/fc[s] as noise) 11 (reject pulses shorter than 127/fc[s] as noise) 000 fc/13 o o o ? 110 (when the transfer clock gen- erated by timer/counter inter- rupt is the same as the right side column) fc/8 o ? ? ? fc/16 o o ? ? fc/32ooo ? the setting except the a b o v eoooo

i table of contents TMP86FH12MG 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.4 pin names and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2. operational description 2.1 cpu core functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1.1 memory address map ............................................................................................................................... 7 2.1.2 program memory (flash) .......................................................................................................................... 7 2.1.3 data memory (ram) ................................................................................................................................. 8 2.2 system clock controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2.1 clock generator ........................................................................................................................................ 8 2.2.2 timing generator .................................................................................................................................... 10 2.2.2.1 configuration of timing generator 2.2.2.2 machine cycle 2.2.3 operation mode control circuit .............................................................................................................. 11 2.2.3.1 single-clock mode 2.2.3.2 dual-clock mode 2.2.3.3 stop mode 2.2.4 operating mode control ......................................................................................................................... 16 2.2.4.1 stop mode 2.2.4.2 idle1/2 mode and sleep1/2 mode 2.2.4.3 idle0 and sleep0 modes (idle0, sleep0) 2.2.4.4 slow mode 2.3 reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.3.1 external reset input ............................................................................................................................... 29 2.3.2 address trap reset ............................................................................................................................... ... 30 2.3.3 watchdog timer reset .............................................................................................................................. 30 2.3.4 system clock reset ............................................................................................................................... ... 30 3. interrupt control circuit 3.1 interrupt latches (il28 to il2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.2 interrupt enable register (eir) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.2.1 interrupt master enable flag (imf) .......................................................................................................... 34 3.2.2 individual interrupt enable flags (ef28 to ef4) ...................................................................................... 35 note 3: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.3 interrupt sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.3.1 interrupt acceptance processing is packaged as follows. ....................................................................... 37 3.3.2 saving/restoring general-purpose registers ............................................................................................ 38 3.3.2.1 using push and pop instructions 3.3.2.2 using data transfer instructions 3.3.3 interrupt return ........................................................................................................................................ 39 3.4 software interrupt (intsw) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.4.1 address error detection .......................................................................................................................... 40 3.4.2 debugging .............................................................................................................................................. 40
ii 3.5 undefined instruction interrupt (intundef) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.6 address trap interrupt (intatrap) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.7 external interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 4. special function r egister (sfr) 4.1 sfr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 4.2 dbr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 5. i/o ports 5.1 port p0 (p07 to p00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 5.2 port p1 (p17 to p10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 5.3 port p2 (p22 to p20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 5.4 port p3 (p37 to 30) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 6. watchdog timer (wdt) 6.1 watchdog timer configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 6.2 watchdog timer control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 6.2.1 malfunction detection methods using the watchdog timer ................................................................... 60 6.2.2 watchdog timer enable ......................................................................................................................... 61 6.2.3 watchdog timer disable ........................................................................................................................ 62 6.2.4 watchdog timer interrupt (intwdt) ...................................................................................................... 62 6.2.5 watchdog timer reset ........................................................................................................................... 63 6.3 address trap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 6.3.1 selection of address trap in internal ram (atas) ................................................................................ 64 6.3.2 selection of operation at address trap (atout) .................................................................................. 64 6.3.3 address trap interrupt (intatrap) ....................................................................................................... 64 6.3.4 address trap reset ............................................................................................................................... . 65 7. time base timer (tbt) 7.1 time base timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 7.1.1 configuration .......................................................................................................................................... 67 7.1.2 control .................................................................................................................................................... 67 7.1.3 function .................................................................................................................................................. 68 7.2 divider output (dvo) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 7.2.1 configuration .......................................................................................................................................... 69 7.2.2 control .................................................................................................................................................... 69 8. real-time clock 8.1 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 8.2 control of the rtc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 8.3 function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
iii 9. 10-bit timer/counter (tc7) 9.1 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 9.2 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 9.3 configuring control and data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 9.4 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 9.4.1 programmable pulse generator output (ppg output) ............................................................................. 78 9.4.1.1 50% duty mode 9.4.1.2 variable duty mode 9.4.1.3 ppg1/ppg2 independent mode 9.4.2 starting a count ....................................................................................................................................... 82 9.4.2.1 command start and capture mode 9.4.2.2 command start and trigger start mode 9.4.2.3 trigger start mode 9.4.2.4 trigger capture mode (cstc = 00) 9.4.2.5 trigger start/stop acceptance mode 9.4.3 configuring how the timer stops ............................................................................................................. 89 9.4.3.1 counting stopped with the outputs initialized 9.4.3.2 counting stopped with the outputs maintained 9.4.3.3 counting stopped with the outputs initialized at the end of the period 9.4.4 one-time/continuous output mode .......................................................................................................... 89 9.4.4.1 one-time output mode 9.4.4.2 continuous output mode 9.4.5 ppg output control (initial value/out put logic, enabling/disabling output) ............................................... 91 9.4.5.1 specifying initial values and output logic for ppg outputs 9.4.5.2 enabling or disabling ppg outputs 9.4.5.3 using the tc7 as a normal timer/counter 9.4.6 eliminating noise from the tc7 pin input ................................................................................................ 91 9.4.7 interrupts ................................................................................................................................................. 93 9.4.7.1 inttc7t (trigger start interrupt) 9.4.7.2 inttc7p (period interrupt) 9.4.7.3 intemg (emergency output stop interrupt) 9.4.8 emergency ppg output stop feature ...................................................................................................... 94 9.4.8.1 enabling/disabling input on the emg pin 9.4.8.2 monitoring the emergency ppg output stop state 9.4.8.3 emg interrupt 9.4.8.4 canceling the emergency ppg output stop state 9.4.8.5 restarting the timer after canceling the emergency ppg output stop state 9.4.8.6 response time between emg pin input and ppg outputs being initialized 9.4.9 tc7 operation and microcontroller operating mode ............................................................................... 96 10. 16-bit timercounter 1 (tc1) 10.1 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 10.2 timercounter control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 10.3 function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 10.3.1 timer mode ............................................................................................................................... .......... 100 10.3.2 external trigger timer mode .............................................................................................................. 102 10.3.3 event counter mode ........................................................................................................................... 104 10.3.4 window mode ............................................................................................................................... ...... 105 10.3.5 pulse width measurement mode ........................................................................................................ 106 10.3.6 programmable pulse generate (ppg) output mode ......................................................................... 109 11. 8-bit timercounter (tc3, tc4) 11.1 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 11.2 timercounter control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 11.3 function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 11.3.1 8-bit timer mode (tc3 and 4) ............................................................................................................ 119 11.3.2 8-bit event counter mode (tc3, 4) .................................................................................................... 120 11.3.3 8-bit programmable divider output (pdo) mode (tc3, 4) ................................................................. 120 11.3.4 8-bit pulse width modulation (pwm) output mode (tc3, 4) .............................................................. 123
iv 11.3.5 16-bit timer mode (tc3 and 4) .......................................................................................................... 125 11.3.6 16-bit event counter mode (tc3 and 4) ............................................................................................ 126 11.3.7 16-bit pulse width modulation (pwm) output mode (tc3 and 4) ...................................................... 126 11.3.8 16-bit programmable pulse generate (ppg) output mode (tc3 and 4) ........................................... 129 11.3.9 warm-up counter mode ..................................................................................................................... 131 11.3.9.1 low-frequency warm-up counter mode (normal1 11.3.9.2 high-frequency warm-up counter mode (slow1 12. synchronous serial interface (sio) 12.1 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 12.2 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 12.3 serial clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 12.3.1 clock source ............................................................................................................................... ........ 135 12.3.1.1 internal clock 12.3.1.2 external clock 12.3.2 shift edge ............................................................................................................................... ............. 137 12.3.2.1 leading edge 12.3.2.2 trailing edge 12.4 number of bits to transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 12.5 number of words to transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 12.6 transfer mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 12.6.1 4-bit and 8-bit transfer modes ............................................................................................................. 138 12.6.2 4-bit and 8-bit receive modes ............................................................................................................. 140 12.6.3 8-bit transfer / receive mode ............................................................................................................... 141 13. asynchronous serial interface (uart ) 13.1 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 13.2 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 13.3 transfer data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 13.4 transfer rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 13.5 data sampling method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 13.6 stop bit length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 13.7 parity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 13.8 transmit/receive operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 13.8.1 data transmit operation .................................................................................................................... 148 13.8.2 data receive operation ..................................................................................................................... 148 13.9 status flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 13.9.1 parity error ............................................................................................................................... ........... 149 13.9.2 framing error ............................................................................................................................... ....... 149 13.9.3 overrun error ............................................................................................................................... ....... 149 13.9.4 receive data buffer full ..................................................................................................................... 150 13.9.5 transmit data buffer empty ............................................................................................................... 150 13.9.6 transmit end flag .............................................................................................................................. 151 14. 10-bit ad converter (adc) 14.1 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 14.2 register configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 14.3 function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 14.3.1 software start mode ........................................................................................................................... 157 14.3.2 repeat mode ............................................................................................................................... ....... 157
v 14.3.3 register setting ............................................................................................................................... . 158 14.4 stop/slow modes during ad conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 14.5 analog input voltage and ad conversion result . . . . . . . . . . . . . . . . . . . . . . . 160 14.6 precautions about ad converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 14.6.1 analog input pin voltage range ........................................................................................................... 161 14.6.2 analog input shared pins .................................................................................................................... 161 14.6.3 noise countermeasure ....................................................................................................................... 161 15. key-on wakeup (kwu) 15.1 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 15.2 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 15.3 function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 16. flash memory 16.1 flash memory control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 16.1.1 flash memory command sequence execution control (flscr) ..................................... 166 16.1.1 .................................................................................................................... ........................................ 166 16.1.2 flash memory standby control (flsstb) ............................................................................ 166 16.2 command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 16.2.1 byte program ............................................................................................................................... ....... 168 16.2.2 sector erase (4-kbyte erase) ............................................................................................................. 168 16.2.3 chip erase (all erase) ........................................................................................................................ 169 16.2.4 product id entry ............................................................................................................................... .. 169 16.2.5 product id exit ............................................................................................................................... ..... 169 16.2.6 read protect ............................................................................................................................... ........ 169 16.3 toggle bit (d6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 16.4 access to the flash memory area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 16.4.1 flash memory control in the serial prom mode ............................................................................... 171 16.4.1.1 how to write to the flash memory by executing the contro l program in the ram area (in the ram loader mode within the serial prom mode) 16.4.2 flash memory control in the mcu mode ............................................................................................ 173 16.4.2.1 how to write to the flash memory by executing a user write control program in the ram area (in the mcu mode) 17. serial prom mode 17.1 outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 17.2 memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 17.3 serial prom mode setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 17.3.1 serial prom mode control pins ........................................................................................................ 176 17.3.2 pin function ............................................................................................................................... ......... 176 17.3.3 example connection for on-board writing ......................................................................................... 177 17.3.4 activating the serial prom mode ...................................................................................................... 178 17.4 interface specifications for uart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 17.5 operation command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 17.6 operation mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 17.6.1 flash memory erasing mode (operating command: f0h) ................................................................. 183 17.6.2 flash memory writing mode (operation command: 30h) .................................................................. 185 17.6.3 ram loader mode (operation command: 60h) ................................................................................ 188 17.6.4 flash memory sum output mode (operation command: 90h) ......................................................... 190 17.6.5 product id code output mode (operation command: c0h) .............................................................. 191 17.6.6 flash memory status output mode (operation command: c3h) ...................................................... 193 17.6.7 flash memory read protection setting mode (operation command: fah) ...................................... 194 17.7 error code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
vi 17.8 checksum (sum) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 17.8.1 calculation method ............................................................................................................................. 1 96 17.8.2 calculation data ............................................................................................................................... ... 197 17.9 intel hex format (binary) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 17.10 passwords . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 17.10.1 password string ............................................................................................................................... . 199 17.10.2 handling of password error .............................................................................................................. 199 17.10.3 password management during program development .................................................................... 199 17.11 product id code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 17.12 flash memory status code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 17.13 specifying the erasure area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 17.14 port input control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 17.15 flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 17.16 uart timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 18. input/output circuit 18.1 control pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 18.2 input/output ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 19. electrical characteristics 19.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 19.2 recommended operating condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 19.2.1 mcu mode (flash memory writing and erasing) ................................................................................ 209 19.2.2 mcu mode (except flash memory writing and erasing) ...................................................................... 210 19.2.3 serial prom mode ............................................................................................................................. 2 10 19.3 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 19.4 ad conversion characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 19.5 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 19.6 flash characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 19.7 recommended oscillating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 19.8 handling precaution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 20. package dimension this is a technical docu ment that describes the operat ing functions and electrical specifications of the 8-bit microc ontroller series tlcs-870/c (lsi).
page 1 060116ebp TMP86FH12MG cmos 8-bit microcontroller ? the information contained herein is subject to change without notice. 021023_d ? toshiba is continually working to improve the quality and reli ability of its products. nevertheless, semiconductor devices in general can malfunction or fail due to their inherent el ectrical sensitivity and vulnerability to physical stre ss. it is the responsibility of the buyer, when utilizing toshiba products, to comply with the standards of sa fety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such toshiba products could cause loss of human life, bodily injury or damage to property. in developing your designs, pleas e ensure that toshiba products are used within specified operating ranges as set forth in the most recent toshiba products specifications. also, please keep in mind the precautions and conditions set forth in the ?handling gui de for semiconductor devices,? or ?toshiba se miconductor reliability handbook? etc. 021023_a ? the toshiba products listed in this document are intended for usage in general electronics applic ations (computer, personal eq uip- ment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). these toshiba products are neithe r intended nor warranted for usage in equipment that requires extr aordinarily high quality and/or re liability or a malfunctionor failure of which may cause loss of human life or bod ily injury (?unintended usage?). unintended us age include atomic energy control instru ments, airplane or spaceship instruments, transporta tion instruments, traffic signal instrume nts, combustion control instruments, medi cal instru- ments, all types of safety dev ices, etc. unintended usage of toshiba products li sted in this document shall be made at the cust omer's own risk. 021023_b ? the products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohibited under any appl icable laws and regulations. 060106_q ? the information contained herein is present ed only as a guide for the applications of our products. no responsibility is assum ed by toshiba for any infringements of patents or other rights of the th ird parties which may result from its use. no license is gran ted by impli- cation or otherwise under any patent or patent rights of toshiba or others. 021023_c ? the products described in this document are subjec t to the foreign exchange and foreign trade laws. 021023_e ? for a discussion of how the reliability of microcontrollers c an be predicted, please refer to section 1.3 of the chapter entit led quality and reliability assurance/h andling precautions. 030619_s this product uses the super flash ? ? the TMP86FH12MG is a single-chip 8-bit high-speed and high-functionality microcomputer incorporating 16384 bytes of flash memory. it is pin-compatible with the tmp86ch12mg (mask rom version). the TMP86FH12MG can realize operations equivalent to those of the tmp86ch12mg by programming the on-chip flash memory. 1.1 features 1. 8-bit single chip microcomputer tlcs-870/c series - instruction execution time : 0.25 s (at 16 mhz) 122 s (at 32.768 khz) - 132 types & 731 basic instructions 2. 22interrupt sources (external : 6 internal : 16) 3. input / output ports (24 pins) large current output: 8pins (typ. 20ma), led direct drive 4. watchdog timer 5. prescaler - time base timer - divider output function 6. 10-bit timer counter: 1ch (2 output pins) 2ports output ppg (programmed pulse generator) 50%duty output mode variable duty output mode external-triggered start and stop product no. rom (flash) ram package mask rom mcu emulation chip TMP86FH12MG 16384 bytes 512 bytes p-ssop30-56-0.65 tmp86ch12mg tmp86c912xb
page 2 1.1 features TMP86FH12MG emargency stop pin 7. 16-bit timer counter: 1 ch - timer, external trigger, wi ndow, pulse width measurement, event counter, programmable pulse generate (ppg) modes 8. 8-bit timer counter : 2 ch - timer, event counter, programmable divider output (pdo), pulse width modulation (pwm) output, programmable pulse generation (ppg) modes 9. 8-bit sio: 1 ch 10. 8-bit uart : 1 ch 11. 10-bit successive approximation type ad converter - analog input: 8 ch 12. key-on wakeup : 4 ch 13. clock operation single clock mode dual clock mode 14. low power consumption operation stop mode: oscillation stops. (battery/capacitor back-up.) slow1 mode: low power consumption operation usin g low-frequency clock.(high-frequency clock stop.) slow2 mode: low power consumption operation usin g low-frequency clock.(high-frequency clock oscillate.) idle0 mode: cpu stops, and only the time-based-tim er(tbt) on peripherals operate using high fre- quency clock. release by falling edge of th e source clock which is set by tbtcr. idle1 mode: cpu stops and peripherals operate us ing high frequency clock. release by interru- puts(cpu restarts). idle2 mode: cpu stops and peripherals operate usin g high and low frequency clock. release by inter- ruputs. (cpu restarts). sleep0 mode: cpu stops, and only the time-based-t imer(tbt) on peripherals operate using low fre- quency clock.release by falling edge of th e source clock which is set by tbtcr. sleep1 mode: cpu stops, and peripherals operate using low frequency clock. release by interru- put.(cpu restarts). sleep2 mode: cpu stops and peripherals operate using high and low frequency clock. release by interruput. 15. wide operation voltage: 2.7 v to 5.5 v at 8 mhz /32.768 khz 4.5 v to 5.5 v at 16 mhz /32.768 khz
page 3 TMP86FH12MG 1.2 pin assignment figure 1-1 pin assignment 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 vss xout test vdd (xtin) p21 (xtout) p22 reset ( int5 / stop ) p20 (tc1/int4) p14 (txd) p00 xin (boot/rxd) p01 (si) p03 (so) p04 p05 (tc7) p07 (ppg2/int2) p10 (tc3/ pdo3/pwm3 ) p11 (tc4/ pdo4/pwm4/ppg4 ) p12 ( dvo ) ( sck ) p02 p06 (ppg1/int1) p32 (ain2) p34 (ain4/stop1) p35 (ain5/stop2) p37 (ain7) p36 (ain6/stop3) p33 (ain3/stop0) p31 (ain1/ int0 ) p30 (ain0/ emg ) p13 ( ppg /int3)
page 4 1.3 block diagram TMP86FH12MG 1.3 block diagram figure 1-2 block diagram
page 5 TMP86FH12MG 1.4 pin names and functions the TMP86FH12MG has mcu mode, parallel prom mode, and serial prom mode. table 1-1 shows the pin functions in mcu mode. the serial prom mode is explained later in a separate chapter. table 1-1 pin names and functions(1/2) pin name pin number input/output functions p07 ppg2 int2 18 io o i port07 timer counter 7 ppg2 output external interrupt 2 input p06 ppg1 int1 17 io o i port06 timer counter 7 ppg1 output external interrupt 1 input p05 tc7 16 io i port05 timer counter 7 input p04 so 15 io o port04 serial data output p03 si 14 io i port03 serial data input p02 sck 13 io io port02 serial clock i/o p01 rxd boot 12 io i i port01 uart data input serial prom mode control input p00 txd 11 io o port00 uart data output p14 int4 tc1 10 io i i port14 external interrupt 4 input tc1 input p13 ppg int3 22 io o i port13 ppg output external interrupt 3 input p12 dvo 21 io o port12 divider output p11 tc4 pdo4/pwm4/ppg4 20 io i o port11 tc4 input pdo4/pwm4/ppg4 output p10 tc3 pdo3/pwm3 19 io i o port10 tc3 input pdo3/pwm3 output p22 xtout 7 io o port22 resonator connecting pins(32.768khz) for inputting external clock p21 xtin 6 io i port21 resonator connecting pins(32.768khz) for inputting external clock p20 stop int5 9 io i i port20 stop mode release signal input external interrupt 5 input p37 ain7 30 io i port37 analog input7
page 6 1.4 pin names and functions TMP86FH12MG p36 ain6 stop3 29 io i i port36 analog input6 stop3 input p35 ain5 stop2 28 io i i port35 analog input5 stop2 input p34 ain4 stop1 27 io i i port34 analog input4 stop1 input p33 ain3 stop0 26 io i i port33 analog input3 stop0 input p32 ain2 25 io i port32 analog input2 p31 ain1 int0 24 io i i port31 analog input1 external interrupt 0 input p30 ain0 emg 23 io i i port30 analog input0 timer counter 7 emergency stop input xin 2 i resonator connecting pins for high-frequency clock xout 3 o resonator connecting pins for high-frequency clock reset 8 i reset signal test 4 i test pin for out-going test. normally, be fixed to low. vdd 5 i +5v vss 1 i 0(gnd) table 1-1 pin names and functions(2/2) pin name pin number input/output functions
page 7 TMP86FH12MG 2. operational description 2.1 cpu core functions the cpu core consists of a cpu, a system cl ock controller, and an interrupt controller. this section provides a description of the cpu core, the program memory, the data memory, and the reset circuit. 2.1.1 memory address map the TMP86FH12MG memory is compos ed flash, ram, dbr(data buffer register) and sfr(special func- tion register). they are all mapped in 64-kbyte address space. figure 2-1 shows the TMP86FH12MG memory address map. figure 2-1 memory address map 2.1.2 program memory (flash) the TMP86FH12MG has a 16384 bytes (address c000h to ffffh) of program memory (flash ). sfr 0000 h 64 bytes sfr: ram: special function register includes: i/o ports peripheral control registers peripheral status registers system control registers program status word random access memory includes: data memory stack 003f h ram 0040 h 512 bytes 023f h dbr 0f80 h 128 bytes dbr: data buffer register includes: peripheral control registers peripheral status registers 0fff h c000 h flash: program memory flash 16384 bytes ffa0 h vector table for interrupts (32 bytes) ffbf h ffc0 h vector table for vector call instructions (32 bytes) ffdf h ffe0 h vector table for interrupts (32 bytes) ffff h
page 8 2. operational description 2.2 system clock controller TMP86FH12MG 2.1.3 data memory (ram) the TMP86FH12MG has 512bytes (address 0040h to 023fh ) of internal ram. the first 192 bytes (0040h to 00ffh) of the internal ram are locat ed in the direct area; instructions with shorten operations are available against such an area. the data memory contents become un stable when the power supply is turned on; therefore, the data memory should be initialized by an initialization routine. 2.2 system clock controller the system clock controller consists of a clock generator, a timing generator, and a standby controller. figure 2-2 syst em colck control 2.2.1 clock generator the clock generator generates the basic clock which pr ovides the system clocks supplied to the cpu core and peripheral hardware. it contains two oscillation ci rcuits: one for the high-frequency clock and one for the low-frequency clock. power consumption can be reduced by switching of the standby controller to low-power operation based on the low-frequency clock. the high-frequency (fc) clock and low-frequency (fs) clock can easily be obtained by connecting a resonator between the xin/xout and xtin/xtout pins respectively. clock input from an exte rnal oscillator is also possible. in this case, external clock is applied to xin/xtin pin with xout/xtout pin not connected. example :clears ram to ?00h?. (TMP86FH12MG) ld hl, 0040h ; start address setup ld a, h ; initial value (00h) setup ld bc, 01ffh sramclr: ld (hl), a inc hl dec bc jrs f, sramclr tbtcr syscr2 syscr1 xin xout xtin xtout fc 0036 h 0038 h 0039 h fs timing generator control register timing generator standby controller system clocks clock generator control high-frequency clock oscillator low-frequency clock oscillator clock generator system control registers
page 9 TMP86FH12MG figure 2-3 examples of resonator connection note:the function to monitor the basic clock directly at external is not provided for hardware, however, with dis- abling all interrupts and watchdog timers, the oscillation frequency can be adjusted by monitoring the pulse which the fixed frequency is outputted to the port by the program. the system to require the adjustment of the oscilla tion frequency should create the program for the adjust- ment in advance. xout xin (open) xout xin xtout xtin (open) xtout xtin (a) crystal/ceramic resonator (b) external oscillator (c) crystal (d) external oscillator high-frequency clock low-frequency clock
page 10 2. operational description 2.2 system clock controller TMP86FH12MG 2.2.2 timing generator the timing generator generates the various system cloc ks supplied to the cpu core and peripheral hardware from the basic clock (fc or fs). the timing generator provides the following functions. 1. generation of main system clock 2. generation of divider output ( dvo ) pulses 3. generation of source clocks for time base timer 4. generation of source clocks for watchdog timer 5. generation of internal source clocks for timer/counters 6. generation of warm-up clocks for releasing stop mode 2.2.2.1 configuration of timing generator the timing generator consists of a 2-stage prescaler, a 21-stage divider, a main system clock generator, and machine cycle counters. an input clock to the 7th stage of the divider depends on the operating mode, syscr2 and tbtcr, that is shown in figure 2-4. as reset and stop mode star ted/canceled, the prescaler and the divider are cleared to ?0?. figure 2-4 configurat ion of timing generator multi- plexer high-frequency clock fc low-frequency clock fs divider sysck fc/4 fc or fs machine cycle counters main system clock generator 1 2 1 4 3 2 8 7 10 9 12 11 14 13 16 15 dv7ck multiplexer warm-up controller watchdog timer a s b y s b0 a0 y0 b1 a1 y1 5 6 17 18 19 20 21 timer counter, serial interface, time-base-timer, divider output, etc. (peripheral functions)
page 11 TMP86FH12MG note 1: in single clock mode, do not set dv7ck to ?1?. note 2: do not set ?1? on dv7ck while the low-frequency clock is not operated stably. note 3: fc: high-frequency clock [hz], fs : low-frequency clock [hz], *: don?t care note 4: in slow1/2 and sleep1/2 modes, the dv7ck setting is ineffective, and fs is input to the 7th stage of the divider. note 5: when stop mode is entered from normal1/2 mode, the dv 7ck setting is ineffective during the warm-up period after release of stop mode, and the 6th stage of the divider is input to the 7th stage during this period. 2.2.2.2 machine cycle instruction execution and peripheral hardware operat ion are synchronized with the main system clock. the minimum instruction execution uni t is called an ?machine cycle?. th ere are a total of 10 different types of instructions for the tlcs-870/c series: ra nging from 1-cycle instructions which require one machine cycle for execution to 10-cyc le instructions which require 10 machine cycles fo r execution. a machine cycle consists of 4 states (s0 to s3), and each state consists of one main system clock. figure 2-5 machine cycle 2.2.3 operation mode control circuit the operation mode control circuit starts and stops the oscillation circuits for the high-frequency and low- frequency clocks, and switches the main system clock. there are three operating modes: single clock mode, dual clock mode and stop mode. these modes are cont rolled by the system cont rol registers (syscr1 and syscr2). figure 2-6 shows the operating mode transition diagram. 2.2.3.1 single-clock mode only the oscillation circuit for the high-frequenc y clock is used, and p21 (xtin) and p22 (xtout) pins are used as input/output ports . the main-system clock is obtained from the high-frequency clock. in the single-clock mode, the machine cycle time is 4/fc [s]. (1) normal1 mode in this mode, both the cpu core and on-chip pe ripherals operate using the high-frequency clock. the TMP86FH12MG is placed in this mode after reset. timing generator control register tbtcr (0036h) 76543210 (dvoen) (dvock) dv7ck (tbten) (tbtck) (initial value: 0000 0000) dv7ck selection of input to the 7th stage of the divider 0: fc/2 8 [hz] 1: fs r/w main system clock state machine cycle s3 s2 s1 s0 s3 s2 s1 s0 1/fc or 1/fs [s]
page 12 2. operational description 2.2 system clock controller TMP86FH12MG (2) idle1 mode in this mode, the internal oscillation circuit remains active. the cpu and the watchdog timer are halted; however on-chip peripherals remain active (operate using the high-frequency clock). idle1 mode is started by syscr2 = "1", and idle1 mode is released to normal1 mode by an interrupt request from the on-chip peri pherals or external interrupt inputs. when the imf (interrupt master enable flag) is ?1? (interrupt enable), the execution will resume with the acceptance of the interrupt, and the operation will return to nor mal after the interrupt service is completed. when the imf is ?0? (interrupt disable), the execution will resume with the instruction which follows the idle1 mode start instruction. (3) idle0 mode in this mode, all the circuit, except oscillator an d the timer-base-timer, stops operation. this mode is enabled by syscr2 = "1". when idle0 mode starts, the cpu stops and the timing generator stops feeding the clock to the peripheral circuits other than tbt. then, upon de tecting the falling edge of the source clock selected with tbtcr, the timing generator starts feeding the clock to al l peripheral circuits. when returned from idle0 mode, the cpu rest arts operating, entering normal1 mode back again. idle0 mode is entered and returned regardless of how tbtcr is set. when imf = ?1?, ef1 (tbt interrupt individu al enable flag) = ?1?, and tb tcr = ?1?, interrupt pro- cessing is performed. when idle0 mode is entered while tbtcr = ?1?, the inttbt interrupt latch is set after returning to normal1 mode. 2.2.3.2 dual-clock mode both the high-frequency and low-frequency oscillatio n circuits are used in th is mode. p21 (xtin) and p22 (xtout) pins cannot be used as input/output ports. the main system clock is obtained from the high-frequency clock in normal2 and idle2 modes, and is obtained from the low-frequency clock in slow and sleep modes. th e machine cycle time is 4/fc [s] in the normal2 and idle2 modes, and 4/fs [s] (122 s at fs = 32.768 khz) in the slow and sleep modes. the tlcs-870/c is placed in the signal-clock mode during reset. to use the dual-clock mode, the low- frequency oscillator should be turned on at the start of a program. (1) normal2 mode in this mode, the cpu core operates with the high-frequency clock. on-chip peripherals operate using the high-frequency clock and/or low-frequency clock. (2) slow2 mode in this mode, the cpu core operates with the lo w-frequency clock, while both the high-frequency clock and the low-frequency clock are operated. as the syscr2 becomes "1", the hard- ware changes into slow2 mode. as the syscr2 becomes ?0?, the hardware changes into normal2 mode. as the syscr2 beco mes ?0?, the hardware changes into slow1 mode. do not clear syscr2 to ?0? during slow2 mode. (3) slow1 mode this mode can be used to reduce power-consu mption by turning off oscillation of the high-fre- quency clock. the cpu core and on-chip peri pherals operate using th e low-frequency clock.
page 13 TMP86FH12MG switching back and forth between slow1 and slow2 modes are performed by syscr2. in slow1 and sleep modes, the input clock to the 1st stage of the divider is stopped; output from the 1st to 6th stages is also stopped. (4) idle2 mode in this mode, the internal oscillation circuit remain active. the cpu and the watchdog timer are halted; however, on-chip peripherals remain activ e (operate using the high-frequency clock and/or the low-frequency clock). starting and releasing of idle2 mode are the same as for idle1 mode, except that operation re turns to normal2 mode. (5) sleep1 mode in this mode, the internal oscillation circuit of the low-frequency clock remains active. the cpu, the watchdog timer, and the internal oscillation circuit of the high-frequency clock are halted; how- ever, on-chip peripherals remain active (operate us ing the low-frequency clock). starting and releas- ing of sleep mode are the same as for idle1 mo de, except that operation returns to slow1 mode. in slow1 and sleep1 modes, the input clock to the 1st stage of the divider is stopped; output from the 1st to 6th stages is also stopped. (6) sleep2 mode the sleep2 mode is the idle mode corresponding to the slow2 mode. the status under the sleep2 mode is same as that under the sleep1 mo de, except for the oscilla tion circuit of the high- frequency clock. (7) sleep0 mode in this mode, all the circuit, except oscillator and the timer-base-timer, stops operation. this mode is enabled by setting ?1? on bit syscr2. when sleep0 mode starts, the cp u stops and the timing generator stops feeding the clock to the peripheral circuits other than tbt. then, upon de tecting the falling edge of the source clock selected with tbtcr, the timing generator starts feeding the clock to all peripheral circuits. when returned from sleep0 mode, the cpu restarts operating, entering slow1 mode back again. sleep0 mode is entered and returned re gardless of how tbtcr is set. when imf = ?1?, ef1 (tbt interrupt individual enable flag ) = ?1?, and tbtcr = ?1?, interrupt pro- cessing is performed. when sleep0 mode is entered while tbtcr = ?1?, the inttbt interrupt latch is set after returning to slow1 mode. 2.2.3.3 stop mode in this mode, the internal oscillation circuit is turned off, causing all system operations to be halted. the internal status immediately prior to the halt is held with a lowest power consumption during stop mode. stop mode is started by the syst em control register 1 (syscr1), an d stop mode is released by a inputting (either level-sensitive or edge-sens itive can be programmably selected) to the stop pin. after the warm-up period is completed, the execution resumes with the instruction which follows the stop mode start instruction.
page 14 2. operational description 2.2 system clock controller TMP86FH12MG note 1: normal1 and normal2 modes are generically called no rmal; slow1 and slow2 are called slow; idle0, idle1 and idle2 are called idle; sleep0, sleep1 and sleep2 are called sleep. note 2: the mode is released by fa lling edge of tbtcr setting. figure 2-6 operating mode transition diagram table 2-1 operating mode and conditions operating mode oscillator cpu core tbt other peripherals machine cycle time high frequency low frequency single clock reset oscillation stop reset reset reset 4/fc [s] normal1 operate operate operate idle1 halt idle0 halt stop stop halt ? dual clock normal2 oscillation oscillation operate with high frequency operate operate 4/fc [s] idle2 halt slow2 operate with low frequency 4/fs [s] sleep2 halt slow1 stop operate with low frequency sleep1 halt sleep0 halt stop stop halt ? note 2 syscr2 = "1" stop pin input stop pin input stop pin input interrupt interrupt syscr2 = "0" syscr2 = "1" syscr2 = "0" syscr2 = "0" syscr1 = "1" syscr1 = "1" syscr1 = "1" syscr2 = "1" syscr2 = "1" interrupt syscr2 = "1" syscr2 = "1" interrupt syscr2 = "1" reset release normal1 mode idle0 mode (a) single-clock mode idle1 mode normal2 mode idle2 mode syscr2 = "1" slow2 mode sleep2 mode slow1 mode sleep1 mode sleep0 mode reset (b) dual-clock mode stop syscr2 = "1" note 2
page 15 TMP86FH12MG note 1: always set retm to ?0? when transiting from normal mode to stop mode. always set retm to ?1? when transiting from slow mode to stop mode. note 2: when stop mode is released with reset pin input, a return is made to normal1 regardless of the retm contents. note 3: fc: high-frequency clock [hz], fs : low-frequency clock [hz], *; don?t care note 4: bits 1 and 0 in syscr1 are read as undefined data when a read instruction is executed. note 5: as the hardware becomes stop mode under outen = ?0?, input value is fixed to ?0?; therefore it may cause external interrupt request on account of falling edge. note 6: when the key-on wakeup is used, relm should be set to "1". note 7: port p20 is used as stop pin. therefore, when stop mode is started, outen does not affect to p20, and p20 becomes high-z mode. note 8: the warmig-up time should be set correctly for using oscillator. note 1: a reset is applied if both xen and xten are cleared to ?0?, xen is cleared to ?0? when sysck = ?0?, or xten is cleared to ?0? when sysck = ?1?. note 2: *: don?t care, tg: timing generator, *; don?t care note 3: bits 3, 1 and 0 in syscr2 are always read as undefined value. note 4: do not set idle and tghalt to ?1? simultaneously. note 5: because returning from idle0/sleep0 to normal1/slow 1 is executed by the asynchronous internal clock, the period of idle0/sleep0 mode might be shorter than the period setting by tbtcr. note 6: when idle1/2 or sleep1/2 mode is rel eased, idle is automatically cleared to ?0?. note 7: when idle0 or sleep0 mode is released, tghalt is automatically cleared to ?0?. note 8: before setting tghalt to ?1?, be sure to stop peripheral s. if peripherals are not stopped, the interrupt latch of periph erals may be set after idle0 or sleep0 mode is released. system control register 1 syscr176543210 (0038h) stop relm retm outen wut (initial value: 0000 00**) stop stop mode start 0: cpu core and peripherals remain active 1: cpu core and peripherals are halted (start stop mode) r/w relm release method for stop mode 0: edge-sensitive release 1: level-sensitive release r/w retm operating mode after stop mode 0: return to normal1/2 mode 1: return to slow1 mode r/w outen port output during stop mode 0: high impedance 1: output kept r/w wut warm-up time at releasing stop mode return to normal mode return to slow mode r/w 00 01 10 11 3 x 2 16 /fc 2 16 /fc 3 x 2 14 /fc 2 14 /fc 3 x 2 13 /fs 2 13 /fs 3 x 2 6 /fs 2 6 /fs system control register 2 syscr2 (0039h) 76543210 xen xten sysck idle tghalt (initial value: 1000 *0**) xen high-frequency oscillator control 0: turn off oscillation 1: turn on oscillation r/w xten low-frequency oscillator control 0: turn off oscillation 1: turn on oscillation sysck main system clock select (write)/main system clock moni- tor (read) 0: high-frequency clock (normal1/normal2/idle1/idle2) 1: low-frequency clock (slow1/slow2/sleep1/sleep2) idle cpu and watchdog timer control (idle1/2 and sleep1/2 modes) 0: cpu and watchdog timer remain active 1: cpu and watchdog timer are stopped (start idle1/2 and sleep1/2 modes) r/w tghalt tg control (idle0 and sleep0 modes) 0: feeding clock to all peripherals from tg 1: stop feeding clock to peripherals except tbt from tg. (start idle0 and sleep0 modes)
page 16 2. operational description 2.2 system clock controller TMP86FH12MG 2.2.4 operating mode control 2.2.4.1 stop mode stop mode is controlled by the system control register 1, the stop pin input and key-on wakeup input (stop3 to stop0) which is controlled by the stop mode release control register (stopcr). the stop pin is also used both as a port p20 and an int5 (external interrupt input 5) pin. stop mode is started by setting syscr1 to ?1?. during stop mode, the following status is maintained. 1. oscillations are turned off, and all internal operations are halted. 2. the data memory, registers, the program status wo rd and port output latches are all held in the status in effect before stop mode was entered. 3. the prescaler and the divider of th e timing generator are cleared to ?0?. 4. the program counter holds the address 2 ahead of th e instruction (e.g., [set (syscr1).7]) which started stop mode. stop mode includes a level-sensitive mode and an edge-sensitive mode, either of which can be selected with the syscr1. do not use any key-on wakeup input (stop3 to stop0) for releas- ing stop mode in edge-sensitive mode. note 1: the stop mode can be released by either the stop or key-on wakeup pin (stop3 to stop0). however, because the stop pin is different from the key-on wakeup and can not inhibit the release input, the stop pin must be used for releasing stop mode. note 2: during stop period (from start of stop mode to end of warm up), due to changes in the external interrupt pin signal, interrupt latches may be set to ?1? and interrupts may be accepted immediately after stop mode is released. before starting stop mode, therefore, disable interrupts. also, before enabling interrupts after stop mode is released, clear unnecessary interrupt latches. (1) level-sensitive release mode (relm = ?1?) in this mode, stop mode is released by setting the stop pin high or setting the stop3 to stop0 pin input which is enabled by stopcr. this mo de is used for capacitor backup when the main power supply is cut off and long term battery backup. even if an instruction for starting stop mode is executed while stop pin input is high or stop3 to stop0 input is low, stop mode does not start but instead the warm-up sequence starts immedi- ately. thus, to start stop mode in the level-sensitive release mode, it is necessary for the program to first confirm that the stop pin input is low or stop3 to stop0 input is high. the following two methods can be used for confirmation. 1. testing a port. 2. using an external interrupt input int5 ( int5 is a falling edge-sensitive input). example 1 :starting stop mode from normal mode by testing a port p20. ld (syscr1), 01010000b ; sets up the level-sensitive release mode sstoph: test (p2prd). 0 ; wait until the stop pin input goes low level jrs f, sstoph di ; imf m 0 set (syscr1). 7 ; starts stop mode
page 17 TMP86FH12MG figure 2-7 level-s ensitive release mode note 1: even if the stop pin input is low after warm-up start, the stop mode is not restarted. note 2: in this case of changing to the level-s ensitive mode from the edge-s ensitive mode, the release mode is not switched until a rising edge of the stop pin input is detected. (2) edge-sensitive release mode (relm = ?0?) in this mode, stop mode is released by a rising edge of the stop pin input. this is used in appli- cations where a relatively short pr ogram is executed repeat edly at periodic intervals. this periodic signal (for example, a clock from a low-power consumption oscillator) is input to the stop pin. in the edge-sensitive release mode, stop mode is started even when the stop pin input is high level. do not use any stop3 to stop0 pin input for releasing stop mode in edge-sensitive release mode. figure 2-8 edge-sensitive release mode example 2 :starting stop mode from normal mode with an int5 interrupt. pint5: test (p2prd). 0 ; to reject noise, stop mode does not start if jrs f, sint5 port p20 is at high ld (syscr1), 01010000b ; sets up the level-sensitive release mode. di ; imf example :starting stop mode from normal mode di ; imf v ih normal operation warm up stop operation confirm by program that the stop pin input is low and start stop mode. always released if the stop pin input is high. stop pin xout pin stop mode is released by the hardware. normal operation normal operation normal operation v ih stop mode is released by the hardware at the rising edge of stop pin input. warm up stop mode started by the program. stop operation stop operation stop pin xout pin
page 18 2. operational description 2.2 system clock controller TMP86FH12MG stop mode is released by the following sequence. 1. in the dual-clock mode, when returning to normal2, both the high-frequency and low- frequency clock oscillators are turned on; when returning to slow1 mode, only the low- frequency clock oscillator is turned on. in the single-clock mode, only the high-frequency clock oscillator is turned on. 2. a warm-up period is inserted to allow oscillation time to stabilize. during warm up, all internal operations remain halted. four differ ent warm-up times can be selected with the syscr1 in accordance with the resonator characteristics. 3. when the warm-up time has elapsed, normal operation resumes with the instruction follow- ing the stop mode start instruction. note 1: when the stop mode is released, the start is made after the prescaler and the divider of the timing generator are cleared to "0". note 2: stop mode can also be released by inputting low level on the reset pin, which immediately performs the normal reset operation. note 3: when stop mode is released with a low hold voltage, the following cautions must be observed. the power supply voltage must be at the operating voltage level before releasing stop mode. the reset pin input must also be ?h? level, rising together with the power supply voltage. in this case, if an external time const ant circuit has been connected, the reset pin input voltage will increase at a slower pace than the power supply vo ltage. at this time, there is a danger that a reset may occur if input voltage level of the reset pin drops below the non-inverting high-level input voltage (hysteresis input). note 1: the warm-up time is obtained by dividing the ba sic clock by the divider. therefore, the warm-up time may include a certain amount of error if ther e is any fluctuation of the oscillation frequency when stop mode is released. thus, the warm -up time must be considered as an approximate value. table 2-2 warm-up time example (at fc = 16.0 mhz, fs = 32.768 khz) wut warm-up time [ms] return to normal mode return to slow mode 00 01 10 11 12.288 4.096 3.072 1.024 750 250 5.85 1.95
page 19 TMP86FH12MG figure 2-9 stop mode start/release instruction address a + 4 0 instruction address a + 3 turn on turn on warm up 0 n halt set (syscr1). 7 turn off (a) stop mode start (example: start with set (syscr1). 7 instruction located at address a) a + 6 a + 5 a + 4 a + 3 a + 2 n + 2 n + 3 n + 4 a + 3 n + 1 instruction address a + 2 2 1 0 3 (b) stop mode release count up turn off halt oscillator circuit program counter instruction execution divider main system clock oscillator circuit stop pin input program counter instruction execution divider main system clock
page 20 2. operational description 2.2 system clock controller TMP86FH12MG 2.2.4.2 idle1/2 mode and sleep1/2 mode idle1/2 and sleep1/2 modes are controlled by the system control register 2 (syscr2) and maskable interrupts. the following status is maintained during these modes. 1. operation of the cpu and watchdog timer (wdt) is halted. on-chip peripherals continue to operate. 2. the data memory, cpu registers, program status word and port output latches are all held in the status in effect before these modes were entered. 3. the program counter holds the address 2 ahead of th e instruction which starts these modes. figure 2-10 idle1/ 2 and sleep1/2 modes reset reset input ?0? ?1? (interrupt release mode) yes no no cpu and wdt are halted interrupt request imf interrupt processing normal release mode yes starting idle1/2 and sleep1/2 modes by instruction execution of the instruc- tion which follows the idle1/2 and sleep1/2 modes start instruction
page 21 TMP86FH12MG ? start the idle1/2 and sleep1/2 modes after imf is set to "0", set the individual inte rrupt enable flag (ef) which releases idle1/2 and sleep1/2 modes. to start idle1/2 and sl eep1/2 modes, set syscr2 to ?1?. ? release the idle1 /2 and sleep1/2 modes idle1/2 and sleep1/2 modes include a normal release mode and an interrupt release mode. these modes are selected by interrupt master en able flag (imf). after releasing idle1/2 and sleep1/2 modes, the syscr2 is automatically cleared to ?0? and the operation mode is returned to the mode preced ing idle1/2 and sleep1/2 modes. idle1/2 and sleep1/2 modes can also be released by inputting low level on the reset pin. after releasing reset, the operation mode is started from normal1 mode. (1) normal release mode (imf = ?0?) idle1/2 and sleep1/2 modes are released by any interrupt source enabled by the individual interrupt enable flag (ef). after the interrupt is generated, the program operation is resumed from the instruction following the idle1/2 and sleep1/2 mo des start instruction. normally, the interrupt latches (il) of the interrupt source used for releas ing must be cleared to ?0? by load instructions. (2) interrupt release mode (imf = ?1?) idle1/2 and sleep1/2 modes are released by any interrupt source enabled with the individual interrupt enable flag (ef) and the interrupt processi ng is started. after the interrupt is processed, the program operation is resumed from the instruction following the instruction, which starts idle1/2 and sleep1/2 modes. note: when a watchdog timer interrupts is generated immediately before idle1/2 and sleep1/2 modes are started, the watchdog timer interrupt will be processed but idle1/2 and sleep1/2 modes will not be started.
page 22 2. operational description 2.2 system clock controller TMP86FH12MG figure 2-11 idle1/2 and sleep1/2 modes start/release halt halt halt halt operate instruction address a + 2 a + 3 a + 2 a + 4 a + 3 a + 3 halt set (syscr2). 4 operate operate operate acceptance of interrupt ?r:wnormal release mode ?s:winterrupt release mode main system clock interrupt request program counter instruction execution watchdog timer main system clock interrupt request program counter instruction execution watchdog timer main system clock interrupt request program counter instruction execution watchdog timer (a) idle1/2 and sleep1/2 modes start (example: star ting with the set instruction located at address a) (b) idle1/2 and sleep1/2 modes release
page 23 TMP86FH12MG 2.2.4.3 idle0 and sleep0 modes (idle0, sleep0) idle0 and sleep0 modes are controlled by the system control register 2 (syscr2) and the time base timer control register (tbtcr). the following stat us is maintained during idle0 and sleep0 modes. 1. timing generator stops feeding clock to peripherals except tbt. 2. the data memory, cpu registers, program status word and port output latches are all held in the status in effect before idle0 and sleep0 modes were entered. 3. the program counter holds the address 2 ahead of the instru ction which starts idle0 and sleep0 modes. note: before starting idle0 or sleep0 mode, be sure to stop (disable) peripherals. figure 2-12 idle 0 and sleep0 modes yes (normal release mode) yes (interrupt release mode) no yes reset input cpu and wdt are halted reset tbt source clock falling edge tbtcr = "1" interrupt processing imf = "1" yes tbt interrupt enable no no no no stopping peripherals by instruction yes starting idle0, sleep0 modes by instruction execution of the instruction which follows the idle0, sleep0 modes start instruction
page 24 2. operational description 2.2 system clock controller TMP86FH12MG ? start the idle0 and sleep0 modes stop (disable) peripherals such as a timer counter. to start idle0 and sleep0 modes, set syscr2 to ?1?. ? release the idle0 and sleep0 modes idle0 and sleep0 modes include a normal re lease mode and an interrupt release mode. these modes are selected by inte rrupt master flag (imf), the i ndividual interrupt enable flag of tbt and tbtcr. after releasing idle0 and sleep0 modes, the syscr2 is automatically cleared to ?0? and the operatio n mode is returned to the mode preceding idle0 and sleep0 modes. before starting the idle0 or sleep0 mode, when the tbtcr is set to ?1?, inttbt interrupt latch is set to ?1?. idle0 and sleep0 modes can also be re leased by inputting low level on the reset pin. after releasing reset, the operation mode is started from normal1 mode. note: idle0 and sleep0 modes start/release wi thout reference to tbtcr setting. (1) normal release mode (imf ? ? idle0 and sleep0 modes are released by the source clock falling edge, which is setting by the tbtcr. after the falling edge is detect ed, the program operation is resumed from the instruction following the idle0 and sleep0 modes start instruction. before starting the idle0 or sleep0 mode, when the tbtcr is set to ?1?, inttbt interrupt latch is set to ?1?. (2) interrupt release mode (imf ? ? idle0 and sleep0 modes are released by the source clock falling edge, which is setting by the tbtcr and inttbt interrupt processing is started. note 1: because returning from idle0, sleep0 to normal1, slow1 is executed by the asynchro- nous internal clock, the period of idle0, sleep0 mode might be the shorter than the period set- ting by tbtcr. note 2: when a watchdog timer interrupt is generat ed immediately before idle0/sleep0 mode is started, the watchdog timer interrupt will be processed but idle0/sleep0 mode will not be started.
page 25 TMP86FH12MG figure 2-13 idle0 and slee p0 modes start/release halt halt operate instruction address a + 2 halt operate set (syscr2). 2 halt operate acceptance of interrupt halt ?r:wnormal release mode ?s:winterrupt release mode main system clock interrupt request program counter instruction execution watchdog timer main system clock tbt clock tbt clock program counter instruction execution watchdog timer main system clock program counter instruction execution watchdog timer a + 3 a + 2 a + 4 a + 3 a + 3 (a) idle0 and sleep0 modes start (example: starting with the set instruction located at address a (b) idle and sleep0 modes release
page 26 2. operational description 2.2 system clock controller TMP86FH12MG 2.2.4.4 slow mode slow mode is controlled by the sy stem control register 2 (syscr2). the following is the methods to switch the mode with the warm-up counter. (1) switching from normal2 mode to slow1 mode first, set syscr2 to switch the main system clock to the low-frequency clock for slow2 mode. next, clear syscr2 to turn off high-frequency oscillation. note: the high-frequency clock can be co ntinued oscillation in order to return to normal2 mode from slow mode quickly. always turn off oscillat ion of high-frequency clock when switching from slow mode to stop mode. example 1 :switching from normal2 mode to slow1 mode. set (syscr2). 5 ; syscr2 example 2 :switching to the slow1 mode after low-frequency clock has stabilized. set (syscr2). 6 ; syscr2
page 27 TMP86FH12MG (2) switching from slow1 mode to normal2 mode note: after sysck is cleared to ?0?, executing the in structions is continiued by the low-frequency clock for the period synchronized with low-frequency and high-frequency clocks. first, set syscr2 to turn on the high-fre quency oscillation. when time for stabilization (warm up) has been taken by the timer/counter (tc4,tc3), clear syscr2 to switch the main system clock to the high-frequency clock. slow mode can also be released by inputting low level on the reset pin. after releasing reset, the operation mode is started from normal1 mode. example :switching from the slow1 mode to the normal2 mode (fc = 16 mhz, warm-up time is 4.0 ms). set (syscr2). 7 ; syscr2 high-frequency clock low-frequency clock main system clock sysck
page 28 2. operational description 2.2 system clock controller TMP86FH12MG figure 2-14 switching between the normal2 and slow modes set (syscr2). 7 normal2 mode clr (syscr2). 7 set (syscr2). 5 normal2 mode turn off (a) switching to the slow mode slow1 mode slow2 mode clr (syscr2). 5 (b) switching to the normal2 mode high- frequency clock low- frequency clock main system clock instruction execution sysck xen high- frequency clock low- frequency clock main system clock instruction execution sysck xen slow1 mode warm up during slow2 mode
page 29 TMP86FH12MG 2.3 reset circuit the TMP86FH12MG has four types of re set generation procedures: an external reset input, an address trap reset, a watchdog timer reset and a system cloc k reset. of these reset, the address trap reset, the watchdog timer and the system clock reset are a malfunction re set. when the malfunction reset request is detected, reset occurs during the maximum 24/fc[s]. the malfunction reset circuit such as watchdog timer reset, address trap reset and system clock reset is not initial- ized when power is turned on. therefore, reset may occur during maximum 24/fc[s] (1.5 s at 16.0 mhz) when power is turned on. table 2-3 shows on-chip hardware initialization by reset action. 2.3.1 external reset input the reset pin contains a schmitt trigger (hysteresis) with an internal pull-up resistor. when the reset pin is held at ?l? level for at least 3 machin e cycles (12/fc [s]) wi th the power supply volt- age within the operating voltage range and oscillation stab le, a reset is applied and the internal state is initial- ized. when the reset pin input goes high, the reset operation is rele ased and the program execution starts at the vector address stored at addresses fffeh to ffffh. figure 2-15 reset circuit table 2-3 initializing internal status by reset action on-chip hardware initial value on-chip hardware initial value program counter (pc) (fffeh) prescaler and divider of timing generator 0 stack pointer (sp) not initialized general-purpose registers (w, a, b, c, d, e, h, l, ix, iy) not initialized jump status flag (jf) not initialized watchdog timer enable zero flag (zf) not initialized output latches of i/o ports refer to i/o port circuitry carry flag (cf) not initialized half carry flag (hf) not initialized sign flag (sf) not initialized overflow flag (vf) not initialized interrupt master enable flag (imf) 0 interrupt individual enable flags (ef) 0 control registers refer to each of control register interrupt latches (il) 0 ram not initialized internal reset reset vdd malfunction reset output circuit watchdog timer reset address trap reset system clock reset
page 30 2. operational description 2.3 reset circuit TMP86FH12MG 2.3.2 address trap reset if the cpu should start looping for some cause such as noise and an attempt be made to fetch an instruction from the on-chip ram (when wdtcr1 is set to ?1 ?), dbr or the sfr area, ad dress trap reset will be generated. the reset time is maximum 24/fc[s] (1.5 s at 16.0 mhz). note:the operating mode under address tr apped is alternative of reset or interrupt. the address trap area is alter- native. note 1: address ?a? is in the sfr, dbr or on-chip ram (wdtcr1 = ?1?) space. note 2: during reset release, reset vector ?r? is read out, and an instruction at address ?r? is fetched and decoded. figure 2-16 addr ess trap reset 2.3.3 watchdog timer reset refer to section ?watchdog timer?. 2.3.4 system clock reset if the condition as follows is detected, the system clock reset occurs automatically to prevent dead lock of the cpu. (the oscillation is continued without stopping.) - in case of clearing syscr2 an d syscr2 simultaneously to ? 0 ? . - in case of clearing syscr2 to ? 0? , when the syscr2 is ? 0? . - in case of clearing syscr2 to ? 0? , when the syscr2 is ? 1? . the reset time is maximum 24/fc (1.5 s at 16.0 mhz). instruction at address r 16/fc [s] maximum 24/fc [s] instruction execution internal reset jp a reset release address trap is occurred 4/fc to 12/fc [s]
page 31 TMP86FH12MG
page 32 2. operational description 2.3 reset circuit TMP86FH12MG
page 33 TMP86FH12MG 3. interrupt control circuit the TMP86FH12MG has a total of 22 interrupt sources excl uding reset. interrupts can be nested with priorities. four of the internal interrupt sources ar e non-maskable while the rest are maskable. interrupt sources are provided with interrupt latches (il) , which hold interrupt requests, and independent vectors. the interrupt latch is set to ?1? by th e generation of its interrupt request wh ich requests the cpu to accept its inter- rupts. interrupts are enabled or disabled by software using the interrupt master enable fl ag (imf) and in terrupt enable flag (ef). if more than one interrupts are generated simultaneously, interrup ts are accepted in order which is domi- nated by hardware. however, there are no prioritized interrupt factors among non-maskable interrupts. note 1: to use the address trap interrupt (intatrap), clear wdtcr1 to ?0? (it is set for the ?reset request? after reset is cancelled). for details , see ?address trap?. note 2: to use the watchdog timer interrupt (intwdt), clear wdtcr1 to "0" (it is set for the "reset request" after reset is released). for details, see "watchdog timer". interrupt factors enable condition interrupt latch vector address priority internal/external (reset) non-maskable ? fffe 1 internal intswi (software interrupt) non-maskable ? fffc 2 internal intundef (executed the undefined instruction interrupt) non-maskable ? fffc 2 internal intatrap (address trap interrupt) non-maskable il2 fffa 2 internal intwdt (watchdog timer interrupt) non-maskable il3 fff8 2 internal intemg imf? ef4 = 1 il4 fff6 5 - reserved imf? ef5 = 1 il5 fff4 6 external int0 imf? ef6 = 1, int0en = 1 il6 fff2 7 internal inttc1 imf? ef7 = 1 il7 fff0 8 external int1 imf? ef8 = 1 il8 ffee 9 internal inttbt imf? ef9 = 1 il9 ffec 10 external int2 imf? ef10 = 1 il10 ffea 11 internal inttc7t imf? ef11 = 1 il11 ffe8 12 - reserved imf? ef12 = 1 il12 ffe6 13 internal inttc4 imf? ef13 = 1 il13 ffe4 14 internal inttc3 imf? ef14 = 1 il14 ffe2 15 - reserved imf? ef15 = 1 il15 ffe0 16 - reserved imf? ef16 = 1 il16 ffbe 17 external int3 imf? ef17 = 1 il17 ffbc 18 internal intsio imf? ef18 = 1 il18 ffba 19 internal intadc imf? ef19 = 1 il19 ffb8 20 internal intrxd imf? ef20 = 1 il20 ffb6 21 internal inttxd imf? ef21 = 1 il21 ffb4 22 external int4 imf? ef22 = 1 il22 ffb2 23 internal inttc7p imf? ef23 = 1 il23 ffb0 24 - reserved imf? ef24 = 1 il24 ffae 25 - reserved imf? ef25 = 1 il25 ffac 26 - reserved imf? ef26 = 1 il26 ffaa 27 internal intrtc imf? ef27 = 1 il27 ffa8 28 external int5 imf? ef28 = 1 il28 ffa6 29 - reserved imf? ef29 = 1 il29 ffa4 30 - reserved imf? ef30 = 1 il30 ffa2 31 - reserved imf? ef31 = 1 il31 ffa0 32
page 34 3. interrupt control circuit 3.1 interrupt latches (il28 to il2) TMP86FH12MG 3.1 interrupt latches (il28 to il2) an interrupt latch is provided for eac h interrupt source, except for a software interrupt and an executed the unde- fined instruction interrupt. when interrupt request is genera ted, the latch is set to ?1?, and the cpu is requested to accept the interrupt if its interrupt is enabled. the interrupt latch is cleared to "0" immediately after accepting inter- rupt. all interrupt latches are initialized to ?0? during reset. the interrupt latches are located on address 002eh, 002fh, 003ch and 003dh in sfr area. each latch can be cleared to "0" individually by instruction. however, il2 and il3 should not be cleared to "0" by software. for clear- ing the interrupt latch, load instruction should be used and then il2 and il3 should be set to "1". if the read-modify- write instructions such as bit manipulation or operation instructions are used, interrupt request would be cleared inadequately if interrupt is requeste d while such instructions are executed. interrupt latches are not set to ?1? by an instruction. since interrupt latches can be read, the status fo r interrupt requests can be monitored by software. note: in main program, before manipulating the interrupt enable flag (ef) or the interrupt latch (il), be sure to clear imf to "0" (disable interrupt by di instruction). then set imf new ly again as required after operating on the ef or il (enable interrupt by ei instruction) in interrupt service routine, because the imf becomes "0 " automatically, clearing imf need not execute normally on interrupt service routine. however, if using multiple inte rrupt on interrupt service routine, manipulating ef or il should be executed before setting imf="1". 3.2 interrupt enab le register (eir) the interrupt enable register (eir) enables and disables the acceptance of interrupts, except fo r the non-maskable interrupts (software interrupt, undefined instruction interr upt, address trap interrupt and watchdog interrupt). non- maskable interrupt is accepted regardless of the contents of the eir. the eir consists of an interrupt mast er enable flag (imf) and the individua l interrupt enable flags (ef). these registers are located on address 002ch, 002dh, 003ah and 003bh in sfr area, and they can be read and written by an instructions (including read-modify-write instruc tions such as bit manipulation or operation instructions). 3.2.1 interrupt ma ster enable flag (imf) the interrupt enable register (imf ) enables and disables the acceptance of the whole maskable interrupt. while imf = ?0?, all maskable interrupts are not accepted regardless of the status on each individual interrupt enable flag (ef). by setting imf to ?1?, the interrupt becomes acceptable if the individuals are enabled. when an interrupt is accepted, imf is cleared to ?0? after the latest status on imf is stacked. thus the maskable inter- rupts which follow are disabled. by executing return interrupt instruction [reti/retn], the stacked data, which was the status before interrup t acceptance, is loaded on imf again. the imf is located on bit0 in eirl (address: 003ah in sfr), and can be read and written by an instruction. the imf is normally set and cl eared by [ei] and [di] instruction respectively. during reset, the imf is initial- ized to ?0?. example 1 :clears interrupt latches di ; imf example 2 :reads interrupt latchess ld wa, (ill) ; w example 3 :tests interrupt latches test (ill). 7 ; if il7 = 1 then jump jr f, sset
page 35 TMP86FH12MG 3.2.2 individual interrupt enable flags (ef28 to ef4) each of these flags enables and disables the acceptan ce of its maskable interrupt . setting the corresponding bit of an individual interrupt enable flag to ?1? enables acceptan ce of its interrupt, and setting the bit to ?0? dis- ables acceptance. during reset, all the individual interrupt enable flags (ef28 to ef4) ar e initialized to ?0? and all maskable interrupts are not accepted until they are set to ?1?. note:in main program, before manipulating the interrupt enable flag (ef) or the interrupt latch (il), be sure to clear imf to "0" (disable interrupt by di instruction). then set imf newly again as required after operating on the ef or il (enable interrupt by ei instruction) in interrupt service routine, because the imf become s "0" automatically, clearing imf need not execute nor- mally on interrupt service routine. however, if using mult iple interrupt on interrupt service routine, manipulat- ing ef or il should be executed before setting imf="1". example 1 :enables interrupts individually and sets imf di ; imf example 2 :c compiler description example unsigned int _io (3ah) eirl; /* 3ah shows eirl address */ _di(); eirl = 10100000b; : _ei();
page 36 3. interrupt control circuit 3.2 interrupt enable register (eir) TMP86FH12MG note 1: to clear any one of bits il7 to il4, be sure to write "1" into il2 and il3. note 2: in main program, before manipulating the interrupt enable fl ag (ef) or the interrupt latch (il), be sure to clear imf to "0" (disable interrupt by di instruction). then set imf newly again as required after operating on the ef or il (enable interrupt by ei instruction) in interrupt service routine, because the imf becomes "0" automatically, clear ing imf need not execute normally on inter- rupt service routine. however, if using multiple interrupt on interrupt service routine, mani pulating ef or il should be exe- cuted before setting imf="1". note 3: do not clear il with read-modify-w rite instructions such as bit operations. note 1: *: don?t care note 2: do not set imf and the interrupt enable flag (ef15 to ef4) to ?1? at the same time. note 3: in main program, before manipulating the interrupt enable fl ag (ef) or the interrupt latch (il), be sure to clear imf to "0" (disable interrupt by di instruction). then set imf newly again as required after operating on the ef or il (enable interrupt by ei instruction) in interrupt service routine, because the imf becomes "0" automatically, clear ing imf need not execute normally on inter- rupt service routine. however, if using multiple interrupt on interrupt service routine, mani pulating ef or il should be exe- cuted before setting imf="1". interrupt latches (initial value: *00*0000 00*000**) ilh,ill (003dh, 003ch) 1514131211109876543210 ? ? ? ??? ??? ? ? ? ? ??? ??? ?
page 37 TMP86FH12MG 3.3 interrupt sequence an interrupt request, which raised interrupt latch, is held, until interrupt is accepted or interrupt latch is cleared to ?0? by resetting or an instruct ion. interrupt acceptance sequence requires 8 machine cycles (2 s @16 mhz) after the completion of the current instruction. the interrupt service task terminates upon execution of an interrupt return instruction [reti] (for maskable interrupts) or [retn] (for non-maskable interrupts). figure 3-1 shows the timing chart of interrupt acceptance processing. 3.3.1 interrupt acceptance proc essing is packaged as follows. a. the interrupt master enab le flag (imf) is cleared to ?0? in or der to disable the acceptance of any fol- lowing interrupt. b. the interrupt latch (il) for the interrupt source accepted is cleared to ?0?. c. the contents of the program coun ter (pc) and the program status word, including the interrupt master enable flag (imf), are saved (pushed) on the st ack in sequence of psw + imf, pch, pcl. mean- while, the stack pointer (s p) is decremented by 3. d. the entry address (interrupt vect or) of the corresponding interrupt service program, loaded on the vec- tor table, is transferred to the program counter. e. the instruction stored at the entry address of the inte rrupt service program is executed. note:when the contents of psw are saved on the stack, the contents of imf are also saved. note 1: a: return address entry address, b: entry address, c: address which reti instruction is stored note 2: on condition that interrupt is enabled, it takes 38/fc [s ] or 38/fs [s] at maximum (if the interrupt latch is set at the first machine cycle on 10 cycle instruction) to start interrupt acceptance processing since its interrupt latch is set. figure 3-1 timing chart of interrupt acceptance/return in terrupt instruction example: correspondence be tween vector table address for inttbt and the entry address of the interrupt service program figure 3-2 vector table address,entry address a b a c + 1 execute instruction sp pc execute instruction n n ? 2 n - 3 n ? 2n ? 1 n ? 1 n a + 2 a + 1 c + 2 b + 3 b + 2 b + 1 a + 1 a a ? 1 execute reti instruction interrupt acceptance execute instruction interrupt service task 1-machine cycle interrupt request interrupt latch (il) imf d2h 03h d203h d204h 06h vector table address entry address 0fh vector interrupt service program ffech ffedh
page 38 3. interrupt control circuit 3.3 interrupt sequence TMP86FH12MG a maskable interrupt is not accepted until the imf is set to ?1? even if th e maskable interrupt higher than the level of current servicing interrupt is requested. in order to utilize nested interrupt service, the imf is set to ?1? in the interrupt service program. in this case, acceptable interrupt sources are selectively en abled by the individual interrupt enable flags. to avoid overloaded nesting, clear the individual interrupt enable flag whose interrupt is currently serviced, before setting imf to ?1?. as for non-maskable interr upt, keep interrupt service shorten compared with length between interrupt requests; otherwise the status cannot be recovered as non-maskable interrupt would simply nested. 3.3.2 saving/restoring general-purpose registers during interrupt acceptance processing , the program counter (pc) and the program status word (psw, includes imf) are automati cally saved on the stack, but the accumulato r and others are not. these registers are saved by software if necessary. when multiple interrupt se rvices are nested, it is also necessary to avoid using the same data memory area for saving registers. the fo llowing methods are used to save/restore the general- purpose registers. 3.3.2.1 using push and pop instructions if only a specific register is saved or interrupts of the same source are nested , general-purpose registers can be saved/restored using the push/pop instructions. figure 3-3 save/store register using push and pop instructions 3.3.2.2 using data transfer instructions to save only a specific register wi thout nested interrupts, data tran sfer instructions are available. example :save/store register us ing push and pop instructions pintxx: push wa ; save wa register (interrupt processing) pop wa ; restore wa register reti ; return pcl pch psw at acceptance of an interrupt at execution of push instruction at execution of reti instruction at execution of pop instruction b-4 b-3 b-2 b-1 b pcl pch psw pcl pch psw sp address (example) sp sp sp a w b-5
page 39 TMP86FH12MG figure 3-4 saving/restoring general-purpose r egisters under interrupt processing 3.3.3 interrupt return interrupt return instructions [reti]/[retn] perform as follows. as for address trap interrupt (intatrap), it is requir ed to alter stacked data for program counter (pc) to restarting address, during interrupt service program. note:if [retn] is executed with the above data unaltered, the program returns to the address trap area and intatrap occurs again.when interrupt acceptance pr ocessing has completed, stacked data for pcl and pch are located on address (sp + 1) and (sp + 2) respectively. example :save/store register us ing data transfer instructions pintxx: ld (gsava), a ; save a register (interrupt processing) ld a, (gsava) ; restore a register reti ; return [reti]/[retn] interrupt return 1. program counter (pc) and program status word (psw, includes imf) are restored from the stack. 2. stack pointer (sp) is incremented by 3. example 1 :returning from address trap interrupt (intatrap) service program pintxx: pop wa ; recover sp by 2 ld wa, return address ; push wa ; alter stacked data (interrupt processing) retn ; return interrupt acceptance interrupt service task restoring registers saving registers interrupt return saving/restoring general-purpose registers using push/pop data transfer instruction main task
page 40 3. interrupt control circuit 3.4 software interrupt (intsw) TMP86FH12MG interrupt requests are sampled during the final cycle of the instruction being executed. thus, the next inter- rupt can be accepted immediately after the interrupt retu rn instruction is executed. note 1: it is recommended that stack pointer be return to rate before intatrap (increment 3 times), if return inter- rupt instruction [retn] is not utilized during inte rrupt service program under intatrap (such as example 2). note 2: when the interrupt processing time is longer than the interrupt request generation time, the interrupt service task is performed but not the main task. 3.4 software interrupt (intsw) executing the swi instruction generates a software interr upt and immediately starts interrupt processing (intsw is highest prioritized interrupt). use the swi instruction only for detection of the address error or for debugging. 3.4.1 address error detection ffh is read if for some cause such as noise the cpu attempts to fetch an instruction from a non-existent memory address during single chip mode. code ffh is th e swi instruction, so a software interrupt is gener- ated and an address error is detect ed. the address error detection range can be further expanded by writing ffh to unused areas of the program memory. address trap reset is generated in case that an instruction is fetched from ram, dbr or sfr areas. 3.4.2 debugging debugging efficiency can be increased by placing the swi instruction at the software break point setting address. 3.5 undefined instruct ion interrupt (intundef) taking code which is not defined as authorized instru ction for instruction causes intundef. intundef is gen- erated when the cpu fetches such a co de and tries to execute it. intundef is accepted even if non-maskable inter- rupt is in process. contemporary process is broken and intundef interrupt process starts, soon after it is requested. note: the undefined instruction interrupt (intundef) forces cpu to jump into vector address, as software interrupt (swi) does. 3.6 address trap interrupt (intatrap) fetching instruction from unauthorized area for instructio ns (address trapped area) cause s reset output or address trap interrupt (intatrap). intatrap is accepted even if non-maskable interrupt is in process. contemporary pro- cess is broken and intatrap interrupt pro cess starts, soon afte r it is requested. note: the operating mode under address trapped, whether to be reset output or interrupt processing, is selected on watchdog timer control register (wdtcr). example 2 :restarting without returning interrupt (in this case, psw (includes imf) befo re interrupt acceptance is discarded.) pintxx: inc sp ; recover sp by 3 inc sp ; inc sp ; (interrupt processing) ld eirl, data ; set imf to ?1? or clear it to ?0? jp restart address ; jump into restarting address
page 41 TMP86FH12MG 3.7 external interrupts the TMP86FH12MG has 6 external interrupt inputs. these in puts are equipped with di gital noise reject circuits (pulse inputs of less than a certa in time are elimin ated as noise). edge selection is also possible with int1 to int4. the int0 /p31 pin can be configured as either an external inter- rupt input pin or an input/output port, and is configured as an input port during reset. edge selection, noise reject control and int0 /p31 pin function selection are performed by the external interrupt control register (eintcr). note 1: in normal1/2 or idle1/2 mode, if a signal with no noise is input on an external interrupt pin, it takes a maximum of "si g- nal establishment time + 6/fs[s]" from the input signal's edge to set the interrupt latch. note 2: when int0en = "0", il6 is not set even if a falling edge is detected on the int0 pin input. note 3: when a pin with more than one function is used as an out put and a change occurs in data or input/output status, an inter - rupt request signal is generated in a pseudo manner. in this ca se, it is necessary to perform appropriate processing such as disabling the interrupt enable flag. source pin enable conditions release edge (level) digital noise reject int0 int0 imf ? ef6 ? int0en=1 falling edge pulses of less than 2/fc [s] are eliminated as noise. pulses of 7/fc [s ] or more are considered to be signals. in the slow or the sleep mode, pulses of less than 1/fs [s] are eliminated as noise. pulses of 3.5/fs [s] or more are consid- ered to be signals. int1 int1 imf ? ef8 = 1 falling edge or rising edge pulses of less than 15/fc or 63/fc [s] are elimi- nated as noise. pulses of 49/fc or 193/fc [s] or more are considered to be signals. in the slow or the sleep mode, pulses of less than 1/fs [s] are eliminated as noise. pulses of 3.5/fs [s] or more are considered to be signals. int2 int2 imf ? ef10 = 1 falling edge or rising edge pulses of less than 7/fc [s] are eliminated as noise. pulses of 25/fc [s] or more are considered to be signals. in the slow or the sleep mode, pulses of less than 1/fs [s] are eliminated as noise. pulses of 3.5/fs [s] or more are consid- ered to be signals. int3 int3 imf ? ef17 = 1 falling edge or rising edge pulses of less than 7/fc [s] are eliminated as noise. pulses of 25/fc [s] or more are considered to be signals. in the slow or the sleep mode, pulses of less than 1/fs [s] are eliminated as noise. pulses of 3.5/fs [s] or more are consid- ered to be signals. int4 int4 imf ? ef22 = 1 falling edge, rising edge, falling and rising edge or h level pulses of less than 7/fc [s] are eliminated as noise. pulses of 25/fc [s] or more are considered to be signals. in the slow or the sleep mode, pulses of less than 1/fs [s] are eliminated as noise. pulses of 3.5/fs [s] or more are consid- ered to be signals. int5 int5 imf ? ef28 = 1 falling edge pulses of less than 2/fc [s] are eliminated as noise. pulses of 7/fc [s ] or more are considered to be signals. in the slow or the sleep mode, pulses of less than 1/fs [s] are eliminated as noise. pulses of 3.5/fs [s] or more are consid- ered to be signals.
page 42 3. interrupt control circuit 3.7 external interrupts TMP86FH12MG note 1: fc: high-frequency clock [hz], *: don?t care note 2: when the system clock frequency is switched between high and low or when the external interrupt control register (eintcr) is overwritten, the noise canceller may not operat e normally. it is recommended that external interrupts are dis- abled using the interrupt enable register (eir). note 3: the maximum time from modifying int1 nc until a noise reject time is changed is 2 6 /fc. note 4: in case reset pin is released while the state of int4 pin keeps "h" level, the external interrupt 4 request is not generated even if the int4 edge select is specified as "h" level. the rising edge is needed after reset pin is released. external interrupt control register eintcr76543210 (0037h) int1nc int0en int4es int3es int2es int1es (initial value: 0000 000*) int1nc noise reject time select 0: pulses of less than 63/fc [s] are eliminated as noise 1: pulses of less than 15/fc [s] are eliminated as noise r/w int0en p31/ int0 pin configuration 0: p31 input/output port 1: int0 pin (port p31 should be set to an input mode) r/w int4 es int4 edge select 00: rising edge 01: falling edge 10: rising edge and falling edge 11: h level r/w int3 es int3 edge select 0: rising edge 1: falling edge r/w int2 es int2 edge select 0: rising edge 1: falling edge r/w int1 es int1 edge select 0: rising edge 1: falling edge r/w
page 43 TMP86FH12MG 4. special function register (sfr) the TMP86FH12MG adopts the memory mapp ed i/o system, and all peripheral control and data transfers are per- formed through the special function register (sfr) or the data buffer register (dbr). the sfr is mapped on address 0000h to 003fh, dbr is mapped on address 0f80h to 0fffh. this chapter shows the arrangement of the special functi on register (sfr) and data buffer register (dbr) for TMP86FH12MG. 4.1 sfr address read write 0000h p0dr 0001h p1dr 0002h p2dr 0003h p3dr 0004h p0outcr 0005h p1cr 0006h p3cr1 0007h p3cr2 0008h tc7dral 0009h tc7drah 000ah tc7drbl 000bh tc7drbh 000ch tc7drcl 000dh tc7drch 000eh p0prd - 000fh p2prd - 0010h tc1dral 0011h tc1drah 0012h tc1drbl 0013h tc1drbh 0014h tc1cr 0015h tc3cr 0016h tc4cr 0017h pwreg3 0018h pwreg4 0019h ttreg3 001ah ttreg4 001bh rtccr 001ch reserved 001dh reserved 001eh reserved 001fh adcdr2 - 0020h adcdr1 - 0021h uartsr uartcr1 0022h - uartcr2 0023h reserved 0024h reserved 0025h adccr1
page 44 4. special function register (sfr) 4.1 sfr TMP86FH12MG note 1: do not access reserved areas by the program. note 2: ?
page 45 TMP86FH12MG 4.2 dbr address read write 0f80h siobr0 0f81h siobr1 0f82h siobr2 0f83h siobr3 0f84h siobr4 0f85h siobr5 0f86h siobr6 0f87h siobr7 0f88h - stopcr 0f89h rdbuf tdbuf 0f8ah reserved 0f8bh reserved 0f8ch reserved 0f8dh reserved 0f8eh reserved 0f8fh reserved 0f90h reserved 0f91h reserved 0f92h reserved 0f93h reserved 0f94h reserved 0f95h reserved 0f96h reserved 0f97h reserved 0f98h reserved 0f99h reserved 0f9ah reserved 0f9bh reserved 0f9ch reserved 0f9dh reserved 0f9eh reserved 0f9fh reserved
page 46 4. special function register (sfr) 4.2 dbr TMP86FH12MG address read write 0fa0h reserved 0fa1h reserved 0fa2h reserved 0fa3h reserved 0fa4h reserved 0fa5h reserved 0fa6h reserved 0fa7h reserved 0fa8h reserved 0fa9h reserved 0faah reserved 0fabh reserved 0fach reserved 0fadh reserved 0faeh reserved 0fafh reserved 0fb0h tc7drdl 0fb1h tc7drdh 0fb2h tc7drel 0fb3h tc7dreh 0fb4h tc7capal - 0fb5h tc7capah - 0fb6h tc7capbl - 0fb7h tc7capbh - 0fb8h reserved 0fb9h reserved 0fbah reserved 0fbbh reserved 0fbch reserved 0fbdh reserved 0fbeh reserved 0fbfh reserved address read write 0fc0h reserved : : : : 0fdfh reserved
page 47 TMP86FH12MG note 1: do not access reserved areas by the program. note 2: ?
page 48 4. special function register (sfr) 4.2 dbr TMP86FH12MG
page 49 TMP86FH12MG 5. i/o ports the TMP86FH12MG has 4 parallel input/output ports (24 pins) as follows. each output port contains a latch, which holds the output data. all input ports do not have latches, so the external input data should be externally held until the input data is read from outside or reading should be performed several timer before processing. figure 5-1 shows input/output timing examples. external data is read from an i/o port in the s1 state of the read cycle during execution of the read instruction. this timing cannot be recognized from outside, so that transient input such as chattering must be processed by the pro- gram. output data changes in the s2 state of the write cycle du ring execution of the instruct ion which writes to an i/o port. note: the positions of the read and write c ycles may vary, depending on the instruction. figure 5-1 input/output timing (example) primary function secondary functions port p0 8-bit i/o port external interrupt, serial interface input/output, uart input/output and timer counter input/output. port p1 5-bit i/o port external interrupt and timer counter input/output. port p2 3-bit i/o port low-frequency resonator connections, external interrupt input, stop mode release signal input. port p3 8-bit i/o port external interrupt, anal og input and stop mode release signal input. data output data input new old example: ld a, (x) fetch cycle read cycle fetch cycle s0 s1 s2 s3 s0 s1 s2 s3 s0 s1 s2 s3 instruction execution cycle input strobe (a) input timing example: ld (x), a fetch cycle write cycle fetch cycle s0 s1 s2 s3 s0 s1 s2 s3 s0 s1 s2 s3 (b) output timing instruction execution cycle output strobe
page 50 5. i/o ports 5.1 port p0 (p07 to p00) TMP86FH12MG 5.1 port p0 (p07 to p00) port p0 is an 8-bit input/output port. port p0 is also used as an external interrupt input, a serial interface input/output, an uart input/output and a timer/counter input/output. it can be selected whether output circuit of p0 port is a c-mos output or a sink open drain individually, by setting p0outcr. during reset, the p0dr is initialized to "1", and the p0outcr is initialized to "0". when a correspond- ing bit of p0outcr is "0". the output circuit is selected to a sink open drain and when a corresponding bit of p0outcr is "1", the output circuit is selected to a c-mos output. when used as an input port, an exte rnal interrupt input, a serial interface input ,a n uart input and a timer/counter input , the corresponding output control (p0outcr) should be set to "0" after p0dr is set to "1". when using this port as a ppg1 and/or ppg2 output, set the output latch (p0dr), and then set the p0outcr. next, set the ppg output initial value in the ppg1ini and/ or ppg2ini, and set the ppg1oe and/or ppg2oe to "1" to enable ppg output. at this time, the output latch (p0dr) should be set to the same value as the ppg output initial value in the ppg1ini, ppg2ini. during reset, the p0dr is initialized to "1", and the p0outcr is initialized to "0". p0 port output latch (p0dr) and p0 port terminal input (p0prd) are located on their respective address. when read the output latch data, the p0dr should be read . when read the terminal input data, the p0prd register should be read. table 5-1 register programming for multi-function ports (p07 to p00) function programmed value p0dr p0outcr port input, external interrupt input, serial interface input, timer counter input or uart input ?1? ?0? port ?0? output ?0? programming for each applications port ?1? output, serial interface output or uart output ?1? timer counter 7 output set to the same value as ppg1ini and ppg2ini
page 51 TMP86FH12MG note: i = 5 to 0, j = 7 and 6, k = 2 and 1 figure 5-2 port 0 &cvcqwvrwv (p0dr) %qpvtqnqwvrwv stop outen p0outcri dq p0i p0outcri kprwv &cvckprwv (p0prd) 17vrwvncvejtgcf (p0dr) %qpvtqnkprwv dq 1wvrwvncvej data output (p0dr) 22)m stop outen p0outcrj dq p0j p0outcrj i &cvckprwv (p0prd) 1wvrwvncvejtgcf (p0dr) %qpvtqnkprwv dq a b s 22)m+0+ 22)m1' 1wvrwvncvej
page 52 5. i/o ports 5.1 port p0 (p07 to p00) TMP86FH12MG p0dr (0000h) r/w 76543210 p07 ppg2 int2 p06 ppg1 int1 p05 tc7 p04 so p03 si p02 sck p01 rxd p00 txd (initial value: 1111 1111) p0outcr (0004h) (initial value: 0000 0000) p0outcr port p0 output circuit control (set for each bit individually) 0: sink open-drain output 1: c-mos output r/w p0prd (0008h) read only p07 p06 p05 p04 p03 p02 p01 p00
page 53 TMP86FH12MG 5.2 port p1 (p17 to p10) port p1 is an 5-bit input/output port which can be configured as an input or output in one-bit unit. port p1 is also used as a timer/counter input/output, an external interrupt input and a divider output. input/output mode is specified by the p1 control register (p1cr). during reset, the p1cr is initialized to "0" and port p1 becomes an input mode. and the p1dr is initialized to "0". when used as an input port, a timer/counter input and an external interrupt input, the corresponding bit of p1cr should be set to "0". when used as an output port, the corresponding bit of p1cr should be set to "1". when used as a timer/counter output and a divider output, p1dr is set to "1" beforehand and the corresponding bit of p1cr should be set to "1". when p1cr is "1", the content of the corresponding output latch is read by reading p1dr. if a read instruction is executed for the p1dr and p1cr, read data of bits 7 to 5 are unstable. note: asterisk (*) indicates ?1? or ?0? either of which can be selected. note: i = 7 to 0 figure 5-3 port 1 note: the port set to an input mode reads the terminal input data. therefore, when the input and output modes are used together, the content of the output latch which is specified as input mode might be changed by executing a bit manipulation instruction. table 5-2 register programming for multi-function ports function programmed value p1dr p1cr port input, timer/counter input or external interrupt input * ?0? port ?0? output ?0? ?1? port ?1? output, a timer output or a divider output ?1? ?1? p1i dq dq stop outen p1cri p1cri input data input (p1dr) data output (p1dr) control output control input output latch
page 54 5. i/o ports 5.2 port p1 (p17 to p10) TMP86FH12MG p1dr (0001h) r/w 76543210 p14 tc1 int4 p13 ppg int3 p12 dvo p11 tc4 pwm4 pdo4 ppg4 p10 tc3 pwm3 pdo3 (initial value: ***0 0000) p1cr (0005h) 76543210 (initial value: ***0 0000) p1cr i/o control for port p1 (specified for each bit) 0: input mode 1: output mode r/w
page 55 TMP86FH12MG 5.3 port p2 (p22 to p20) port p2 is a 3-bit input/output port. it is also used as an external interr upt, a stop mode release signal input, and low-frequency crys tal oscillator con- nection pins. when used as an input port or a secondary function pins, respective output latch (p2dr) should be set to ?1?. during reset, the p2dr is initialized to ?1?. a low-frequency crystal osci llator (32.768 khz) is connected to pins p21 (xtin) and p22 (xtout) in the dual- clock mode. in the single-clock mode, pins p21 and p22 can be used as normal input/output ports. it is recommended that pin p20 should be used as an exte rnal interrupt input, a stop mode release signal input, or an input port. if it is used as an output port, the in terrupt latch is set on the falling edge of the output pulse. p2 port output latch (p2dr) and p2 port terminal i nput (p2prd) are located on their respective address. when read the output latch data, the p2dr should be r ead and when read the termin al input data, the p2prd reg- ister should be read. if a read instruction is execute d for port p2, read data of bits 7 to 3 are unstable. figure 5-4 port 2 note: port p20 is used as stop pin. therefore, when stop mode is started, outen does not affect to p20, and p20 becomes high-z mode. p2dr (0002h) r/w 76543210 p22 xtout p21 xtin p20 int5 stop (initial value: **** *111) p2prd (0009h) read only p22 p21 p20 output latch osc. enable output latch dq p20 (int5, stop) dq output latch dq p21 (xtin) p22 (xtout) data input (p20prd) data input (p20) data output (p20) contorl input data input (p21prd) output latch read (p21) data output (p21) data input (p22prd) output latch read (p22) data output (p22) stop outen xten fs
page 56 5. i/o ports 5.4 port p3 (p37 to 30) TMP86FH12MG 5.4 port p3 (p37 to 30) port p3 is an 8-bit input/output port which can be configured as an input or output in one-bit unit. port p3 is also used as an analog input, key-on wakeup input, an external interrupt and tc7 emergency stop input. input/output mode is specified by the p3 control register (p3cr1) and p3 input control register (p3cr2). during reset, the p3cr1 is initialized to "0" the p3cr2 is initialized to "1" and port p3 becomes an input mode. and the p3dr is initialized to "0". when used as an output port, the corresponding bit of p3cr1 should be set to "1". when used as an input port, key-on wakeup input, an external interrupt input and tc7 emergency stop input, the corresponding bit of p3cr1 should be set to "0" and then, the corresponding bit of p3cr2 should be set to "1". when used as an analog input, the corresponding bit of p3cr1 should be set to "0" and then, the corresponding bit of p6cr2 should be set to "0". when p3cr1 is "1", the content of the corres ponding output latch is read by reading p3dr. note: asterisk (*) indicates ?1? or ?0? either of which can be selected. table 5-3 register programming for multi-function ports function programmed value p3dr p3cr1 p3cr2 port input or key-on wakeup input or external input or tc7 emergency stop input *?0??1? analog input * ?0? ?0? port ?0? output ?0? ?1? * port ?1? output ?1? ?1? * table 5-4 values read from p3dr and register programming conditions values read from p3dr p3cr1 p3cr2 ?0? ?0? ?0? ?0? ?1? terminal input data ?1? ?0? output latch contents ?1?
page 57 TMP86FH12MG note: i = 7 to 0 figure 5-5 port 3 p3i dq dq p3cr2i p3cr2i kprwv p3cr1i p3cr1i kprwv &cvckprwv (p3dri) &cvcqwvrwv (p3dri) stop outten #pcnqikprwv ainds sain dq %qpvtqnqwvrwv p3j dq dq p3cr2j p3cr2j kprwv p3cr1j p3cr1j kprwv &cvcqwvrwv (p3drj) stop outten #pcnqikprwv ainds stopken -g[qpycmgwr dq &cvckprwv (p3drj) a) p37,p32 to p30 sain b) p36 to p33
page 58 5. i/o ports 5.4 port p3 (p37 to 30) TMP86FH12MG note 1: the port placed in input mode reads the pin input stat e. therefore, when the input and output modes are used together, the output latch contents for the port in input mode might be changed by executing a bit manipulation instruction. note 2: when used as an analog inport, be sure to clear the corresponding bit of p3cr2 to disable the port input. note 3: do not set the output mode (p3cr1 = ?1?) for the pin used as an analog input pin. note 4: pins not used for analog input can be used as i/o ports. during ad conversion, output instructions should not be execute d to keep a precision. in addition, a variabl e signal should not be input to a port ad jacent to the analog input during ad con- version. p3dr (0003h) r/w 76543210 p37 ain7 p36 ain6 stop3 p35 ain5 stop2 p34 ain4 stop1 p33 ain3 stop0 p32 ain2 p31 ain1 int0 p30 ain0 emg (initial value: 0000 0000) p3cr1 (0006h) 76543210 (initial value: 0000 0000) p3cr1 i/o control for port p3 (specified for each bit) 0: input mode 1: output mode r/w p3cr2 (0007h) 76543210 (initial value: 1111 1111) p3cr2 p3 port input control (specified for each bit) 0: analog input 1: port input or key-on wakeup input or external interrupt input or tc7 emergency stop input r/w
page 59 TMP86FH12MG 6. watchdog timer (wdt) the watchdog timer is a fail-safe system to detect rapidly the cpu malfunctions such as endless loops due to spu- rious noises or the deadlock conditions, and return the cpu to a sy stem recovery routine. the watchdog timer signal for detecting malfunctions can be programmed only once as ?reset request? or ?inter- rupt request?. upon the reset release, this signal is initialized to ?reset request?. when the watchdog timer is not used to detect malfunctions, it can be used as the timer to provide a periodic inter- rupt. note: care must be taken in system des ign since the watchdog timer functions are not be operated completely due to effect of disturbing noise. 6.1 watchdog timer configuration figure 6-1 watchdog timer configuration 0034 h overflow wdt output internal reset binary counters wdtout writing clear code writing disable code wdten wdtt 2 0035 h watchdog timer control registers wdtcr1 wdtcr2 intwdt interrupt request interrupt request reset request reset release clock clear 1 2 controller q sr s r q selector fc/2 23 or fs/2 15 fc/2 21 or fs/2 13 fc/2 19 or fs/2 11 fc/2 17 or fs/2 9
page 60 6. watchdog timer (wdt) 6.2 watchdog timer control TMP86FH12MG 6.2 watchdog timer control the watchdog timer is controlled by the watchdog timer control registers (wdtcr1 and wdtcr2). the watch- dog timer is automatically enabled after the reset release. 6.2.1 malfunction detection me thods using the watchdog timer the cpu malfunction is detected, as shown below. 1. set the detection time, select the output, and clear the binary counter. 2. clear the binary counter repeatedly within the specified detection time. if the cpu malfunctions such as en dless loops or the deadlock condition s occur for some reason, the watch- dog timer output is activated by the binary-counter overflow unless the binary counters are cleared. when wdtcr1 is set to ?1? at this time, the reset request is generated and then internal hardware is initialized. when wdtcr1 is set to ?0?, a watchdog timer interrupt (intwdt) is generated. the watchdog timer temporarily stops counting in th e stop mode including the warm-up or idle/sleep mode, and automatically restarts (continues counting) when the stop/idle/sleep mode is inactivated. note:the watchdog timer consists of an internal divider and a two-stage binary counter. when the clear code 4eh is written, only the binary counter is cleared, but not the internal divider . the minimum binary-counter overflow time, that depends on the timing at which the clear code (4eh) is written to the wdtcr2 register, may be 3/ 4 of the time set in wdtcr1. therefore, writ e the clear code using a cycle shorter than 3/4 of the time set to wdtcr1. example :setting the watchdog timer detection time to 2 21 /fc [s], and resetting the cpu malfunction detection ld (wdtcr2), 4eh : clears the binary counters. ld (wdtcr1), 00001101b : wdtt
page 61 TMP86FH12MG note 1: after clearing wdtout to ?0?, the program cannot set it to ?1?. note 2: fc: high-frequency clock [hz], fs : low-frequency clock [hz], *: don?t care note 3: wdtcr1 is a write-only register and must not be used with any of read-modify-write instructions. if wdtcr1 is read, a don?t care is read. note 4: to activate the stop mode, disable the watchdog timer or clear the counter immediately before entering the stop mode. after clearing the counter, clear the counter again immediately after the stop mode is inactivated. note 5: to clear wdten, set the register in accordance wi th the procedures shown in ?1.2.3 watchdog timer disable?. note 1: the disable code is valid only when wdtcr1 = 0. note 2: *: don?t care note 3: the binary counter of the watchdog timer must not be cleared by the interrupt task. note 4: write the clear code 4eh using a cycle shor ter than 3/4 of the time set in wdtcr1. 6.2.2 watchdog timer enable setting wdtcr1 to ?1? enables the watc hdog timer. since wdtcr1 is initialized to ?1? during reset, the watchdog timer is enabled automatically after the reset release. watchdog timer control register 1 wdtcr1 (0034h) 76543210 (atas) (atout) wdten wdtt wdtout (initial value: **11 1001) wdten watchdog timer enable/disable 0: disable (writing the disable code to wdtcr2 is required.) 1: enable write only wdtt watchdog timer detection time [s] normal1/2 mode slow1/2 mode write only dv7ck = 0 dv7ck = 1 00 2 25 /fc 2 17 /fs 2 17 /fs 01 2 23 /fc 2 15 /fs 2 15 fs 10 2 21 fc 2 13 /fs 2 13 fs 11 2 19 /fc 2 11 /fs 2 11 /fs wdtout watchdog timer output select 0: interrupt request 1: reset request write only watchdog timer control register 2 wdtcr2 (0035h) 76543210 (initial value: **** ****) wdtcr2 write watchdog timer control code 4eh: clear the watchdog timer binary counter (clear code) b1h: disable the watchdog timer (disable code) d2h: enable assigning address trap area others: invalid write only
page 62 6. watchdog timer (wdt) 6.2 watchdog timer control TMP86FH12MG 6.2.3 watchdog timer disable to disable the watchdog timer, set the register in accordance with the fo llowing procedures . setting the reg- ister in other procedures causes a malfunction of the microcontroller. 1. set the interrupt master flag (imf) to ?0?. 2. set wdtcr2 to the clear code (4eh). 3. set wdtcr1 to ?0?. 4. set wdtcr2 to the disable code (b1h). note:while the watchdog timer is disabled, the binary counters of the watchdog timer are cleared. 6.2.4 watchdog time r interrupt (intwdt) when wdtcr1 is cleared to ?0?, a watchdog timer interrupt request (intwdt) is generated by the binary-counter overflow. a watchdog timer interrupt is the non-maskable interr upt which can be accepted regardless of the interrupt master flag (imf). when a watchdog timer interrupt is generated while the other interrupt including a watchdog timer interrupt is already accepted, the new watchdog timer interrupt is processed immediately and the previous interrupt is held pending. therefore, if watchdog timer interrupts are generated continuously without execution of the retn instruction, too many levels of nesting may cause a malfunction of the microcontroller. to generate a watchdog timer interrupt, set the stack pointer before setting wdtcr1. example :disabling the watchdog timer di : imf example :setting watchdog timer interrupt ld sp, 023fh : sets the stack pointer ld (wdtcr1), 00001000b : wdtout
page 63 TMP86FH12MG 6.2.5 watchdog timer reset when a binary-counter overflow occurs while wdt cr1 is set to ?1?, a watchdog timer reset request is generated. when a watchdog timer reset request is generated, the internal hardware is reset. the reset time is maximum 24/fc [s] (1.5 s @ fc = 16.0 mhz). note:when a watchdog timer reset is generated in the sl ow1 mode, the reset time is maximum 24/fc (high-fre- quency clock) since the high-frequency cl ock oscillator is restarted. however, when crystals have inaccura- cies upon start of the high-frequency clock oscillator, the reset time should be considered as an approximate value because it has slight errors. figure 6-2 watchdog timer interrupt clock binary counter overflow intwdt interrupt request (wdtcr1= "0") 2 17 /fc 2 19 /fc [s] (wdtt=11) write 4e h to wdtcr2 1 2 30 1 2 3 0 internal reset (wdtcr1= "1") a reset occurs
page 64 6. watchdog timer (wdt) 6.3 address trap TMP86FH12MG 6.3 address trap the watchdog timer control register 1 and 2 share the a ddresses with the control regi sters to generate address traps. 6.3.1 selection of address tr ap in internal ram (atas) wdtcr1 specifies whether or not to generate address traps in the inte rnal ram area. to execute an instruction in the internal ram area, clear wdtcr1 to ?0?. to enable the wdtcr1 set- ting, set wdtcr1 and then write d2h to wdtcr2. executing an instruction in the sfr or dbr area generates an address trap unconditionally regardless of the setting in wdtcr1. 6.3.2 selection of operati on at address trap (atout) when an address trap is generated, either the inte rrupt request or the reset request can be selected by wdtcr1. 6.3.3 address trap interrupt (intatrap) while wdtcr1 is ?0?, if the cpu should start looping for some cause such as noise and an attempt be made to fetch an instruction from the on-chip ram (while wdtcr1 is ?1?), dbr or the sfr area, address trap interrupt (intatrap) will be generated. an address trap interrupt is a non-maskable interrupt which can be accepted regardless of the interrupt mas- ter flag (imf). when an address trap interrupt is generated while th e other interrupt including a watchdog timer interrupt is already accepted, the new address trap is processed immediately and the previous interrupt is held pending. therefore, if address trap interrupts are generated continuously without execution of the retn instruction, too many levels of nesting may cause a malfunction of the microcontroller. to generate address trap interrupts, set the stack pointer beforehand. watchdog timer control register 1 wdtcr1 (0034h) 7654 3 21 0 atas atout (wdten) (wdtt) (wdtout) (initial value: **11 1001) atas select address trap generation in the internal ram area 0: generate no address trap 1: generate address traps (after setting atas to ?1?, writing the control code d2h to wdtcr2 is reguired) write only atout select opertion at address trap 0: interrupt request 1: reset request watchdog timer control register 2 wdtcr2 (0035h) 76543210 (initial value: **** ****) wdtcr2 write watchdog timer control code and address trap area control code d2h: enable address trap area selection (atrap control code) 4eh: clear the watchdog timer binary counter (wdt clear code) b1h: disable the watchdog timer (wdt disable code) others: invalid write only
page 65 TMP86FH12MG 6.3.4 address trap reset while wdtcr1 is ?1?, if the cpu should start looping for some cause such as noise and an attempt be made to fetch an instruction from the on-chip ram (while wdtcr1 is ?1?), dbr or the sfr area, address trap reset will be generated. when an address trap reset request is generated, the in ternal hardware is reset. the reset time is maximum 24/fc [s] (1.5 s @ fc = 16.0 mhz). note:when an address trap reset is generated in the slow1 mode, the reset time is maximum 24/fc (high-fre- quency clock) since the high-frequency cl ock oscillator is restarted. however, when crystals have inaccura- cies upon start of the high-frequency clock oscillator, the reset time should be considered as an approximate value because it has slight errors.
page 66 6. watchdog timer (wdt) 6.3 address trap TMP86FH12MG
page 67 TMP86FH12MG 7. time base timer (tbt) the time base timer generates time base for key scanning, dynamic displaying, etc. it also provides a time base timer interrupt (inttbt). 7.1 time base timer 7.1.1 configuration figure 7-1 time base timer configuration 7.1.2 control time base timer is controled by time base timer control register (tbtcr). note 1: fc; high-frequency clock [hz], fs ; low-frequency clock [hz], *; don't care time base timer control register 7 6543210 tbtcr (0036h) (dvoen) (dvock) (dv7ck) tbten tbtck (initial value: 0000 0000) tbten time base timer enable / disable 0: disable 1: enable tbtck time base timer interrupt frequency select : [hz] normal1/2, idle1/2 mode slow1/2 sleep1/2 mode r/w dv7ck = 0 dv7ck = 1 000 fc/2 23 fs/2 15 fs/2 15 001 fc/2 21 fs/2 13 fs/2 13 010 fc/2 16 fs/2 8 ? 011 fc/2 14 fs/2 6 ? 100 fc/2 13 fs/2 5 ? 101 fc/2 12 fs/2 4 ? 110 fc/2 11 fs/2 3 ? 111 fc/2 9 fs/2 ? fc/2 23 or fs/2 15 fc/2 21 or fs/2 13 fc/2 16 or fs/2 8 fc/2 14 or fs/2 6 fc/2 13 or fs/2 5 fc/2 12 or fs/2 4 fc/2 11 or fs/2 3 fc/2 9 or fs/2 tbtcr tbten tbtck 3 mpx source clock falling edge detector time base timer control register inttbt interrupt request idle0, sleep0 release request
page 68 7. time base timer (tbt) 7.1 time base timer TMP86FH12MG note 2: the interrupt frequency (tbtck) must be selected with t he time base timer disabled (tbten="0"). (the interrupt fre- quency must not be changed with the disable from the enable state.) both frequency selection and enabling can be per- formed simultaneously. 7.1.3 function an inttbt ( time base timer interrupt ) is generated on the first falling edge of source clock ( the divider output of the timing generato which is selected by tbtck. ) after time base timer has been enabled. the divider is not cleared by the progra m; therefore, only the first interrupt may be generated ahead of the set interrupt period ( figure 7-2 ). figure 7-2 time base timer interrupt example :set the time base timer frequency to fc/2 16 [hz] and enable an inttbt interrupt. ld (tbtcr) , 00000010b ; tbtck source clock enable tbt interrupt period tbtcr inttbt
page 69 TMP86FH12MG 7.2 divider output ( dvo ) approximately 50% duty pulse can be output using the divider output circuit, which is useful for piezoelectric buzzer drive. divider output is from dvo pin. 7.2.1 configuration figure 7-3 divider output 7.2.2 control the divider output is controlled by the time base timer control register. note: selection of divider output frequency (dvock) must be made whil e divider output is disabled (dvoen="0"). also, in other words, when changing the state of the divider output frequen cy from enabled (dvoen="1") to disable(dvoen="0"), do not change the setting of the divider output frequency. time base timer control register 7654 321 0 tbtcr (0036h) dvoen dvock (dv7ck) (tbten) (tbtck) (initial value: 0000 0000) dvoen divider output enable / disable 0: disable 1: enable r/w dvock divider output ( dvo ) frequency selection: [hz] normal1/2, idle1/2 mode slow1/2 sleep1/2 mode r/w dv7ck = 0 dv7ck = 1 00 fc/2 13 fs/2 5 fs/2 5 01 fc/2 12 fs/2 4 fs/2 4 10 fc/2 11 fs/2 3 fs/2 3 11 fc/2 10 fs/2 2 fs/2 2 tbtcr output latch port output latch mpx dvoen tbtcr dvo pin output dvock divider output control register (a) configuration (b) timing chart data output 2 a b c y d s d q dvo pin fc/2 13 or fs/2 5 fc/2 12 or fs/2 4 fc/2 11 or fs/2 3 fc/2 10 or fs/2 2
page 70 7. time base timer (tbt) 7.2 divider output (dvo) TMP86FH12MG example :1.95 khz pulse output (fc = 16.0 mhz) ld (tbtcr) , 00000000b ; dvock
page 71 TMP86FH12MG 8. real-time clock the TMP86FH12MG include a real time co unter (rtc). a low-frequency clock can be used to provide a periodic interrupt (0.0625[s],0.125[s],0 .25[s],0.50[s]) at a programm ed interval, implement the clock function. the rtc can be used in the mode in which the low-frequency oscillator is active (except for the sleep0 mode). 8.1 configuration figure 8-1 confi guration of the rtc 8.2 control of the rtc the rtc is controlled by the rtc control register (rtccr). note 1: program the rtccr during low-frequency oscillation (when syscr2 = ?1?). for selecting an interrupt genera- tion period, program the rtcsel when the timer is inacti ve (rtcrun = ?0?). during the timer operation, do not change the rtcsel programming at the same moment the timer stops. note 2: the timer automatically stops, and this register is initialized (the timer's binary counter is also initialized) if one of the fol- lowing operations is performed while the timer is active: 1. stopping the low-frequency oscillation (with syscr2 = ?0?) 2. when the TMP86FH12MG are put in stop or sleep0 mode therefore, before activating the timer after releasing fr om stop or sleep0 mode, r eprogram the registers again. note 3: if a read instruction for rtccr is exec uted, undefined value is set to bits 7 to 3. note 4: if break processing is performed on the debugger for the development tool during the time r operation, the timer stops counting (contents of the rtccr isn't altered). when the break is cancelled, processing is restarted from the point at which it was suspended. rtc control register rtccr (001bh) 7654321 0 rtcsel rtcrun (initial value: **** *000) rtcsel interrupt generation period (fs = 32.768 khz) 00: 0.50 [s] 01: 0.25 [s] 10: 0.125 [s] 11: 0.0625 [s] r/w rtcrun rtc control 0: stops and clears the binary counter. 1: starts counting selector rtccr rtcsel interrupt request intrtc binary counter rtcrun 2 14 /fs 2 13 /fs 2 12 /fs 2 11 /fs fs (32.768 khz)
page 72 8. real-time clock 8.3 function TMP86FH12MG 8.3 function the rtc counts up on the internal low-frequency clock. when rtccr is set to ?1?, the binary counter starts counting up. each time the end of the period specified with rtccr is detected, an intrtc interrupt is generated, and the binary counter is cleared. the timer continue s counting up even after the binary counter is cleared.
page 73 TMP86FH12MG 9. 10-bit timer/counter (tc7) 9.1 configuration figure 9-1 10-bi t timer/counter 7 9.2 control timer/counter 7 is controlled by timer/counter control register 1 (tc7cr1), timer/counter control register 2 (tc7cr2), timer/counter control register 3 (tc7cr3), 10-b it dead time 1 setup register (tc7dra), pulse width 1 setup register (tc7drb), period setup register (tc7drc) , dead time 2 setup register (tc7drd), pulse width 2 setup register (tc7dre), and two capture value registers (tc7capa and tc7capb). timer/counter 7 control register 1 tc7cr1 (0029h) 76543210 trgam trgsel ppg2ini ppg1ini ncrsel tc7ck (initial value: 0000 0000) 10-bit up counter compare register e a b cy d s compare register d compare register c compare register b compare register a tc7cr1 tc7cr2 tc7capa tc7capb tc7cr3 noise canceller emergency output stop control edge detection ppg output control comparator tc7dra tc7drb tc7drc tc7drd tc7dre transfer control capture control inttc7t interrupt request fc fc/2 fc/2 2 fc/2 3 inttc7p interrupt request intemg interrupt request emergency stop tc7ck tgram start/ clear emgf csidis cstc tc7st stm cntbf trgsel emgf cstc emgie emgr ppg2oe ppg1oe tc7out csidis ncrsel tc7 pin emg pin ppg1 ppg2 ppg2ini ppg1ini ppg1ini/ ppg2ini ppg1oe/ ppg2oe tc7out
page 74 9. 10-bit timer/counter (tc7) 9.2 control TMP86FH12MG note: due to the circuit configuration, a pulse shorter than 1/fc may be eliminated as noise or accepted as a trigger. tc7ck select a source clock (supplied to the up counter). 00: fc [hz] 01: fc/2 [hz] 10 fc/2 2 [hz] 11: fc/2 3 [hz] r/w ncrsel select the duration of noise elimination for tc7 input (after passing through the flip-flop). 00: eliminate pulses shorter than 16/fc [s] as noise. 01: eliminate pulses shorter than 8/fc [s] as noise. 10: eliminate pulses shorter than 4/fc [s] as noise. 11: do not eliminate noise. (note) ppg1ini specify the initial value of ppg1 out- put. select positive or negative logic. 0: low (positive logic) 1: high (negative logic) ppg2ini specify the initial value of ppg2 out- put. 0: low (positive logic) 1: high (negative logic) trgsel select a trigger start edge. 0: start on trigger falling edge. 1: start on trigger rising edge. trgam trigger edge acceptance mode 0: always accept trigger edges. 1: do not accept trigger edges during active output. timer/counter 7 control register 2 tc7cr2 (002ah) 76543210 emgr emgie ppg2oe ppg1oe cstc tc7out (initial value: 0000 0000) tc7out select an output waveform mode. 00: ppg1/ppg2 independent output 01: ? 10: output with variable duty ratio 11: output with 50% duty ratio r/w cstc select a count start mode. 00: command start and capture mode 01: command start and trigger start mode. 10: trigger start mode 11: - ppg1oe enable/disable ppg1 output. 0: disable 1: enable ppg2oe enable/disable ppg2 output. 0: disable 1: enable emgie enable/disable input on the emg pin. 0: disable input. 1: enable input. emgr cancel the emergency output stop state. 0: - 1: cancel the emergency output stop state. (upon canceling the state, this bit is automatically cleared to 0.) timer/counter 7 control register 3 tc7cr3 (002bh) 76543210 emgf cntbf csidis stm tc7st (initial value: **00 0000)
page 75 TMP86FH12MG note 1: the tc7cr1 and tc7cr2 registers should not be rewritten after a timer start (when tc7st, bit0 of the tc7cr3, is set to 1). note 2: before attempting to modify the tc7cr1 or tc7cr2, clear tc7st and then check that cntbf = 0 to determine that the timer is stopped. note 3: the tc7st bit only causes the timer to start or stop; it does not indicate the current operating state of the counter. i ts value does not change automatically when counting starts or stops note 4: in command start and capture mode or command start and tr igger start mode, writing 1 to tc7st causes the timer to restart immediately. it means that rewriting any bit other than tc7st in the tc7cr3 after a command start causes the rewriting of tc7st, resulting in the timer being restarted (ppg output is started from the initial state). when tc7st is set to 1, rewriting the tc7cr3 (using a bit manipulation or ld instruction) clears the counter and restarts the timer. note 5: tc7cr2 is always read as 0 even after 1 is written. note 6: data registers are not updated by merely modifying the output mode with tc7cr2. after modifying the output mode, reconfigure data registers tc7dra to tc7dre. ensure that the data registers are written in an appropriate order because they are not enabled until the upper byte of the tc7drc is written. tc7st start/stop the timer. 0: stop 1: start r/w stm select the state when stopped. select continuous or one-time output. tc7st = 0 tc7st = 1 00: immediately stop and clear the counter with the output initialized. continuous out- put 01: immediately stop and clear the counter with the output maintained. continuous out- put 10: stop the counter after completing output in the current period. one-time output 11: - ? csidis disable the first interrupt at upon a com- mand start. 0: allow a periodic interrupt (inttc7p) to occur in the first period upon a command start. 1: do not allow a periodic interrupt (inttc7p) to occur in the first period upon a command start. cntbf counting status flag 0: counting stopped 1: counting in progress read only emgf emergency output stop flag 0: operating normally 1: output stopped in emergency dead time 1 setup register 1514131211109876543210 tc7dra tc7drah (0009h) tc7dral (0008h) (0009h, 0008h) read/write (initial value: **** **00 0000 0000) pulse width 1 setup register 1514131211109876543210 tc7drb tc7drbh (000bh) tc7drbl (000ah) (000bh, 000ah) read/write (initial value: **** **00 0000 0000) period setup register 1514131211109876543210 tc7drc tc7drch (000dh) tc7drcl (000ch) (000dh, 000ch) read/write (initial value: **** **00 0000 0000)
page 76 9. 10-bit timer/counter (tc7) 9.2 control TMP86FH12MG note 1: data registers tc7dra to tc7dre have double-stage configur ation, consisting of a data register that stores data written by an instruction and a compare register to be compared with the counter. note 2: when writing data to data registers tc7dra to tc7dre, first write the lower byte and then the upper byte. note 3: unused bits (bits 10 to 15) in the upper bytes of dat a registers tc7dra to tc7dre ar e not assigned specific register functions. these bits are always read as 0 even when a 1 is written. note 4: values read from data registers tc7dra to tc7dre may differ from the actual ppg output waveforms due to their dou- ble-stage configuration. note 5: data registers are not updated by merely modifying the output mode with tc7cr2. after modifying the output mode, reconfigure data registers tc7dra to tc7dre. ensure that the data registers are written in an appropriate order because they are not enabled until the upper byte of the tc7drc is written. note 1: capture registers (tc7capa and tc7capb) must be read in the following order: lower byte of the tc7capa, upper byte of the tc7capa, lower byte of the tc7capb, upper byte of the tc7capb. note 2: the next captured data is not updated by reading the tc7capa only. the tc7capb must also be read. note 3: it is possible to read the tc7capb only. read the lower byte first. note 4: if a capture edge is not detected within a period, the previous capture value is maintained in the next period. note 5: if more than one capture edge is detected within a period, the capture value for the edge detected last is valid in the next period. note 6: bits 10 to 15 of the tc7capa and tc7capb are always read as 0. dead time 2 setup register 1514131211109876543210 tc7drd tc7drdh (0fb1h) tc7drdl (0fb0h) (0fb1h, 0fb0h) read/write (initial value: **** **00 0000 0000) pulse width 2 setup register 1514131211109876543210 tc7dre tc7dreh (0fb3h) tc7drel (0fb2h) (0fb3h, 0fb2h) read/write (initial value: **** **00 0000 0000) rising-edge capture value register 1514131211109876543210 tc7capa tc7capah (0fb5h) tc7capal (0fb4h) (0fb5h, 0fb4h) read only (initial value: 0000 00** **** ****) falling-edge capture value register 1514131211109876543210 tc7capb tc7capbh (0fb7h) tc7capbl (0fb6h) (0fb7h, 0fb6h) read only (initial value: 0000 00** **** ****)
page 77 TMP86FH12MG 9.3 configuring control and data registers configure control and data registers in the following order: 1. configure mode settings: tc7cr1, tc7cr2 2. configure data registers (dead time, pulse width): tc7dra, tc7drb, tc7drd, tc7dre (only those required for selected mode) 3. configure data registers (period): tc7drc 4. configure timer start/stop:tc7cr3 ? data registers have double-stage conf iguration, consisting of a data regi ster that stores data written by an instruction and a compare register to be compared with the counter. ? data stored in a data register is processed according to the output mode specified in the tc7out, transferred to the compare regi ster, and then used for comp arison with th e up counter. ? data registers required for the speci fied output mode are used for data register processing and transfer to the compare register. ensure that the output mode is specified in the tc7out (bits 0 and 1 of the tc7cr2) before configuring data registers. ? writing data to the upper byte of the tc7drc causes a da ta transfer request to be issued for data in data registers tc7dra to tc7dre. if a counter matc h or clear occurs while th at request is valid, the data is transferred to the compare register and becomes valid for comparison. ? if a data register is written more than once within a period, the data in the data register that was set when the upper byte of the tc7drc was written is valid as data for the next period. the data in the data register written last in the first period will be valid for the period that follows the next period. figure 9-2 example c onfiguration of contro l/data registers (1) if data is rewritten more than once within a period, the data written first is valid in the next period. valid in next period execute write instruction. period (1) tc7dra tc7drb tc7drc period (2) period (3) period (4) a1 b1 c1 execute write instruction. a2 b2 c2 execute write instruction. a3 b3 c3 previous data is maintained if data is not rewritten within the period. execute write instruction. data valid in each period period (1) tc7dra tc7drb tc7drc period (2) period (3) period (4) period (5) a1 b1 c1 execute write instruction. a5 c7 a1 b1 c1 a2 b1 c2 a3 b2 c5 a5 b2 c7 a2 c2 a4 c6 a3 c5 b2 c4 c3 execute write instruction. a6 b3 c8 a7 b4 c9 a6 b3 c8 if data is rewritten more than once within a period, the data written last is valid in the period following the next period. execute more than one data write instruction. no data write
page 78 9. 10-bit timer/counter (tc7) 9.4 features TMP86FH12MG figure 9-3 example c onfiguration of contro l/data registers (2) 9.4 features 9.4.1 programmable pulse gener ator output (ppg output) the ppg1 and ppg2 pins provide ppg outputs. the output waveform mode for ppg outputs is specified with tc7cr2 and their waveforms are contro lled by comparing the co ntents of the 10-bit up counter with the data set in data registers (tc7dra to tc7dre). three output waveform modes are available: 50% duty mode, variable duty mode, and ppg1/ppg2 independent mode. 9.4.1.1 50% duty mode (1) description with a period specified in the tc7drc, the ppg1 and ppg2 pins provide waveforms having a pulse width (active duration) that equals a half the period. the ppg1 output is active at the beginning of a period and becomes inactive at half the period. the ppg2 output is inactive at the be ginning of a period, becomes active at half the period, and remains active until the end of the period. if a dead time is specified in the tc7dra, the pulse width (active duration) is shortened by the dead time. (2) register settings tc7out = ?11?, tc7dra = ?dead time?, tc7drc = ?period? (3) valid range for data register values (a) period: 002h tc7drc 400h (writing 400h to tc7drc results in 000h being read from it.) if tc7drc is written in the next period data valid in each period period (1) tc7dra tc7drb tc7drc period (2) period (3) period (4) period (5) period (6) a1 b1 c1 a1 b1 c1 a1 b1 c1 a3 b3 c3 a1 b1 c1 a2 b2 c2 c3 a3 b3 a3 b3 c3 a1 b1 c1 a2 b2 c2 a3 b3 c3 a4 b4 c3 a4 b4 c3 more than one data write more than one data write no data write
page 79 TMP86FH12MG when the value set in the tc7drc is an odd number, the ppg2 pulse width is one count longer than the ppg1 pulse width. (b) dead time tc7dra: 000h tc7dra < tc7drc/2 to specify no dead time, set the tc7dra to 000h. figure 9-4 example oper ation in 50% duty mode: command and capture start, pos itive logic, continuous output 9.4.1.2 variable duty mode (1) description with a period specified in the tc7drc and a pulse width in the tc7drb, the ppg1 pin provides a waveform having the specified pulse width while the ppg2 pin provides a waveform having a pulse width that equals (tc7drc ? tc7drb). the ppg1 output is active at the beginning of a period, remains active during the pulse width spec- ified in the tc7drb, after which it is inactive until the end of the period. the ppg2 output is inac- tive at the beginning of a period, remains inactive during the pulse width specified in the tc7drb, after which it is active until the end of the peri od, that is, during the pulse width of (tc7drc ? tc7drb). if a dead time is specified in the tc7dra, the pulse width (active duration) is shortened by the dead time. (2) register settings tc7out = ?10?, tc7dra = ?dead time?, tc7drb = ?pulse width?, tc7drc = ?period? s, 0 m s m ' s 1 m s/2 s, 0 2 13 s/2+1 s/2+m counter period dead time source clock ppg1 output m: dead time dead time (tc7dra) period (tc7drc) pulse width (tc7drc/2) pulse width (tc7drc/2) dead time (tc7dra) m: dead time s: period active duration active duration ppg2 output inttc7t inttc7p
page 80 9. 10-bit timer/counter (tc7) 9.4 features TMP86FH12MG (3) valid range for data register values (a) period: 002h tc7drb + tc7dra < tc7drc 400h (writing 400h to tc7drc results in 000h being read from it.) (b) pulse width: 001h tc7drb < tc7drc (c) dead time: 000h tc7dra < tc7drb, 000h tc7dra < (tc7drc ? tc7drb) (to specify no dead time, set the tc7dra to 000h.) figure 9-5 example operat ion in variable duty mode: command and capture start, positi ve logic, c ontinuous output 9.4.1.3 ppg1/ppg2 independent mode (1) description for the ppg1 output, specify the dead time in the tc7dra and pulse width in the tc7drb. for the ppg2 output, specify the dead time in the tc7drd and pulse width in the tc7dre. with a common period specified in the tc7drc, the ppg1 and ppg2 pins provide waveforms having the specified pulse widths. s, 0 m s m ' s 1m n s , 02 13 n+1 n+m counter period dead time n n ' pulse width source clock ppg1 output m: dead time dead time (tc7dra) period (tc7drc) pulse width (tc7drc ? tc7drb) pulse width (tc7drb) dead time (tc7dra) m: dead time s: period n: pulse width active duration active duration ppg2 output inttc7t inttc7p
page 81 TMP86FH12MG the ppg1 output is active at the beginning of a period, remains active during the pulse width spec- ified in the tc7drb, after which it is inactive until the end of the period. the ppg2 output is active at the beginning of a period, remains active during the pulse width spec- ified in the tc7dre, after which it is inactive until the end of the period. if a dead time is specified in the tc7dra for the ppg1 output or in the tc7drd for the ppg2 output, the pulse width (active duration) is shortened by the dead time. (2) register settings tc7out = ?00?, tc7drc = ?period? tc7dra = ?ppg1 dead time?, tc7drb = ?ppg1 pulse width? tc7drd = ?ppg2 dead time?, tc7dre = ?ppg2 pulse width? (3) valid range for data register values (a) period: 002h tc7drc 400h (writing 400h to tc7drc results in 000h being read from it.) (b) pulse width: 001h tc7drb 400h (writing 400h to tc7drb results in 000h being read from it.) 001h tc7dre 400h (writing 400h to tc7dre results in 000h being read from it.) (c) dead time: 000h tc7dra 3ffh, where tc7dra < tc7drb tc7drc 000h tc7drd 3ffh, where tc7drd < tc7dre tc7drc (to specify no dead time, write 000h.) ? settings for a duty ratio of 0% 002h tc7drc tc7dra 3ffh (ppg1 output) 002h tc7drc tc7drd 3ffh (ppg2 output) ? settings for a duty ratio greater than 0%, up to 100% 000h tc7dra < tc7drb tc7drc 400h (ppg1 output) 000h tc7drd < tc7dre tc7drc 400h (ppg2 output) period 0% duty period 100% duty
page 82 9. 10-bit timer/counter (tc7) 9.4 features TMP86FH12MG figure 9-6 example operation in ppg1/ppg2 independent mode: command and capture start, positi ve logic, c ontinuous output 9.4.2 starting a count a count can be started by using a command or tc7 pin input. 9.4.2.1 command start and capture mode (1) description writing a 1 to tc7st causes the current count to be cleared and the counter to start counting. once the count has reached a specified period, the count er is cleared. the counter subsequently restarts counting if stm specifies continuous mode; it stops counting if stm specifies one-time mode. writing a 1 to tc7st before the count reaches a period causes the counter to be cleared, after which it operates as specified with stm. the count values at the rising and falling edges on the tc7 pin can be stored in capture registers (details for the capture are gi ven in a separate section). 0 m s m ' s 1m t us , 02 13 n counter period dead time n n ' pulse width source clock ppg1 output m: dead time ppg1 dead time (tc7dra) period (tc7drc) ppg2 pulse width (tc7dre) ppg2 dead time (tc7drd) ppg1 pulse width (tc7drb) s: period u: pulse width t: dead time n: pulse width active duration active duration ppg2 output inttc7t inttc7p t t ' dead time u u ' pulse width
page 83 TMP86FH12MG (2) register settings cstc = ?00?: command start and capture mode stm: continuous/one-time output tc7st = ?1?: starts counting figure 9-7 exampl e operation in comma nd start and capture mode 9.4.2.2 command start and trigger start mode (1) description writing a 1 to tc7st causes the current count to be cleared and the counter to start counting. the operation is the same as that in command start and capture mode if there is no trigger input on the tc7 pin. if an edge specified with the start edge selection field (trgsel) appears on the tc7 pin, however, the timer starts counting. the counter is cleared and stopped while the tc7 pin is driven to the specified clear/stop level. if the tc7 pin is at the clear/stop level when a count start command is issued (1 is written to tc7st), counting does not start (inttc7p does not occur) until a trigger start edge appears, causing inttc7t to occur (a trig ger input takes precedence over a command start). note: for more information on the acceptance of a trigger, see 9.4.2.5 ?trigger start/stop acceptance mode?. (2) register settings cstc = ?01?: command start and trigger start mode stm: continuous/one-time output tc7st = ?1?: starts counting trgsel: trigger selection figure 9-8 example operation in command st art and trigger start mode tc7st = 1 count start (command) count cleared start count cleared start count cleared restart ppg1 ppg output with a period specified with tc7drc ppg output with a period specified with tc7drc ppg output with a period specified with tc7drc count start (command) count cleared start count cleared count start ppg1 when trgsel = 0 (start on falling edge) tc7 input (signal after noise elimination) period (tc7drc) count stopped ppg output with a period specified with tc7drc if there is no trigger count stops with a trigger (high level). count starts with a trigger (falling edge).
page 84 9. 10-bit timer/counter (tc7) 9.4 features TMP86FH12MG 9.4.2.3 trigger start mode (1) description if an edge specified with the st art edge selection field (trgsel) appears on the tc7 pin, the timer starts counting. the counter is cleared and stopped wh ile the tc7 pin is driven to the specified clear/ stop level. in trigger start mode, writing a 1 to tc7st is ignored and does not initialize the ppg output. note: for more information on the acceptance of a trigger, see 9.4.2.5 ?trigger start/stop acceptance mode?. (2) register settings cstc = ?10?: trigger start mode stm: continuous/one-time output tc7st = ?1?: starts waiting for a trigger on the tc7 pin trgsel: trigger selection figure 9-9 example operat ion in trigger start mode 9.4.2.4 trigger capture mode (cstc = 00) (1) description when counting starts in command start and capture mode, the count values at the rising and falling edges of the tc7 pin input are captured and st ored in capture registers tc7capa and tc7capb, respectively. count start count stopped count stopped count start count cleared count cleared ppg1 output (example) tc7 input (signal after noise elimination) after a command is set, counting does not start until a specified trigger appears. count start count stopped count start command set command set count cleared ppg1 output (example) tc7 input (signal after noise elimination) after a command is set, counting does not start until a specified trigger appears.
page 85 TMP86FH12MG the captured data is first stored in the capture buffer. at the end of the period, the data is trans- ferred from the capture buffer to the capture register. if a trigger input does not appear within a period, the data captured in the previous period rema ins in the capture buffer and is transferred to the capture register at the end of the period. if more th an one trigger edge is detected within a period, the data captured last is written to the capture register. captured data must be read in the following order: lower byte of capture register a (tc7capal), upper byte of capture register a (tc7capah), lo wer byte of capture register b (tc7capbl), and upper byte of capture register b (tc7capbh). note that reading only the rising-edge captured data (tc7capa) does not update the next captured data. the falling-edge captured data (tc7capb) must also be read. an attempt to read a captured va lue from a register other than the upper byte of the tc7capb causes the capture registers to enter protected state, in which captured data cannot be updated. read- ing a value from the upper byte of the tc7capb can cels that state, re-enabl ing the updating of cap- tured data (the tc7capa and tc7capb ar e read as a single set of operation). note that the protected state may be still effective immediately after the c ounter starts. ensure that a dummy read of capture registers is performed in the first period to cancel the protected state. the capture feature of the tc7 assumes that a capture trigger (rising or falling edge) appears within a period. captured data is updated (an edge is detected) only when the timer is operating (tc7st = 1). if a timer stop command (tc7st = 0) is written within a period, captured data will be undefined. captured data is not updated after a one-time stop command is written. in one-time stop mode, no trigger is accepted af ter a stop command is given. (2) register settings cstc = ?00?: command start and capture mode stm: continuous/one-time output tc7st = ?1?: starts counting
page 86 9. 10-bit timer/counter (tc7) 9.4 features TMP86FH12MG figure 9-10 exam ple operation in tr igger capture mode 9.4.2.5 trigger start/stop acceptance mode (1) selecting an input signal logi c for the tc7 pin (trigger input) the logic for an input trigger signal on the tc7 pin can be specified using tc7cr1 . ? trgsel = 0: counting starts on the falling edge. the counte r is cleared and stopped while the tc7 pin is high. ? trgsel = 1: counting starts on the rising edge. the counter is cleared and stopped while the tc7 pin is low. a b c d a c x a c y b d b d capture registers 1 period rising edge falling edge rising edge falling edge captured values read (c and d read) 1 period tc7 input (signal after noise elimination) captured values read (a and b read) captured values read (data read skipped) capture buffers a b c d a1 b1 c1 a2 c2 a c2 c c1 a1 x c2 c c1 a1 y a2 d b1 d ba 2 d b1 capture registers 1 period captured values read (a1 and d read) 1 period 1 period 1 period tc7 input (signal after noise elimination) captured values read (c and d read) captured values read (data read skipped) capture buffers started reading other than upper capb in this period
page 87 TMP86FH12MG figure 9-11 tr igger input signal when trgsel is set to 0 to select a falling-edge trigger, a falling edge detected on the tc7 pin causes the counter to start counting and a high level on the tc7 pin causes the counter to be cleared and the ppg output to be initialized. the counter is stopped while the tc7 pin input is high. when trgsel is set to 1 to sel ect a rising-edge trigger, a rising edge detected on the tc7 pin causes the counter to start counting and a low leve l on the tc7 pin causes the counter to be cleared and the ppg output to be initialized. the counter is stopped while the tc7 pin input is low. in one-time stop mode, th e counter accepts a stop trigger but does not accept a start trigger (when a stop trigger is accepted within a period, the output is immediatel y initialized a nd the counter is stopped). all triggers (start and stop) are ignored when the timer is stopped (tc7st = 0). (2) specifying whether triggers are always accepted or ignored when ppg outputs are active the tc7cr1 specifies whether triggers from the tc7 pin are always accepted or ignored when the ppg output is active. ?trgam = 0: triggers from the tc7 pin are always accepted regardless of whether ppg1 and ppg2 out- puts are active or inactiv e. a trigger starts or clears/stops the timer and deactivates ppg1 and ppg2 outputs. ?trgam = 1: triggers from the tc7 pin are accepted only wh en ppg1 and ppg2 outputs are inactive. a trigger starts or clears/stops the timer. trigge rs are ignored when ppg1 and ppg2 outputs are active. the active/inactive state of the ppg1 or ppg2 pin has meaning only when output on the pin is enabled with ppg1oe or ppg2oe. count started count cleared count started tc7 pin input counter operating counter stopped counter operating trgsel = 0 count started count cleared count started tc7 pin input counter operating counter stopped counter operating trgsel = 1 count cleared tc7 pin input ppg output counting stop mode with the outputs at the end of the period counter stopped initial value one-time mode
page 88 9. 10-bit timer/counter (tc7) 9.4 features TMP86FH12MG figure 9-12 start and clear /stop triggers on the tc7 pin: falling-edge trigger (counting stopped at high leve l), triggers always accepted (3) ignoring triggers when ppg outputs are active setting trgam to 1 specifies that triggers are ignored when ppg outputs are active; trigger edges detected when ppg1 and ppg2 ou tputs are inactive are accepted and cause the counter to be cleared and stopped. if a trigger is detected when ppg1 and ppg2 outputs are active, the counter does not stop immediately but continues counting until the outputs become inactive. if the trigger signal level is a stop level when the outputs become inactive, the counter is cl eared/stopped and waits for a next start trigger. if output is enabled for both ppg 1 and ppg2, triggers are accepted only when both ppg1 and ppg2 outputs are inactive. figure 9-13 start tr iggers on the tc7 pin: falling-edge trigger (counting stopped at high level), tri ggers ignored when ppg outputs are active tc7 pin input ppg1 output (positive logic) ppg2 output (positive logic) inttc7t inttc7p counter operating counter operating counter operating counter operating counter stopped counter stopped counter stopped count started count started count started count started count cleared count cleared end of a period count cleared tc7 pin input (signal after noise elimination) igbt1 (positive logic) igbt2 (positive logic) inttc7 triggers not accepted inttcr counter operating counter operating counter operating counter stopped counter stopped a trigger detected when ppg1 and ppg2 are inactive causes the counter to stop or start. a trigger detected when ppg1 or ppg2 is active does not cause the counter to stop. a high level of the trigger input causes the counter to stop when ppg1 and ppg2 become inactive. a trigger detected when ppg1 or ppg2 is active does not cause the counter to stop or restart.
page 89 TMP86FH12MG 9.4.3 configuring how the timer stops setting tc7st to 0 causes the timer to stop with the specified output st ate according to the setting of stm. 9.4.3.1 counting stopped with the outputs initialized when stm is set to 00, the counter stops immediately with the ppg1 and ppg2 outputs initialized to the values specified wi th ppg1ini and ppg2ini. 9.4.3.2 counting stopped with the outputs maintained when stm is set to 01, the counter stops immediat ely with the curr ent ppg1 and ppg2 output states maintained. to restart the counter from the maintained state (stm = 01), set tc7st to 1. the counter is restarted with the initial output values, specified with ppg1ini and ppg2ini. 9.4.3.3 counting stopped with the outputs initialized at the end of the period when stm is set to 10, the counter continues counting until the end of the current period and then stops. if a stop trigger is detect ed before the end of the period, how ever, the counter stops immediately. tc7cr1 and tc7cr2 must not be rewritten before the counter stops completely. the cntbf flag (tc7cr3) can be read to determine whether the counter has stopped. 9.4.4 one-time/continuous output mode 9.4.4.1 one-time output mode starting the timer (tc7st = 1) with stm set to 10 specifies one-time output mode. in this mode, the timer stops counting at the end of a period. for a trigger start, the counter is stopped until a trigger is detected. a specified trigger restarts counting and the counter stops at the end of the period or when a stop trigger is detected, after which it waits for a trigger again. for a command start, the counter is stopped until tc7st is reset to 1. tc7cr1 and tc7cr2 must not be rewritten before the counter stops completely. the cntbf flag (tc7cr3) can be read to determine whether the counter has stopped. tc7st remains set to 1 after the counter is stopped. when tc7st is set to 1, setting stm to 10 clears the counter, which then restarts counting from the beginning in one-time output mode. 9.4.4.2 continuous output mode starting the timer (tc7st = 1) with stm set to 00 or 01 specifies continuous output mode. in this mode, the timer outputs specified waveforms continuously.
page 90 9. 10-bit timer/counter (tc7) 9.4 features TMP86FH12MG figure 9-14 immedi ately stopping and clearing the count er with the ou tputs initialized (stm = 00) figure 9-15 immediately st opping and clearing the counter with the outputs maintained (stm = 01) figure 9-16 stopping th e counter at the end of the period (stm = 10) figure 9-17 stopping the counter at the end of the period (stm = 10): tc7st = 1, one-time output mode count started tc7st = 1 stm = 00 output enabled ppg1e/ppg2e = 1 stop command tc7st = 0 the counter is forcibly stopped and cleared, with the outputs initialized. ppg1 (positive logic) ppg1ini = 0 ppg2 (negative logic) ppg1ini = 1 count started tc7st = 1 stm = 01 output enabled ppg1e/ppg2e = 1 stop command tc7st = 0 the counter is forcibly stopped and cleared, with the outputs maintained. ppg1 (positive logic) ppg1ini = 0 ppg2 (negative logic) ppg1ini = 1 count started tc7st = 1 stm = 00 or 01 1 period 1 period count stopped output enabled ppg1e/ppg2e = 1 stop command tc7st = 0 stm = 10 after a stop command is executed, the counter continues counting until the end of the period. it stops at the end of the period. ppg1 (positive logic) ppg1ini = 0 ppg2 (negative logic) ppg1ini = 1 count started tc7st = 1 stm = 10 1 period output enabled ppg1e/ppg2e = 1 count stopped at the end of the period the counter stops at the end of the period and then waits for a command start or a start trigger. ppg1 (positive logic) ppg1ini = 0 ppg2 (negative logic) ppg1ini = 1
page 91 TMP86FH12MG 9.4.5 ppg output control (initial value/output logi c, enabling/disabling output) 9.4.5.1 specifying initial values and output logic for ppg outputs the ppg1ini and ppg2ini bits (tc7cr1 and tc7cr1) specify the initial val- ues of ppg1 and ppg2 outputs as well as their output logic. (1) positive logic output setting the bit to 0 specifies that the output is initially low and driven high upon a match between the counter value and specified dead time. (2) negative logic output setting the bit to 1 specifies that the output is initially high and driven low upon a match between the counter value and specified dead time. 9.4.5.2 enabling or disabling ppg outputs the ppg1oe and ppg2oe bits (tc7cr2 and tc7cr2) specify whether ppg outputs are enabled or disabled. wh en outputs are disabled, no ppg waveforms appear while the counter is operating, allowing the ppg1 and ppg2 pins to be used as normal input/output pins. the states of the pins when outputs are disabled depend on the settings in port registers. 9.4.5.3 using the tc7 as a normal timer/counter the tc7 can be used as a normal timer/counte r when ppg outputs are disabled using ppg1e and ppg2e. in that case, use an inttc7 p interrupt, which occurs upon a match with the value specified in the data register (tc7drc). to start the counter, us e start control (tc7s) in command start and capture mode. figure 9-18 using the tc7 as a normal timer/counter 9.4.6 eliminating noise from the tc7 pin input a digital noise canceller eliminates noise from the input signal on the tc7 pin. the digital noise canceller uses a sampling clock of fc/4, fc/2 or fc, as specified with ncrsel, and samples the signal five times. it accepts a level input which is co ntinuous at least over the period of time required for five samplings. any level input which does not continue over the period of time required for five samplings is canceled as noise. n 0 12 34 n/0 1 2 3 4 5 6 7 counter source clock tc7drc inttc7p match detected start
page 92 9. 10-bit timer/counter (tc7) 9.4 features TMP86FH12MG figure 9-19 noise canceller operation ? when ncrsel = 00, a tc7 input level after passing through the f/f is always canceled if its duration is 16/fc [s] or less and always assumed as a signal if its duration is 20/fc [s] or greater. after the input signal supplied on the tc7 pin passes through the f/f, there is a delay between 21/fc [s] and 24/fc [s] before the ppg outputs vary. ? when ncrsel = 01, a tc7 input level after passing through the f/f is always canceled if its duration is 8/fc [s] or less and always assumed as a signal if its duration is 10/fc [s] or greater. after the input signal supplied on the tc7 pin passes through the f/f, there is a delay between 13/fc [s] and 14/fc [s] before the ppg outputs vary. ? when ncrsel = 10, a tc7 input level after passing through the f/f is always canceled if its duration is 4/fc [s] or less and always assumed as a signal if its duration is 5/fc [s] or greater. after the input sig- nal supplied on the tc7 pin passes through the f/f, there is a delay of 5/fc [s] before the ppg outputs vary. ? when ncrsel = 11, a pulse shorter than 1/fc may be assumed as a signal or canceled as noise in the first-stage f/f. ensure that input signal pulses are longer than 1/fc. after the input signal supplied on the tc7 pin passes through the f/f, there is a delay of 4/fc [s] before the ppg outputs vary. table 9-1 noise canceller settings ncrsel sampling frequency (number of samplings) pulse width always assumed as nois e pulse width always assumed as signal at 8 mhz at 16 mhz at 8 mhz at 16 mhz 00 fc/4 (5) 16/fc [s] 2 [ms] 1 [ms] 20/fc [s] 2.5 [ms] 1.25 [ms] 01 fc/2 (5) 8/fc [s] 1 [ms] 500 [ns] 10/fc [s] 1.25 [ms] 0.625 [ms] 10 fc (5) 4/fc [s] 0.5 [ms] 250 [ns] 5/fc [s] 0.625 [ms] 0.3125 [ms] 11 (none) none ? ? (1/fc) fc fc/2 a fter noise elimination fc/4 when ncrsel = 00 when ncrsel = 01 when ncrsel = 10 pulses of 5/fc or longer are assumed as a signal. pulses of 10/fc or longer are assumed as a signal. pulses of 20/fc or longer are assumed as a signal. pulses of 4/fc or shorter are canceled. pulses of 8/fc or shorter are canceled. pulses of 16/fc or shorter are canceled. tc7 pin input (after passing through f/f) 1 2 3 4 5 1 2 3 4 5 1 2 3 4 1 2 3 4 5 1 2 3 4 5 1 2 3 4 5 b a z s a b z c noise canceller edge detection ppg output control circuit f/f tc7 input fc ppg output sampling clock fc fc/2 fc/4 ncrsel ncrsel = 11
page 93 TMP86FH12MG note 1: if the pin input level changes while the specified noise elimination threshold is being modified, the noise canceller may assume noise as a pul se or cancel a pulse as noise. note 2: if noise occurs in synchronization with the inter nal sampling timing consecutiv ely, it may be assumed as a signal. note 3: the signal supplied on the tc7 pin requires 1/fc [s] or less to pass through the f/f. 9.4.7 interrupts the tc7 supports three interrupt sources. 9.4.7.1 inttc7t (trigger start interrupt) a trigger interrupt (inttc7t) occurs when the counter star ts upon the detection of a trigger edge spec- ified with tc7cr1. this interrupt does not occur with a trigger edge for clearing the count. a trigger edge detected in trigger capture mode does not cause an interrupt. a start trigger causes an inter- rupt even when the counte r is stopped in emergency. figure 9-20 trigger start interrupt 9.4.7.2 inttc7p (period interrupt) a period interrupt (inttc7p) occurs when the coun ter starts with a command and when the counter is cleared with the specified counter period (tc7drc) r eached, that is, at the end of a period. a match with the set period causes an interrupt even when the counter is stopped in emergency. figure 9-21 period interrupt x0 12 m-2 m-1 012 0 12 counter tc7 trigger inttc7t inttc7p ppg output count started cleared cleared 1 period cleared upon match tc7drc x12 m-2 m-2 m-1 m, 0 1 2 m-1 m, 0 counter inttc7t inttc7p ppg output 1 period timer stopped command start command stop stop at the end of period clear upon match tc7drc 1 period csidis specifies whether the first inttc7p occurs.
page 94 9. 10-bit timer/counter (tc7) 9.4 features TMP86FH12MG if a command start is specified (1 is written in tc7st) when the tc7 pin is at a stop level, the counter does not start (inttc7p does not occur); a subsequent trigger start edge causes the counter to start and inttc7t to occur. 9.4.7.3 intemg (emergency output stop interrupt) an emergency output stop interrupt (intemg) occurs when the emergency output stop circuit operates to stop ppg outputs in emergency. 9.4.8 emergency ppg output stop feature setting tc7cr2 to 1 enables the emergency ppg output stop feature (enables the emg pin input). a low level input detected on the emg pin causes an emg interrupt (intemg) to occur with the ppg wave- forms initialized (as specified with ppg1ini and ppg2ini). (emergency ppg output stop) this feature only disables ppg outputs without stoppin g the counter. use the emg interrupt handler routine to stop the timer. note:ensure that a low level on the emg pin continues for at least 4/fc [s ]. the emergency ppg output stop feature may not operate normally with a low level shorter than 4/fc [s]. figure 9-22 emg pin 9.4.8.1 enabling/disabling input on the emg pin setting tc7cr2 to 1 enables input on the emg pin and setting the bit to 0 disables input on the pin. (initially, emgie is set to 0, disabling an emergency output stop ( emg pin) input.) the input signal on the emg pin is valid only when its shared po rt pin is placed in input mode. ensure that the shared port pin is placed in i nput mode before atte mpting to enable the emg pin input. the emg pin input is sampled using a high-frequency clock. the emergency ppg output stop feature does not operate normally if the high-frequency clock is stopped. 9.4.8.2 monitoring the emergency ppg output stop state when the emergency ppg output stop feature activates, the tc7cr3 is set to 1. 1 read from emgf indicates that ppg outputs are disabled by the emergency ppg output stop feature. to restart the timer in that state, first make necessary settings for stopping the timer befo re canceling the emergency ppg output stop state (by writing 1 to emgr, bit7 of the tc7cr2) and then reconfiguring the control and data registers to restart the timer. f/f f/f f/f sampling circuit s q r emg interrupt (intemg) ppg circuit output emg pin emgie tc7st stm emgr emgf (status flag) port output latch a b z s ppg1oe ppg2oe ppg1oe ppg2oe ppg1ini ppg2ini ppg1 ppg2 tc7 control register 1 tc7 control register 3 tc7 control register 2
page 95 TMP86FH12MG 9.4.8.3 emg interrupt an emg interrupt (intemg) occurs when an emergency ppg out put stop input is accepted. to use an intemg interrupt for some processing, ensure that the interrupt is enabled beforehand. when the emg pin is low with emgie set to 1 ( emg pin input enabled), an at tempt to cancel the emer- gency ppg output stop state results in an interrupt being generated again, with the emergency ppg output stop state reestablished. an intemg interrupt occurs when ever a stop input is accepted when emgie = 1, regardless of whether the timer is operating. 9.4.8.4 canceling the emergency ppg output stop state to cancel the emergency ppg output stop state, en sure that the input on the emg pin is high, set tc7cr3 to 0 and tc7cr3 to 00 to stop the timer, and then set tc7cr2 to 1. setting emgr to 1 cancels the stop state only when tc7st = 0 and stm = 00; ensure that tc7st = 0 and stm = 00 before setting emgr to 1. if the input on the emg pin is low and emgie = 1 when the emergency ppg ou tput stop state is can- celed, the timer re-enters the em ergency ppg output stop state and an intemg interrupt occurs. 9.4.8.5 restarting the timer after canceling the emergency ppg output stop state to restart the timer after canceling the emergency pp g output stop state, rec onfigure the control regis- ters (tc7cr1, tc7cr2, tc7cr3) before restarting the timer. the timer cannot restart in the emergency ppg out put stop state. monitor the emergency ppg output stop state and cancel the stat e before reconfiguring the control register s to restart the timer. ensure that the control registers are rec onfigured according to the appropriate procedure for configuring timer operation control. 9.4.8.6 response time between emg pin input and ppg outputs being initialized the time between a low level input being detected on the emg pin and the ppg outputs being initialized is up to 10/fc [s].
page 96 9. 10-bit timer/counter (tc7) 9.4 features TMP86FH12MG figure 9-23 timing between emg pin input being detected and ppg outputs being dis- abled 9.4.9 tc7 operation and mi crocontroller operating mode the tc7 operates when the microcontroller is pl aced in normal1, normal2, idle1, or idle2 mode. if the mode changes from normal or idle to stop, sl ow, or sleep while the tc7 is operating, the tc7 is initialized and stops operating. to change the microcontroller operating mode from normal or idle to stop, slow, or sleep, ensure that the tc7 timer is stopped before attempting to execute a mode change instruction. to change the mode from stop, slow, or sleep to normal to restart the tc7, reconfigure all registers according to the appropriate tc7 operation procedure. ppg pin output emg pin input emgie 10/fc [s] 1.25 s (at 8 mhz) tc7st stm emgf (state monitor) emg interrupt specified with an instruction emergency stop input output initialized forcibly initial output state emergency stop input share port in input mode emgr = 1, protection feature enabled intemg (emg interrupt) emgf = 1, emergency output stop state emergency output stop state tc7st = 1, timer operating stm = 01, timer operating (continuous mode) emgr = 1, cancel emergency output stop state stm = 00 tg7st = 0
page 97 TMP86FH12MG 10. 16-bit timercounter 1 (tc1) 10.1 configuration figure 10-1 timercounter 1 (tc1) :::? pin tc1:w:?::? mett1 start capture clear source clock ppg output mode write to tc1cr 16-bit up-counter clear tc1drb selector tc1dra tc1cr tc1 control register match inttc1 interript tff1 acap1 tc1ck window mode set toggle q 2 toggle set clear q y a d b c s b a y s tc1s clear mppg1 ppg output mode internal reset s enable mcap1 s y a b tc1s 2 set clear command start decoder external trigger start edge detector note: function i/o may not operate depending on i/o port setting. for more details, see the chapter "i/o port". port (note) q pulse width measurement mode falling rising trigger external cmp 16-bit timer register a, b pulse width measurement mode port (note) fc/2 11, fs/2 3 fc/2 7 fc/2 3
page 98 10. 16-bit timercounter 1 (tc1) 10.2 timercounter control TMP86FH12MG 10.2 timercounter control the timercounter 1 is controlled by the timercounter 1 control register (tc1cr) and two 16-bit timer registers (tc1dra and tc1drb). note 1: fc: high-frequency clock [hz], fs: low-frequency clock [hz] note 2: the timer register consists of two shift registers. a va lue set in the timer register becomes valid at the rising edge of the first source clock pulse that occurs after the upper byte (t c1drah and tc1drbh) is written. therefore, write the lower byte and the upper byte in this order (it is recommended to write the register with a 16-bit acce ss instruction). writing only the lower byte (tc1dral and tc1drbl) does not enable the setting of the timer register. note 3: to set the mode, source clock, ppg output control and time r f/f control, write to tc1cr1 during tc1s=00. set the timer f/f1 control until the first timer start after setting the ppg mode. timer register 1514131211109876543210 tc1dra (0011h, 0010h) tc1drah (0011h) tc1dral (0010h) (initial value: 1111 1111 1111 1111) read/write tc1drb (0013h, 0012h) tc1drbh (0013h) tc1drbl (0012h) (initial value: 1111 1111 1111 1111) read/write (write e nabled only in the ppg output mode) timercounter 1 control register tc1cr (0014h) 76543210 tff1 acap1 mcap1 mett1 mppg1 tc1s tc1ck tc1m read/write (initial value: 0000 0000) tff1 timer f/f1 control 0: clear 1: set r/w acap1 auto capture control 0:auto-capture disable 1:auto-capture enable r/w mcap1 pulse width measure- ment mode control 0:double edge capture 1:single edge capture mett1 external trigger timer mode control 0:trigger start 1:trigger start and stop mppg1 ppg output control 0:continuous pulse generation 1:one-shot tc1s tc1 start control timer extrig- ger event win- dow pulse ppg r/w 00: stop and counter clear oooooo 01: command start o????o 10: rising edge start (ex-trigger/pulse/ppg) rising edge count (event) positive logic count (window) ? ooooo 11: falling edge start (ex-trigger/pulse/ppg) falling edge count (event) negative logic count (window) ? ooooo tc1ck tc1 source clock select [hz] normal1/2, idle1/2 mode divider slow, sleep mode r/w dv7ck = 0 dv7ck = 1 00 fc/2 11 fs/2 3 dv9 fs/2 3 01 fc/2 7 fc/2 7 dv5 ? 10 fc/2 3 fc/2 3 dv1 ? 11 external clock (tc1 pin input) tc1m tc1 operating mode select 00: timer/external trigger timer/event counter mode 01: window mode 10: pulse width measurement mode 11: ppg (programmable pulse generate) output mode r/w
page 99 TMP86FH12MG note 4: auto-capture can be used only in t he timer, event counter, and window modes. note 5: to set the timer registers, the following relationship must be satisfied. tc1dra > tc1drb > 1 (ppg output mode), tc1dra > 1 (other modes) note 6: set tff1 to ?0? in the mode except ppg output mode. note 7: set tc1drb after setting tc1m to the ppg output mode. note 8: when the stop mode is entered, the start control (tc1s) is cleared to ?00? automatically, and the timer stops. after the stop mode is exited, set the tc1s to use the timer counter again. note 9: use the auto-capture function in the operative condition of tc1. a captured value may not be fixed if it's read after th e execution of the timer stop or auto-capture disable. read the capture value in a capture enabled condition. note 10:since the up-counter value is captured into tc1drb by the source clock of up-counter after setting tc1cr to "1". therefore, to read the captured value, wait at least one cycle of the internal source clock before reading tc1drb for the first time.
page 100 10. 16-bit timercounter 1 (tc1) 10.3 function TMP86FH12MG 10.3 function timercounter 1 has six types of operating modes: timer, external trigger timer, event counter, window, pulse width measurement, programmable pulse generator output modes. 10.3.1 timer mode in the timer mode, the up-counter counts up using the internal clock. when a match between the up-counter and the timer register 1a (tc1dra) value is detected, an inttc1 interr upt is generated and the up-counter is cleared. after being cleared, the up-counter restarts counting. setting tc1cr to ?1? captures the up-counter value into the timer reg- ister 1b (tc1drb) with the auto-capture function. use the auto-capture function in the operative conditio n of tc1. a cap- tured value may not be fixed if it's read after the execution of the timer stop or auto-capture disa ble. read the capture value in a capture enabled condition. since the up-counter value is captured into tc1drb by the source clock of up-counter after setting tc1cr to "1". therefore, to read the captured value, wait at leas t one cycle of the internal source clock before reading tc1drb for the first time. note: since the up-counter value is captured into tc1drb by the source clock of up-counter after setting tc1cr to "1". therefore, to read the captured value, wait at least one cycle of the internal source clock before reading tc1drb for the first time. table 10-1 internal source clock for timercounter 1 (example: fc = = example 1 :setting the timer mode with source clock fc/2 11 [hz] and generating an interrupt 1 second later (fc = 16 mhz, tbtcr = ?0?) ldw (tc1dra), 1e84h ; sets the timer register (1 s = = = example 2 :auto-capture ld (tc1cr), 01010000b ; acap1
page 101 TMP86FH12MG figure 10-2 timer mode timing chart match detect acap1 tc1drb tc1dra inttc1 interruput request source clock counter source clock counter ? (a) timer mode (b) auto-capture ? 7 6 345 0 timer start 12 32 1 4 0 counter clear capture n + 1 n n n m + 2 m + 1 m m capture m + 2 m + 1 n + 1 n m ? 1 m ? 1 m ? 2 n ? 1 n ? 1 n ? 1
page 102 10. 16-bit timercounter 1 (tc1) 10.3 function TMP86FH12MG 10.3.2 external tr igger timer mode in the external trigger timer mode, the up-counter starts counting by the input pulse triggering of the tc1 pin, and counts up at the edge of the internal clock. for the trigger edge used to start counting, either the rising or falling edge is defined in tc1cr. ? when tc1cr is set to ?1? (trigger st art and stop) when a match between the up-counter and the tc1dra value is detected after the timer starts, the up-counter is cleared and halted and an inttc1 interrupt request is generated. if the edge opposite to trigger edge is detected before detecting a match between the up-counter and the tc1dra, the up-counter is cleared and ha lted without generating an interrupt request. therefore, this mode can be used to det ect exceeding the specified pulse by interrupt. after being halted, the up-count er restarts counting when th e trigger edge is detected. ? when tc1cr is set to ?0? (trigger start) when a match between the up-counter and the tc1dra value is detected after the timer starts, the up-counter is cleared and halted and an inttc1 interrupt request is generated. the edge opposite to the trigger edge has no effect in count up. the trigger edge for the next count- ing is ignored if detecting it before detectin g a match between the up-counter and the tc1dra. since the tc1 pin input has the noise rejection, pulses of 4/fc [s] or less are rejected as noise. a pulse width of 12/fc [s] or more is required to ensure edge detectio n. the rejection circuit is turned off in the slow1/2 or sleep1/2 mode, but a pulse width of one machine cycl e or more is required. example 1 :generating an interrupt 1 ms after the rising edge of the input pulse to the tc1 pin (fc =16 mhz) ldw (tc1dra), 007dh ; 1ms = = = = example 2 :generating an interrupt when the low-level pulse with 4 ms or more width is input to the tc1 pin (fc =16 mhz) ldw (tc1dra), 01f4h ; 4 ms = = = =
page 103 TMP86FH12MG figure 10-3 external tri gger timer mode timing chart inttc1 interrupt request source clock up-counter tc1dra tc1 pin input inttc1 interrupt request source clock up-counter tc1dra tc1 pin input 0 at the rising edge (tc1s = 10) at the rising edge (tc1s = 10) (a) trigger start (mett1 = 0) count start match detect count start 0 1 2 3 4 2 3 n (b) trigger start and stop (mett1 = 1) count start count start 0 1 2 3 m 0 n n 0 count clear note: m < n count clear 1 2 3 1 n m ? 1 n ? 1 match detect count clear
page 104 10. 16-bit timercounter 1 (tc1) 10.3 function TMP86FH12MG 10.3.3 event counter mode in the event counter mode, the up-counter counts up at the edge of the input pulse to the tc1 pin. either the rising or falling edge of the input pulse is se lected as the count up edge in tc1cr. when a match between the up-counter and the tc1dra va lue is detected, an inttc1 interrupt is generated and the up-counter is cleared. after being cleared, the up-counter restarts counting at each edge of the input pulse to the tc1 pin. since a match between the up-counter and the value set to tc1dra is detected at the edge opposite to the selected edge, an inttc1 interrupt request is generated after a match of the value at the edge opposite to the selected edge. two or more machine cycles are required for th e low-or high-level pulse input to the tc1 pin. setting tc1cr to ?1? captures the up-counter value into tc1drb with the auto capture function. use the auto-capture function in the operative condition of tc1. a captured value may not be fixed if it's read after the execution of the timer stop or auto-capture disable. read the captu re value in a captu re enabled condi- tion. since the up-counter value is captured into tc1drb by the source clock of up-counter after setting tc1cr to "1". theref ore, to read the captured value, wait at least one cycle of the internal source clock before reading tc1drb for the first time. figure 10-4 event count er mode timing chart table 10-2 input pulse width to tc1 pin minimum pulse width [s] normal1/2, idle1/2 mode slow1/2, sleep1/2 mode high-going 2 3 /fc 2 3 /fs low-going 2 3 /fc 2 3 /fs at the rising edge (tc1s = 10) inttc1 interrput request tc1 pin input up-counter tc1dra ? 2 1 0 n timer start 2 1 0 n match detect counter clear n ? 1
page 105 TMP86FH12MG 10.3.4 window mode in the window mode, the up-counter counts up at the rising edge of the pulse that is logical anded product of the input pulse to the tc1 pin (window pulse) and the internal source clock. eith er the positive logic (count up during high-going pulse) or negative logic (count up during low-going pulse) can be selected. when a match between the up-counter and the tc1dra va lue is detected, an inttc1 interrupt is generated and the up-counter is cleared. define the window pulse to the frequency which is sufficiently lower than the internal source clock pro- grammed with tc1cr. figure 10-5 window mode timing chart match detect tc1dra inttc1 interrput request interrput request internal clock counter tc1dra tc1 pin input internal clock counter tc1 pin input inttc1 (a) positive logic (tc1s = 10) (b) negative logic (tc1s = 11) ? ? match detect 1 0 7 47 5 46 31 21 0 7 5 3 6 2 0 2 3 counter clear timer start 890 1 9 timer start counter clear count start count stop count start count start count stop count start
page 106 10. 16-bit timercounter 1 (tc1) 10.3 function TMP86FH12MG 10.3.5 pulse widt h measurement mode in the pulse width measurement mode, the up-counter starts counting by the input pulse triggering of the tc1 pin, and counts up at the edge of the internal clock. either the rising or falling edge of the internal clock is selected as the trigger edge in tc1cr< tc1s>. either the single- or double-e dge capture is selected as the trig- ger edge in tc1cr. ? when tc1cr is set to ?1? (single-edge capture) either high- or low-level input pulse width can be measured. to measure the high-level input pulse width, set the rising edge to tc1cr. to measure the low-level input pulse width, set the falling edge to tc1cr. when detecting the edge opposite to the trigger ed ge used to start countin g after the timer starts, the up-counter captures the up-counter value in to tc1drb and generates an inttc1 interrupt request. the up-counter is cleared at this time, a nd then restarts counting wh en detecting the trigger edge used to start counting. ? when tc1cr is set to ?0? (double-edge capture) the cycle starting with either the high- or low-going input pulse can be measured. to measure the cycle starting with the high-going pulse, set the ri sing edge to tc1cr. to measure the cycle starting with the low-going pulse, set the falling edge to tc1cr. when detecting the edge opposite to the trigger ed ge used to start countin g after the timer starts, the up-counter captures the up-counter value in to tc1drb and generates an inttc1 interrupt request. the up-counter continues counting up, a nd captures the up-counter value into tc1drb and generates an inttc1 interrupt request when detecting the trigger edge used to start counting. the up-counter is cleared at this time, and then continues counting. note 1: the captured value must be read from tc1drb until the next trigger edge is detected. if not read, the cap- tured value becomes a don?t care. it is recommended to us e a 16-bit access instruction to read the captured value from tc1drb. note 2: for the single-edge capture, the counter after capturing the value stops at ?1? until detecting the next edge. therefore, the second captured value is ?1? larger than the captured value i mmediately after counting starts. note 3: the first captured value after the timer starts may be read incorrectively, therefore, ignore the first captured value.
page 107 TMP86FH12MG example :duty measurem ent (resolution fc/2 7 [hz]) clr (inttc1sw). 0 ; inttc1 serv ice switch initial setting address set to convert inttc1sw at each inttc1 ld (tc1cr), 00000110b ; sets the tc1 mode and source clock di ; imf = = width hpulse tc1 pin inttc1 interrupt request inttc1sw
page 108 10. 16-bit timercounter 1 (tc1) 10.3 function TMP86FH12MG figure 10-6 pulse wi dth measurement mode tc1drb inttc1 interrupt request interrupt request tc1 pin input counter internal clock (mcap1 = "1") 23 n count start count start trigger (tc1s = "10") 1 321 4 0 n 0 capture n - 1 tc1drb inttc1 tc1 pin input counter internal clock (mcap1 = "0") 12 n count start count start (tc1s = "10") 321 4 0 n capture capture n + 1 m - 2 n + 3 n + 2 n + 1 m - 1 m0 m [application] high-or low-level pulse width measurement [application] (1) cycle/frequency measurement (2) duty measurement (a) single-edge capture (b) double-edge capture
page 109 TMP86FH12MG 10.3.6 programmable pulse generate (ppg) output mode in the programmable pulse generation (ppg) mode, an arbitrary duty pulse is generated by counting per- formed in the internal clock. to start the timer, tc1c r specifies either the edge of the input pulse to the tc1 pin or the command start. tc1cr specifies whether a duty pulse is produced continuously or not (one-shot pulse). ? when tc1cr is set to ?0? (continuous pulse generation) when a match between the up-counter and the tc1drb value is detected after the timer starts, the level of the ppg pin is inverted and an inttc1 interrupt request is generated. the up-counter contin- ues counting. when a match between the up-counter and the tc1dra value is detected, the level of the ppg pin is inverted and an inttc1 interrupt requ est is generated. the up-counter is cleared at this time, and then continues counting and pulse generation. when tc1s is cleared to ?00? during ppg output, the ppg pin retains the level immediately before the counter stops. ? when tc1cr is set to ?1? (one-shot pulse generation) when a match between the up-counter and the tc1drb value is detected after the timer starts, the level of the ppg pin is inverted and an inttc1 interrupt request is generated. the up-counter contin- ues counting. when a match between the up-counter and the tc1dra value is detected, the level of the ppg pin is inverted and an inttc1 interrupt re quest is generated. tc1cr is cleared to ?00? automatically at this time, and the timer stops. the pulse generated by ppg retains the same level as that when the timer stops. since the output level of the ppg pin can be set with tc1cr when the timer starts, a positive or neg- ative pulse can be generated. since the inverted level of the timer f/f1 output level is output to the ppg pin, specify tc1cr to ?0? to set the high level to the ppg pin, and ?1? to set the low level to the ppg pin. upon reset, the timer f/f1 is initialized to ?0?. note 1: to change tc1dra or tc1drb during a run of the ti mer, set a value sufficiently larger than the count value of the counter. setting a value smaller than the count value of the counter during a run of the timer may generate a pulse different from that specified. note 2: do not change tc1cr during a run of the ti mer. tc1cr can be set correctly only at initial- ization (after reset). when the timer stops during pp g, tc1cr can not be set correctly from this point onward if the ppg output has the level which is inverted of the level when the timer starts. (setting tc1cr specifies the timer f/f1 to the level inverted of the programmed value.) therefore, the timer f/f1 needs to be initialized to ensure an arbitrar y level of the ppg output. to initialize the timer f/f1, change tc1cr to the timer mode (it is not required to start the timer mode), and then set the ppg mode. set tc1cr at this time. note 3: in the ppg mode, the follow ing relationship must be satisfied. tc1dra > tc1drb note 4: set tc1drb after changing the mode of tc1m to the ppg mode.
page 110 10. 16-bit timercounter 1 (tc1) 10.3 function TMP86FH12MG figure 10-7 ppg output example :generating a pulse which is high-going for 800 s and low-going for 200 s (fc = 16 mhz) setting port ld (tc1cr), 10000111b ; sets the ppg mode, selects the source clock ldw (tc1dra), 007dh ; sets the cycle (1 ms example :after stopping ppg, setting the ppg pin to a high-level to restart ppg (fc = 16 mhz) setting port ld (tc1cr), 10000111b ; sets the ppg mode, selects the source clock ldw (tc1dra), 007dh ; sets the cycle (1 ms q r d ppg pin function output port output enable i/o port output latch shared with ppg output data output toggle set clear q tc1cr write to tc1cr internal reset match to tc1drb match to tc1dra tc1cr clear timer f/f1 inttc1 interrupt request
page 111 TMP86FH12MG figure 10-8 ppg mode timing chart inttc1 tc1dra internal clock counter tc1drb tc1dra ppg pin output 0 inttc1 interrupt request interrupt request 12 m01 2 n m01 n 2 n n + 1 n + 1 m (a) continuous pulse generation (tc1s = 01) tc1drb trigger count start timer start counter internal clock tc1 pin input ppg pin output 0 1m n n n + 1 m 0 (b) one-shot pulse generation (tc1s = 10) match detect note: m > n note: m > n [application] one-shot pulse output
page 112 10. 16-bit timercounter 1 (tc1) 10.3 function TMP86FH12MG
page 113 TMP86FH12MG 11. 8-bit timercounter (tc3, tc4) 11.1 configuration figure 11-1 8-bit timercouter 3, 4 8-bit up-counter decode en a y b s a b y c d e f g h s a y b s s a y b toggle q set clear 8-bit up-counter a b y c d e f g h s decode en toggle q set clear pwm mode pdo, ppg mode pdo mode pwm, ppg mode pwm mode pwm mode 16-bit mode 16-bit mode 16-bit mode 16-bit mode timer, event counter mode overflow overflow timer, event couter mode 16-bit mode clear clear fc/2 7 fc/2 5 fc/2 3 fc/2 fc fc/2 7 fc/2 5 fc/2 3 fc/2 fc pdo, pwm, ppg mode pdo, pwm mode 16-bit mode fc/2 11 or fs/2 3 fc/2 11 or fs/2 3 fs fs tc4cr tc3cr ttreg4 pwreg4 ttreg3 pwreg3 tc3 pin tc4 pin tc4s tc3s inttc3 interrupt request inttc4 interrupt request tff4 tff3 pdo 4/pwm 4/ ppg 4 pin pdo 3/pwm 3/ pin tc3ck tc4ck tc3m tc3s tff3 tc4m tc4s tff4 timer f/f4 timer f/f3
page 114 11. 8-bit timercounter (tc3, tc4) 11.1 configuration TMP86FH12MG 11.2 timercounter control the timercounter 3 is controlled by the timercounter 3 control register (tc3cr) and two 8-bit timer registers (ttreg3, pwreg3). note 1: do not change the timer register (t treg3) setting while the timer is running. note 2: do not change the timer register (pwreg3) setting in the operating mode except the 8-bit and 16-bit pwm modes while the timer is running. note 1: fc: high-frequency clock [hz] fs: low-frequency clock[hz] note 2: do not change the tc3m, tc3ck and tff3 settings while the timer is running. note 3: to stop the timer operation (tc3s= 1
page 115 TMP86FH12MG note 7: the timer register settings are limited depending on the timer operating mode. for the detailed descriptions, see table 11- 3. note 8: the operating clock fc in the slow or sleep mode can be used only as the high-frequency warm-up mode.
page 116 11. 8-bit timercounter (tc3, tc4) 11.1 configuration TMP86FH12MG the timercounter 4 is controlled by the timercounter 4 control register (tc4cr) and two 8-bit timer registers (ttreg4 and pwreg4). note 1: do not change the timer register (t treg4) setting while the timer is running. note 2: do not change the timer register (pwreg4) setting in the operating mode except the 8-bit and 16-bit pwm modes while the timer is running. note 1: fc: high-frequency clock [hz] fs: low-frequency clock [hz] note 2: do not change the tc4m, tc4ck and tff4 settings while the timer is running. note 3: to stop the timer operation (tc4s= 1
page 117 TMP86FH12MG note 6: to the timercounter in the 16-bit mode, select the so urce clock by programming tc3cr. set the timer start control and timer f/f control by prog ramming tc4s and tff4, respectively. note 7: the operating clock settings are limited depending on the timer operating mode. for the detailed descriptions, see table 11-1 and table 11-2. note 8: the timer register settings are limited depending on the timer operating mode. for the detailed descriptions, see table 11- 3. note 1: for 16-bit operations (16-bit timer/event counter, warm- up counter, 16-bit pwm and 16-bit ppg), set its source clock on lower bit (tc3ck). note 2: ??? ??? ?????? ??? ??????? ??? ?
page 118 11. 8-bit timercounter (tc3, tc4) 11.1 configuration TMP86FH12MG note: n = 3 to 4 table 11-3 constraints on register values being compared operating mode register value 8-bit timer/event counter 1
page 119 TMP86FH12MG 11.3 function the timercounter 3 and 4 have the 8-bit timer, 8-bit ev ent counter, 8-bit programmable divider output (pdo), 8- bit pulse width modulation (pwm) output modes. the time rcounter 3 and 4 (tc3, 4) are cascadable to form a 16- bit timer. the 16-bit timer has the operat ing modes such as the 16-bit timer, 16-bit event counter, warm-up counter, 16-bit pulse width modulation (pwm) output and 16-bit programmable pulse generation (ppg) modes. 11.3.1 8-bit timer mode (tc3 and 4) in the timer mode, the up-counter counts up using the internal clock. when a match between the up-counter and the timer register j (ttregj) value is detected, an inttcj interrupt is generated and the up-counter is cleared. after being cl eared, the up-counter restarts counting. note 1: in the timer mode, fix tcjcr to 0. if not fixed, the pdoj, pwmj and ppgj pins may output pulses. note 2: in the timer mode, do not change the ttregj setting while the timer is running. si nce ttregj is not in the shift register configuration in the timer mode, the new value programmed in ttregj is in effect immediately after the programming. therefore, if ttregi is changed while the timer is r unning, an expected operation may not be obtained. note 3: j = 3, 4 table 11-4 source clock for timercounter 3, 4 (internal clock) source clock resolution repeated cycle normal1/2, idle1/2 mode slow1/2, sleep1/2 mode fc = 16 mhz fs = 32.768 khz fc = 16 mhz fs = 32.768 khz dv7ck = 0 dv7ck = 1 fc/2 11 [hz] fs/2 3 [hz] fs/2 3 [hz] 128 example :setting the timer mode with source clock fc/2 7 hz and generating an interrupt 80 s later (timercounter4, fc = 16.0 mhz) ld (ttreg4), 0ah : sets the timer register (80
page 120 11. 8-bit timercounter (tc3, tc4) 11.1 configuration TMP86FH12MG figure 11-2 8-bit time r mode timing chart (tc4) 11.3.2 8-bit event counter mode (tc3, 4) in the 8-bit event counter mode, the up-counter counts up at the falling edge of the input pulse to the tcj pin. when a match between the up-counter and the ttregj value is detected, an inttcj interrupt is generated and the up-counter is cleared. after being cleared, the up-counter restarts counti ng at the falling edge of the input pulse to the tcj pin. two machine cycles are required for the low- or high-level pulse input to the tcj pin. therefore, a maximum freque ncy to be supplied is fc/2 4 hz in the normal1/2 or idle1/2 mode, and fs/2 4 hz in the slow1/2 or sleep1/2 mode. note 1: in the event counter mode, fix tcjcr to 0. if not fixed, the pdoj, pwmj and ppgj pins may output pulses. note 2: in the event counter mode, do not change the ttre gj setting while the timer is running. since ttregj is not in the shift register configuration in the event counter mode, the new value programmed in ttregj is in effect immediately after the programming. therefore, if ttregi is changed whil e the timer is running, an expected operation may not be obtained. note 3: j = 3, 4 figure 11-3 8-bit event co unter mode timing chart (tc4) 11.3.3 8-bit programmable divi der output (pdo) mode (tc3, 4) this mode is used to generate a pu lse with a 50% duty cycle from the pdoj pin. in the pdo mode, the up-counter counts up using the internal clock. when a match between the up-counter and the ttregj value is detected , the logic level output from the pdoj pin is switched to the opposite state and the up-counter is cleared. the inttcj interrupt request is generated at the time. the logic state opposite to the timer f/fj logic level is output from the pdoj pin. an arbitrary value can be set to the timer f/fj by tcjcr. upon reset, the timer f/fj value is initialized to 0. to use the programmable divider output, set the output latch of the i/o port to 1. 1 2 3 n-1 n 0 1 n-1 n 2 0 1 2 0 n ? internal source clock counter match detect counter clear match detect counter clear tc4cr ttreg4 inttc4 interrupt request 1 0 2 n-1 n 0 1 2 0 n ? counter match detect counter clear n-1 n 2 0 1 match detect counter clear tc4cr ttreg4 inttc4 interrupt request tc4 pin input
page 121 TMP86FH12MG note 1: in the programmable divider output mode, do not change the ttregj setting while the timer is running. since ttregj is not in the shift register configur ation in the programmable divider output mode, the new value programmed in ttregj is in effect immediately after programming. therefore, if ttregi is changed while the timer is running, an ex pected operation may not be obtained. note 2: when the timer is stopped during pdo output, the pdoj pin holds the output status when the timer is stopped. to change the output status, program tcjcr after the timer is stopped. do not change the tcjcr setting upon stopping of the timer. example: fixing the pdoj pin to the high level when the timercounter is stopped clr (tcjcr).3: stops the timer. clr (tcjcr).7: sets the pdoj pin to the high level. note 3: j = 3, 4 example :generating 1024 hz pulse using tc4 (fc = 16.0 mhz) setting port ld (ttreg4), 3dh : 1/1024
page 122 11. 8-bit timercounter (tc3, tc4) 11.1 configuration TMP86FH12MG figure 11-4 8-bit pdo mode timing chart (tc4) 12 0 n 0 n 0 n 0 n 0 1 2 2 1 2 1 2 3 1 0 n ? internal source clock counter match detect match detect match detect match detect held at the level when the timer is stopped set f/f write of "1" tc4cr tc4cr ttreg4 timer f/f4 pdo 4 pin inttc4 interrupt request
page 123 TMP86FH12MG 11.3.4 8-bit pulse width modulat ion (pwm) output mode (tc3, 4) this mode is used to generate a pulse-width modulated (pwm) signals with up to 8 bits of resolution. the up-counter counts up using the internal clock. when a match between the up-counter and the pwregj value is detected, the logic level output from the timer f/fj is switched to the opposite state. the counter continues counting. the logic level output from the timer f/fj is switched to the opposite state again by the up-co unter overflow, and the counter is cleared. the inttcj interrupt request is generated at this time. since the initial value can be set to the timer f/fj by tcjcr, positive and negative pulses can be gen- erated. upon reset, the tim er f/fj is cleared to 0. (the logic level output from the pwmj pin is the opposite to the timer f/fj logic level.) since pwregj in the pwm mode is se rially connected to the shift regist er, the value set to pwregj can be changed while the timer is running. the value set to pwregj during a run of the timer is shifted by the inttcj interrupt request and loaded into pwregj. while the timer is stopped, the value is shifted immedi- ately after the programming of pwre gj. if executing the read instruction to pwregj during pwm output, the value in the shift register is read, but not the valu e set in pwregj. therefore, after writing to pwregj, the reading data of pwregj is previo us value until inttcj is generated. for the pin used for pwm output, the output latch of the i/o port must be set to 1. note 1: in the pwm mode, program the timer register pw regj immediately after the inttcj interrupt request is generated (normally in the inttcj interrupt service r outine.) if the programming of pwregj and the inter- rupt request occur at the same time, an unstable value is shifted, that may result in generation of the pulse different from the programmed value until the next inttcj interrupt request is generated. note 2: when the timer is stopped during pwm output, the pwmj pin holds the output status when the timer is stopped. to change the output status, program tcjcr after the timer is stopped. do not change the tcjcr upon stopping of the timer. example: fixing the pwmj pin to the high level when the timercounter is stopped clr (tcjcr).3: stops the timer. clr (tcjcr).7: sets the pwmj pin to the high level. note 3: to enter the stop mode during pwm output, stop the timer and then enter the stop mode. if the stop mode is entered without stopping the timer when fc, fc/2 or fs is selected as the source clock, a pulse is out- put from the pwmj pin during the warm-up period time after exiting the stop mode. note 4: j = 3, 4 table 11-5 pwm output mode source clock resolution repeated cycle normal1/2, idle1/2 mode slow1/2, sleep1/2 mode fc = 16 mhz fs = 32.768 khz fc = 16 mhz fs = 32.768 khz dv7ck = 0 dv7ck = 1 fc/2 11 [hz] fs/2 3 [hz] fs/2 3 [hz] 128
page 124 11. 8-bit timercounter (tc3, tc4) 11.1 configuration TMP86FH12MG figure 11-5 8-bit pwm mode timing chart (tc4) 1 0 n n+1 ff 0 n n+1 ff 0 1 m m+1 ff 0 1 1 p n ? internal source clock counter write to pwreg4 write to pwreg4 m p m p n ? shift registar shift shift shift shift match detect match detect one cycle period match detect match detect n m p n tc4cr tc4cr pwreg4 timer f/f4 pwm 4 pin inttc4 interrupt request
page 125 TMP86FH12MG 11.3.5 16-bit timer mode (tc3 and 4) in the timer mode, the up-counter counts up using the internal clock. the timercounter 3 and 4 are cascad- able to form a 16-bit timer. when a match between the up-counter and the timer regi ster (ttreg3, ttreg4) valu e is detected after the timer is started by setting tc4cr to 1, an inttc4 interrupt is generated and the up-counter is cleared. after being cleared, the up-counter continues counting. pr ogram the upper byte and lower byte in this order in the timer register. (programming only the uppe r or lower byte should not be attempted.) note 1: in the timer mode, fix tcjcr to 0. if not fixed, the pdoj , pwmj , and ppgj pins may output a pulse. note 2: in the timer mode, do not change the ttregj setting while the timer is running. si nce ttregj is not in the shift register configuration in the timer mode, the new value programmed in ttregj is in effect immediately after programming of ttregj. therefore, if ttreg j is changed while the time r is running, an expected operation may not be obtained. note 3: j = 3, 4 figure 11-6 16-bit timer mode timing chart (tc3 and tc4) table 11-6 source clock for 16-bit timer mode source clock resolution repeated cycle normal1/2, idle1/2 mode slow1/2, sleep1/2 mode fc = 16 mhz fs = 32.768 khz fc = 16 mhz fs = 32.768 khz dv7ck = 0 dv7ck = 1 fc/2 11 fs/2 3 fs/2 3 128 example :setting the timer mode with source clock fc/2 7 hz, and generating an interrupt 300 ms later (fc = 16.0 mhz) ldw (ttreg3), 927ch : sets the timer register (300 ms 10 2 3 mn-1 mn 0 1 mn-1 mn 2 0 1 2 0 n? m? internal source clock counter match detect counter clear match detect counter clear tc4cr ttreg3 (lower byte) inttc4 interrupt request ttreg4 (upper byte)
page 126 11. 8-bit timercounter (tc3, tc4) 11.1 configuration TMP86FH12MG 11.3.6 16-bit event c ounter mode (tc3 and 4) 11.3.7 16-bit pulse width modulatio n (pwm) output mode (tc3 and 4) this mode is used to generate a pulse-width modulated (pwm) signals with up to 16 bits of resolution. the timercounter 3 and 4 are cascadable to form the 16-bit pwm signal generator. the counter counts up using the internal clock or external clock. when a match between the up-counter and the timer register (pwreg3, pwreg4) value is detected, the logic level output from the timer f/f4 is switched to the opposite state. the counter continues counting. the logic level output from the timer f/f4 is switched to the opposite state again by the counter overflow, and the counter is cleared. the inttc4 interrupt is generated at this time. two machine cycles are required for the high- or low-level pulse input to the tc3 pin. therefore, a maxi- mum frequency to be supplied is fc/2 4 hz in the normal1 or idle1 mode, and fs/2 4 to in the slow1/2 or sleep1/2 mode. since the initial value can be set to the timer f/f4 by tc4cr, positive and negative pulses can be generated. upon reset, the timer f/f4 is cleared to 0. (the logic level output from the pwm 4 pin is the opposite to the timer f/f4 logic level.) since pwreg4 and 3 in the pwm mode are serially connected to the shift register, the values set to pwreg4 and 3 can be changed while the timer is runni ng. the values set to pwreg4 and 3 during a run of the timer are shifted by the inttcj interrupt request and loaded into pwreg4 and 3. while the timer is stopped, the values are shifted i mmediately after the programming of pwreg4 and 3. set the lower byte (pwreg3) and upper byte (pwreg3) in this order to program pwreg4 and 3. (programming only the lower or upper byte of the register should not be attempted.) if executing the read instruction to pwreg4 and 3 during pwm output, the values set in the shift register is read, but not the values set in pwreg4 and 3. therefore, after writing to the pwreg4 and 3, reading data of pwreg4 and 3 is previous value until inttc4 is generated. for the pin used for pwm output, the output latch of the i/o port must be set to 1. note 1: in the pwm mode, program the timer register pwreg4 and 3 immediately after the inttc4 interrupt request is generated (normally in the inttc4 interrupt service routine.) if the programming of pwregj and the interrupt request occur at the same time, an unstable value is shifted, that may result in generation of pulse different from the programmed value until the next inttc4 interrupt request is generated. note 2: when the timer is stopped during pwm output, the pwm 4 pin holds the output status when the timer is stopped. to change the output status, program tc4cr after the timer is stopped. do not program tc4cr upon stopping of the timer. example: fixing the pwm 4 pin to the high level when the timercounter is stopped in the event counter mode, the up-counter counts up at the falling edge to the tc3 pin. the timercounter 3 and 4 are cascadable to fo rm a 16-bit event counter. when a match between the up-counter and the timer register (ttreg3, ttreg4) value is detected after the timer is started by setting tc4cr to 1, an inttc4 interrupt is generated and the up-counter is cleared. after being cleared, the up-counter rest arts counting at the falling edge of the input pulse to the tc3 pin. two machine cycles are required for the low- or high-level pulse input to the tc3 pin. therefore, a maximum freque ncy to be supplied is fc/2 4 hz in the normal1 or idle1 mode, and fs/2 4 in the slow1/2 or sleep1/2 mode. program the lower by te (ttreg3), and upper byte (ttreg4) in this order in the timer register. (programming only the upper or lower byte should not be attempted.) note 1: note 2: note 3: in the event counter mode, fix tcjcr to 0. if not fixed, the pdoj, pwmj and ppgj pins may output pulses. in the event counter mode, do not change the ttregj setti ng while the timer is running. since ttregj is not in the shift register configuration in the event counter mode, the new value programmed in ttregj is in effect imme- diately after the programming. therefore, if ttregj is changed while the timer is running, an expected operation may not be obtained. j = 3, 4
page 127 TMP86FH12MG clr (tc4cr).3: stops the timer. clr (tc4cr).7 : sets the pwm 4 pin to the high level. note 3: to enter the stop mode, stop the timer and then enter the stop mode. if the stop mode is entered with- out stopping of the timer when fc, fc/2 or fs is select ed as the source clock, a pulse is output from the pwm 4 pin during the warm-up period time after exiting the stop mode. table 11-7 16-bit pwm output mode source clock resolution repeated cycle normal1/2, idle1/2 mode slow1/2, sleep1/2 mode fc = 16 mhz fs = 32.768 khz fc = 16 mhz fs = 32.768 khz dv7ck = 0 dv7ck = 1 fc/2 11 fs/2 3 [hz] fs/2 3 [hz] 128 example :generating a pulse with 1-ms high-level width and a period of 32.768 ms (fc = 16.0 mhz) setting ports ldw (pwreg3), 07d0h : sets the pulse width. ld (tc3cr), 33h : sets the operating clock to fc/2 3 , and 16-bit pwm output mode (lower byte). ld (tc4cr), 056h : sets tff4 to the initial value 0, and 16-bit pwm signal generation mode (upper byte). ld (tc4cr), 05eh : starts the timer.
page 128 11. 8-bit timercounter (tc3, tc4) 11.1 configuration TMP86FH12MG figure 11-7 16-bit pwm mode timing chart (tc3 and tc4) 1 0 an an+1 ffff 0 an an+1 ffff 0 1 bm bm+1 ffff 0 bm cp b c 1 1 cp n a an ? ? ? internal source clock 16-bit shift register shift shift shift shift counter match detect match detect one cycle period match detect match detect an bm cp an m p tc4cr tc4cr pwreg3 (lower byte) timer f/f4 pwm 4 pin inttc4 interrupt request pwreg4 (upper byte) write to pwreg4 write to pwreg4 write to pwreg3 write to pwreg3
page 129 TMP86FH12MG 11.3.8 16-bit programmable pulse generate (ppg) ou tput mode (tc3 and 4) this mode is used to generate pulses with up to 16- bits of resolution. the timer counter 3 and 4 are cascad- able to enter the 16-bit ppg mode. the counter counts up using the inte rnal clock or external clock. when a match between the up-counter and the timer register (pwreg3, pwreg4 ) value is detected, the logic level output from the timer f/f4 is switched to the opposite state. the counter continues counting. the logic level output from the timer f/f4 is switched to the opposite state again when a match betw een the up-counter and th e timer register (ttreg3, ttreg4) value is detected, and the counter is cleared. the inttc4 interrupt is generated at this time. since the initial value can be set to the timer f/f4 by tc4cr, positive and negative pulses can be generated. upon reset, the timer f/f4 is cleared to 0. (the logic level output from the ppg 4 pin is the opposite to the timer f/f4.) set the lower byte and upper byte in this order to program the timer register. (ttreg3 ttreg4, pwreg3 pwreg4) (programming only the upper or lower byte should not be attempted.) for ppg output, set the output latch of the i/o port to 1. note 1: in the ppg mode, do not change the pwregi and ttregi settings while the timer is running. since pwregi and ttregi are not in the shift register c onfiguration in the ppg mode, the new values pro- grammed in pwregi and ttregi are in effect immediately after progra mming pwregi and ttregi. therefore, if pwregi and ttregi are changed whil e the timer is running, an expected operation may not be obtained. note 2: when the timer is stopped during ppg output, the ppg 4 pin holds the output status when the timer is stopped. to change the output status, program tc4cr after the timer is stopped. do not change tc4cr upon stopping of the timer. example: fixing the ppg 4 pin to the high level when the timercounter is stopped clr (tc4cr).3: stops the timer clr (tc4cr).7: sets the ppg 4 pin to the high level note 3: i = 3, 4 two machine cycles are required for the high- or low- level pulse input to the tc3 pin. therefore, a maxi- mum frequency to be supplied is fc/2 4 hz in the normal1 or idle1 mode, and fc/2 4 to in the slow1/2 or sleep1/2 mode. example :generating a pulse with 1-ms high-level width and a period of 16.385 ms (fc = 16.0 mhz) setting ports ldw (pwreg3), 07d0h : sets the pulse width. ldw (ttreg3), 8002h : sets the cycle period. ld (tc3cr), 33h : sets the operating clock to fc/2 3 , and16-bit ppg mode (lower byte). ld (tc4cr), 057h : sets tff4 to the initial value 0, and 16-bit ppg mode (upper byte). ld (tc4cr), 05fh : starts the timer.
page 130 11. 8-bit timercounter (tc3, tc4) 11.1 configuration TMP86FH12MG figure 11-8 16-bit ppg mode timing chart (tc3 and tc40) 1 0 mn mn+1 qr-1 mn qr-1 1 mn mn+1 mn+1 0 qr 0 qr 1 0 internal source clock counter write of "0" match detect match detect match detect mn mn mn match detect match detect ? n m ? ? r q ? held at the level when the timer stops f/f clear tc4cr tc4cr pwreg3 (lower byte) timer f/f4 ppg 4 pin inttc4 interrupt request pwreg4 (upper byte) ttreg3 (lower byte) ttreg4 (upper byte)
page 131 TMP86FH12MG 11.3.9 warm-up counter mode in this mode, the warm-up period time is obtained to assure oscillation stability when the system clocking is switched between the high-frequency and low-frequency. the timer counter 3 and 4 are cascadable to form a 16-bit timercouter. the warm-up counter mode has two types of mode; switching from the high-frequency to low-frequency, and vice-versa. note 1: in the warm-up counter mode, fi x tcicr to 0. if not fixed, the pdoi , pwmi and ppgi pins may output pulses. note 2: in the warm-up counter mode, only upper 8 bits of the timer register ttreg4 and 3 are used for match detection and lower 8 bits are not used. note 3: i = 3, 4 11.3.9.1 low-frequency warm-up counter mode (normal1 in this mode, the warm-up period time from a stop of the low-frequency clock fs to oscillation stability is obtained. before starting the timer, set syscr2 to 1 to oscillate the low-frequency clock. when a match between the up-counter and the timer regist er (ttreg4, 3) value is detected after the timer is started by setting tc4cr to 1, the counter is cleared by generating the inttc4 interrupt request. after stopping the timer in the inttc4 inte rrupt service routine, set syscr2 to 1 to switch the system clock fr om the high-frequency to low-frequenc y, and then clear of syscr2 to 0 to stop the high-frequency clock. table 11-8 setting time of low-frequency warm-up counter mode (fs = 32.768 khz) maximum time setting (ttreg4, 3 = 0100h) maximum time setting (ttreg4, 3 = ff00h) 7.81 ms 1.99 s example :after check ing low-frequency clock oscillation stability with tc4 and 3, switching to the slow1 mode set (syscr2).6 : syscr2
page 132 11. 8-bit timercounter (tc3, tc4) 11.1 configuration TMP86FH12MG 11.3.9.2 high-frequency warm-up counter mode (slow1 in this mode, the warm-up period time from a stop of the high-frequency clock fc to the oscillation sta- bility is obtained. before starting the timer, set sy scr2 to 1 to oscillat e the high-frequency clock. when a match between the up-counter and the timer regist er (ttreg4, 3) value is detected after the timer is started by setting tc4cr to 1, the counter is cleared by generating the inttc4 interrupt request. after stopping the timer in the inttc4 inte rrupt service routine, clear syscr2 to 0 to switch the system clock from the low-frequency to high-frequency, and then syscr2 to 0 to stop the low-frequency clock. table 11-9 setting time in high-frequency warm-up counter mode minimum time (ttreg4, 3 = 0100h) maximum time (ttreg4, 3 = ff00h) 16 example :after check ing high-frequency clock oscillation stability with tc4 and 3, switching to the normal1 mode set (syscr2).7 : syscr2
page 133 TMP86FH12MG 12. synchronous serial interface (sio) the TMP86FH12MG has a clocked-synchronous 8-bit serial interface. serial interface has an 8-byte transmit and receive data buffer that can automatically and continuously transfer up to 64 bits of data. serial interface is connected to outside peripherl devices via so, si, sck port. 12.1 configuration figure 12-1 serial interface sio control / status register serial clock shift clock shift register 3 2 1 0 7 6 5 4 transmit and receive data buffer (8 bytes in dbr) control circuit cpu serial data output serial data input 8-bit transfer 4-bit transfer serial clock i/o buffer control circuit so si sck siocr2 siocr1 siosr intsio interrupt request
page 134 12. synchronous serial interface (sio) 12.2 control TMP86FH12MG 12.2 control the serial interface is controlled by sio control registers (s iocr1/siocr2). the serial interface status can be determined by reading sio status register (siosr). the transmit and receive data buffer is controlled by the siocr2. th e data buffer is assigned to address 0f80h to 0f87h for sio in the dbr area, and can continuously transfer up to 8 words (bytes or nibbles) at one time. when the specified number of words has b een transferred, a buffer empty (in th e transmit mode) or a buffer full (in the receive mode or tran smit/receive mode) interrupt (intsio) is generated. when the internal clock is used as the serial clock in the 8-bit receive mode and the 8-bit transmit/receive mode, a fixed interval wait can be applied to the serial clock fo r each word transferred. four different wait times can be selected with siocr2. note 1: fc; high-frequency clock [hz], fs; low-frequency clock [hz] note 2: set sios to "0" and sioinh to "1" when setting the transfer mode or serial clock. note 3: siocr1 is write-only register, whic h cannot access any of in read-modify-wri te instruction such as bit operate, etc. sio control register 1 siocr176543210 (0031h) sios sioinh siom sck (initial value: 0000 0000) sios indicate transfer start / stop 0: stop write only 1: start sioinh continue / abort transfer 0: continuously transfer 1: abort transfer (automatically cleared after abort) siom transfer mode select 000: 8-bit transmit mode 010: 4-bit transmit mode 100: 8-bit transmit / receive mode 101: 8-bit receive mode 110: 4-bit receive mode except the above: reserved sck serial clock select normal1/2, idle1/2 mode slow1/2 sleep1/2 mode write only dv7ck = 0 dv7ck = 1 000 fc/2 13 fs/2 5 fs/2 5 001 fc/2 8 fc/2 8 - 010 fc/2 7 fc/2 7 - 011 fc/2 6 fc/2 6 - 100 fc/2 5 fc/2 5 - 101 fc/2 4 fc/2 4 - 110 reserved 111 external clock ( input from sck pin ) sio control register 2 siocr276543210 (0032h) wait buf (initial value: ***0 0000)
page 135 TMP86FH12MG note 1: the lower 4 bits of each buffer are used during 4-bit tr ansfers. zeros (0) are stored to the upper 4bits when receiving. note 2: transmitting starts at the lowest address. received data are also stored starting from the lowest address to the highest address. ( the first buffer address transmitted is 0f80h ). note 3: the value to be loaded to buf is held after transfer is completed. note 4: siocr2 must be set when the serial interface is stopped (siof = 0). note 5: *: don't care note 6: siocr2 is write-only register, whic h cannot access any of in read-modify-wri te instruction such as bit operate, etc. note 1: t f ; frame time, t d ; data transfer time note 2: after sios is cleared to "0", siof is cleared to "0" at the termination of transfer or the setting of sioinh to "1". figure 12-2 fr ame time (t f ) and data transfer time (t d ) 12.3 serial clock 12.3.1 clock source internal clock or external clock for the source clock is selected by siocr1. wait wait control always sets "00" except 8-bit transmit / receive mode. write only 00: t f = t d (non wait) 01: t f = 2t d (wait) 10: t f = 4t d (wait) 11: t f = 8t d (wait) buf number of transfer words (buffer address in use) 000: 1 word transfer 0f80h 001: 2 words transfer 0f80h ~ 0f81h 010: 3 words transfer 0f80h ~ 0f82h 011: 4 words transfer 0f80h ~ 0f83h 100: 5 words transfer 0f80h ~ 0f84h 101: 6 words transfer 0f80h ~ 0f85h 110: 7 words transfer 0f80h ~ 0f86h 111: 8 words transfer 0f80h ~ 0f87h sio status register siosr76543210 (0032h) siof sef siof serial transfer operating status moni- tor 0: 1: transfer terminated transfer in process read only sef shift operating status monitor 0: 1: shift operation terminated shift operation in process td tf (output) s ck output
page 136 12. synchronous serial interface (sio) 12.3 serial clock TMP86FH12MG 12.3.1.1 internal clock any of six frequencies can be selected. the serial clock is output to the outside on the sck pin. the sck pin goes high when transfer starts. when data writing (in the transmit mo de) or reading (in the receive mode or the transmit/receive mode) cannot keep up with the serial clock rate, there is a wa it function that automatically stops the serial clock and holds the next shift operation until the read/write processing is completed. note: 1 kbit = 1024 bit (fc = 16 mhz, fs = 32.768 khz) figure 12-3 automatic wait fu nction (at 4-bit transmit mode) 12.3.1.2 external clock an external clock connected to the sck pin is used as the serial clock. in this case, output latch of this port should be set to "1". to ensure shifting, a pulse width of at least 4 machine cycles is required. this pulse is needed for the shift operatio n to execute certainly. actually, there is necessary processing time for interrupting, writing, and reading. the minimum pulse is determined by setting the mode and the pro- gram. therfore, maximum transfer frequenc y will be 488.3k bit/sec (at fc=16mhz). figure 12-4 external clock pulse width table 12-1 serial clock rate normal1/2, idle1/2 mode slow1/2, sleep1/2 mode dv7ck = 0 dv7ck = 1 sck clock baud rate clock baud rate clock baud rate 000 fc/2 13 1.91 kbps fs/2 5 1024 bps fs/2 5 1024 bps 001 fc/2 8 61.04 kbps fc/2 8 61.04 kbps - - 010 fc/2 7 122.07 kbps fc/2 7 122.07 kbps - - 011 fc/2 6 244.14 kbps fc/2 6 244.14 kbps - - 100 fc/2 5 488.28 kbps fc/2 5 488.28 kbps - - 101 fc/2 4 976.56 kbps fc/2 4 976.56 kbps - - 110 - - - - - - 111 external external external external external external a 1 a 2 b 0 b 1 b 2 b 3 c 0 c 1 a 3 a c b a 0 pin (output) pin (output) written transmit data a utomat i ca ll y wait function sck so t sckl t sckh tcyc = 4/fc (in the normal1/2, idle1/2 modes) 4/fs (in the slow1/2, sleep1/2 modes) t sckl , t sckh > 4tcyc sck pin (output)
page 137 TMP86FH12MG 12.3.2 shift edge the leading edge is used to transmit, a nd the trailing edge is used to receive. 12.3.2.1 leading edge transmitted data are shifted on the leading edge of the serial clock (falling edge of the sck pin input/ output). 12.3.2.2 trailing edge received data are shifted on the trailing edge of the serial clock (rising edge of the sck pin input/out- put). figure 12-5 shift edge 12.4 number of bits to transfer either 4-bit or 8-bit serial transfer can be selected. when 4-bit serial transfer is selected, only the lower 4 bits of the transmit/receive data buffer register are used. the upper 4 bits are cleared to ?0? when receiving. the data is transferred in sequence star ting at the least significant bit (lsb). 12.5 number of words to transfer up to 8 words consisting of 4 bits of data (4-bit serial tran sfer) or 8 bits (8-bit serial tr ansfer) of data can be trans- ferred continuously. the number of words to be transferred can be selected by siocr2. an intsio interrupt is generated when the specified number of words has been transferred. if the number of words is to be changed during transfer , the serial interface must be stopped before making the ch ange. the number of words can be changed during automatic-wa it operation of an internal clock. in this case, the serial interface is not required to be stopped. bit 1 bit 2 bit 3 * 321 3210 ** 32 *** 3 bit 0 shift register shift register bit 1 bit 0 bit 2 bit 3 0 *** **** 210 * 10 ** 3210 (a) leading edge (b) trailing edge * ; don?t care so pin si pin sck pin sck pin
page 138 12. synchronous serial interface (sio) 12.6 transfer mode TMP86FH12MG figure 12-6 number of words to transfer (example: 1word = 4bit) 12.6 transfer mode siocr1 is used to select the tr ansmit, receive, or tr ansmit/receive mode. 12.6.1 4-bit and 8-bit transfer modes in these modes, firstly set the sio control register to the transmit mode, and then write first transmit data (number of transfer words to be transfer red) to the data buffer registers (dbr). after the data are written, the transmission is star ted by setting siocr1 to ?1?. the data are then output sequentially to the so pin in synchronous with th e serial clock, starting with the least significant bit (lsb). as soon as the lsb has been output, the data are transferred from the data buffer register to the shift register. when the final data bit has been transferred a nd the data buffer register is empty, an intsio (buffer empty) interrupt is generated to request the next transmitted data. when the internal clock is used, the serial clock will stop and an automatic-wait will be initiated if the next transmitted data are not loaded to the data buffer regist er by the time the number of data words specified with the siocr2 has been transmitted . writing even one word of data can cels the automatic- wait; therefore, when transmitting two or more words, always write the ne xt word before transmission of the previous word is completed. note:automatic waits are also canceled by writing to a dbr not being used as a transmit data buffer register; there- fore, during sio do not use such dbr for other applications. for example, when 3 words are transmitted, do not use the dbr of the remained 5 words. when an external clock is used, the data must be writte n to the data buffer register before shifting next data. thus, the transfer speed is determin ed by the maximum delay time from the generation of the interrupt request to writing of the data to the data buffer register by the interrupt service program. the transmission is ended by clearing siocr1 to ?0? or setting siocr1 to ?1? in buffer empty interrupt service program. a 1 a 2 a 3 a 0 a 1 a 2 a 3 b 0 b 1 b 2 b 3 c 0 c 1 c 2 c 3 a 0 a 1 a 0 a 2 a 3 b 0 b 1 b 2 b 3 c 0 c 1 c 2 c 3 (a) 1 word transmit (b) 3 words transmit (c) 3 words receive so pin intsio interrupt intsio interrupt intsio interrupt so pin si pin sck pin sck pin sck pin
page 139 TMP86FH12MG siocr1 is cleared, the operation will end after all bits of words are transmitted. that the transmission has ended can be determined from the status of siosr becau se siosr is cleared to ?0? when a transfer is completed. when siocr1 is set, the transmission is immediately ended and siosr is cleared to ?0?. when an external clock is used, it is also necessary to clear siocr1 to ?0? before shifting the next data; if siocr1 is not cleared before shift out, dummy data will be transmitted and the operation will end. if it is necessary to change the number of word s, siocr1 should be cleared to ?0?, then siocr2 must be rewritten after confirming that siosr has been cleared to ?0?. figure 12-7 transfer m ode (example: 8bit, 1word tr ansfer, internal clock) figure 12-8 transfer mode (example: 8b it, 1word transfer , external clock) a 1 a 2 a 3 a 4 a 5 a 6 a 7 b 0 b 1 b 2 b 3 b 4 b 5 b 6 b 7 a 0 dbr b a clear sios write (a) write (b) sck pin (output) so pin intsio interrupt siocr1 siosr siosr siosr a 1 a 2 a 3 a 4 a 5 a 6 a 7 b 0 b 1 b 2 b 3 b 4 b 5 b 6 b 7 a 0 dbr b a clear sios write (a) write (b) sck pin (input) so pin intsio interrupt siocr1 siosr siosr
page 140 12. synchronous serial interface (sio) 12.6 transfer mode TMP86FH12MG figure 12-9 transmiiied data ho ld time at end of transfer 12.6.2 4-bit and 8- bit receive modes after setting the control registers to the receive mode , set siocr1 to ?1? to enable receiving. the data are then transferred to the shift register via the si pin in synchronous with the serial clock. when one word of data has been received, it is tran sferred from the shift register to the data buffer register (dbr). when the number of words specified w ith the siocr2 has been received, an intsio (buffer full) interrupt is generated to request that these data be read out. the da ta are then read from the data buffer registers by the interrupt service program. when the internal clock is used, and the previous data are not read from the data buffer register before the next data are received, the serial cloc k will stop and an automatic-wait will be initiated until the data are read. a wait will not be initiated if even one data word has been read. note:waits are also canceled by reading a dbr not being used as a received data buffer register is read; therefore, during sio do not use such dbr for other applications. when an external clock is used, the shift operation is synchronized with the extern al clock; therefore, the previous data are read before the next data are transferred to the data buffer register. if the previous data have not been read, the next data will not be transferred to th e data buffer register and th e receiving of any more data will be canceled. when an external clock is used, th e maximum transfer speed is determined by the delay between the time when the interrupt request is gene rated and when the data received have been read. the receiving is ended by clearing si ocr1 to ?0? or setting sio cr1 to ?1? in buffer full interrupt service program. when siocr1 is cleared, th e current data are transferred to the buffer. after siocr1 cleared, the receiving is ended at the ti me that the final bit of the data has been received. that the receiving has ended can be determined from the st atus of siosr. siosr is cleared to ?0? when the receiv- ing is ended. after confirmed the r eceiving termination, the final receiving data is read. when siocr1 is set, the receiving is immediately ended and si osr is cleared to ?0 ?. (the received data is ignored, and it is not required to be read out.) if it is necessary to change the number of words in external clock operation, siocr1 should be cleared to ?0? then siocr2 mu st be rewritten after confirming th at siosr ha s been cleared to ?0?. if it is necessary to change the number of words in internal clock, during automatic-wait operation which occurs after completion of data recei ving, siocr2 must be rewritten before the received data is read out. note:the buffer contents are lost when the transfer mode is switched. if it should become necessary to switch the transfer mode, end receiving by cl earing siocr1 to ?0?, read the last data and then switch the trans- fer mode. msb of last word t sodh = min 3.5/fc [s] ( in the normal1/2, idle1/2 modes) t sodh = min 3.5/fs [s] (in the slow1/2, sleep1/2 modes) sck pin so pin siosr
page 141 TMP86FH12MG figure 12-10 receive mode (example: 8b it, 1word transfer, internal clock) 12.6.3 8-bit trans fer / receive mode after setting the sio control register to the 8-bit transmit/recei ve mode, write the data to be transmitted first to the data buffer registers (dbr). after that, enable the transmit/receive by sett ing siocr1 to ?1?. when transmitting, the data are output from the so pin at leading edges of the serial clock. when receiving, the data are input to the si pin at th e trailing edges of the serial clock. wh en the all receive is enabled, 8-bit data are transferred from th e shift register to the data buffer regist er. an intsio interrupt is generated when the number of data words specified with the siocr2 has been transferred. usually, read the receive data from the buffer register in the interrupt service. the data buffer register is used for both transmitting and receiving; therefore, always write the data to be transmitted af ter reading the all received data. when the internal clock is used, a wait is initiated until the received data are read and the next transfer data are written. a wait will not be initiated if ev en one transfer data word has been written. when an external clock is used, the shift operation is synchronized with the external clock; therefore, it is necessary to read the received data and write the data to be transmitted next before starting the next shift oper- ation. when an external clock is us ed, the transfer speed is determined by the maximum delay between genera- tion of an interrupt request and the received data are read and the data to be transmitted next are written. the transmit/receive operatio n is ended by clearing siocr1 to ?0? or setting siocr1 to ?1? in intsio interrupt service program. when siocr1 is cleared, the current data ar e transferred to the buff er. after siocr1 cleared, the transmitting/ receiving is ended at the time that the fi nal bit of the data has been transmitted. that the transmitting/ receiving has ended can be determined from the status of siosr. siosr is cleared to ?0? when the transmitting/recei ving is ended. when siocr1 is set, the transmit/receive operation is immediately ended and siosr is cleared to ?0?. if it is necessary to change the number of words in external clock operation, siocr1 should be cleared to ?0?, then sio cr2 must be rewritten after confirmi ng that siosr has been cleared to ?0?. if it is necessary to change the number of words in internal clock, during automatic-wait operation which occurs after completion of transmit/receive operation, siocr2 must be rewritten before reading and writing of the receive/transmit data. a 1 a 0 a 2 a 3 a 4 a 5 a 6 a 7 b 0 b 1 b 2 b 3 b 4 b 5 b 6 b 7 dbr b a clear sios read out read out sck pin (output) si pin intsio interrupt siocr1 siosr siosr
page 142 12. synchronous serial interface (sio) 12.6 transfer mode TMP86FH12MG note:the buffer contents are lost when the transfer mode is switched. if it should become necessary to switch the transfer mode, end receiving by cl earing siocr1 to ?0?, read the last data and then switch the trans- fer mode. figure 12-11 transfer / receive mode (examp le: 8bit, 1word transfe r, internal clock) figure 12-12 transmitted data hold ti me at end of tr ansfer / receive a 1 a 0 a 2 a 3 a 4 a 5 a 6 a 7 b 0 b 1 b 2 b 3 b 4 b 5 b 6 b 7 c 1 c 0 c 2 c 3 c 4 c 5 c b c 6 c 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 clear sios dbr d a read out (c) write (a) read out (d) write (b) sck pin (output) so pin intsio interrupt siocr1 siosr siosr si pin bit 7 of last word bit 6 t sodh = min 4/fc [s] ( in the normal1/2, idle1/2 modes) t sodh = min 4/fs [s] (in the slow1/2, sleep1/2 modes) sck pin so pin siosr
page 143 TMP86FH12MG 13. asynchronous serial interface (uart ) 13.1 configuration figure 13-1 uart (asynch ronous serial interface) counter y a b c s s a b c d y e f g h uart status register uart control register 2 uart control register 1 transmit data buffer receive data buffer fc/13 fc/26 fc/52 fc/104 fc/208 fc/416 fc/96 stop bit parity bit fc/2 6 fc/2 7 fc/2 8 baud rate generator transmit/receive clock 2 4 3 2 2 2 noise rejection circuit m p x transmit control circuit shift register shift register receive control circuit mpx: multiplexer uartcr1 tdbuf rdbuf inttxd intrxd uartsr uartcr2 rxd txd inttc3
page 144 13. asynchronous serial interface (uart ) 13.2 control TMP86FH12MG 13.2 control uart is controlled by the uart control registers (uartcr1, uartcr2). the operating status can be moni- tored using the uart status register (uartsr). note 1: when operations are disabled by se tting txe and rxe bit to ?0?, the setting becomes valid when data transmit or receive complete. when the transmit data is stored in the transmit data buffer, the data are not transmitted. even if data transmit is enabled, until new data are written to the transmit data buffer, the current data are not transmitted. note 2: the transmit clock and the parity are common to transmit and receive. note 3: uartcr1 and uartcr1 should be set to ?0? before uartcr1 is changed. note: when uartcr2 = ?01?, pulses longer than 96/fc [s] are always regarded as signals; when uartcr2 = ?10?, longer than 192/fc [s]; and when uart cr2 = ?11?, longer than 384/fc [s]. uart control register1 uartcr1 (0021h) 76543210 txe rxe stbt even pe brg (initial value: 0000 0000) txe transfer operation 0: 1: disable enable write only rxe receive operation 0: 1: disable enable stbt transmit stop bit length 0: 1: 1 bit 2 bits even even-numbered parity 0: 1: odd-numbered parity even-numbered parity pe parity addition 0: 1: no parity parity brg transmit clock select 000: 001: 010: 011: 100: 101: 110: 111: fc/13 [hz] fc/26 fc/52 fc/104 fc/208 fc/416 tc3 ( input inttc3) fc/96 uart control register2 uartcr2 (0022h) 7654321 0 rxdnc stopbr (initial value: **** *000) rxdnc selection of rxd input noise rejectio time 00: 01: 10: 11: no noise rejection (hysteresis input) rejects pulses shorter than 31/fc [s] as noise rejects pulses shorter than 63/fc [s] as noise rejects pulses shorter than 127/fc [s] as noise write only stopbr receive stop bit length 0: 1: 1 bit 2 bits
page 145 TMP86FH12MG note: when an inttxd is generated, tbep flag is set to "1" automatically. uart status register uartsr (0021h) 76543210 perr ferr oerr rbfl tend tbep (initial value: 0000 11**) perr parity error flag 0: 1: no parity error parity error read only ferr framing error flag 0: 1: no framing error framing error oerr overrun error flag 0: 1: no overrun error overrun error rbfl receive data buffer full flag 0: 1: receive data buffer empty receive data buffer full tend transmit end flag 0: 1: on transmitting transmit end tbep transmit data buffer empty flag 0: 1: transmit data buffer full (transmit data writing is finished) transmit data buffer empty uart receive data buffer rdbuf (0f89h) 76543210read only (initial value: 0000 0000) uart transmit data buffer tdbuf (0f89h) 76543210write only (initial value: 0000 0000)
page 146 13. asynchronous serial interface (uart ) 13.3 transfer data format TMP86FH12MG 13.3 transfer data format in uart, an one-bit start bit (low level), stop bit (bit length selectable at high level, by uartcr1), and parity (select parity in uartcr1

; even- or odd-number ed parity by uartcr1) are added to the transfer data. the transfer data formats are shown as follows. figure 13-2 tran sfer data format figure 13-3 caution on c hanging transfer data format note: in order to switch the transfer data format, perfor m transmit operations in the above figure 13-3 sequence except for the initial setting. start bit 0 bit 1 bit 6 bit 7 stop 1 start bit 0 bit 1 bit 6 bit 7 stop 1 stop 2 start bit 0 bit 1 bit 6 bit 7 parity stop 1 start bit 0 bit 1 bit 6 bit 7 parity stop 1 stop 2 pe 0 0 1 1 stbt frame length 0 1 123 89101112 0 1 without parity / 1 stop bit with parity / 1 stop bit without parity / 2 stop bit with parity / 2 stop bit
page 147 TMP86FH12MG 13.4 transfer rate the baud rate of uart is set of uartcr1. th e example of the baud rate are shown as follows. when tc3 is used as the uart transfer rate (when uartcr1 = ?110?), the tr ansfer clock and transfer rate are determined as follows: transfer clock [hz] = tc3 source clock [hz] / ttreg3 setting value transfer rate [baud] = transfer clock [hz] / 16 13.5 data sampling method the uart receiver keeps sampling input using the cloc k selected by uartcr1 until a start bit is detected in rxd pin input. rt clock star ts detecting ?l? level of the rxd pin. once a start bit is detected, the start bit, data bits, stop bi t(s), and parity bit are sampled at three times of rt7, rt8, and rt9 during one receiver clock interval (rt clock). (rt0 is the position where the bit supposedly starts.) bit is determined according to majority rule (the data are the same twice or more out of three samplings). figure 13-4 data sampling method table 13-1 transfer rate (example) brg source clock 16 mhz 8 mhz 4 mhz 000 76800 [baud] 38400 [baud] 19200 [baud] 001 38400 19200 9600 010 19200 9600 4800 011 9600 4800 2400 100 4800 2400 1200 101 2400 1200 600 rt0 1 2 3 4 5 6 7 8 9101112131415 01234567891011 bit 0 start bit bit 0 start bit (a) without noise rejection circuit rt clock internal receive data rt0 1 2 3 4 5 6 7 8 9101112131415 01234567891011 bit 0 start bit bit 0 start bit rt clock internal receive data (b) with noise rejection circuit rxd pin rxd pin
page 148 13. asynchronous serial interface (uart ) 13.6 stop bit length TMP86FH12MG 13.6 stop bit length select a transmit stop bit length (1 bit or 2 bits) by uartcr1. 13.7 parity set parity / no parity by uartcr1 and set parity type (odd- or even-numbered) by uartcr1. 13.8 transmit/receive operation 13.8.1 data transmit operation set uartcr1 to ?1?. read uartsr to check ua rtsr = ?1?, then write data in tdbuf (transmit data buffer). writing data in tdbuf zero-cl ears uartsr, transfers the data to the transmit shift register and the data are sequenti ally output from the txd pin. the data output include a one-bit start bit, stop bits whose number is specified in uartcr1 and a parity bit if parity addition is specified. select the data transfer baud rate using uartcr1. when data transmit st arts, transmit buffer empty flag uartsr is set to ?1? a nd an inttxd interrupt is generated. while uartcr1 = ?0? and from when ?1? is written to uartcr1 to when send data are written to tdbuf, the txd pin is fixed at high level. when transmitting data, first read uartsr, then write data in tdbuf. otherwise, uartsr is not zero-cleared and transm it does not start. 13.8.2 data receive operation set uartcr1 to ?1?. when data are received vi a the rxd pin, the receive data are transferred to rdbuf (receive data buffer). at this time, the data transmitted includes a start bit and stop bit(s) and a parity bit if parity addition is specified. when stop bit(s) are received, data only are extracted and transferred to rdbuf (receive data buffer). then the receive buffer full flag ua rtsr is set and an intrxd interrupt is generated. select the data transfer baud rate using uartcr1. if an overrun error (oerr) occurs when data are received, the da ta are not transferre d to rdbuf (receive data buffer) but discarded; data in the rdbuf are not affected. note:when a receive operation is disabled by setting ua rtcr1 bit to ?0?, the setting becomes valid when data receive is completed. however, if a framing error occurs in data receive, the receive-disabling setting may not become valid. if a framing error occurs , be sure to perform a re-receive operation.
page 149 TMP86FH12MG 13.9 status flag 13.9.1 parity error when parity determined using the receive data bits differs from the received parity bit, the parity error flag uartsr is set to ?1?. the uartsr is cl eared to ?0? when the rdbuf is read after read- ing the uartsr. figure 13-5 generati on of parity error 13.9.2 framing error when ?0? is sampled as the stop bit in the receive data, framing error flag uartsr is set to ?1?. the uartsr is cleared to ?0? when the rdbuf is r ead after reading the uartsr. figure 13-6 generati on of framing error 13.9.3 overrun error when all bits in the next data are received while unread data are still in rdbuf, overrun error flag uartsr is set to ?1?. in this case, the receive data is discarded; data in rdbuf are not affected. the uartsr is cleared to ?0? when the rdbuf is read af ter reading the uartsr. parity stop shift register pxxxx0 * 1pxxxx0 xxxx0 ** rxd pin uartsr intrxd interrupt after reading uartsr then rdbuf clears perr. final bit stop shift register xxxx0 * 0xxxx0 xxx0 ** rxd pin uartsr intrxd interrupt after reading uartsr then rdbuf clears ferr.
page 150 13. asynchronous serial interface (uart ) 13.9 status flag TMP86FH12MG figure 13-7 generation of overrun error note:receive operations are di sabled until the overrun error flag uartsr is cleared. 13.9.4 receive data buffer full loading the received data in rdbuf sets receive data buffer full flag uartsr to "1". the uartsr is cleared to ?0? when the rdbuf is read after reading the uartsr. figure 13-8 generat ion of receive data buffer full note:if the overrun error flag uartsr is set during the period between reading the uartsr and reading the rdbuf, it cannot be cleared by only reading the rdbuf. therefore, after reading the rdbuf, read the uartsr again to check whether or not the overrun er ror flag which should have been cleared still remains set. 13.9.5 transmit data buffer empty when no data is in the transmit buffer tdbuf, uartsr is set to ?1?, that is, when data in tdbuf are transferred to the transmit shift register and data transmit star ts, transmit data buffer empty flag uartsr is set to ?1?. the uartsr is cleared to ?0? when the tdbuf is written after reading the uartsr. final bit stop shift register xxxx0 * 1xxxx0 yyyy xxx0 ** rxd pin uartsr intrxd interrupt after reading uartsr then rdbuf clears oerr. rdbuf uartsr final bit stop shift register xxxx0 * 1xxxx0 xxxx yyyy xxx0 ** rxd pin uartsr intrxd interrupt rdbuf after reading uartsr then rdbuf clears rbfl.
page 151 TMP86FH12MG figure 13-9 generation of transmit data buffer empty 13.9.6 transmit end flag when data are transmitted and no data is in tdbuf (uartsr = ?1?), transmit end flag uartsr is set to ?1?. the uartsr is cleared to ?0? when the data transmit is stated after writing the tdbuf. figure 13-10 generation of transmit end flag and transmit data buffer empty shift register data write data write zzzz xxxx yyyy start bit 0 final bit stop 1xxxx0 ***** 1 * 1xxxx **** 1x ***** 1 1yyyy0 tdbuf txd pin uartsr inttxd interrupt after reading uartsr writing tdbuf clears tbep. shift register * 1yyyy *** 1xx **** 1x ***** 1 stop start 1yyyy0 bit 0 txd pin uartsr uartsr inttxd interrupt data write for tdbuf
page 152 13. asynchronous serial interface (uart ) 13.9 status flag TMP86FH12MG
page 153 TMP86FH12MG 14. 10-bit ad converter (adc) the TMP86FH12MG have a 10-bit successive approximation type ad converter. 14.1 configuration the circuit configuration of the 10-bit ad converter is shown in figure 14-1. it consists of control register adccr1 and adccr2 , converted value register adcdr1 and adcdr2, a da converter, a sample-hold circuit, a compar ator, and a successive comparison circuit. note: before using ad converter, set appropriate value to i/o port register conbining a analog input port. for details, see the sec- tion on "i/o ports". figure 14-1 10-bit ad converter 2 4 10 8 ainds adrs r/2 r/2 r ack amd irefon ad conversion result register 1, 2 ad converter control register 1, 2 adbf eocf intadc sain n successive approximate circuit adccr2 adcdr1 adcdr2 adccr1 sample hold circuit a s en shift clock da converter analog input multiplexer y reference voltage analog comparator 2 3 control circuit vss vdd ain0 ain7
page 154 14. 10-bit ad converter (adc) 14.2 register configuration TMP86FH12MG 14.2 register configuration the ad converter consists of the following four registers: 1. ad converter control register 1 (adccr1) this register selects the analog channels and operatio n mode (software start or repeat) in which to per- form ad conversion and controls the ad converter as it starts operating. 2. ad converter control register 2 (adccr2) this register selects the ad conversion time and controls the connection of the da converter (ladder resistor network). 3. ad converted value register 1 (adcdr1) this register used to store the digital value fter being converted by the ad converter. 4. ad converted value register 2 (adcdr2) this register monitors the oper ating status of the ad converter. note 1: select analog input channel during ad converter stops (adcdr2 = "0"). note 2: when the analog input channel is all use dis abling, the adccr1 should be set to "1". note 3: during conversion, do not perform port output instruction to maintain a precision for all of the pins because analog input port use as general input port. and for port near to anal og input, do not input intense signaling of change. note 4: the adccr1 is automatically cleared to "0" after starting conversion. note 5: do not set adccr1 newly again during ad conv ersion. before setting adccr1 newly again, check adcdr2 to see that the conversion is completed or wait until the interrupt signal (intadc) is generated (e.g., interrupt handling routine). note 6: after stop or slow/sleep mode are started, ad conver ter control register1 (adccr1) is all initialized and no data can be written in this register. therfore, to use ad converter again, set the adccr1 newly after returning to normal1 or normal2 mode. ad converter control register 1 adccr1 (0025h) 76543210 adrs amd ainds sain (initial value: 0001 0000) adrs ad conversion start 0: 1: - ad conversion start r/w amd ad operating mode 00: 01: 10: 11: ad operation disable software start mode reserved repeat mode ainds analog input control 0: 1: analog input enable analog input disable sain analog input channel select 0000: 0001: 0010: 0011: 0100: 0101: 0110: 0111: 1000: 1001: 1010: 1011: 1100: 1101: 1110: 1111: ain0 ain1 ain2 ain3 ain4 ain5 ain6 ain7 reserved reserved reserved reserved reserved reserved reserved reserved
page 155 TMP86FH12MG note 1: always set bit0 in adccr2 to "0" and set bit4 in adccr2 to "1". note 2: when a read instruction for adccr2, bi t6 to 7 in adccr2 read in as undefined data. note 3: after stop or slow/sleep mode are started, ad conver ter control register2 (adccr2) is all initialized and no data can be written in this register. therfore, to use ad converter again, set the adccr2 newly after returning to normal1 or normal2 mode. note 1: setting for " ?
page 156 14. 10-bit ad converter (adc) 14.2 register configuration TMP86FH12MG note 1: the adcdr2 is cleared to "0" when reading the a dcdr1. therfore, the ad conversion result should be read to adcdr2 more first than adcdr1. note 2: the adcdr2 is set to "1" when ad conversion star ts, and cleared to "0" when ad conversion finished. it also is cleared upon entering stop mode or slow mode . note 3: if a read instruction is executed for a dcdr2, read data of bit3 to bit0 are unstable. eocf ad conversion end flag 0: 1: before or during conversion conversion completed read only adbf ad conversion busy flag 0: 1: during stop of ad conversion during ad conversion
page 157 TMP86FH12MG 14.3 function 14.3.1 software start mode after setting adccr1 to ?01? (software start mode), set adccr1 to ?1?. ad conver- sion of the voltage at the analog input pin specified by adccr1 is thereby started. after completion of the ad conversion, the conversion result is stored in ad converted value registers (adcdr1, adcdr2) and at the same time adcdr2 is set to 1, the ad conversion finished inter- rupt (intadc) is generated. adrs is automatically cleared afte r ad conversion has started. do not set adccr1 newly again (restart) during ad conversion. before setting adrs newly again, check adcdr2 to see that the conversion is completed or wait until the interrupt signa l (intadc) is generated (e.g., interrupt handling rou- tine). figure 14-2 software start mode 14.3.2 repeat mode ad conversion of the voltage at the analog input pin specified by adccr1 is performed repeatedly. in this mode, ad conversion is started by setti ng adccr1 to ?1? after setting adccr1 to ?11? (repeat mode). after completion of the ad conversion, the conversion result is stored in ad converted value registers (adcdr1, adcdr2) and at the same time adcdr2 is set to 1, the ad conversion finished inter- rupt (intadc) is generated. in repeat mode, each time one ad conversion is complete d, the next ad conversion is started. to stop ad conversion, set adccr1 to ?00? (disable mode) by writing 0s. the ad convert operation is stopped immediately. the converted valu e at this time is not stored in the ad converted value register. adcdr1 status eocf cleared by reading conversion result conversion result read adcdr2 intadc interrupt request adcdr2 adccr1 1st conversion result 2nd conversion result indeterminate ad conversion start ad conversion start a dcdr1 a dcdr2 conversion result read conversion result read conversion result read
page 158 14. 10-bit ad converter (adc) 14.3 function TMP86FH12MG figure 14-3 repeat mode 14.3.3 regi ster setting 1. set up the ad converter control register 1 (adccr1) as follows: ? choose the channel to ad convert using ad input channel select (sain). ? specify analog input enable fo r analog input control (ainds). ? specify amd for the ad converter control operation mode (software or repeat mode). 2. set up the ad converter control register 2 (adccr2) as follows: ? set the ad conversion time using ad conversion time (ack). for details on how to set the con- version time, refer to figure 14-1 and ad converter control register 2. ? choose irefon for da converter control. 3. after setting up (1) and (2) above, set ad conversion start (adrs) of ad converter control register 1 (adccr1) to ?1?. if software start mode has been selected, ad conversi on starts immediately. 4. after an elapse of the specified ad conversion time, the ad converted value is stored in ad con- verted value register 1 (adcdr1) and the ad conv ersion finished flag (e ocf) of ad converted value register 2 (adcdr2) is set to ?1?, upon wh ich time ad conversion interrupt intadc is gener- ated. 5. eocf is cleared to ?0? by a read of the conversion result. however, if reconverted before a register read, although eocf is cl eared the previous conversi on result is retained until the next conversion is completed. a dcdr1,adcdr2 eocf cleared by reading conversion result conversion result read a dcdr2 intadc interrupt request conversion operation a dccr1 indeterminate ad conversion start adccr1 ?11? ?00? 1st conversion result ad convert operation suspended. conversion result is not stored. 2nd conversion result 3rd conversion result a dcdr1 a dcdr2 2nd conversion result 3rd conversion result 1st conversion result conversion result read conversion result read conversion result read conversion result read conversion result read
page 159 TMP86FH12MG 14.4 stop/slow modes during ad conversion when standby mode (stop or slow mode) is entered fo rcibly during ad conversi on, the ad convert operation is suspended and the ad converter is in itialized (adccr1 and adccr2 are initia lized to initial value). also, the conversion result is indeterminate. (conversion results up to the previous operation are cleared, so be sure to read the conversion results before entering standby mode (stop or slow mode).) when restored from standby mode (stop or slow mode), ad conversion is not automatically restarted, so it is necessa ry to restart ad conversion. note that since the analog reference voltage is automatically disconnected, there is no possibility of current flowing into the analog reference voltage. example :after selecting the conversion time 19.5 s at 16 mhz and the analog input channel ain3 pin, perform ad con- version once. after checking eocf, read the converted value, store the lower 2 bits in address 0009eh nd store the upper 8 bits in address 0009fh in ram. the operation mode is software start mode. : (port setting) : ;set port register approrriately before setting ad converter registers. : : (refer to section i/o port in details) ld (adccr1) , 00100011b ; select ain3 ld (adccr2) , 11011000b ;select conversion time(312/fc) and operation mode set (adccr1) . 7 ; adrs = 1(ad conversion start) sloop : test (adcdr2) . 5 ; eocf= 1 ? jrs t, sloop ld a , (adcdr2) ; read result data ld (9eh) , a ld a , (adcdr1) ; read result data ld (9fh), a
page 160 14. 10-bit ad converter (adc) 14.5 analog input voltage and ad conversion result TMP86FH12MG 14.5 analog input voltage and ad conversion result the analog input voltage is corresponded to the 10-bit digital value converted by the ad as shown in figure 14-4. figure 14-4 analog input voltage and ad c onversion result (typ.) 10 01 h 02 h 03 h 3fd h 3fe h 3ff h 2 3 1021 1022 1023 1024 analog input voltage 1024 ad conversion result vdd vss
page 161 TMP86FH12MG 14.6 precautions about ad converter 14.6.1 analog input pin voltage range make sure the analog input pins (ain0 to ain7) are us ed at voltages within vdd to vss. if any voltage outside this range is applied to one of the analog input pins, the converted value on that pin becomes uncertain. the other analog input pins also are affected by that. 14.6.2 analog input shared pins the analog input pins (ain0 to ain7) are shared w ith input/output ports. when using any of the analog inputs to execute ad conversion, do not execute input/output instructions for all other ports. this is necessary to prevent the accuracy of ad conversi on from degrading. not only these analog input shared pins, some other pins may also be affected by noise arising from input/o utput to and from adjacent pins. 14.6.3 noise countermeasure the internal equivalent circuit of the analog input pins is shown in figure 14-5. the higher the output impedance of the analog input source, more easily they are susceptible to no ise. therefore, make sure the out- put impedance of the signal source in your design is 5 k ? or less. toshiba also recommends attaching a capac- itor external to the chip. figure 14-5 analog i nput equivalent circuit and exam ple of input pin processing da converter aini analog comparator internal resistance permissible signal source impedance internal capacitance 5 k ? ?
page 162 14. 10-bit ad converter (adc) 14.6 precautions about ad converter TMP86FH12MG
page 163 TMP86FH12MG 15. key-on wakeup (kwu) in the TMP86FH12MG, the stop mode is released by not only p20( int5 / stop ) pin but also four (stop0 to stop3) pins. when the stop mode is released by stop0 to stop3 pins, the stop pin needs to be used. in details, refer to the following section " 15.2 control ". 15.1 configuration figure 15-1 key-on wakeup circuit 15.2 control stop0 to stop3 pins can controlled by key-on wakeup c ontrol register (stopcr). it can be configured as enable/disable in 1-bit unit. when thos e pins are used for stop mode releas e, configure corresponding i/o pins to input mode by i/o port register beforehand. 15.3 function stop mode can be entered by setting up the system control register (syscr1), and can be exited by detecting the "l" level on stop0 to stop3 pins, which are enabled by stopcr, for releasing stop mode (note1). key-on wakeup control register stopcr76543210 (0f88h) stop3 stop2 stop1 stop0 (initial value: 0000 ****) stop3 stop mode released by stop3 0:disable 1:enable write only stop2 stop mode released by stop2 0:disable 1:enable write only stop1 stop mode released by stop1 0:disable 1:enable write only stop0 stop mode released by stop0 0:disable 1:enable write only stopcr int5 stop stop mode release signal (1: release) (0f88h) stop0 stop1 stop2 stop3 stop0 stop1 stop2 stop3
page 164 15. key-on wakeup (kwu) 15.3 function TMP86FH12MG also, each level of the stop0 to stop3 pins can be confirmed by reading corresponding i/o port data register, check all stop0 to stop3 pins "h" that is enabled by stopcr before the stop mode is startd (note2). note 1: when the stop mode released by the edge release mo de (syscr1 = ?0?), inhibit input from stop0 to stop3 pins by key-on wakeup control register (stopcr) or must be set "h" level into stop0 to stop3 pins that are available input during stop mode. note 2: when the stop pin input is high or stop0 to stop3 pins input which is enabled by stopcr is low, executing an instruction which starts stop mode wi ll not place in stop mode but instead will immediately start the release sequence (warm up). note 3: stop pin doesn?t have the control register such as stop cr, so when stop mode is released by stop0 to stop3 pins, stop pin also should be used as stop mode release function. note 4: in stop mode, key-on wakeup pin which is enabled as input mode (for releasing stop mode) by key-on wakeup control register (stopcr) may genarate the penet ration current, so the said pin must be disabled ad conversion input (analog voltage input). note 5: when the stop mode is released by stop0 to stop3 pins, the level of stop pin should hold "l" level (figure 15-2). figure 15-2 priority of stop pin and stop0 to stop3 pins table 15-1 release level (edge) of stop mode pin name release level (edge) syscr1="1" (note2) syscr1="0" stop "h" level rising edge stop0 "l" level don?t use (note1) stop1 "l" level don?t use (note1) stop2 "l" level don?t use (note1) stop3 "l" level don?t use (note1) stop pin a) stop release stop mode stop mode stop pin "l" b) release stop mode stop mode in case of stop0 to stop3 stop0 pin
page 165 TMP86FH12MG 16. flash memory TMP86FH12MG has 16384byte flash memory (address: c000h to ffffh). the write and erase operations to the flash memory are controlled in th e following three types of mode. - mcu mode the flash memory is accessed by the cpu control in the mcu mode. this mode is used for software bug correction and firmware change after shipment of the device since the write operation to the flash memory is available by retaining the application behavior. - serial prom mode the flash memory is accessed by the cpu control in the serial prom mode. use of the serial interface (uart) enables the flash memory to be controlled by the small number of pins. TMP86FH12MG in the serial prom mode supports on-board programming wh ich enables users to prog ram flash memory after the microcontroller is mounted on a user board. - parallel prom mode the parallel prom mode allows the flash memory to be accessed as a stand-alone flash memory by the program writer provided by the third party. high-speed access to th e flash memory is available by control- ling address and data signals directly. for the suppor t of the program writer, please ask toshiba sales rep- resentative. in the mcu and serial prom modes, the flash memory c ontrol register (flscr) is used for flash memory con- trol. this chapter describes how to acce ss the flash memory using the flash memo ry control register (flscr) in the mcu and serial prom modes.
page 166 16. flash memory 16.1 flash memory control TMP86FH12MG 16.1 flash memory control the flash memory is controlled via the flash memory control register (flscr) and flash memory stanby control resister (flsstb). note 1: the command sequence of the flash me mory can be executed only when flsmd=" 0011b". in other cases, any attempts to execute the command sequence are ineffective. note 2: flsmd must be set to either "1100b" or "0011b". note 3: bits 3 through 0 in flscr are always read as don?t care. note 1: when fstb is set to 1, do not execute the read/write in struction to the flash memory bec ause there is a possibility that the expected data is not read or the program is not operated correctly. if executing the read/write instruction, fstb is initial- ized to 0 automatically. note 2: if an interrupt is issued when fstb is set to 1, fstb is initialized to 0 automatically and then the vector area of the flash memory is read. note 3: if the idle0/1/2, sleep0/1/2 or stop mode is activated when fstb is set to 1, fstb is initialized to 0 automatically. in the idle0/1/2, sleep0/1/2 or stop mode, the standby function operates regardless of fstb setting. 16.1.1 flash memory command sequenc e execution control (flscr) the flash memory can be protected fr om inadvertent write due to program error or microcontroller misoper- ation. this write protection feature is realized by disabling flash memo ry command sequence execution via the flash memory control register (write protect). to enable command sequence execution, set flscr to ?0011b?. to disable comman d sequence execution, set flscr to ?1100b?. after reset, flscr is initialized to ?1100b? to disable command sequence execution. normally, flscr should be set to ?1100b? except when the flash memory needs to be written or erased. 16.1.2 flash memory stan dby control (flsstb) low power consumption is enabled by cutting off the steady-state current of the flash memory. in the idle0/1/2, sleep0/1/2 or stop mode, th e steady-state current of the flas h memory is cut off automatically. when the program is executed in the ram area (with out accessing the flash me mory) in the normal 1/2 or slow1/2 mode, the current can be cut off by the contro l of the register. to cut off the steady-state current of the flash memory, set flsstb to ?1? by the c ontrol program in the ram area. the procedures for controlling the flsstb regi ster are explained below. (steps1 and 2 are controlled by the program in the flash memory, and steps 3 through 8 are controlled by the write control program ex ecuted in the ram area.) flash memory control register f l s c r76543210 (0fffh) flsmd (initial value : 1100 ****) flsmd flash memory command sequence exe- cution control 1100: disable command sequence execution 0011: enable command sequence execution others: reserved r/w flash memory standby control register f l s s t b76543210 (0fe9h) fstb (initial value : **** ***0) fstb flash memory standby control 0: disable the standby function. 1: enable the standby function. write only
page 167 TMP86FH12MG 1. transfer the control program of th e flsstb register to the ram area. 2. jump to the ram area. 3. disable (di) the interrupt mast er enable flag (imf = ?0?). 4. set flsstb to ?1?. 5. execute the user program. 6. repeat step 5 until the return requ est to the flash memory is detected. 7. set flsstb to ?0?. 8. jump to the flash memory area. note 1: the standby function is not operated by setting fl sstb with the program in the flash memory. you must set flsstb by the program in the ram area. note 2: to use the standby function by setting flsstb to ?1? with the program in the ram area, flsstb must be set to ?0? by the program in the ram area before returning the program control to the flash memory. if the program control is returned to the flash memory with flsstb set to ?1?, the program may misoperate and run out of control.
page 168 16. flash memory 16.2 command sequence TMP86FH12MG 16.2 command sequence the command sequence in the mcu and the serial prom modes consists of six commands (jedec compatible), as shown in table 16-1. addresses specified in the command sequence are recognized with the lower 12 bits (excluding ba, sa, and ff7fh used for read protection). the upper 4 bits are used to specify the flash memory area, note 1: set the address and data to be written. note 2: the area to be erased is specified with the upper 4 bits of the address. 16.2.1 byte program this command writes the fl ash memory for each byte unit. the addresses and data to be written are specified in the 4th bus write cycle. each byte can be programmed in a maximum of 40 s. the next command sequence cannot be executed until the write operation is completed. to check the completion of the write operation, per- form read operations repeat edly until the same data is read twice fr om the same address in the flash memory. during the write operation, any consecutive attempts to r ead from the same address is reversed bit 6 of the data (toggling between 0 and 1). note:to rewrite data to flash memory addresses at which dat a (including ffh) is already written, make sure to erase the existing data by "sector erase" or "chip erase" before rewriting data. 16.2.2 sector erase (4-kbyte erase) this command erases the flash memory in units of 4 kbytes. the flash memory area to be erased is specified by the upper 4 bits of the 6th bus write cycle address. for example, to erase 4 kbytes from f000h to ffffh, specify one of the addresses in f000 h-ffffh as the 6th bus wr ite cycle. the sector erase command is effec- tive only in the mcu and serial prom modes, and it cannot be used in the parallel prom mode. a maximum of 30 ms is required to erase 4 kbytes. the next command sequence cannot be executed until the erase operation is completed. to check the completion of the erase operation, perf orm read operations repeat- edly for data polling until the same data is read twice from the same address in the flash memory. during the erase operation, any consecutive attempts to read from the same address is reversed bit 6 of the data (toggling between 0 and 1). table 16-1 command sequence command sequence 1st bus write cycle 2nd bus write cycle 3rd bus write cycle 4th bus write cycle 5th bus write cycle 6th bus write cycle address data address data address data address data address data address data 1 byte program 555h aah aaah 55h 555h a0h ba (note 1) data (note 1) ---- 2 sector erase (4-kbyte erase) 555h aah aaah 55h 555h 80h 555h aah aaah 55h sa (note 2) 30h 3 chip erase (all erase) 555h aah aaah 55h 555h 80h 555h aah aaah 55h 555h 10h 4product id entry555haahaaah55h555h90h------ 5 product id exitxxhf0h---------- product id exit555haahaaah55h555hf0h------ 6read protect555haahaaah55h555ha5hff7fh00h----
page 169 TMP86FH12MG 16.2.3 chip erase (all erase) this command erases the entire flash memory in approximately 30 ms. the next command sequence cannot be executed until the erase operation is completed. to check the completio n of the erase operation, perform read operations repeatedly for data polling until the same data is read twice from the same address in the flash memory. during the erase operation, any consecutive attemp ts to read from the same address is reversed bit 6 of the data (toggling between 0 and 1). after the chip is erased, all bytes contain ffh. 16.2.4 product id entry this command activates the product id mode. in the product id mode, the vendor id, the flash id, and the read protection status can be read from the flash memory. note: the value at address f002h (flash size) depends on the size of flash memory incorporated in each product. for example, if the product has 60-kbyte flash memory, "0eh" is read from address f002h. 16.2.5 product id exit this command is used to exit the product id mode. 16.2.6 read protect this command enables the r ead protection setting in the flash memory . when the read protection is enabled, the flash memory cannot be read in the parallel prom mode. in the serial prom mode, the flash write and ram loader commands cannot be executed. to disable the read protection setting, it is necessary to execute the chip eras e command sequence. whether or not the read protection is enabled can be checked by reading ff7fh in the product id mode. for details, see table 16-2. it takes a maximum of 40 s to set read protection in the flash memory. the next command sequence cannot be executed until this operation is completed. to check the completion of the read protect operation, perform read operations repeatedly for data polling until the same data is read twice from the same address in the flash memory. during the read protect operation, any attempts to read from the same address is reversed bit 6 of the data (toggling between 0 and 1). table 16-2 values to be read in the product id mode address meaning read value f000h vendor id 98h f001h flash macro id 41h f002h flash size 0eh: 60 kbytes 0bh: 48 kbytes 07h: 32 kbytes 05h: 24 kbytes 03h: 16 kbytes 01h: 8 kbytes 00h: 4 kbytes ff7fh read protection status ffh: read protection disabled other than ffh: read protection enabled
page 170 16. flash memory 16.3 toggle bit (d6) TMP86FH12MG 16.3 toggle bit (d6) after the byte program, chip erase, and read protect command sequence is executed, any consecutive attempts to read from the same address is reversed bit 6 (d6) of the data (toggling between 0 and 1) until the operation is com- pleted. therefore, this toggle bit provides a software mechanism to check the completion of each operation. usually perform read operations repeatedly for data polling until th e same data is read twice from the same address in the flash memory. after the byte program, chip erase, or read protect command sequence is executed, the initial read of the toggle bit always produces a "1".
page 171 TMP86FH12MG 16.4 access to the flash memory area when the write, erase and read protect ions are set in the flash memory, read and fetch operations cannot be per- formed in the entire flash memory area. therefore, to perform these operations in the entire flash memory area, access to the flash memory area by the control program in the bootrom or ram area. (the flash memory pro- gram cannot write to the flash memory.) the serial prom or mcu mode is used to run the control program in the bootrom or ram area. note 1: the flash memory can be written or read for each by te unit. erase operations can be performed either in the entire area or in units of 4 kbytes, whereas read operations can be performed by an one transfer instruction. however, the command sequence method is adopted for write and erase operations, requiring several-byte transfer instruc- tions for each operation. note 2: to rewrite data to flash memory addresses at which data (including ffh) is already written, make sure to erase the existing data by "sector erase" or "chip erase" before rewriting data. 16.4.1 flash memory contro l in the serial prom mode the serial prom mode is used to access to the fl ash memory by the contro l program provided in the bootrom area. since almost of all op erations relating to access to the flash memory can be controlled sim- ply by the communication data of th e serial interface (uart), these functio ns are transparent to the user. for the details of the serial prom mode, see ?serial prom mode.? to access to the flash memory by using peripheral func tions in the serial prom mode, run the ram loader command to execute the control prog ram in the ram area. the procedures to execute the control program in the ram area is shown in " 16.4.1.1 how to write to the flash memory by executing the control program in the ram area (in the ram loader mode within the serial prom mode) ". 16.4.1.1 how to write to the flash memory by executing the control program in the ram area (in the ram loader mode within the serial prom mode) (steps 1 and 2 are controlled by the bootrom, and steps 3 through 9 are controlled by the control program executed in the ram area.) 1. transfer the write control program to the ram area in the ram loader mode. 2. jump to the ram area. 3. disable (di) the interrup t master enable flag (imf "0"). 4. set flscr to "0011b" (to enable command sequence execution). 5. execute the erase command sequence. 6. read the same flash memory address twice. (repeat step 6 until the same data is re ad by two consecutive reads operations.) 7. execute the write command sequence. 8. read the same flash memory address twice. (repeat step 8 until the same data is read by two consecutive reads operations.) 9. set flscr to "1100b" (to disable command sequence execution). note 1: before writing to the flash memory in the ram area, disable interrupts by setting the interrupt master enable flag (imf) to "0". usually disable interrupts by executing the di instruction at the head of the write control program in the ram area. note 2: since the watchdog timer is disabled by the boot rom in the ram loader mode, it is not required to disable the watchdog timer by the ram loader program.
page 172 16. flash memory 16.4 access to the flash memory area TMP86FH12MG example :after chip erasure, the program in the ram area writ es data 3fh to address f000h. di : disable interrupts (imf
page 173 TMP86FH12MG 16.4.2 flash memory c ontrol in the mcu mode in the mcu mode, write operations are performed by executing the control program in the ram area. before execution of the control pr ogram, copy the control program into the ram area or obtain it from the external using the communication pin. the procedures to execute the cont rol program in the ram area in the mcu mode are described below. 16.4.2.1 how to write to the flash memory by executing a user write control program in the ram area (in the mcu mode) (steps 1 and 2 are controlled by the program in the flash memory, and steps 3 through 11 are controlled by the control program in the ram area.) 1. transfer the write contro l program to the ram area. 2. jump to the ram area. 3. disable (di) the interrup t master enable flag (imf "0"). 4. disable the watchdog timer, if it is used. 5. set flscr to "0011b" (to enable command sequence execution). 6. execute the erase command sequence. 7. read the same flash memory address twice. (repeat step 7 until the same data is read by two consecutive read operations.) 8. execute the write command sequence. 9. read the same flash memory address twice. (repeat step 9 until the same data is read by two consecutive read operations.) 10. set flscr to "1100b" (to disable command sequence execution). 11. jump to the flash memory area. note 1: before writing to the flash memory in the ram area, disable interrupts by setting the interrupt master enable flag (imf) to "0". usually disable interrupts by executing the di instruction at the head of the write control program in the ram area. note 2: when writing to the flash memory, do not in tentionally use non-maskable interrupts (the watchdog timer must be disabled if it is used). if a non-mask able interrupt occurs while the flash memory is being written, unexpected data is read from the flash memory (interrupt vector), resulting in malfunc- tion of the microcontroller.
page 174 16. flash memory 16.4 access to the flash memory area TMP86FH12MG example :after sector eras ure (e000h-efffh), the program in the ram area writes data 3fh to address e000h. di : disable interrupts (imf example :this write control program reads data from address f000h and stores it to 98h in the ram area. ld a,(0f000h) : read data from address f000h. ld (98h),a : store data to address 98h.
page 175 TMP86FH12MG 17. serial prom mode 17.1 outline the TMP86FH12MG has a 2048 byte bootrom (mask rom) for programming to flash memory. the bootrom is available in the serial prom mode, and controlled by test, boot and reset pins. communica- tion is performed via uart. the serial prom mode ha s seven types of operating mode: flash memory writing, ram loader, flash memory sum output, product id code output, flash memory status output, flash memory eras- ing and flash memory read protection setting. memory addr ess mapping in the serial pr om mode differs from that in the mcu mode. figure 17-1 shows memory address mapping in the serial prom mode. note: though included in above operating range, some of high fr equencies are not supported in the serial prom mode. for details, refer to ?table 17-5?. 17.2 memory mapping the figure 17-1 shows memory mapping in the serial prom mode and mcu mode. in the serial prom mode, the bootrom (mask rom) is mapped in addresses from 7800h to 7fffh. figure 17-1 memory address maps table 17-1 operating range in the serial prom mode parameter min max unit power supply 4.5 5.5 v high frequency (note) 2 16 mhz 003fh 0000h 64 bytes 2048 bytes 0040h 7800h 7fffh c000h ffffh ffffh sfr ram dbr sfr ram dbr bootrom flash memory serial prom mode mcu mode 16384 bytes 003fh 0000h 64 bytes 0040h flash memory c000h 16384 bytes 0fffh 0fffh 512 bytes 128 bytes 128 bytes 023fh 0f80h 0f80h 512 bytes 023fh
page 176 17. serial prom mode 17.3 serial prom mode setting TMP86FH12MG 17.3 serial prom mode setting 17.3.1 serial prom mode control pins to execute on-board programming, act ivate the serial prom mode. table 17-2 shows pin setting to activate the serial prom mode. note: the boot pin is shared with the uart communication pin (rxd pin) in the serial prom m ode. this pin is used as uart communication pin after activating serial prom mode 17.3.2 pin function in the serial prom mode, tx d (p00) and rxd (p01 ) are used as a serial interface pin. note 1: during on-board programming with other parts mounted on a user board, be careful no to affect these communication control pins. note 2: operating range of high frequency in serial prom mode is 2 mhz to 16 mhz. table 17-2 serial prom mode setting pin setting test pin high boot/rxd pin high reset pin table 17-3 pin function in the serial prom mode pin name (serial prom mode) input/ output function pin name (mcu mode) txd output serial data output (note 1) p00 boot/rxd input/input serial prom mode control/serial data input p01 reset input serial prom mode control reset test input fixed to high test vdd power supply 4.5 to 5.5 v vss power supply 0 v i/o ports except p00, p01 i/o these ports are in the high-impedance state in the serial prom mode. the input level is fixed to the port inputs with a hardware feature to prevent overlap current. (the port inputs are invalid.) to make the port inputs valid, set the pin of the spcr register to ?1? by the ram loader control pro- gram. xin input self-oscillate with an oscillator. (note 2) xout output
page 177 TMP86FH12MG figure 17-2 serial prom mode pin setting note 1: for connection of other pins, refer to " t able 17-3 pin function in the serial prom mode ". 17.3.3 example connection for on-board writing figure 17-3 shows an example connection to perform on-board wring. figure 17-3 example conn ection for on-board writing note 1: when other parts on the application board effect th e uart communication in the serial prom mode, iso- late these pins by a jumper or switch. note 2: when the reset control circuit on the application board effect s activation of the serial prom mode, isolate the pin by a jumper or switch. note 3: for connection of other pins, refer to " t able 17-3 pin function in the serial prom mode ". vdd(4.5 v to 5.5 v) serial prom mode mcu mode vdd test reset external control pull-up xin xout vss gnd boot / rxd (p01) txd (p00) TMP86FH12MG vdd(4.5 v to 5.5 v) serial prom mode mcu mode vdd test reset pc control pull-up level converter xin xout vss gnd external control board application board rc power-on reset circuit reset control other parts (note 1) (note 2) boot / rxd (p01) txd (p00)
page 178 17. serial prom mode 17.3 serial prom mode setting TMP86FH12MG 17.3.4 activating t he serial prom mode the following is a procedure to ac tivate the serial prom mode. " figure 17-4 serial prom mode timing " shows a serial prom mode timing. 1. supply power to the vdd pin. 2. set the reset pin to low. 3. set the test pin and boot/rxd pins to high. 4. wait until the power supply and clock oscillation stabilize. 5. set the reset pin to high. 6. input the matching data (5ah) to the boot/rxd pin after setup sequence. for details of the setup timing, refer to " 17.16 uart timing ". figure 17-4 serial prom mode timing vdd test(input) reset(input) program setup time for serial prom mode (rxsup) high level setting matching data don't care reset mode serial prom mode input boot/rxd (input)
page 179 TMP86FH12MG 17.4 interface specifications for uart the following shows the uart communication format used in the serial prom mode. to perform on-board programming, the communication format of the write controller must also be set in the same manner. the default baud rate is 9600 bps regardless of operating frequency of the microcontroller. the baud rate can be modified by transmitting the baud rate modification data shown in table 1-4 to TMP86FH12MG. the table 17-5 shows an operating frequency and baud rate. the frequencies which are not described in table 17-5 can not be used. - baud rate (default): 9600 bps - data length: 8 bits - parity addition: none - stop bit: 1 bit table 17-4 baud rate modification data baud rate modification data 04h 05h 06h 07h 0ah 18h 28h baud rate (bps) 76800 62500 57600 38400 31250 19200 9600
page 180 17. serial prom mode 17.4 interface specifications for uart TMP86FH12MG note 1: ?ref. frequency? and ?rating? show frequencies availabl e in the serial prom mode. though the frequency is supported in the serial prom mode, the serial prom mode may not be activated correctly due to the frequency difference in the external controller (such as pers onal computer) and oscillator, and load capacitance of communication pins. note 2: it is recommended that the total frequency difference is within
page 181 TMP86FH12MG 17.5 operation command the eight commands shown in table 17-6 are used in the serial prom mode. after reset release, the TMP86FH12MG waits for the matching data (5ah). 17.6 operation mode the serial prom mode has seven types of modes, that are (1) flash memory erasin g, (2) flash memory writing, (3) ram loader, (4) flash memory sum output, (5) product id code output, (6) flash memory status output and (7) flash memory read protection setting modes. description of each mode is shown below. 1. flash memory erasing mode the flash memory is erased by the chip erase (erasing an entire flash area) or sector erase (erasing sectors in 4-kbyte units). the erased area is filled with ffh. when the read protection is enabled, the sector erase in the flash erasing mode can not be performed. to disabl e the read protection, perfor m the chip erase. before erasing the flash memory , TMP86FH12MG checks the passwords except a blank product. if the password is not matched, the flash memory erasing mode is not activated. 2. flash memory writing mode data is written to the specified flas h memory address for each byte unit. the external controller must trans- mit the write data in the intel hex format (binary). if no error is encountered till the end record, TMP86FH12MG calculates the checksum for the entire flash memory area (c000h to ffffh), and returns the obtained result to the external controller. when the read protection is enabled, the flash memory writing mode is not activated. in this case, perform the chip erase command beforehand in the flash memory eras- ing mode. before activating the flash memory wr iting mode, TMP86FH12MG checks the password except a blank product. if the password is not matched, flash memory writing mode is not activated. 3. ram loader mode the ram loader transfers the data in intel hex format sent from the external controller to the internal ram. when the transfer is completed normally, the ram loader calculates the checksum. after transmit- ting the results, the ram loader jumps to the ram address specified with the first data record in order to execute the user program. when the read protection is enabled, the ram loader mode is not activated. in this case, perform the chip erase beforehand in the fl ash memory erasing mode. before activating the ram loader mode, TMP86FH12MG checks the password excep t a blank product. if the password is not matched, flash ram loader mode is not activated. 4. flash memory sum output mode the checksum is calculated for the entire flash memory area (c000h to ffffh), and the result is returned to the external controller. since the bootrom does not support the oper ation command to read the flash memory, use this checksum to identify programs when managing revisions of application programs. 5. product id code output the code used to identify the product is output. the code to be output consists of 13-byte data, which includes the information indicating th e area of the rom incorporated in the product. the external control- ler reads this code, and recognizes the product to write. (in the case of TMP86FH12MG, the addresses from c000h to ffffh become the rom area.) table 17-6 operation command in the serial prom mode command data operating mode description 5ah setup matching data. execute this command after releasing the reset. f0h flash memory erasing erases the flash memory area (address c000h to ffffh). 30h flash memory writing writes to the flash memory area (address c000h to ffffh). 60h ram loader writes to the specified ram area (address 0050h to 023fh). 90h flash memory sum output outputs the 2-byte checksum upper byte and lower byte in this order for the entire area of the flash memory (address c000h to ffffh). c0h product id code output outputs the product id code (13-byte data). c3h flash memory status output outputs the status code (7-byte data) such as the read protection condition. fah flash memory read protection setting enables the read protection.
page 182 17. serial prom mode 17.6 operation mode TMP86FH12MG 6. flash memory status output mode the status of the area from ffe0h to ffffh, and the read protection co ndition are output as 7-byte code. the external controller reads this code to recognize the flash memory status. 7. flash memory read protection setting mode this mode disables reading the flash memory data in parallel prom mode. in the serial prom mode, the flash memory writing and ram loader modes are disabled. to disable th e flash memory read protection, perform the chip erase in th e flash memory erasing mode.
page 183 TMP86FH12MG 17.6.1 flash memory erasi ng mode (operati ng command: f0h) table 17-7 shows the flash memory erasing mode. note 1: ?xxh description of the flash memory erasing mode 1. the 1st through 4th bytes of the transmitted and r eceived data contain the same data as in the flash memory writing mode. table 17-7 flash memory erasing mode transfer byte transfer data from the external controller to TMP86FH12MG baud rate transfer data from TMP86FH12MG to the external controller boot rom 1st byte 2nd byte matching data (5ah) - 9600 bps 9600 bps - (automatic baud rate adjustment) ok: echo back data (5ah) error: no data transmitted 3rd byte 4th byte baud rate change data (table 17-4) - 9600 bps 9600 bps - ok: echo back data error: a1h
page 184 17. serial prom mode 17.6 operation mode TMP86FH12MG 2. the 5th byte of the received data contains th e command data in the flash memory erasing mode (f0h). 3. when the 5th byte of the receive d data contains the operation command data shown in table 17-6, the device echoes back the value which is the same data in the 6th byte position of the received data (in this case, f0h). if the 5th byte of the received data does not contain the operation command data, the device enters the halt condition after sending 3 bytes of the operation command error code (63h). 4. the 7th thorough m'th bytes of the transmitted and received data contai n the same data as in the flash memory writing mode. in the case of a blank produc t, do not transmit a password string. (do not transmit a dummy password string.) 5. the n?th - 2 byte contains the erasure area specification data. the upper 4 bits and lower 4 bits specify the start address and end address of the erasure area, respectively. for the detailed description, see ?1.13 specifying the erasure area?. 6. the n?th - 1 byte and n?th byte contain the upper and lower bytes of the checksum, respectively. for how to calculate the checksum, refer to ?1.8 checksum (sum)?. checksum is calculated unless a receiving error or intel hex format error occurs. after sending the e nd record, the external controller judges whether the transmission is completed corr ectly by receiving the checksum sent by the device. 7. after sending the checksum, the device waits for the next operation command data.
page 185 TMP86FH12MG 17.6.2 flash memory writing mode (operation command: 30h) table 17-8 shows flash memory writing mode process. note 1: ?xxh
page 186 17. serial prom mode 17.6 operation mode TMP86FH12MG description of the flash memory writing mode 1. the 1st byte of the received data contains the ma tching data. when the serial prom mode is acti- vated, TMP86FH12MG (hereafter called device), waits to receive the matching data (5ah). upon reception of the matching data, the device automatically adjusts the uart?s initial baud rate to 9600 bps. 2. when receiving the matching data (5ah), the device transmits an ech o back data (5ah) as the second byte data to the external controller. if the devi ce can not recognize the matching data, it does not transmit the echo back data and waits for the matc hing data again with automatic baud rate adjust- ment. therefore, the external cont roller should transmit the matching data repeatedly till the device transmits an echo back data. the transmission repe tition count varies depending on the frequency of device. for details, refer to table 17-5. 3. the 3rd byte of the received data contains the baud rate modification data. the five types of baud rate modification data shown in table 17-4 are available. even if baud rate is not modified, the external controller should transmit the initial baud rate data (28h: 9600 bps). 4. only when the 3rd byte of the received data contai ns the baud rate modification data corresponding to the device's operating frequency, th e device echoes back data the valu e which is the same data in the 4th byte position of the received data. after the ech o back data is transmitted, baud rate modification becomes effective. if the 3rd byte of the received data does not co ntain the baud rate modification data, the device enters the halts condition after se nding 3 bytes of baud rate modification error code (62h). 5. the 5th byte of the received data contains the command data (30h) to write the flash memory. 6. when the 5th byte of the received data contains the operation command data shown in table 1-6, the device echoes back the value which is the same data in the 6th byte position of the received data (in this case, 30h). if the 5th byte of the received da ta does not contain the op eration command data, the device enters the halt condition after sending 3 bytes of the operation command error code (63h). 7. the 7th byte contains the data for 15 to 8 bits of the password count storage address. when the data received with the 7th byte has no receiving error, the device does not send any data. if a receiving error or password error occurs, the device does not send any data and enters the halt condition. 8. the 9th byte contains the data for 7 to 0 bits of the password count storage address. when the data received with the 9th byte has no receiving error, the device does not send any data. if a receiving error or password error occurs, the device does not send any data and enters the halt condition. 9. the 11th byte contains the data for 15 to 8 bits of the password comparison start address. when the data received with the 11th byte has no receiving error, the device does not send any data. if a receiv- ing error or password error occurs, the device does not send any data and enters the halt condition. 10. the 13th byte contains the data for 7 to 0 bits of the password comparison start address. when the data received with the 13th byte ha s no receiving error, the device does not send any data. if a receiv- ing error or password error occurs, the device does not send any data and enters the halt condition. 11. the 15th through m?th bytes contain the passwor d data. the number of passwords becomes the data (n) stored in the password count storage address. the external password data is compared with n- byte data from the address specified by the passwor d comparison start addre ss. the external control- ler should send n-byte password data to the device. if the passwords do not match, the device enters the halt condition without returning an error code to the external controller . if the addresses from ffe0h to ffffh are filled with ?f fh?, the passwords are not conpare d because the device is consid- ered as a blank product. 12. the m?th + 1 through n?th - 2 bytes of the receive d data contain the binary data in the intel hex for- mat. no received data is echoed back to the extern al controller. after receiving the start mark (3ah for ?:?) in the intel hex format, the device starts data record reception. ther efore, the received data except 3ah is ignored until the start mark is received. afte r receiving the start mark, the device receives the data record, that consists of data lengt h, address, reco rd type, write data and checksum. since the device starts checksum cal culation after receiving an end r ecord, the external controller should wait for the checksum afte r sending the end record. if a recei ving error or intel hex format error occurs, the device enters the halts condition without returning an error code to the external con- troller. 13. the n?th - 1 and n?th bytes contain the checksum upper and lower bytes. for details on how to calcu- late the sum, refer to " 17.8 checksum (sum) ". the checksum is calculated only when the end record is detected and no receivi ng error or intel hex format er ror occurs. after sending the end
page 187 TMP86FH12MG record, the external controller ju dges whether the transmission is co mpleted correctly by receiving the checksum sent by the device. 14. after transmitting the checksu m, the device waits for the next operation command data. note 1: do not write only the address from ffe0h to ffffh when all flash memory data is the same. if only these area are written, the subsequent operation can not be executed due to password error. note 2: to rewrite data to flash memory addresses at whic h data (including ffh) is already written, make sure to erase the existing data by "sector erase" or "chip erase" before rewriting data.
page 188 17. serial prom mode 17.6 operation mode TMP86FH12MG 17.6.3 ram loader mode (o peration command: 60h) table 17-9 shows ram loader mode process. note 1: ?xxh
page 189 TMP86FH12MG note 8: if an error occurs during the reception of a password address or a password string, TMP86FH12MG stops uart commu- nication and enters the halt condition. in th is case, initialize TMP86FH12MG by the reset pin and reactivate the serial prom mode. description of ram loader mode 1. the 1st through 4th bytes of the transmitted and recei ved data contains the same data as in the flash memory writing mode. 2. in the 5th byte of the received data contains the ram loader command data (60h). 3. when th 5th byte of the received data contains the operation command data shown in table 1-6, the device echoes back the value which is the same data in the 6th byte position (in this case, 60h). if the 5th byte does not contain the operation command data, the device enters the halt condition after send- ing 3 bytes of operation command error code (63h). 4. the 7th through m?th bytes of the transmitted and received data contai n the same data as in the flash memory writing mode. 5. the m?th + 1 through n?th - 2 bytes of the received data contain the binary data in the intel hex for- mat. no received data is echoed back to the extern al controller. after receiving the start mark (3ah for ?:?) in the intel hex format, the device starts data record reception. ther efore, the received data except 3ah is ignored until the start mark is received. afte r receiving the start mark, the device receives the data record, that consists of data lengt h, address, reco rd type, write data and checksum. the writing data of the data record is written in to ram specified by address. since the device starts checksum calculation after receiving an end record, the external contro ller should wait for the check- sum after sending the end record. if a receiving error or intel hex format error occurs, the device enters the halts condition without returning an error code to the external controller. 6. the n?th - 1 and n?th bytes contain the checksum upper and lower bytes. for details on how to calcu- late the sum, refer to " 17.8 checksum (sum) ". the checksum is calculated only when the end record is detected and no receivi ng error or intel hex format er ror occurs. after sending the end record, the external controller ju dges whether the transmission is co mpleted correctly by receiving the checksum sent by the device. 7. after transmitting the checksum to the external controller, the boot program jumps to the ram address that is specified by the first received data record. note 1: to rewrite data to flash memory addresses at whic h data (including ffh) is already written, make sure to erase the existing data by "sector erase" or "chip erase" before rewriting data.
page 190 17. serial prom mode 17.6 operation mode TMP86FH12MG 17.6.4 flash memory sum out put mode (operati on command: 90h) table 17-10 shows flash memory sum output mode process. note 1: ?xxh description of the flash memory sum output mode 1. the 1st through 4th bytes of the transmitted and recei ved data contains the same data as in the flash memory writing mode. 2. the 5th byte of the received data contains the command data in the flash memory sum output mode (90h). 3. when the 5th byte of the received data contains the operation command data shown in table 1-6, the device echoes back the value which is the same data in the 6th byte position of the received data (in this case, 90h). if the 5th byte of the received da ta does not contain the op eration command data, the device enters the halt condition after transmitting 3 bytes of operation command error code (63h). 4. the 7th and the 8th bytes contain the upper and lowe r bits of the checksum, respectively. for how to calculate the checksum, refer to " 17.8 checksum (sum) ". 5. after sending the checksum, the device waits for the next operation command data. table 17-10 flash memo ry sum output process transfer bytes transfer data from external control- ler to TMP86FH12MG baud rate transfer data from TMP86FH12MG to external controller boot rom 1st byte 2nd byte matching data (5ah) - 9600 bps 9600 bps - (automatic baud rate adjustment) ok: echo back data (5ah) error: nothing transmitted 3rd byte 4th byte baud rate modification data (see table 17-4) - 9600 bps 9600 bps - ok: echo back data error: a1h
page 191 TMP86FH12MG 17.6.5 product id code output mode (operation command: c0h) table 17-11 shows product id code output mode process. note: ?xxh description of product id code output mode 1. the 1st through 4th bytes of the transmitted and r eceived data contain the same data as in the flash memory writing mode. 2. the 5th byte of the received data contains the product id code output mode command data (c0h). 3. when the 5th byte contains the operation command data shown in table 17-6, the device echoes back the value which is the same data in the 6th byte positio n of the received data (i n this case, c0h). if the 5th byte data does not contain the operation command data, the device enters the halt condition after sending 3 bytes of operation command error code (63h). 4. the 9th through 19th bytes contain the product id code. for details, refer to " 17.11 product id code ". table 17-11 product id code output process transfer bytes transfer data from external controller to TMP86FH12MG baud rate transfer data from TMP86FH12MG to external controller boot rom 1st byte 2nd byte matching data (5ah) - 9600 bps 9600 bps - (automatic baud rate adjustment) ok: echo back data (5ah) error: nothing transmitted 3rd byte 4th byte baud rate modification data (see table 17-4) - 9600 bps 9600 bps - ok: echo back data error: a1h
page 192 17. serial prom mode 17.6 operation mode TMP86FH12MG 5. after sending the checksum, the device waits for the next operation command data.
page 193 TMP86FH12MG 17.6.6 flash memory status out put mode (operati on command: c3h) table 17-12 shows flash memory status output mode process. note 1: ?xxh description of flash memory status output mode 1. the 1st through 4th bytes of the transmitted and r eceived data contain the same data as in the flash memory writing mode. 2. the 5th byte of the received data contains the flash memory status output mode command data (c3h). 3. when the 5th byte contains the operation command data shown in table 17-6, the device echoes back the value which is the same data in the 6th byte positio n of the received data (i n this case, c3h). if the 5th byte does not contain the operation command data, the device enters the halt condition after send- ing 3 bytes of operation command error code (63h). 4. the 9th through 13th bytes contain the status code. for details on the status code, refer to " 17.12 flash memory status code ". 5. after sending the status code, the device wa its for the next operation command data. table 17-12 flash memory status output mode process transfer bytes transfer data from external con- troller to TMP86FH12MG baud rate transfer data from TMP86FH12MG to exter- nal controller boot rom 1st byte 2nd byte matching data (5ah) - 9600 bps 9600 bps - (automatic baud rate adjustment) ok: echo back data (5ah) error: nothing transmitted 3rd byte 4th byte baud rate modification data (see table 17-4) - 9600 bps 9600 bps - ok: echo back data error: a1h
page 194 17. serial prom mode 17.6 operation mode TMP86FH12MG 17.6.7 flash memory read protection setting mode (operation command: fah) table 17-13 shows flash memory read protection setting mode process. note 1: ?xxh description of the flash memory read protection setting mode 1. the 1st through 4th bytes of the transmitted and r eceived data contain the same data as in the flash memory writing mode. 2. the 5th byte of the received data contains the command data in th e flash memory status output mode (fah). 3. when the 5th byte of the received data contains the operation command data shown in table 1-6, the device echoes back the value which is the same data in the 6th byte position of the received data (in table 17-13 flash memory read protection setting mode process transfer bytes transfer data from external con- troller to TMP86FH12MG baud rate transfer data from TMP86FH12MG to external controller boot rom 1st byte 2nd byte matching data (5ah) - 9600 bps 9600 bps - (automatic baud rate adjustment) ok: echo back data (5ah) error: nothing transmitted 3rd byte 4th byte baud rate modification data (see table 17-4) - 9600 bps 9600 bps - ok: echo back data error: a1h
page 195 TMP86FH12MG this case, fah). if the 5th byte does not contai n the operation command data, the device enters the halt condition after transmitting 3 bytes of operation command error code (63h). 4. the 7th through m?th bytes of the transmitted and received data contai n the same data as in the flash memory writing mode. 5. the n'th byte contains the status to be transmitted to the external controller in the case of the success- ful read protection.
page 196 17. serial prom mode 17.7 error code TMP86FH12MG 17.7 error code when detecting an error, the device tr ansmits the error code to the external controller, as shown in table 17-14. note: if a password error occurs, TMP86FH12MG does not transmit an error code. 17.8 checksum (sum) 17.8.1 calculation method the checksum (sum) is calculated with the sum of all bytes, and the obtain ed result is returned as a word. the data is read for each byte unit and th e calculated result is returned as a word. example: the checksum which is transmitted by executing the fl ash memory write comman d, ram loader command, or flash memory sum output command is calculated in the manner, as shown above. table 17-14 error code transmit data meaning of error data 62h, 62h, 62h baud rate modification error. 63h, 63h, 63h operation command error. a1h, a1h, a1h framing error in the received data. a3h, a3h, a3h overrun error in the received data. a1h if the data to be calculated consists of the four bytes, the checksum of the data is as shown below. b2h a1h + b2h + c3h + d4h = 02eah sum (high)= 02h sum (low)= eah c3h d4h
page 197 TMP86FH12MG 17.8.2 calculation data the data used to calculate the ch ecksum is listed in table 17-15. table 17-15 checksum calculation data operating mode calculation data description flash memory writing mode data in the entire area of the flash memory even when a part of the flash memory is written, the checksum of the entire flash memory area (c000h to fffh) is calcu- lated. the data length, address, record type and checksum in intel hex format are not included in the checksum. flash memory sum output mode ram loader mode ram data written in the first received ram address through the last received ram address the length of data, address, record type and checksum in intel hex format are not included in the checksum. product id code output mode 9th through 18th bytes of the transferred data for details, refer to " 17.11 product id code ". flash memory status output mode 9th through 12th bytes of the tran sferred data for details, refer to " 17.12 flash memory status code " flash memory erasing mode all data in the erased area of the flash memory (the whole or part of the flash memory) when the sector erase is exec uted, only the erased area is used to calculate the checksum. in the case of the chip erase, an entire area of the flash memory is used.
page 198 17. serial prom mode 17.9 intel hex format (binary) TMP86FH12MG 17.9 intel hex format (binary) 1. after receiving the checksum of a data record, the device waits for the start mark (3ah ?:?) of the next data record. after receiving the checksum of a data reco rd, the device ignores the data except 3ah transmitted by the external controller. 2. after transmitting the checksum of en d record, the external controller mu st transmit nothing, and wait for the 2-byte receive data (upper and lower bytes of the checksum). 3. if a receiving error or intel hex fo rmat error occurs, the device enters the halt condition without returning an error code to the external controller. the in tel hex format error occurs in the following case: when the record type is not 00h, 01h, or 02h when a checksum error occurs when the data length of an extended record (record type = 02h) is not 02h when the device receives the data reco rd after receiving an extended record (record type = 02h) with extended address of 1000h or larger. when the data length of the end record (record type = 01h) is not 00h 17.10passwords the consecutive eight or mo re-byte data in the flash memory ar ea can be specified to the password. TMP86FH12MG compares the data string specified to the password with the password string transmitted from the external controller. the area in which passwords can be specified is locat ed at addresses c000h to ff9fh. the area from ffa0h to ffffh can not be specified as the passwords area. if addresses from ffe0h through fff fh are filled with ?ffh?, the passwords are not compared because the product is considered as a blank product. even in this case, the password count stor age addresses and password comparison start address must be specified. table 17-16 shows the password setting in the blank product and non- blank product. note 1: when addresses from ffe0h through ffffh are filled wi th ?ffh?, the product is re cognized as a blank product. note 2: the data including the same consecutive data (three or mo re bytes) can not be used as a password. (this causes a pass- word error data. TMP86FH12MG transmits no data and enters the halt condition.) note 3: *: don?t care. note 4: when the above condition is not met, a password error oc curs. if a password error occurs , the device enters the halt con - dition without returning the error code. note 5: in the flash memory writing mode or ram loader mode, the blank product receives the intel hex format data immediately after receiving pcsa without receiving password strings. in this case, the subsequent processing is performed correctly because the blank product ignores the data exc ept the start mark (3ah ?:?) as the intel hex format data, even if the exter- nal controller transmits the dummy password string. however, if the dummy password string contains ?3ah?, it is detected as the start mark erroneously. the micr ocontroller enters the halt mode. if this causes the problem, do not transmit the dummy password strings. note 6: in the flash memory erasing mode, t he external controller must not transmit the password string for the blank product. table 17-16 password setting in the blank product and non-blank product password blank product (note 1) non-blank product pnsa (password count storage address) c000h
page 199 TMP86FH12MG figure 17-5 password comparison 17.10.1password string the password string transmitted from th e external controller is compared w ith the specified data in the flash memory. when the password string is not matched to the data in the flash memory, the device enters the halt condition due to the password error. 17.10.2handling of password error if a password error occurs, the device enters the halt c ondition. in this case, reset the device to reactivate the serial prom mode. 17.10.3password management during program development if a program is modified many times in the development stage, confusion may arise as to the password. therefore, it is recommended to use a fixed password in the program development stage. example :specify pnsa to f000h, and the pa ssword string to 8 bytes from address f001h (pcsa becomes f001h.) password section code abs = 0f000h db 08h : pnsa definition db ?code1234? : password string definition 08h 01h 02h 03h 04h 05h 08h f012h f107h f108h flash memory f109h f10ah f10bh f10ch uart f0h 12h f1h 07h 01h 02h 03h 04h 05h 06h 07h 08h pnsa pcsa password string 06h 07h f10dh f10eh "08h" becomes the umber of passwords 8 bytes compare example pnsa = f012h pcsa = f107h password string = 01h,02h,03h,04h,05h 06h,07h,08h rxd pin
page 200 17. serial prom mode 17.11 product id code TMP86FH12MG 17.11product id code the product id code is the 13-byte data containing the start address and the end address of rom. table 17-17 shows the product id code format. 17.12flash memory status code the flash memory status code is the 7-byte data including the read protection status and the status of the data from ffe0h to ffffh. table 17-18 shows the flash memory status code. table 17-17 product id code format data description in the case of TMP86FH12MG 1st start mark (3ah) 3ah 2nd the number of transfer data (10 bytes from 3rd to 12th byte) 0ah 3rd address length (2 bytes) 02h 4th reserved data 1dh 5th reserved data 00h 6th reserved data 00h 7th reserved data 00h 8th rom block count 01h 9th the first address of rom (upper byte) c0h 10th the first address of rom (lower byte) 00h 11th the end address of rom (upper byte) ffh 12th the end address of rom (lower byte) ffh 13th checksum of the transferred data (2?s compliment for the sum of 3rd through 12th bytes) 22h table 17-18 flash memory status code data description in the case of TMP86FH12MG 1st start mark 3ah 2nd transferred data count (3rd through 6th byte) 04h 3rd status code 00h to 03h (see figure below) 4th reserved data 00h 5th reserved data 00h 6th reserved data 00h 7th checksum of the transferred data (2?s compliment for the sum of 3rd through 6th data) 3rd byte 00h 01h 02h 03h checksum 00h ffh feh fdh status code 1 76543210 rpena blank (initial value: 0000 00**)
page 201 TMP86FH12MG some operation commands are limited by the flash memory stat us code 1. if the read pr otection is enabled, flash memory writing mode command and ram loader mode co mmand can not be executed. erase all flash memory before executing these command. note: m : the command can be executed. pass: the command can be executed with a password. mmmmmm mmm pass pass 10 mmmm mmm pass
page 202 17. serial prom mode 17.13 specifying the erasure area TMP86FH12MG 17.13specifying the erasure area in the flash memory erasing mode, the erasure area of the flas h memory is specified by n ? 2 byte data. the start address of an erasure area is specified by erasta, and the end address is specified by eraend. if erasta is equal to or smaller than eraend, the sector erase (erasure in 4 kbyte units) is executed. executing the sector erase while the read protection is enabled results in an infinite loop. if erasta is larger than eraend, th e chip erase (erasure of an entire flash memory area) is executed and the read protection is disabled. therefore, execute the chip erase (not sector erase) to disable the read protection. note: when the sector erase is executed for the area contai ning no flash cell, TMP86FH12MG stops the uart communi- cation and enters the halt condition. 17.14port input control register in the serial prom mode, the input level is fixed to the all ports except p00 and p01 ports with a hardware feature to prevent overlap current to unused ports. (all port inpu ts and peripheral function inputs shared with the ports become invalid.) therefore, to access to the flash memory in the ram load er mode without uart communication, port inputs must be valid. to make port inputs valid, set the pin of the port input contro l register (spcr) to ?1?. the spcr register is not operated in the mcu mode. erasure area specification data (n ?
page 203 TMP86FH12MG note 1: the spcr register can be read or written only in the seri al prom mode. when the write instruction is executed to the spcr register in the mcu mode, the port input control can not be performed. when the read instruction is executed for the spcr register in the mcu mode, read data of bit7 to 1 are unstable. note 2: all i/o ports except p00 and p01 po rts are controlled by the spcr register. port input control register spcr (0feah) 76543210 pin (initial value: **** ***0) pin port input control in the serial prom mode 0 : invalid port inputs (the input level is fixed with a hardware feature.) 1 : valid port inputs r/w
page 204 17. serial prom mode 17.15 flowchart TMP86FH12MG 17.15flowchart start setup receive uart data receive data = 5ah adjust the baud rate (adjust the source clock to 9600 bps) no yes transmit uart data (transmit data = 5ah) receive uart data modify the baud rate based on the receive data receive data = 30h (flash memory writing mode) receive data = 60h (ram loader mode) receive uart data (intel hex format) transmit uart data (checksum of an entire area) receive uart data transmit uart data (transmit data = 60h) receive uart data (intel hex format) jump to the start address of ram program transmit uart data (checksum of an entire area) receive data = c0h (product id code output mode) transmit uart data (transmit data = c0h) flash memory write process ram write process transmit uart data (product id code) transmit uart data (echo back the baud rate modification data) verify the password (compare the receive data and flash memory data) read protection check protection disabled read protection check protection disabled infinite loop infinite loop ng protection enable ng receive data = c3h (flash memory status output mode) transmit uart data (transmit data = c3h) receive data = f0h (flash memory erasing mode) transmit uart data (transmit data = f0h) infinite loop ng chip erase (erase on entire area) transmit uart data (checksum of an entire area) receive data = fah (read protection setting mode) transmit uart data (transmit data = fah) read protection setting read protection check blank product check infinite loop ng blank product check blank product check non-blank product non-blank product ok blank product ok blank product check non-blank product ok ok blank product check non-blank product blank product protection enable blank product disable read protection blank product receive uart data receive data sector erase (block erase) upper 4 bits x 1000h to lower 4 bits x 1000h transmit uart data (checksum of the erased area) upper 4 bits > lower 4 bits transmit uart data (transmit data = 30h) transmit uart data (transmit data = 90h) receive data = 90h (flash memory sum output mode) verify the password (compare the receive data and flash memory data) transmit uart data (checksum) verify the password (compare the receive data and flash memory data) verify the password (compare the receive data and flash memory data) transmit uart data (status of the read protection and blank product) transmit uart data (transmit data = fbh) read protection check upper 4 bits < lower 4 bits protection enabled infinite loop protection disabled
page 205 TMP86FH12MG 17.16uart timing table 17-19 uart timing-1 (vdd = 4.5 to 5.5 v, fc = 2 to 16 mhz, topr = -10 to 40c) parameter symbol clock frequency (fc) minimum required time at fc = 2 mhz at fc = 16 mhz time from matching data reception to the echo back cmeb1 approx. 930 465 reset pin rxd pin rxsup (5ah) cmeb1 (5ah) cmtr2 (28h) (28h) cmeb2 cmtr3 (30h) (30h) cmeb3 cmtr4 txd pin rxd pin txd pin (5ah) (5ah) (5ah) cmtr1
page 206 17. serial prom mode 17.16 uart timing TMP86FH12MG
page 207 TMP86FH12MG 18. input/output circuit 18.1 control pins the input/output circuitries of the TMP86FH12MG control pins are shown below. control pin i/o input/output circuitry remarks xin xout input output resonator connecting pins (high frequency) r f = 1.2 m ? ? ? ? ? ? ? fc r f r o osc.enable xin xout vdd vdd fs r f r o osc.enable xtin xtout vdd xten vdd address-trap-reset watchdog-timer-reset system-clock-reset r r in vdd r vdd
page 208 18. input/output circuit 18.2 input/output ports TMP86FH12MG 18.2 input/output ports port i/o input/output circuitry remarks p0 i/o sink open drain output or tri-state output hysteresis input high current output r = 100 ? ? ? ? initial "high-z" disable data output pin input vdd r pch control input from output latch +pkvkcn"*kij<" &kucdng &cvcqwvrwv 2kpkprwv vdd r vdd r initial "high-z" data output input from output latch pin input data output disable vdd r initial "high-z" input from output latch analog input pin input
page 209 TMP86FH12MG 19. electrical characteristics 19.1 absolute maximum ratings the absolute maximum ratings are rated values, which must not be exceeded during oper ation, even for an instant. any one of the ratings must not be exceeded. if any absolute maximum ra ting is exceeded, a device may break down or its performance may be degraded, causi ng it to catch fire or ex plode resulting in injury to the user. thus, when designing products which include this de vice, ensure that no absolute maximum rating value will ever be exceeded. 19.2 recommended op erating condition the recommended operating co nditions for a device are operating conditions under which it can be guaranteed that the device will operate as specified. if the device is used under operating conditions other than the recommended operating conditions (supply voltage, operating temperature range, specified ac/dc values etc.), malfunction may occur. thus, when designing products which include this device, ensure that the recommended operating conditions for the device are always adhered to. 19.2.1 mcu mode (flash me mory writing and erasing) (v ss = 0 v) parameter symbol pins rating unit supply voltage vdd -0.3 to 6.5 v input voltage vin1 -0.3 to vdd+0.3 output voltage vout -0.3 to vdd+0.3 output current (per 1 pin) iout1 p0, p1, p3 ports ? ? ? ? ?
page 210 19. electrical characteristics 19.2 recommended operating condition TMP86FH12MG 19.2.2 mcu mode (except flas h memory writing and erasing) note: the operating temperature(topr) must not exceed the range between -20 to 85 ? ?
page 211 TMP86FH12MG 19.3 dc characteristics note 1: typical values show those at topr = 25 ? ? n program coutner (pc) n+1 n+2 n+3 1 machine cycle (4/fc or 4/fs) mcu current i [ma] ddp-p typ. current momentary flash current max. current sum of average momentary flash current and mcu current
page 212 19. electrical characteristics 19.4 ad conversion characteristics TMP86FH12MG 19.4 ad conversi on characteristics note 1: the total error includes all errors except a quantizati on error, and is defined as a maximum deviation from the ideal co n- version line. note 2: conversion time is different in recommended value by power supply voltage. about conversion time, please refer to ?10-bit ad converter (adc)?. note 3: please use input voltage to ain input pin in limit of v dd ? ? ? ? ? ? ?
page 213 TMP86FH12MG 19.6 flash characteristics parameter condition min typ. max unit number of guaranteed writes to flash memory v ss = 0 v, topr = ?
page 214 19. electrical characteristics 19.7 recommended oscillating conditions TMP86FH12MG 19.7 recommended osc illating conditions note 1: to ensure stable oscillation, the re sonator position, load capacitance, etc. must be appropriate. because these factors are greatly affected by board patterns, please be sure to evaluate operation on the board on which the device will actually be mounted. note 2: for the resonators to be used with toshiba microcontroll ers, we recommend ceramic resonators manufactured by murata manufacturing co., ltd. for details, please visit the website of murata at the following url: http://www.murata.co m 19.8 handling precaution - the solderability test conditions for lead-free produc ts (indicated by the suffix g in product name) are shown below. 1. when using the sn-37pb solder bath solder bath temperature = 230 c dipping time = 5 seconds number of times = once r-type flux used 2. when using the sn-3.0ag-0.5cu solder bath solder bath temperature = 245 c dipping time = 5 seconds number of times = once r-type flux used note: the pass criteron of the above test is as follows: solderability rate until forming 95 % - when using the device (oscillator) in places exposed to high electric fields such as cathode-ray tubes, we recommend electrically shielding the package in order to maintain normal operating condition. xin xout c 2 c 1 xtin (1) high-frequency oscillation (2) low-frequency oscillation xtout c 2 c 1
page 215 TMP86FH12MG 20. package dimension p-ssop30-56-0.65 unit: mm
page 216 20. package dimension TMP86FH12MG
this is a technical document that de scribes the operating functi ons and electrical specif ications of the 8-bit microcontroller series tlcs-870/c (lsi). toshiba provides a variety of development tools a nd basic software to enable efficient software development. these development tools have specifi cations that support advances in microcomputer hardware (lsi) and can be used extensively. both the hardware and so ftware are supported continuous ly with version updates. the recent advances in cmos lsi production technology have be en phenomenal and microcomputer systems for lsi design are constant ly being improved. the products described in this document may also be revised in the future. be sure to check the latest specific ations before using. toshiba is developing highly integrated, high-perfo rmance microcomputers using advanced mos production technology and especially well proven cmos technology. we are prepared to meet the requests for custom packaging for a variet y of application areas. we are confident that our products can satisfy your application needs now and in the future.

▲Up To Search▲

Price & Availability of TMP86FH12MG

	To Download TMP86FH12MG Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .