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| silego technology, inc. rev 1.14 SLG46533_ds_114 revised october 12, 2017 greenpak programmable mixed-signal matrix SLG46533 block diagram features ? logic & mixed signal circuits ? highly versatile macrocells ? read back protection (read lock) ? 1.8 v (5%) to 5 v (10%) supply ? operating temperature range: -40c to 85c ? rohs compliant / halogen-free ? 20-pin stqfn: 2 x 3 x 0 .55 mm, 0.4 mm pitch or 22-pin mstqfn 2 x 2.2 x 0.55 mm, 0.4 mm pitch applications ? personal computers and servers ? pc peripherals ? consumer electronics ? data communications equipment ? handheld and portable electronics available package options stqfn-20 (top view) mstqfn-22 (top view) packages drawn to scale 2 mm 2.2 mm 2 mm 3 mm 3-bit lut3_4 or dff7 programmable delay rc oscillator acmp0 acmp1 acmp2 acmp3 additional logic functions combination function macrocells 2-bit lut2_0 or dff0 2-bit lut2_2 or dff2 2-bit lut2_1 or dff1 3bit lut3_0 or dff3 3-bit lut3_2 or dff5 3-bit lut3_1 or dff4 3-bit lut3_12 or dff9 3-bit lut3_11 or dff8 filter_1 with edge detect por i 2 c serial communication 3-bit lut3_5 or cnt/dly2 3-bit lut3_6 or cnt/dly3 3-bit lut3_7 or cnt/dly4 3-bit lut3_8 or cnt/dly5 3-bit lut3_9 or cnt/dly6 3-bit lut3_10 or pipe delay 16x8 ram memory with defined nvm otp initial state 4-bit lut lut4_2 3-bit lut3_14 or dff11 3-bit lut3_16 or dff13 3-bit lut3_15 or dff12 2-bit lut2_3 or pgen 3-bit lut3_3 or dff6 3-bit lut3_13 or dff10 3-bit lut3_17 or dff14 4-bit lut4_0 or cnt/dly0 4-bit lut4_1 or cnt/dly1 vref crystal oscillator 25m oscillator io4 io5 vdd io0 io1 io2 io3 io9 gnd io14 io13 io12 io11 io10 io6 io7 io8 io17 io16 io15 filter_0 with edge detect
SLG46533_ds_114 page 1 of 184 SLG46533 1.0 overview the SLG46533 provides a small, low power component for commonly used mixed-signal functions. the user creates their circuit design by programming the one time non-volatile memory (nvm) to configure the interconnect logic, the i/o pins and the macrocells of the SLG46533. this highly versatile device allows a wide variety of mixed-signal functions to be designed within a very small, low power single in tegrated circuit. the macrocells in the device include the following: ? four analog comparators (acmp) ? two voltage references (vref) ? twenty-six combination function macrocells ? three selectable dff/latch or 2-bit luts ? twelve selectable dff/latch or 3-bit luts ? one selectable pipe delay or 3-bit lut ? one selectable programmable pattern generator or 2-bit lut ? five 8-bit delays/co unters or 3-bit luts ? two 16-bit delays/co unters or 4-bit luts ? two deglitch filters with edge detectors ? combinatorial logic ? one 4-bit lut ? serial communications ?i 2 c protocol compliant ? 16x8 ram memory w ith defined nvm otp initial state ? pipe delay C 16 sta ge/3 output (part of c ombination function m acrocell) ? programmable delay ? two oscillators (osc) ? configurable 25 khz/2 mhz ? 25 mhz rc oscillator ? crystal oscillator ? power-on-reset (por) ? analog temperature sensor SLG46533_ds_114 page 2 of 184 SLG46533 2.0 pin description 2.1 functional pin description stqfn 20l pin # mstqfn 22l pin# pin name signal name function input options output options 1 16 vdd vdd power supply -- -- 2 1 io0 io0 general purpose input digital input without schmitt trigger -- digital input with schmitt trigger -- low voltage digital input -- 3 2 io1 io1 general purpose i/o with oe* digital input without schmitt trigger push-pull (1x) (2x) digital input with schmitt trigger open drain nmos (1x) (2x) low voltage digital input -- 4 3 io2 io2 general purpose i/o digital input without schmitt trigger push-pull (1x) (2x) digital input with schmitt trigger open drain nmos (1x) (2x) low voltage digital input open drain pmos (1x) (2x) 5 4 io3 io3 general purpose i/o with oe* digital input without schmitt trigger push-pull (1x) (2x) digital input with schmitt trigger open drain nmos (1x) (2x) low voltage digital input -- 6 5 io4 io4 general purpose i/o digital input without schmitt trigger push-pull (1x) (2x) digital input with schmitt trigger open drain nmos (1x) (2x) low voltage digital input open drain pmos (1x) (2x) acmp0+ analog comparator 0 positive input analog -- 7 6 io5 io5 general purpose i/o with oe* digital input without schmitt trigger push-pull (1x) (2x) digital input with schmitt trigger open drain nmos (1x) (2x) low voltage digital input -- acmp0- analog comparator 0 negative input analog -- SLG46533_ds_114 page 3 of 184 SLG46533 8 19 io6 io6 general purpose i/o with oe* digital input without schmitt trigger open drain nmos (1x) (2x) digital input with schmitt trigger -- low voltage digital input -- scl i 2 c serial clock digital input without schmitt trigger open drain nmos digital input with schmitt trigger open drain nmos low voltage digital input open drain nmos 9 7 io7 io7 general purpose i/o digital input without schmitt trigger open drain nmos (1x) (2x) digital input with schmitt trigger -- low voltage digital input -- sda i 2 c serial data digital input without schmitt trigger open drain nmos digital input with schmitt trigger open drain nmos low voltage digital input open drain nmos 10 8 io8 io8 general purpose i/o with oe* digital input without schmitt trigger push-pull (1x) (2x) digital input with schmitt trigger open drain nmos (1x) (2x) (4x) low voltage digital input open drain pmos (1x) (2x) acmp1+ analog comparator 1 positive input analog -- 11 20 gnd gnd ground -- -- 12 21 io9 io9 general purpose i/o digital input without schmitt trigger push-pull (1x) (2x) digital input with schmitt trigger open drain nmos (1x) (2x) (4x) low voltage digital input -- ext_vref analog comparator negative input analog -- 13 11 io10 io10 general purpose i/o with oe* digital input without schmitt trig- ger push-pull (1x) (2x) digital input with schmitt trigger open drain nmos (1x) (2x) low voltage digital input -- acmp2+ analog comparator 2 positive input analog -- acmp3+ analog comparator 3 positive input analog -- stqfn 20l pin # mstqfn 22l pin# pin name signal name function input options output options SLG46533_ds_114 page 4 of 184 SLG46533 14 12 io11 io11 general purpose i/o with oe* digital input without schmitt trig- ger push-pull (1x) (2x) digital input with schmitt trigger open drain nmos (1x) (2x) low voltage digital input -- acmp2- analog comparator 2 negative input analog -- acmp3- analog comparator 3 negative input analog -- 15 22 io12 io12 general purpose i/o digital input without schmitt trigger push-pull (1x) (2x) digital input with schmitt trigger open drain nmos (1x) (2x) low voltage digital input open drain pmos (1x) (2x) acmp3+ analog comparator 3 positive input analog -- 16 13 io13 io13 general purpose i/o with oe* digital input without schmitt trigger push-pull (1x) (2x) digital input with schmitt trigger open drain nmos (1x) (2x) low voltage digital input -- acmp3+ analog comparator 3 positive input analog -- xtal0 external crystal connection 0 -- analog 17 14 io14 io14 general purpose i/o digital input without schmitt trigger push-pull (1x) (2x) digital input with schmitt trigger open drain nmos (1x) (2x) low voltage digital input open drain pmos (1x) (2x) xtal1 external crystal connection 1 analog -- ext_clk0 external clock connection 0 digital input without schmitt trigger -- digital input with schmitt trigger -- low voltage digital input -- stqfn 20l pin # mstqfn 22l pin# pin name signal name function input options output options SLG46533_ds_114 page 5 of 184 SLG46533 18 18 io15 io15 general purpose i/o with oe* digital input without schmitt trig- ger push-pull (1x) (2x) digital input with schmitt trigger open drain nmos (1x) (2x) low voltage digital input -- vref0 voltage reference 0 output -- analog ext_clk1 external clock connection 1 digital input without schmitt trigger -- digital input with schmitt trigger -- low voltage digital input -- 19 15 io16 io16 general purpose i/o with oe* digital input without schmitt trigger push-pull (1x) (2x) digital input with schmitt trigger open drain nmos (1x) (2x) low voltage digital input -- vref0 voltage reference 0 out- put -- analog 20 17 io17 io17 general purpose i/o digital input without schmitt trig- ger push-pull (1x) (2x) digital input with schmitt trigger open drain nmos (1x) (2x) low voltage digital input open drain pmos (1x) (2x) ext_clk2 external clock connec- tion 2 digital input without schmitt trig- ger -- digital input with schmitt trigger -- low voltage digital input -- -- 9 nc nc no connection -- -- -- 10 nc nc no connection -- -- note: * general purpose i/o's with oe can be used to implement bidirectional signals under user control via connection matrix to oe signal in i/o structure stqfn 20l pin # mstqfn 22l pin# pin name signal name function input options output options SLG46533_ds_114 page 6 of 184 SLG46533 2.2 pin configuration - stqfn20l 2.3 pin configuration - mstqfn-22l io11 io12 io13 io14 io2 io1 2 3 414 15 16 17 io0 vdd 1 stqfn-20 (top view) io4 io3 5 6 io9 io10 12 13 io5 7 gnd 11 io7 io6 8 9 io8 10 io16 io15 18 19 io17 20 pin # signal name pin functions 1vdd 2 io0 gpi 3 io1 gpio with oe 4 io2 gpio 5 io3 gpio with oe 6 io4 gpio / acmp0+ 7 io5 gpio with oe / acmp0- 8 io6 gpio / scl 9 io7 gpio / sda 10 io8 gpio with oe/ acmp1+ 11 gnd gnd 12 io9 gpio / acmp0- / acmp1- / acmp2- / acmp3- 13 io10 gpio with oe / acmp2+ / acmp3+ 14 io11 gpio with oe / acmp2- / acmp3- 15 io12 gpio with oe / acmp3+ 16 io13 gpio with oe / acmp3+ / xtal0 17 io14 gpio with oe / xtal1 / ext_clk0 18 io15 gpio with oe / vref0 / ext_clk1 19 io16 gpio with oe / vref0 20 io17 gpio with oe / ext_clk2 nc io10 io11 io13 io3 io2 2 3 410 11 12 13 io1 io0 1 mstqfn-22l (top view) io4 5 nc 9 io7 io5 6 7 io8 8 io16 io14 14 15 vdd 16 20 21 22 19 18 17 gnd io6 io15 io17 20 19 18 17 io12 io9 22 21 pin # signal name pin functions 1 io0 gpi 2 io1 gpio with oe 3 io2 gpio 4 io3 gpio with oe 5 io4 gpio / acmp0+ 6 io5 gpio with oe 7 io7 gpio / sda 8 io8 gpio with oe/ acmp1+ 9nc 10 nc 11 io10 gpio with oe / acmp2+ / acmp3+ 12 io11 gpio with oe / acmp2- / acmp3- 13 io13 gpio with oe / acmp3+ / xtal0 14 io14 gpio with oe / xtal1 / ext_clk0 15 io16 gpio with oe / vref0 16 vdd 17 io17 gpio with oe / ext_clk2 18 io15 gpio with oe / vref0 / ext_clk1 19 io6 gpio / scl 20 gnd gnd 21 io9 gpio / acmp0- / acmp1- / acmp2- / acmp3- 22 io12 gpio with oe / acmp3+ oe : output enable acmpx+ : acmpx positive input acmpx- : acmpx negative input scl/od : i 2 c clock input/ nmos open drain output only sda/od : i 2 c data input/ nmos open drain output only vrefx : voltage reference output ext_clkx : external clock input legend: SLG46533_ds_114 page 7 of 184 SLG46533 3.0 user programmability the SLG46533 is a user programmable device with one-time-progra mmable (otp) memory elements that are able to construct combinatorial logic elements. three of the i/o pins provide a c onnection for the bit patterns into the otp on board memory. a programming development kit allows the user the ability to crea te initial devices. once the design is finalized, the programmi ng code (.gpx file) is forwarded to silego to integrate into a pro duction process. figure 1. steps to create a cu stom silego greenpak device 3 u r g x f w ' h i l q l w l r q & x v w r p h u & u h d w h v w k h l u r z q g h v l j q l q * u h h q 3 $ . ' h v l j q h u 3 u r j u d p ( q j l q h h u l q j 6 d p s o h v z l w k * u h h q 3 $ . 3 u r j u d p p h u & x v w r p h u y h u l i l h v * u h h q 3 $ . l q v \ v w h p g h v l j q ( p d l o j s [ i l o h w r * u h h q 3 $ . # v l o h j r f r p ( p d l o 3 u r g x f w , g h d ' h i l q l w l r q ' u d z l q j r u 6 f k h p d w l f w r * u h h q 3 $ . # v l o h j r f r p 6 l o h j r $ s s o l f d w l r q v ( q j l q h h u v z l o o u h y l h z g h v l j q v s h f l i l f d w l r q v z l w k f x v w r p h u 6 d p s o h v d q g ' h v l j q & k d u d f w h u l ] d w l r q 5 h s r u w v h q w w r f x v w r p h u & x v w r p h u y h u l i l h v * u h h q 3 $ . g h v l j q & x v w r p * u h h q 3 $ . s d u w h q w h u v s u r g x f w l r q * u h h q 3 $ . ' h v l j q d s s u r y h g l q v \ v w h p w h v w * u h h q 3 $ . ' h v l j q d s s u r y h g * u h h q 3 $ . ' h v l j q d s s u r y h g SLG46533_ds_114 page 8 of 184 SLG46533 4.0 ordering information part number type SLG46533v 20-pin stqfn SLG46533vtr 20-pin stqfn - tape and reel (3k units) SLG46533m 22-pin mstqfn SLG46533mtr 22-pin mstqfn - tape and reel (3k units) SLG46533_ds_114 page 9 of 184 SLG46533 5.0 electrical specifications 5.1 absolute maximum conditions 5.2 electrical charac teristics (1.8 v 5% v dd ) parameter min. max. unit supply voltage on vdd relative to gnd -0.5 7 v dc input voltage gnd - 0.5 vdd + 0.5 v maximum average or dc current (through pin) push-pull 1x -- 11 ma push-pull 2x -- 16 od 1x -- 11 od 2x -- 21 od 4x -- 43 current at input pin -1.0 1.0 ma storage temperature range -65 150 c junction temperature -- 150 c esd protection (human body model) 2000 -- v esd protection (charged device model) 1300 -- v moisture sensitivity level 1 symbol parameter condition/note min. typ. max. unit v dd supply voltage 1.71 1.80 1.89 v t a operating temperature -40 25 85 c v pp programming voltage 7.25 7.50 7.75 v v acmp acmp input voltage range positive input 0 -- v dd v negative input 0 -- 1.2 v v ih high-level input voltage logic input 1.06 -- v dd v logic input with schm itt trigger 1.28 -- v dd v low-level logic input 0.94 -- v dd v v il low-level input voltage logic input 0 -- 0.76 v logic input with schm itt trigger 0 -- 0.49 v low-level logic input 0 -- 0.52 v v hys schmitt trigger hysteresis voltage logic input with schmit t trigger 0.10 0.41 0.66 v i lkg input leakage (absolute value) -- 1 1000 na v oh high-level output voltage push-pull, i oh = 100 ? a, 1x drive 1.69 1.79 -- v pmos od, i oh = 100 ? a, 1x drive 1.69 1.79 -- v push-pull, i oh = 100 ? a, 2x drive 1.70 1.79 -- v pmos od, i oh = 100 ? a, 2x drive 1.70 1.79 -- v SLG46533_ds_114 page 10 of 184 SLG46533 v ol low-level output voltage push-pull, i ol = 100 ? a, 1x drive -- 0.009 0.013 v push-pull, i ol = 100 ? a, 2x drive -- 0.004 0.006 v open drain, i ol = 100 ? a, 1x drive -- 0.006 0.009 v open drain, i ol = 100 ? a, 2x drive -- 0.003 0.004 v open drain nmos 4x, i ol = 100 ? a -- 0.001 0.002 v i oh high-level output pulse current (see note 1) push-pull, v oh = v dd - 0.2, 1x drive 1.07 1.70 -- ma pmos od, v oh = v dd - 0.2, 1x drive 1.07 1.70 -- ma push-pull, v oh = v dd - 0.2, 2x drive 2.22 3.41 -- ma pmos od, v oh = v dd - 0.2, 2x drive 2.22 3.41 -- ma i ol low-level output pulse current (see note 1) push-pull, v ol = 0.15 v, 1x drive 0.92 1.69 -- ma push-pull, v ol = 0.15 v, 2x drive 1.83 3.38 -- ma open drain, v ol = 0.15 v, 1x drive 1.38 2.53 -- ma open drain, v ol = 0.15 v, 2x drive 2.75 5.07 -- ma open drain nmos 4x, v ol = 0.15 v 7.21 9.00 -- ma i vdd maximum average or dc current through vdd pin (per chip side, see note 2) t j = 85c -- -- 45 ma t j = 110c -- -- 22 ma i gnd maximum average or dc current through gnd pin (per chip side, see note 2) t j = 85c -- -- 86 ma t j = 110c -- -- 41 ma v o maximal voltage applied to any pin in high-impedance state -- -- v dd v t su startup time from vdd rising past pon thr 0.67 1.38 2.03 ms pon thr power on threshold v dd level required to start up the chip 1.39 1.55 1.68 v poff thr power off threshold v dd level required to switch off the chip 1.01 1.17 1.35 v r pup pull up resistance 1 m pull up 859.8 1097.1 1358.9 k ? 100 k pull up 86.47 110.13 136.18 k ? 10 k pull up 10.82 12.86 15.36 k ? r pdwn pull down resistance 1 m pull down 873.9 1097.0 1359.0 k ? 100 k pull down 88.89 110.53 136.55 k ? 10 k pull down 9.65 12.75 15.76 k ? note 1: dc or average current through any pin should not exceed value given in absolute maximum conditions. note 2: the greenpak?s power rails are divided in two sides. ios 0, 1, 2, 3, 4, 5, 6, 7 and 8 are connected to one side, ios 9, 10, 11, 12, 13, 14, 15, 16 and 17 to another. symbol parameter condition/note min. typ. max. unit SLG46533_ds_114 page 11 of 184 SLG46533 5.3 electrical charac teristics (3.3 v 10% v dd ) symbol parameter condition/note min. typ. max. unit v dd supply voltage 3.0 3.3 3.6 v t a operating temperature -40 25 85 c v pp programming voltage 7.25 7.50 7.75 v v acmp acmp input voltage range positive input 0 -- v dd v negative input 0 -- 1.2 v v ih high-level input voltage logic input 1.81 -- v dd v logic input with schm itt trigger 2.14 -- v dd v low-level logic input 1.06 -- v dd v v il low-level input voltage logic input 0 -- 1.31 v logic input with schm itt trigger 0 -- 0.97 v low-level logic input 0 -- 0.67 v v hys schmitt trigger hysteresis voltage logic input with schmit t trigger 0.29 0.62 0.94 v i lkg input leakage (absolute value) -- 1 1000 na v oh high-level output voltage push-pull, i oh = 3 ma, 1x drive 2.70 3.12 -- v pmos od, i oh = 3 ma, 1x drive 2.70 3.12 -- v push-pull, i oh = 3 ma, 2x drive 2.85 3.21 -- v pmos od, i oh = 3 ma, 2x drive 2.86 3.21 -- v v ol low-level output voltage push-pull, i ol = 3 ma, 1x drive -- 0.13 0.23 v push-pull, i ol = 3 ma, 2x drive -- 0.06 0.11 v open drain, i ol = 3 ma, 1x drive -- 0.08 0.15 v open drain, i ol = 3 ma, 2x drive -- 0.04 0.08 v open drain nmos 4x, i ol = 3 ? ma -- 0.02 0.04 v i oh high-level output pulse current (see note 1) push-pull, v oh = 2.4 v, 1x drive 6.05 12.08 -- ma pmos od, v oh = 2.4 v, 1x drive 6.05 12.08 -- ma push-pull, v oh = 2.4 v, 2x drive 11.54 24.16 -- ma pmos od, v oh = 2.4 v, 2x drive 11.52 24.16 -- ma i ol low-level output pulse current (see note 1) push-pull, v ol = 0.4 v, 1x drive 4.88 8.24 -- ma push-pull, v ol = 0.4 v, 2x drive 9.75 16.49 -- ma open drain, v ol = 0.4 v, 1x drive 7.31 12.37 -- ma open drain, v ol = 0.4 v, 2x drive 14.54 24.74 -- ma open drain nmos 4x, v ol = 0.4 v 31.32 41.06 -- ma i vdd maximum average or dc current through vdd pin (per chip side, see note 2) t j = 85c -- -- 45 ma t j = 110c -- -- 22 ma i gnd maximum average or dc current through gnd pin (per chip side, see note 2) t j = 85c -- -- 86 ma t j = 110c -- -- 41 ma SLG46533_ds_114 page 12 of 184 SLG46533 v o maximal voltage applied to any pin in high-impedance state -- -- v dd v t su startup time from vdd rising past pon thr 0.78 1.27 1.87 ms pon thr power on threshold v dd level required to start up the chip 1.39 1.55 1.68 v poff thr power off threshold v dd level required to switch off the chip 1.01 1.17 1.35 v r pup pull up resistance 1 m pull up 873.2 1094.7 1364.3 k ? 100 k pull up 85.17 109.30 135.52 k ? 10 k pull up 9.61 11.86 14.73 k ? r pdwn pull down resistance 1 m pull down 862.5 1096.3 1357.4 k ? 100 k pull down 87.95 109.76 136.06 k ? 10 k pull down 8.66 11.81 15.05 k ? note 1: dc or average current through any pin should not exceed value given in absolute maximum conditions. note 2: the greenpak?s power rails are divided in two sides. ios 0, 1, 2, 3, 4, 5, 6, 7 and 8 are connected to one side, ios 9, 10, 11, 12, 13, 14, 15, 16 and 17 to another. symbol parameter condition/note min. typ. max. unit SLG46533_ds_114 page 13 of 184 SLG46533 5.4 electrical charac teristics (5 v 10% v dd ) symbol parameter condition/note min. typ. max. unit v dd supply voltage 4.5 5.0 5.5 v t a operating temperature -40 25 85 c v pp programming volt age 7.25 7.50 7.75 v v acmp acmp input voltage range positive input 0 -- v dd v negative input 0 -- 1.2 v v ih high-level i nput voltage logic input 2.68 -- v dd v logic input with schmitt trigger 3.34 -- v dd v low-level logic input 1.15 -- v dd v v il low-level input voltage logic input 0 -- 1.96 v logic input with schmitt trigger 0 -- 1.41 v low-level logic input 0 -- 0.77 v v hys schmitt trigger hysteresis voltage logic input with schmitt trigger 0.44 0.90 1.38 v i lkg input leakage (absolute value) -- 1 1000 na v oh high-level output voltage push-pull, i oh = 5 ma, 1x drive 4.15 4.76 -- v pmos od, i oh = 5 ma, 1x drive 4.16 4.76 -- v push-pull, i oh = 5 ma, 2x drive 4.32 4.89 -- v pmos od, i oh = 5 ma, 2x drive 4.33 4.89 -- v v ol low-level output voltage push-pull, i ol = 5 ma, 1x drive -- 0.19 0.24 v push-pull, i ol =5 ma, 2x drive -- 0.09 0.12 v open drain, i ol = 5 ma, 1x drive -- 0.12 0.16 v open drain, i ol = 5 ma, 2x drive -- 0.07 0.08 v open drain nmos 4x, i ol = 5 ma -- 0.03 0.05 v i oh high-level output pulse current (see note 1) push-pull, v oh = 2.4 v, 1x drive 22.08 34.04 -- ma pmos od, v oh = 2.4 v, 1x drive 22.08 34.04 -- ma push-pull, v oh = 2.4 v, 2x drive 41.76 68.08 -- ma pmos od, v oh = 2.4 v, 2x drive 41.69 68.08 -- ma i ol low-level output pulse current (see note 1) push-pull, v ol = 0.4 v, 1x drive 7.22 11.58 -- ma push-pull, v ol = 0.4 v, 2x drive 13.83 23.16 -- ma open drain, v ol = 0.4 v, 1x drive 10.82 17.38 -- ma open drain, v ol = 0.4 v, 2x drive 17.34 34.76 -- ma open drain nmos 4x, v ol = 0.4 v 41.06 55.18 -- ma i vdd maximum average or dc current through vdd pin (per chip side, see note 2) t j = 85c -- -- 45 ma t j = 110c -- -- 22 ma i gnd maximum average or dc current through gnd pin (per chip side, see note 2) t j = 85c -- -- 86 ma t j = 110c -- -- 41 ma SLG46533_ds_114 page 14 of 184 SLG46533 5.5 i 2 c specifications v o maximal voltage applied to any pin in high-impedance state -- -- v dd v t su startup time from v dd rising past pon thr 0.77 1.24 1.91 ms pon thr power on threshold v dd level required to start up the chip 1.39 1.55 1.68 v poff thr power off threshold v dd level required to switch off the chip 1.01 1.17 1.35 v r pup pull up resistance 1 m pull up 864.6 1093.4 1348.1 k ? 100 k pull up 84.32 108.97 135.24 k ? 10 k pull up 8.74 11.37 14.52 k ? r pdwn pull down resistance 1 m pull down 873.3 1096.1 1370.5 k ? 100 k pull down 87.57 109.48 135.89 k ? 10 k pull down 7.95 11.33 14.78 k ? note 1: dc or average current through any pin should not exceed value given in absolute maximum conditions. note 2: the greenpak?s power rails are divided in two sides. ios 0, 1, 2, 3, 4, 5, 6, 7 and 8 are connected to one side, ios 9, 10, 11, 12, 13, 14, 15, 16 and 17 to another. symbol parameter condition/note min. typ. max. unit f scl clock frequency, scl v dd = (1.71...5.5) v -- -- 400 khz t low clock pulse width low v dd = (1.71...5.5) v 1300 ns t high clock pulse width high v dd = (1.71...5.5) v 600 -- -- ns t i input filter spike suppression (scl, sda) v dd = 1.8 v 5 % -- -- 95 ns v dd = 3.3 v 10% 95 v dd = 5.0 v 10 % 111 t aa clock low to data out valid v dd = (1.71...5.5) v -- -- 900 ns t buf bus free time between stop and start v dd = (1.71...5.5) v 1300 -- -- ns t hd_sta start hold time v dd = (1.71...5.5) v 600 -- -- ns t su_sta start set-up time v dd = (1.71...5.5) v 600 -- -- ns t hd_dat data hold time v dd = (1.71...5.5) v 0 -- -- ns t su_dat data set-up time v dd = (1.71...5.5) v 100 -- -- ns t r inputs rise time v dd = (1.71...5.5) v -- -- 300 ns t f inputs fall time v dd = (1.71...5.5) v -- -- 300 ns t su_sto stop set-up time v dd = (1.71...5.5) v 600 -- -- ns t dh data out hold time v dd = (1.71...5.5) v 50 -- -- ns symbol parameter condition/note min. typ. max. unit SLG46533_ds_114 page 15 of 184 SLG46533 5.6 idd estimator 5.7 timing estimator table 1. typical current estimated for each macrocell at t=25c symbol parameter note v dd = 1.8 v v dd = 3.3v v dd = 5.0v unit i current chip quiescent 0.31 0.57 0.89 ? a osc 2 mhz, predivi de = 1 34.0 53.5 82.2 ? a osc 2 mhz, predivi de = 8 19.2 25.0 35.6 ? a osc 25 khz, predivide = 1 5.3 6.0 7.3 ? a osc 25 khz, predivide = 8 5.3 6.0 7.3 ? a osc 25 mhz, predivide = 1 83.0 218.6 397.5 ? a osc 25 mhz, predivide = 1, force on 83.0 218.8 397.5 ? a osc 25 mhz, predivide = 8 73.7 194.5 362.0 ? a acmp (each) 48.2 45.1 53.6 ? a acmp with buffer ( each) 59.5 56.5 65.3 ? a vref (each) 44.4 40.7 49.2 ? a vref with buffer ( each) 57.7 55.1 68.1 ? a table 2. typical delay estimate d for each macrocell at t=25c symbol parameter note v dd = 1.8 v v dd = 3.3v v dd = 5.0v unit rising falling rising falling rising falling tpd delay digital input to pp 1x 45 50 19 21 14 15 ns tpd delay digital input with schmitt trigger to pp 1x 44 49 19 21 14 15 ns tpd delay low voltage digital input to pp 1x 46 447 19 195 14 134 ns tpd delay digital input to pmos output 46 - 19 - 13 - ns tpd delay digital input to nmos output - 87 - 32 - 20 ns tpd delay output enable from pin, oe hi-z to 1 52 - 21 - 14 - ns tpd delay output enable from pin, oe hi-z to 0 - 49 - 20 - 14 ns tpd delay lut 2bit (latch) 34 35 15 15 11 10 ns tpd delay latch (lut 2bit) 35 38 15 16 11 11 ns tpd delay lut 3bit (latch) 43 40 18 16 13 11 ns tpd delay latch+nreset (lut 3bit) -- 87 -- 35 -- 23 ns tpd delay lut4bit 37 43 16 18 11 12 ns tpd delaycnt/dly logic 686730292120ns tpd delaydff 758730352023ns tpd delay p_dly1c 326 329 148 149 107 108 ns tpd delay p_dly2c 660 662 299 300 216 217 ns tpd delay p_dly3c 995 998 450 451 326 326 ns tpd delay p_dly4c 1324 1328 600 601 434 435 ns tpd delay filter 233 248 93 97 60 63 ns tpd delay acmp (5 mv overdrive, in- = 600 mv) 1600 1900 1500 1800 1600 1800 ns tw pulse width i/o with 1x push pull (min transmitted)202020202020ns tw pulse width filter (min transmitted) 150 150 55 55 35 35 ns SLG46533_ds_114 page 16 of 184 SLG46533 5.8 typical counter/de lay offset measurements 5.9 expected delays and pulse widths 5.10 typical pulse width performance table 3. typical counter/de lay offset measurements parameter rc osc freq rc osc power v dd = 1.8 v v dd = 3.3v v dd = 5.0v unit offset (power on delay) 25 khz auto 1.6 1.6 1.6 ? s offset (power on delay), fast start 25 khz auto 2.1 2.1 2.1 ? s offset (power on delay) 2 mhz auto 0.4 0.2 0.2 ? s offset (power on delay), fast start 2 mhz auto 0.7 0.5 0.4 ? s offset (power on delay) 2 5 mhz auto 0.01 0.05 0.04 ? s frequency settling time 25 khz auto 19 14 12 ? s frequency settling time 2 mhz auto 14 14 14 ? s variable (clk period) 25 khz forced 0-40 0-40 0-40 ? s variable (clk period) 2 mhz forced 0-0.5 0-0.5 0-0.5 ? s variable (clk period) 25 mhz 0-0.04 0-0.04 0-0.04 ? s tpd (non-delayed edge) 25 khz/ 2 mhz either 35 14 10 ns table 4. expected delays and pulse widths (typical) symbol parameter note v dd = 1.8 v v dd = 3.3v v dd = 5.0v unit tw pulse width, 1 cell mode:(any)edge detect, edge detect output 296 135 101 ns tw pulse width, 2 cell mode:(any)edge detect, edge detect output 597 272 203 ns tw pulse width, 3 cell mode:(any)edge detect, edge detect output 898 410 305 ns tw pulse width, 4 cell mode:(any)edge detect, edge detect output 1195 546 407 ns time1 delay, 1 cell mode:(any)edge detect, edge detect output 55 24 18 ns time1 delay, 2 cell mode:(any)edge detect, edge detect output 55 24 18 ns time1 delay, 3 cell mode:(any)edge detect, edge detect output 55 24 18 ns time1 delay, 4 cell mode:(any)edge detect, edge detect output 55 24 18 ns time2 delay, 1 cell m ode: both edge delay, edg e detect output 367 165 106 ns time2 delay, 2 cell m ode: both edge delay, edg e detect output 667 300 193 ns time2 delay, 3 cell m ode: both edge delay, edg e detect output 968 440 279 ns time2 delay, 4 cell m ode: both edge delay, edg e detect output 126 5 575 365 ns table 5. typical pulse widt h performance at t=25c parameter v dd = 1.8 v v dd = 3.3v v dd = 5.0v unit filtered pulse width for filter 0 < 114 < 47 < 30 ns filtered pulse width for filter 1 <75 <30 <19 ns SLG46533_ds_114 page 17 of 184 SLG46533 5.11 osc specifications table 6. 25 khz rc osc0 frequency limits power supply range (vdd), v temperature range +25 c 0 c ... +85 c -40 c ... +85 c minimum value, khz maximum value, khz minimum value, khz maximum value, khz minimum value, khz maximum value, khz 1.8 v 5% 24.240 25.781 21.963 27.188 21.963 27.562 3.3 v 10% 24.447 25.556 21.905 27.221 21.905 27.263 5 v 10% 24.315 25.911 22.045 27.099 22.045 27.422 2.5 v ... 4.5 v 24.398 25.576 21.897 27.221 21.897 27.277 1.71 v 5.5 v 24.089 26.1 28 21.897 27.373 21.897 27.613 table 7. 25 khz rc osc0 frequen cy error (error cal culated relati ve to nominal value) power supply range (vdd), v temperature range +25 c 0 c ... +85 c -40 c ... +85 c error (% at minimum) error (% at maximum) error (% at minimum) error (% at maximum) error (% at minimum) error (% at maximum) 1.8 v 5% -2.76% 3.42% -1 1.89% 9.07% -11.89% 10.57% 3.3 v 10% -2.01% 2.43% - 12.20% 9.11% -12.20% 9.28% 5 v 10% -2.51% 3.89% -11. 61% 8.65% -11.61% 9.95% 2.5 v ... 4.5 v -2.21% 2.52% -12.23% 9.11% -12.23% 9.33% 1.71 v 5.5 v -3.44% 4.73% -12.23% 9.72% -12.23% 10.68% SLG46533_ds_114 page 18 of 184 SLG46533 5.11.1 2 mhz rc oscillator table 8. 2 mhz rc osc0 frequency limits power supply range (vdd) v temperature range +25 c 0 c ... +85 c -40 c ... +85 c minimum value, mhz maximum value, mhz minimum value, mhz maximum value, mhz minimum value, mhz maximum value, mhz 1.8 v 5% 1.932 2.058 1.793 2.171 1.793 2.171 3.3 v 10% 1.932 2.099 1. 808 2.204 1.808 2.204 5 v 10% 1.981 2.194 1.759 2.316 1.759 2.316 2.5 v ... 4.5 v 1.920 2.120 1.800 2.214 1.800 2.214 1.71 v 5.5 v 1.811 2.288 1.710 2.337 1.710 2.361 table 9. 2 mhz rc osc0 f requency error (error calculated relativ e to nominal value) power supply range (vdd) v temperature range +25 c 0 c ... +85 c -40 c ... +85 c error (% at minimum) error (% at maximum) error (% at minimum) error (% at maximum) error (% at minimum) error (% at maximum) 1.8 v 5% -3.23% 3.10% -10. 21% 8.73% -10.21% 8.73% 3.3 v 10% -3.40% 4.94% -9 .60% 10.19% -9.60% 10.19% 5 v 10% -5.44% 9.70% - 12.03% 2.32% -12.03% 15.81% 2.5 v ... 4.5 v -4.00% 5.98% -9.99% 10.68% -9.99% 10.68% 1.71 v 5.5 v -9.46% 14.4 2% -14.48% 16.85% -14.48% 18.05% SLG46533_ds_114 page 19 of 184 SLG46533 5.11.2 25 mhz rc oscillator note 1: operating 25 mhz rc osc1 is not recommended at vdd < 2.5 v. table 10. 25 mhz rc os c1 frequency limits power supply range (vdd) v temperature range +25 c 0 c ... +85 c -40 c ... +85 c minimum value, mhz maximum value, mhz minimum value, mhz maximum value, mhz minimum value, mhz maximum value, mhz 2.5 v 10% 22.344 27.023 21.687 27.777 21.687 27.706 3.3 v 10% 22.412 26.290 21.399 26.595 21.399 27.069 5 v 10% 23.049 26.646 21.900 27.220 21.900 27.647 2.5 v ... 4.5 v 21.511 26.29 0 20.738 26.685 20.738 27.123 1.71 v 5.5 v (see note1) 13.290 26.290 12.770 26.685 11.908 27.123 table 11. 25 mhz rc osc1 frequency error (error calculated relat ive to nominal value) power supply range (vdd) v temperature range +25 c 0 c ... +85 c -40 c ... +85 c error (% at minimum) error (% at maximum) error (% at minimum) error (% at maximum) error (% at minimum) error (% at maximum) 2.5 v 10% -10.37% 8.40% -13.00% 9.42% -13.00% 11.14% 3.3 v 10% -11.10% 4.28% - 15.12% 5.49% -15.12% 7.37% 5 v 10% -9.80% 4.27% -14. 30% 6.52% -14.30% 8.19% 2.5 v ... 4.5 v -14.68% 4.28% -17.74% 5.85% -17.74% 7.58% 1.71 v 5.5 v (see note1) -47.29 % 4.28% -49.35% 5.85% -52.77% 7.58% SLG46533_ds_114 page 20 of 184 SLG46533 5.11.3 osc power on delay table 12. oscillators power on delay at room temperature, dly/cn t counter data = 100, rc osc power setting: "auto power on", rc osc clock to matrix input: "enable" power supply range (vdd), v rc osc0 2 mhz rc osc0 25 khz rc osc1 typical value, s maximum value, s typical value, ms maximum value, ms typical value, s maximum value, s 1.71 368.7 402.3 16.26 17.87 114.4 134.8 1.80 347.0 375.4 15.93 17.79 104.9 122.0 1.89 329.4 354.2 15.58 17.67 96.5 111.5 2.50 278.4 295.2 14.08 16.75 72.0 80.3 2.70 263.2 277.8 13.20 16.21 65.0 71.4 3.00 251.6 264.9 8.38 9.11 60.0 65.1 3.30 238.3 250.6 1.64 2.02 55.2 58.7 3.60 228.3 240.0 1.57 1.92 51.7 55.0 4.20 220.3 231.7 1.55 1.93 49.1 51.9 4.50 208.0 219.2 1.55 2.01 45.5 47.8 5.00 203.0 213.9 1.56 2.01 44.3 46.5 5.50 195.7 206.5 1.58 2.07 43.0 44.8 table 13. oscillators power on delay at room temperature, dly/cn t counter data = 100, rc osc power setting: "auto power on", rc osc clock to matrix input: "enable", fast start-u p time mode power supply range (vdd), v rc osc0 2 mhz rc osc0 25 khz typical value, s maximum value, s typical value, ms maximum value, ms 1.71 741.8 924.7 20.78 21.36 1.80 703.9 861.5 20.80 21.26 1.89 672.5 809.0 20.81 21.42 2.50 578.5 651.8 20.84 21.40 2.70 546.8 592.8 20.88 21.42 3.00 520.6 549.2 20.93 21.63 3.30 490.4 515.8 21.00 21.65 3.60 468.9 504.7 21.09 21.75 4.20 453.0 496.6 21.18 21.98 4.50 430.1 478.2 21.36 22.34 5.00 420.7 468.5 21.39 22.34 5.50 406.1 451.9 21.38 22.34 SLG46533_ds_114 page 21 of 184 SLG46533 5.12 acmp specifications table 14. acmp specifications symbol parameter description/note conditions min. typ. max. unit v acmp acmp input voltage range positive input vdd = 1.8 v 5 % 0--v dd v negative input 0 -- 1.2 v positive input vdd = 3.3 v 10 % 0--v dd v negative input 0 -- 1.2 v positive input vdd = 5.0 v 10 % 0--v dd v negative input 0 -- 1.2 v v offset acmp input offset voltage low bandwidth - enable, vhys = 0 mv, gain = 1, vref = (50..1200) mv, vdd = (1.71..5.5) v t = 25c -9.1 -- 8.4 mv t = (-40..85)c -10.9 -- 10.9 mv low bandwidth - disable, vhys = 0 mv, gain =1, vref = (50..1200) mv, vdd = (1.71..5.5) v t = 25c -7.5 -- 7.2 mv t = (-40..85)c -10.7 -- 10.5 mv t start acmp start time acmp power on delay, minimal required wake time for the "wake and sleep function", regulator and charge pump set to automatic on/off bg = 550 s, t = 25c vdd = (1.71..5.5) v -- 609.7 862.2 s bg = 550 s, t = (-40..85)c vdd = (1.71..5.5) v -- 675.0 1028.8 s bg = 100 s, t = 25c vdd = 2.7..5.5 v -- 132.4 176.2 s bg = 100 s, t = (-40..85)c vdd = 2.7..5.5 v -- 149.4 213.5 s acmp power on delay, minimal required wake time for the "wake and sleep function", regulator and charge pump always off bg = 550 s, t = 25c vdd = (3..5.5) v -- 609.5 862.0 s bg = 550 s, t = (-40..85)c vdd = (3..5.5) v -- 674.6 1027.5 s bg = 100 s, t = 25c vdd = 3..5.5 v -- 131.6 176.0 s bg = 100 s, t = (-40..85)c vdd = 3..5.5 v -- 149.2 213.3 s SLG46533_ds_114 page 22 of 184 SLG46533 v hys built-in hysteresis v hys = 25 mv v il = vin - v hys /2 v ih = vin + v hys /2 lb - enabled, t = 25c 7.32 -- 35.5 mv lb - disabled, t = 25c 10.0 -- 38.5 mv v hys = 50 mv v il = vin - v hys v ih = v hys lb - enabled, t = 25c 42.9 -- 57.8 mv lb - disabled, t = 25c 44.2 -- 54.3 mv v hys = 200 mv v il = vin - v hys v ih = v hys lb - enabled, t = 25c 192.7 -- 208.7 mv lb - disabled, t = 25c 193.3 -- 204.8 mv v hys = 25 mv v il = vin - v hys /2 v ih = vin + v hys /2 lb - enabled, t = (-40+85)c 0.0 -- 58.0 mv lb - disabled, t = (-40+85)c 0.0 -- 52.9 mv v hys = 50 mv v il = vin - v hys v ih = v hys lb - enabled, t = (-40+85)c 22.5 -- 86.9 mv lb - disabled, t = (-40+85)c 29.2 -- 76.5 mv v hys = 200 mv v il = vin - v hys v ih = v hys lb - enabled, t = (-40+85)c 157.1 -- 251.6 mv lb - disabled, t = (-40+85)c 160.2 -- 245.3 mv r sin series input resistance gain = 1x -- 100.0 -- ?? gain = 0.5x -- 1.0 -- ?? gain = 0.33x -- 0.8 -- ?? gain = 0.25x -- 1.0 -- ?? prop propagation delay, response time low bandwidth - enable, gain = 1, vdd=(1.71..3.3)v, overdrive=5 mv low to high, t = (-40+85)c -- 103.93 1853.68 s high to low, t = (-40+85)c -- 101.06 1656.70 s low bandwidth - disable, gain = 1, vdd=(1.71..3.3)v, overdrive=5 mv low to high, t = (-40+85)c -- 68.29 1753.33 s high to low, t = (-40+85)c -- 63.06 1568.55 s low bandwidth - enable, gain = 1, vdd=(3.3..5.5)v, overdrive=5 mv low to high, t = (-40+85)c -- 30.62 167.56 s high to low, t = (-40+85)c -- 33.54 181.40 s low bandwidth - disable, gain = 1, vdd=(3.3..5.5)v, overdrive=5 mv low to high, t = (-40+85)c -- 5.00 32.61 s high to low, t = (-40+85)c -- 5.24 33.88 s symbol parameter description/note conditions min. typ. max. unit SLG46533_ds_114 page 23 of 184 SLG46533 g gain error (including threshold and internal vref error), t = (-40+85)c g = 1, vdd = 1.71 v vref = 501200 mv -- 1 -- g = 1, vdd = 3.3 v -- 1 -- g = 1, vdd = 5.5 v -- 1 -- g = 0.5, vdd = 1.71 v -1.00% -- 0.93% g = 0.5, vdd = 3.3 v -0.96% -- 0.82% g = 0.5, vdd = 5.5 v -1.04% -- 0.90% g = 0.33, vdd = 1.71v -1.75% -- 2.10% g = 0.33, vdd = 3.3 v -1.95% -- 1.69% g = 0.33, vdd = 5.5 v -2.03% -- 1.77% g = 0.25, vdd = 1.71v -1.91% -- 2.13% g = 0.25, vdd = 3.3 v -1.98% -- 1.80% g = 0.25, vdd = 5.5 v -2.12% -- 1.90% vref internal vref error, vref = 1200 mv vdd = 1.8 v 5 % t = 25c -0.58% -- 0.56% t = (-40+85)c -1.01% -- 0.70% vdd = 3.3 v 10 % t = 25c -0.59% -- 0.58% t = (-40+85)c -1.06% -- 0.72% vdd = 5.0 v 10 % t = 25c -0.64% -- 0.60% t = (-40+85)c -1.16% -- 0.74% internal vref error, vref = 1000 mv vdd = 1.8 v 5 % t = 25c -0.57% -- 0.58% t = (-40+85)c -1.14% -- 0.76% vdd = 3.3 v 10 % t = 25c -0.59% -- 0.58% t = (-40+85)c -1.04% -- 0.73% vdd = 5.0 v 10 % t = 25c -0.67% -- 0.64% t = (-40+85)c -1.15% -- 0.73% internal vref error, vref = 500 mv vdd = 1.8 v 5 % t = 25c -0.64% -- 0.64% t = (-40+85)c -1.11% -- 0.75% vdd = 3.3 v 10 % t = 25c -0.63% -- 0.63% t = (-40+85)c -1.10% -- 0.78% vdd = 5.0 v 10 % t = 25c -0.72% -- 0.70% t = (-40+85)c -1.15% -- 0.80% symbol parameter description/note conditions min. typ. max. unit SLG46533_ds_114 page 24 of 184 SLG46533 5.13 analog temperature sensor (ts) specifications table 15. ts output vs temperature, without buffer t, c vdd = 1.8 v vdd = 3.3 v vdd = 5.0 v typical, v accuracy, % typical, v accuracy, % typical, v accuracy, % -40 0.69 0.85 0.70 1.13 0.70 1.09 -30 0.67 0.70 0.68 1.12 0.68 1.02 -20 0.66 0.78 0.66 1.27 0.66 1.19 -10 0.64 0.70 0.64 1.03 0.64 1.05 0 0.62 0.66 0.62 1.13 0.62 1.10 10 0.60 0.54 0.60 1.16 0.60 1.15 20 0.58 0.50 0.58 0.74 0.58 0.76 30 0.56 0.91 0.56 1.29 0.56 1.22 40 0.54 0.48 0.54 0.53 0.54 0.53 50 0.51 0.89 0.51 1.33 0.51 1.25 60 0.49 0.95 0.49 1.14 0.49 1.18 70 0.47 0.77 0.47 0.98 0.47 1.01 80 0.45 0.63 0.45 0.70 0.45 0.70 90 0.43 1.12 0.43 1.22 0.43 1.22 table 16. ts output vs temperature, with buffer (output range 1) t, c vdd = 1.8 v vdd = 3.3 v vdd = 5.0 v typical, v accuracy, % typical, v accuracy, % typical, v accuracy, % -40 1.20 3.33 1.20 3.29 1.20 3.29 -30 1.16 3.35 1.16 3.32 1.16 3.29 -20 1.13 3.49 1.13 3.42 1.13 3.42 -10 1.10 3.42 1.10 3.33 1.10 3.38 0 1.06 3.51 1.06 3.46 1.06 3.45 10 1.03 3.63 1.03 3.60 1.03 3.60 20 0.99 3.72 0.99 3.61 0.99 3.58 30 0.96 4.00 0.96 3.92 0.96 3.87 40 0.92 3.73 0.92 3.64 0.92 3.64 50 0.88 4.01 0.88 3.90 0.88 3.92 60 0.85 4.11 0.85 4.03 0.85 3.97 70 0.81 4.18 0.81 4.12 0.81 4.06 80 0.78 4.43 0.78 4.36 0.78 4.26 90 0.75 4.98 0.75 4.89 0.75 4.81 table 17. ts output vs temperature, with buffer (output range 2) t, c vdd = 1.8 v vdd = 3.3 v vdd = 5.0 v typical, v accuracy, % typical, v accuracy, % typical, v accuracy, % -40 0.99 3.29 0.99 3.28 0.99 3.28 -30 0.96 3.33 0.96 3.24 0.96 3.31 -20 0.93 3.37 0.93 3.30 0.93 3.34 SLG46533_ds_114 page 25 of 184 SLG46533 -10 0.90 3.46 0.90 3.39 0.90 3.40 0 0.87 3.45 0.87 3.39 0.87 3.40 10 0.85 3.62 0.85 3.51 0.85 3.53 20 0.82 3.66 0.82 3.58 0.82 3.53 30 0.79 3.93 0.79 3.81 0.79 3.80 40 0.76 3.71 0.76 3.65 0.76 3.62 50 0.73 3.97 0.73 3.90 0.73 3.91 60 0.70 4.02 0.70 3.97 0.70 4.00 70 0.67 4.22 0.67 4.13 0.67 4.08 80 0.64 4.38 0.64 4.29 0.64 4.26 90 0.61 4.89 0.61 4.88 0.61 4.77 table 18. ts output error, without buffer vdd, v error at t -40c, % -20c, % 0c, % 20c, % 40c, % 60c, % 80c, % 1.71 2.78 1.27 0.68 0.48 0.46 0.91 0.60 1.80 0.85 0.78 0.66 0.50 0.48 0.95 0.63 1.89 0.71 0.90 0.79 0.56 0.48 0.96 0.66 2.30 1.05 1.23 1.04 0.66 0.49 1.03 0.73 2.50 1.12 1.24 1.16 0.74 0.51 1.07 0.70 2.70 1.11 1.22 1.12 0.71 0.52 1.10 0.67 3.00 1.14 1.25 1.11 0.74 0.53 1.03 0.66 3.30 1.13 1.27 1.13 0.74 0.53 1.14 0.70 3.60 1.07 1.24 1.17 0.79 0.54 1.13 0.77 4.20 1.10 1.19 1.11 0.73 0.56 1.23 0.72 4.50 1.04 1.23 1.14 0.75 0.53 1.19 0.68 5.00 1.09 1.19 1.10 0.76 0.53 1.18 0.70 5.50 1.05 1.14 1.06 0.77 0.57 1.17 0.69 table 19. ts output error, with buffer (output range 1) vdd, v error at t -40c, % -20c, % 0c, % 20c, % 40c, % 60c, % 80c, % 1.71 3.28 3.38 3.43 3.67 3.72 4.13 4.42 1.80 3.29 3.37 3.45 3.66 3.71 4.02 4.38 1.89 3.21 3.38 3.44 3.63 3.72 4.06 4.39 2.30 3.23 3.34 3.46 3.56 3.66 4.03 4.32 2.50 3.27 3.37 3.44 3.59 3.68 4.03 4.26 table 17. ts output vs temperature, with buffer (output range 2) t, c vdd = 1.8 v vdd = 3.3 v vdd = 5.0 v typical, v accuracy, % typical, v accuracy, % typical, v accuracy, % SLG46533_ds_114 page 26 of 184 SLG46533 2.70 3.24 3.31 3.39 3.59 3.65 4.04 4.29 3.00 3.27 3.33 3.39 3.57 3.65 4.02 4.26 3.30 3.28 3.30 3.39 3.58 3.65 3.97 4.29 3.60 3.28 3.28 3.34 3.58 3.64 3.96 4.30 4.20 3.23 3.36 3.34 3.58 3.62 4.04 4.28 4.50 3.27 3.31 3.38 3.56 3.61 4.03 4.26 5.00 3.28 3.34 3.40 3.53 3.62 4.00 4.26 5.50 3.26 3.37 3.44 3.57 3.61 4.01 4.22 table 20. ts output error, with buffer (output range 2) vdd, v error at t -40c, % -20c, % 0c, % 20c, % 40c, % 60c, % 80c, % 1.71 3.34 3.50 3.56 3.69 3.73 4.09 4.43 1.80 3.33 3.49 3.51 3.72 3.73 4.11 4.43 1.89 3.33 3.47 3.55 3.70 3.72 4.11 4.40 2.30 3.31 3.46 3.50 3.69 3.66 4.05 4.38 2.50 3.31 3.44 3.51 3.62 3.66 4.03 4.36 2.70 3.30 3.46 3.46 3.64 3.65 3.97 4.31 3.00 3.31 3.46 3.46 3.62 3.64 4.07 4.34 3.30 3.29 3.42 3.46 3.61 3.64 4.03 4.36 3.60 3.25 3.42 3.46 3.59 3.62 3.98 4.34 4.20 3.28 3.42 3.45 3.62 3.62 4.01 4.30 4.50 3.32 3.41 3.46 3.63 3.62 4.01 4.29 5.00 3.29 3.42 3.45 3.58 3.64 3.97 4.26 5.50 3.30 3.47 3.50 3.61 3.64 4.02 4.31 table 19. ts output error, with buffer (output range 1) vdd, v error at t -40c, % -20c, % 0c, % 20c, % 40c, % 60c, % 80c, % SLG46533_ds_114 page 27 of 184 SLG46533 6.0 summary of macrocell function 6.1 i/o pins ? digital input (low voltage or normal voltage, with or without schmitt trigger) ? open drain output s (nmos and pmos) ? push pull outputs (1x and 2x) ? analog i/o ? 10 k ? /100 k ? /1 m ?? pull-up/pull-down resistors ? 40 ma open drain 4x drive output 6.2 connection matrix ? digital matrix for circuit co nnections based on user design 6.3 analog compa rators (4 total) ? selectable hysteresis 0 m v / 25 mv / 50 mv / 200 mv ? wake and sleep control (part of combination function macrocell ) 6.4 voltage reference ? used for references on analog comparators ? can also be driven to external pins 6.5 combination functi on macrocells (26 total) ? three selectable dff/latch or 2-bit luts ? twelve selectable dff/latch or 3-bit luts ? one selectable pipe delay or 3-bit lut ? one selectable programmable pa ttern generator or 2-bit lut ? five selectable 8-bit cnt/dlys or 3-bit luts ? two selectable 16-bit cnt/dlys or 4-bit luts ? two deglitch filters with edge detectors 6.6 combinatinatorial logic macrocell ? one 4-bit lut 6.7 serial communications ?i 2 c protocol compliant macrocell ? 8-bit register connected to the connection matrix 6.8 16x8 ram memory with def ined nvm otp initial state 6.9 pipe delay (part of combination function macrocell) ? 16 stage / 3 output ? one single stage fixed output ? two 1 to 16 stage selectable outputs SLG46533_ds_114 page 28 of 184 SLG46533 6.10 programmable delay ? 125 ns/250 ns/375 ns/ 500 ns @ vdd = 3.3 v ? includes edge detection function 6.11 rc oscillator ? 25 khz or 2 mhz selectable frequency ? 25 mhz rc oscillator ? first stage divider (4): osc /1, osc/2, osc/4, and osc/8 ? second stage divider for 25 khz and 2 mhz (5): output to matri x: osc/1, osc/2, osc/3, osc/4, osc/8, osc/12, osc/24, osc/64 6.12 crystal oscillator 6.13 analog temperature sensor SLG46533_ds_114 page 29 of 184 SLG46533 7.0 i/o pins the SLG46533 has a total of 18 mu lti-function i/o pins which ca n function as either a user defined input or output, as well as serving as a special function (such as voltage reference output ), or serving as a signal for programming of the on-chip non v olatile memory (nvm). refer to section 2.0 pin description for normal and programming modepin definitions. normal mode pin definitions are as follows: ? vdd: v dd power supply ? io0: general purpose input ? io1: general purpose input or output with oe ? io2: general purpose input or output ? io3: general purpose input or output with oe ? io4: general purpose input or ou tput or analog comparator 0(+) ? io5: general purpose input or ou tput with oe or analog compara tor 0(-) ? io6: general purpose input or od output i 2 c scl ? io7: general purpose input or od output i 2 c sda ? io8: general purpose input or ou tput with oe or analog compara tor 1(+) ? gnd: ground ? io9: general purpose input or ou tput or analog comparator 1(-) ? io10: general purpose input or output with oe or analog compar ator 2(+) ? io11: general purpose input or output with oe or analog compar ator 2(-) ? io12: general purpose input or ou tput or analog comparator 3(+ ) ? io13: general purpose input or output with oe ? io14: general purpose input or output ? io15: general purpose input or output with oe and vref output (vref1) ? io16: general purpose input or output with oe and vref output (vref0) ? io17: general purpose input or output or external clock input programming mode pin definitions are as follows: ? vdd: v dd power supply ? io0: v pp programming voltage ? io6: programming scl ? io7: programming sda ? gnd: ground ? io13: programming mode control of the 18 user defined i/o pins on the SLG46533, all but one of the pins (io0) can serve as both digital input and digital out put. io0 can only serve as a digital input pin. 7.1 input modes each i/o pin can be configured as a digital input pin with/with out buffered schmitt trigger, or can also be configured as a lo w voltage digital input. ios 4, 5, 8, 9, 10, 11, and 12 can also be configured to serve as analog inputs to the on-chip comparat ors. ios 15 and 16 can also be configured as analog reference voltag e inputs. 7.2 output modes ios 1, 2, 3, 4, 5, 6, 7, 8, 8, 1 0, 11, 12, 13, 14, 15, 16, and 17 can all be configured as digital output pins. 7.3 pull up/down resistors all i/o pins have the option for user selectable resistors conn ected to the input structure. th e selectable values on these re sistors are 10 k ? , 100 k ? and 1 m ? . in the case of io0, the resistors are fixed to a pull-down co nfiguration. in the case of all other i/o pins, the internal resistors can be configured as either pull-u p or pull-downs. SLG46533_ds_114 page 30 of 184 SLG46533 7.4 i/o register settings 7.4.1 io0 register settings 7.4.2 io1 register settings table 21. io0 register settings signal function register bit address register definition io0 pull down resistor value selection <1028:1029> 00: floating 01: 10 k ? resistor 10: 100 k ? resistor 11: 1 m ? resistor io0 mode control <1030:1031> 00: digital input without schmitt tr igger 01: digital input with schmitt trigger 10: low voltage digital input 11: reserved table 22. io1 register settings signal function register bit address register definition io1 pull up/down resistor selection <1033> 0: pull down resistor 1: pull up resistor io1 pull up/down resistor value selection <1035:1034> 00: floating 01: 10 k ? resistor 10: 100 k ? resistor 11: 1 m ? resistor io1 mode control (sig_io1_oe =0) <1037:1036> 00: digital input without schmitt trigger 01: digital input with schmitt trigger 10: low voltage digital input 11: reserved io1 mode control (sig_io1_oe =1) <1039:1038> 00: push pull 1x 01: push pull 2x 10: open drain nmos 1x 11: open drain nmos 2x SLG46533_ds_114 page 31 of 184 SLG46533 7.4.3 io2 register settings 7.4.4 io3 register settings table 23. io2 register settings signal function register bit address register definition io2 driver strength selection <1041> 0: 1x 1: 2x io2 pull up/down resistor selection <1042> 0: pull down resistor 1: pull up resistor io2 pull up/down resistor value selection <1044:1043> 00: floating 01: 10 k ? resistor 10: 100 k ? resistor 11: 1 m ? resistor io2 mode control <1047:1045> 000: digital input wit hout schmitt t rigger 001: digital input with schmitt trigger 010: low voltage digital input 011: reserved 100: push pull 101: open drain nmos 110: open drain pmos 111: reserved table 24. io3 register settings signal function register bit address register definition io3 pull up/down resistor selection <1049> 0: pull down resistor 1: pull up resistor io3 pull up/down resistor value selection <1051:1050> 00: floating 01: 10 k ? resistor 10: 100 k ? resistor 11: 1 m ? resistor io3 mode control (sig_io3_oe =0) <1053:1052> 00: digital input without schmitt trigger 01: digital input with schmitt trigger 10: low voltage digital input 11: reserved io3 mode control (sig_io3_oe =1) <1055:1054> 00: push pull 1x 01: push pull 2x 10: open drain nmos 1x 11: open drain nmos 2x SLG46533_ds_114 page 32 of 184 SLG46533 7.4.5 io4 register settings 7.4.6 io5 register settings table 25. io4 register settings signal function register bit address register definition io4 driver strength selection <1057> 0: 1x 1: 2x io4 pull up/down resistor selection <1058> 0: pull down resistor 1: pull up resistor io4 pull up/down resistor value selection <1060:1059> 00: floating 01: 10 k ? resistor 10: 100 k ? resistor 11: 1 m ? resistor io4 mode control <1063:1061> 000: digital input wit hout schmitt t rigger 001: digital input with schmitt trigger 010: low voltage digital input 011: analog input/output 100: push pull 101: open drain nmos 110: open drain pmos 111: analog input & open drain table 26. io5 register settings signal function register bit address register definition io5 pull up/down resistor selection <1065> 0: pull down resistor 1: pull up resistor io5 pull up/down resistor value selection <1067:1066> 00: floating 01: 10 k ? resistor 10: 100 k ? resistor 11: 1 m ? resistor io5 mode control (sig_io5_oe =0) <1069:1068> 00: digital input without schmitt trigger 01: digital input with schmitt trigger 10: low voltage digital input 11: analog input/output io5 mode control (sig_io5_oe =1) <1071:1070> 00: push pull 1x 01: push pull 2x 10: open drain nmos 1x 11: open drain nmos 2x SLG46533_ds_114 page 33 of 184 SLG46533 7.4.7 io6 register settings 7.4.8 io7 register settings table 27. io6 register settings signal function register bit address register definition io6 driver strength selection <1073> 0: 1x 1: 2x sele ct sc l & virt ua l input 0 or io6 <1074> 0: scl & virtual input 0 1: io6 io6 pull down resistor value selection <1076:1075> 00: floating 01: 10 k ? resistor 10: 100 k ? resistor 11: 1 m ? resistor io6 mode control <1079:1077> 000: digital input wit hout schmitt t rigger 001: digital input with schmitt trigger 010: low voltage digital input 011: reserved 100: reserved 101: open drain nmos 110: reserved 111: reserved table 28. io7 register settings signal function register bit address register definition io7 (or sda) driver strength selection <1081> 0: 1x 1: 2x select sda & virtual input 1 or io7 <1082> 0: sda & virtual input 1 1: io7 io7 pull down resistor value selection <1084:1083> 00: floating 01: 10 k ? resistor 10: 100 k ? resistor 11: 1 m ? resistor io7 (or sda) mode control <1087:1085> 000: digital i nput without sc hmitt trigger 001: digital input with schmitt trigger 010: low voltage digital input 011: reserved 100: reserved 101: open drain nmos 110: reserved 111: reserved SLG46533_ds_114 page 34 of 184 SLG46533 7.4.9 io8 register settings 7.4.10 io9 register settings 7.4.11 io10 register settings table 29. io8 register settings signal function register bit address register definition io8 4x drive (4x, nmos open drain) selection <1088> 0: 4x drive off 1: 4x drive on (if <884:882> = 101) (io8 oe = 1 and pin mode is od nmos 1x) io8 pull up/down resistor selection <1089> 0: pull down resistor 1: pull up resistor io8 pull up/down resistor value selection <1091:1090> 00: floating 01: 10 k ? resistor 10: 100 k ? resistor 11: 1 m ? resistor io8 mode control (sig_io8_oe =0) <1093:1092> 00: digital input without schmitt trigger 01: digital input with schmitt trigger 10: low voltage digital input 11: analog input/output io8 mode control (sig_io8_oe =1) <1095:1094> 00: push pull 1x 01: push pull 2x 10: open drain nmos 1x 11: open drain nmos 2x table 30. io9 register settings signal function register bit address register definition io9 4x drive (4x, nmos open drain) selection <1096> 0: 4x drive off 1: 4x drive on (if <892:890> = 101) (io9 oe = 1 and pin mode is od nmos 1x) io9 driver strength selection <1097> 0: 1x 1: 2x io9 pull up/down resistor selection <1098> 0: pull down resistor 1: pull up resistor io9 pull up/down resistor value selection <1100:1099> 00: floating 01: 10 k ? resistor 10: 100 k ? resistor 11: 1 m ? resistor io9 mode control <1103:1101> 000: digital input wit hout schmitt t rigger 001: digital input with schmitt trigger 010: low voltage digital input 011: analog input/output 100: push pull 101: open drain nmos 110: open drain pmos 111: analog input & open drain table 31. io10 register settings signal function register bit address register definition io10 pull up/down resistor selection <1105> 0: pull down resistor 1: pull up resistor SLG46533_ds_114 page 35 of 184 SLG46533 7.4.12 io11 register settings io10 pull up/down resistor value selection <1107:1106> 00: floating 01: 10 k ? resistor 10: 100 k ? resistor 11: 1 m ? resistor io10 mode control (sig_io10_oe =0) <1109:1108> 00: digital input without schmitt trigger 01: digital input with schmitt trigger 10: low voltage digital input 11: analog input/output io10 mode control (sig_io10_oe =1) <1111:1110> 00: push pull 1x 01: push pull 2x 10: open drain nmos 1x 11: open drain nmos 2x table 32. io11 register settings signal function register bit address register definition io11 pull up/down resistor selection <1113> 0: pull down resistor 1: pull up resistor io11 pull up/down resistor value selection <1115:1114> 00: floating 01: 10 k ? resistor 10: 100 k ? resistor 11: 1 m ? resistor io11 mode control (sig_io11_oe =0) <1117:1116> 00: digital input without schmitt trigger 01: digital input with schmitt trigger 10: low voltage digital input 11: analog input/output io11 mode control (sig_io11_oe =1) <1119:1118> 00: push pull 1x 01: push pull 2x 10: open drain nmos 1x 11: open drain nmos 2x table 31. io10 register settings signal function register bit address register definition SLG46533_ds_114 page 36 of 184 SLG46533 7.4.13 io12 register settings 7.4.14 io13 register settings table 33. io12 register settings signal function register bit address register definition io12 driver strength selection <1121> 0: 1x 1: 2x io12 pull up/down resistor selection <1122> 0: pull down resistor 1: pull up resistor io12 pull up/down resistor value selection <1124:1123> 00: floating 01: 10 k ? resistor 10: 100 k ? resistor 11: 1 m ? resistor io12 mode control <1127:1125> 000 : digital input without schmitt trigger 001: digital input with schmitt trigger 010: low voltage digital input 011: analog input/output 100: push pull 101: open drain nmos 110: open drain pmos 111: analog input & open drain table 34. io13 register settings signal function register bit address register definition io13 pull up/down resistor selection <1129> 0: pull down resistor 1: pull up resistor io13 pull up/down resistor value selection <1131:1130> 00: floating 01: 10 k ? resistor 10: 100 k ? resistor 11: 1 m ? resistor io13 mode control (sig_io13_oe =1) <1135:1134> 00: push pull 1x 01: push pull 2x 10: open drain nmos 1x 11: open drain nmos 2x io13 mode control (sig_io13_oe =0) <1133:1132> 00: digital input without schmitt trigger 01: digital input with schmitt trigger 10: low voltage digital input 11: reserved SLG46533_ds_114 page 37 of 184 SLG46533 7.4.15 io14 register settings 7.4.16 io15 register settings table 35. io14 register settings signal function register bit address register definition io14 driver strength selection <1137> 0: 1x 1: 2x io14 pull up/down resistor selection <1138> 0: pull down resistor 1: pull up resistor io14 pull up/down resistor value selection <1140:1139> 00: floating 01: 10 k ? resistor 10: 100 k ? resistor 11: 1 m ? resistor io14 mode control <1143:1141> 000 : digital input without schmitt trigger 001: digital input with schmitt trigger 010: low voltage digital input 011: reserved 100: push pull 101: open drain nmos 110: open drain pmos 111: reserved table 36. io15 register settings signal function register bit address register definition io15 pull up/down resistor selection <1145> 0: pull down resistor 1: pull up resistor io15 pull up/down resistor value selection <1147:1146> 00: floating 01: 10 k ? resistor 10: 100 k ? resistor 11: 1 m ? resistor io15 mode control (sig_io15_oe =0) <1149:1148> 00: digital input without schmitt trigger 01: digital input with schmitt trigger 10: low voltage digital input 11: analog input/output io15 mode control (sig_io15_oe =1) <1151:1150> 00: push pull 1x 01: push pull 2x 10: open drain nmos 1x 11: open drain nmos 2x SLG46533_ds_114 page 38 of 184 SLG46533 7.4.17 io16 register settings 7.4.18 io17 register settings table 37. io16 register settings signal function register bit address register definition io16 pull up/down resistor selection <1153> 0: pull down resistor 1: pull up resistor io16 pull up/down resistor value selection <1155:1154> 00: floating 01: 10 k ? resistor 10: 100 k ? resistor 11: 1 m ? resistor io16 mode control (sig_io16_oe =0) <1157:1156> 00: digital input without schmitt trigger 01: digital input with schmitt trigger 10: low voltage digital input 11: analog input/output io16 mode control (sig_io16_oe =1) <1159:1158> 00: push pull 1x 01: push pull 2x 10: open drain nmos 1x 11: open drain nmos 2x table 38. io17 register settings signal function register bit address register definition io17 driver strength selection <1161> 0: 1x 1: 2x io17 pull up/down resistor selection <1162> 0: pull down resistor 1: pull up resistor io17 pull up/down resistor value selection <1164:1163> 00: floating 01: 10 k ? resistor 10: 100 k ? resistor 11: 1 m ? resistor io17 mode control <1167:1165> 000 : digital input without schmitt trigger 001: digital input with schmitt trigger 010: low voltage digital input 011: reserved 100: push pull 101: open drain nmos 110: open drain pmos 111: reserved SLG46533_ds_114 page 39 of 184 SLG46533 7.5 gpi structure 7.5.1 gpi structure (for io0) figure 2. io0 gpi structure diagram digital in low voltage input non-schmitt trigger input oe lv_en shmitt trigger input oe smt_en oe wosmt_en pad s0 s1 s2 s3 floating 10 k ? 90 k ? 900 k ? res_sel[1:0] 00: floating 01: 10 k ? 10: 100 k ? 11: 1 m ? input mode [1:0] 00: digital in without schmitt trigger, wosmt_en=1, oe=0 01: digital in with schmit t trigger, smt_en=1, oe=0 10: low voltage digital in mode, lv_en = 1, oe=0 11: reserved note 1: oe cannot be selected by user note 2: oe is matrix output , digital in is matrix input SLG46533_ds_114 page 40 of 184 SLG46533 7.6 matrix oe io structure 7.6.1 matrix oe io structure (fo r ios 1, 3, 5, 10, 11, 13, 15 , 16) figure 3. matrix oe io structure diagram pad s0 s1 s2 s3 floating s0 s1 pull_up_en 10 k ? 90 k ? 900 k ? res_sel[1:0] 00: floating 01: 10 k ? 10: 100 k ? 11: 1 m ? input mode [1:0] 00: digital in without schmitt trigger, wosmt_en=1 01: digital in with schm itt trigger, smt_en=1 10: low voltage digital in mode, lv_en = 1 11: analog io mode output mode [1:0] 00: 1x push-pull mode, pp1x_en=1 01: 2x push-pull mode, pp2x_en=1, pp1x_en=1 10: 1x nmos open drain mode, od1x_en=1 11: 2x nmos open drain mode, od2x_en=1, od1x_en=1 note: digital out and oe are matrix output, digital in is matri x input (for ios 5, 10, 11, 15 and 16 only) digital out digital out oe od2x_en oe od1x_en digital out oe pp2x_en digital out oe pp1x_en digital in low voltage input non-schmitt trigger input analog io oe lv_en shmitt trigger input oe smt_en oe wosmt_en SLG46533_ds_114 page 41 of 184 SLG46533 7.6.2 matrix oe io structure (for ios 6 and 7) figure 4. matrix oe io structure diagram pad s0 s1 s2 s3 floating 10 k ? 90 k ? 900 k ? res_sel[1:0] 00: floating 01: 10 k ? 10: 100 k ? 11: 1 m ? io6, io7 mode [2:0] 000: digital input without schmitt trigger 001: digital input with schmitt trigger 010: low voltage digital input 011: reserved 100: reserved 101: open drain nmos 110: reserved 111: reserved note: digital out and oe are matrix output, digital in is matri x input digital out oe od1x_en digital in low voltage input non-schmitt trigger input oe lv_en shmitt trigger input oe smt_en oe wosmt_en SLG46533_ds_114 page 42 of 184 SLG46533 7.6.3 matrix oe 4x dr ive structure (for io8) figure 5. matrix oe io 4x drive structure diagram pad digital in s0 s1 s2 s3 floating s0 s1 pull_up_en 10 k ? 90 k ? 900 k ? res_sel[1:0] 00: floating 01: 10 k ? 10: 100 k ? 11: 1 m ? low voltage input non-schmitt trigger input input mode [1:0] 00: digital in without schmitt trigger, wosmt_en=1 01: digital in with schmitt trigger, smt_en=1 10: low voltage digital in mode, lv_en = 1 11: analog io mode output mode [1:0] 00: 1x push-pull mode, pp1x_en=1 01: 2x push-pull mode, pp2x_en=1, pp1x_en=1 10: 1x nmos open drain mode, od1x_en=1, odn_en=1 11: 2x nmos open drain mode, od2x_en=1, od1x_en=1, odn_en=1 note: digital out and oe are matrix output, digital in is matri x input analog io digital out digital out oe oe digital out oe pp2x_en digital out oe pp1x_en oe lv_en shmitt trigger input oe smt_en oe wosmt_en odn_en od1x_en 4x_en oe digital out od2x_en 4x_en odn_en odn_en 4x_en digital out oe odn_en 4x_en SLG46533_ds_114 page 43 of 184 SLG46533 7.7 io structure 7.7.1 io structure (fo r ios 2, 4, 12, 14, 17) figure 6. io structure diagram pad s0 s1 s2 s3 floating s0 s1 pull_up_en 10 k ? 90 k ? 900 k ? res_sel[1:0] 00: floating 01: 10 k ? 10: 100 k ? 11: 1 m ? mode [2:0] 000: digital in without schmitt trigger, wosmt_en=1, oe = 0 001: digital in with schmitt trigger, smt_en=1, oe = 0 010: low voltage digital in mode, lv_en = 1, oe = 0 011: analog io mode 100: push-pull mode, pp_en=1, oe = 1 101: nmos open drain mode, odn_en=1, oe = 1 110: pmos open drain mode, odp_en=1, oe = 1 111: analog io and nmos open-drain mode, odn_en=1 and aio_en=1 note: oe cannot be selected by user and is controlled by regist er digital out digital out oe odn_en oe odn_en digital out oe 2x_en pp_en 2x_en odp_en digital out oe pp_en 2x_en odp_en digital in low voltage input non-schmitt trigger input analog io oe lv_en shmitt trigger input oe smt_en oe wosmt_en SLG46533_ds_114 page 44 of 184 SLG46533 7.7.2 4x drive structure (for io9) figure 7. io 4x drive structure diagram pad digital in s0 s1 s2 s3 floating s0 s1 pull_up_en 10 k ? 90 k ? 900 k ? res_sel[1:0] 00: floating 01: 10 k ? 10: 100 k ? 11: 1 m ? low voltage input non-schmitt trigger input analog io digital out digital out oe oe digital out oe pp2x_en digital out oe pp1x_en oe lv_en shmitt trigger input oe smt_en oe wosmt_en odn_en od1x_en 4x_en oe digital out od2x_en 4x_en odn_en odn_en 4x_en digital out oe odn_en 4x_en mode [2:0] 000: digital in without schmitt trigger, wosmt_en=1, oe = 0 001: digital in with schmitt trigger, smt_en=1, oe = 0 010: low voltage digital in mode, lv_en = 1, oe = 0 011: analog io mode 100: push-pull mode, pp_en=1, oe = 1 101: nmos open drain mode, odn_en=1, oe = 1 110: pmos open drain mode, odp_en=1, oe = 1 111: analog io and nmos open-drain mode, odn_en=1 and aio_en=1 note 1: oe cannot be selected by user note 2: digital out and oe are matrix output, digital in is mat rix input SLG46533_ds_114 page 45 of 184 SLG46533 8.0 connection matrix the connection matrix in the SLG46533 is used to create the int ernal routing for internal functional macrocells of the device once it is programmed. the registers are programmed from the one-tim e nvm cell during test mode operation. the output of each functional macrocell within the SLG46533 has a specific digital bit code assigned to it that is either set to active high or inactive low based on the design that is created. once the 2048 regist er bits within the SLG46533 are programmed a fully custom circu it will be created. the connection matrix has 64 inputs and 110 outputs. each of th e 64 inputs to the connection matrix is hard-wired to the digit al output of a particular source ma crocell, including i/o pins, lu ts, analog comparators, other d igital resources and vdd and gnd . the input to a digital macrocell uses a 6-bit register to selec t one of these 64 input lines. for a complete list of the slg 46533s register t able, see secti on 21.0 appendix a - SLG46533 register definition . figure 8. connection matrix figure 9. connection matrix example gnd 0 io0 digital in 1 io1 digital in 2 io2 digital in 3 matrix input signal functions n resetb_core 62 vdd 63 n function registers 109 matrix out: pd of xtal osc reg<877:872> 0 matrix out: in0 of lut3_11 or clk input of dff8 reg<5:0> 1 matrix out: in1 of lut3_11 or data input of dff8 reg<13:8> 2 matrix out: in2 of lut3_11 or nrst (nset) of dff8 reg<21:16> matrix inputs matrix outputs io9 io10 io11 connection matrix lut io10 io9 lut io11 function SLG46533_ds_114 page 46 of 184 SLG46533 8.1 matrix input table table 39. matrix input table matrix input number matrix input signal function matrix decode 5 4 3 2 1 0 0 gnd 000000 1 io0 digital input 0 0 0 0 0 1 2 io1 digital input 0 0 0 0 1 0 3 io2 digital input 0 0 0 0 1 1 4 io3 digital input 0 0 0 1 0 0 5 io4 digital input 0 0 0 1 0 1 6 io5 digital input 0 0 0 1 1 0 7 io8 digital input 0 0 0 1 1 1 8 lut2_0 / dff0 output 0 0 1 0 0 0 9 lut2_1 / dff1 output 0 0 1 0 0 1 10 lut2_2 / dff2 output 0 0 1 0 1 0 11 lut2_3 / pgen output 0 0 1 0 1 1 12 lut3_0 / dff3 (set/rst) output 0 0 1 1 0 0 13 lut3_1 / dff4 (set/rst) output 0 0 1 1 0 1 14 lut3_2 / dff5 (set/rst) output 0 0 1 1 1 0 15 lut3_3 / dff6 (set/rst) output 0 0 1 1 1 1 16 lut3_4 / dff7 (set/rst) output 0 1 0 0 0 0 17 lut3_5 / cnt_dly2(8bit) output 0 1 0 0 0 1 18 lut3_6 / cnt_dly3(8bit) output 0 1 0 0 1 0 19 lut3_7 / cnt_dly4(8bit) output 0 1 0 0 1 1 20 lut3_8 / cnt_dly5(8bit) output 0 1 0 1 0 0 21 lut3_9 / cnt_dly6(8bit) output 0 1 0 1 0 1 22 lut4_0 / cnt_dly0(16bit) output 0 1 0 1 1 0 23 lut4_1 / cnt_dly1(16bit) output 0 1 0 1 1 1 24 lut3_10 / pipe delay ( 1st stage) output 0 1 1 0 0 0 25 pipe delay output0 0 1 1 0 0 1 26 pipe delay output1 0 1 1 0 1 0 27 internal osc post-divided by 1/2/3/4/8/12/24/64 output (25khz/2mhz) 011011 28 internal osc post-divided by 1/2/3/4/8/12/24/64 output (25khz/2mhz) 011100 29 internal osc pre-divided by 1/2/4/8 output (25mhz) 011101 30 filter0 / edge det ect0 output 0 1 1 1 1 0 31 filter1 / edge det ect1 output 0 1 1 1 1 1 32 io6 digital or i2c_virtual_0 input 1 0 0 0 0 0 33 io7 digital or i2c_virtual_1 input 1 0 0 0 0 1 34 i2c_virtual_2 input 1 0 0 0 1 0 35 i2c_virtual_3 input 1 0 0 0 1 1 SLG46533_ds_114 page 47 of 184 SLG46533 36 i2c_virtual_4 input 1 0 0 1 0 0 37 i2c_virtual_5 input 1 0 0 1 0 1 38 i2c_virtual_6 input 1 0 0 1 1 0 39 i2c_virtual_7 input 1 0 0 1 1 1 40 lut3_11 / dff8 (set/rst) output 1 0 1 0 0 0 41 lut3_12 / dff9 (set/rst) output 1 0 1 0 0 1 42 lut3_13 / dff10 (set/rst) output 1 0 1 0 1 0 43 lut3_14 / dff11 (set/rst) output 1 0 1 0 1 1 44 lut3_15 / dff12 (set/rst) output 1 0 1 1 0 0 45 lut3_16 / dff13 (set/rst) output 1 0 1 1 0 1 46 lut3_17 / dff14 (set/rst) output 1 0 1 1 1 0 47 lut4_2 output 1 0 1 1 1 1 48 io9 digital input 1 1 0 0 0 0 49 io10 digital input 1 1 0 0 0 1 50 io11 digital input 1 1 0 0 1 0 51 io12 digital input 1 1 0 0 1 1 52 io13 digital input 1 1 0 1 0 0 53 io14 digital input 1 1 0 1 0 1 54 io15 digital input 1 1 0 1 1 0 55 io16 digital input 1 1 0 1 1 1 56 io17 digital input 1 1 1 0 0 0 57 acmp_0 output 1 1 1 0 0 1 58 acmp_1 output 1 1 1 0 1 0 59 acmp_2 output 1 1 1 0 1 1 60 acmp_3 output 1 1 1 1 0 0 61 programmable delay with e dge detector output 1 1 1 1 0 1 62 nrst_core (por) as matrix input 1 1 1 1 1 0 63 vdd 111111 table 39. matrix input table matrix input number matrix input signal function matrix decode 5 4 3 2 1 0 SLG46533_ds_114 page 48 of 184 SLG46533 8.2 matrix output table table 40. matrix output table register bit address matrix output signal function note: for each address, the two m ost significant bits are unuse d) matrix output number reg <7:0> matrix out: in0 of l ut3_11 or clock input of dff8 0 reg <15:8> matrix out: in1 of lut3_11 or data input of dff8 1 reg <23:16> matrix out: in2 of l ut3_11 or nrst (nset) of dff8 2 reg <31:24> matrix out: in0 of l ut3_12 or clock input of dff9 3 reg <39:32> matrix out: in1 of l ut3_12 or data input of dff9 4 reg <47:40> matrix out: in2 of l ut3_12 or nrst (nset) of dff9 5 reg <55:48> matrix out: in0 of l ut3_13 or clock input of dff10 6 reg <63:56> matrix out: in1 of l ut3_13 or data input of dff10 7 reg <71:64> matrix out: in2 of l ut3_13 or nrst (nset) of dff10 8 reg <79:72> matrix out: in0 of l ut3_14 or clock input of dff11 9 reg <87:80> matrix out: in1 of l ut3_14 or data input of dff11 10 reg <95:88> matrix out: in2 of l ut3_14 or nrst (nset) of dff11 11 reg <103:96> matrix out: in0 of l ut3_15 or clock input of dff12 1 2 reg <111:104> matrix out: in1 of l ut3_15 or data input of dff12 1 3 reg <119:112> matrix out: in2 of lut3_15 or nrst (nset) of dff12 14 reg <127:120> matrix out: in0 o f lut3_16 or clock input of dff13 15 reg <135:128> matrix out: in1 of l ut3_16 or data input of dff13 1 6 reg <143:136> matrix out: in2 of lut3_16 or nrst (nset) of dff13 17 reg <151:144> matrix out: in0 o f lut3_17 or clock input of dff14 18 reg <159:152> matrix out: in1 of l ut3_17 or data input of dff14 1 9 reg <167:160> matrix out: in2 of lut3_17 or nrst (nset) of dff14 20 reg <175:168> matrix out: in0 of lut4_2 21 reg <183:176> matrix out: in1 of lut4_2 22 reg <191:184> matrix out: in2 of lut4_2 23 reg <199:192> matrix out: in3 of lut4_2 24 reg <207:200> matrix out: io1 digital output source 25 reg <215:208> matrix out : io1 output enable 26 reg <223:216> matrix out: io2 digital output source 27 reg <231:224> matrix out: io3 digital output source 28 reg <239:232> matrix out : io3 output enable 29 reg <247:240> matrix out: io4 digital output source 30 reg <255:248> matrix out: io5 digital output source 31 reg <263:256> matrix out : io5 output enable 32 reg <271:264> matrix out: io6 dig ital output source (scl with vi /input & nmos open-drain) 33 reg <279:272> matrix out: io7 dig ital output source (sda with vi /input & nmos open-drain) 34 reg <287:280> matrix out: io8 digital output source 35 reg <295:288> matrix out : io8 output enable 36 reg <303:296> matrix out: io9 digital output source 37 SLG46533_ds_114 page 49 of 184 SLG46533 reg <311:304> matrix out: io 10 digital output source 38 reg <319:312> matrix out : io10 output enable 39 reg <327:320> matrix out: io1 1 digital output source 40 reg <335:328> matrix out: io11 output enable 41 reg <343:336> matrix out: io 12 digital output source 42 reg <351:344> matrix out: io 13 digital output source 43 reg <359:352> matrix out : io13 output enable 44 reg <367:360> matrix out: io 14 digital output source 45 reg <375:368> matrix out: io 15 digital output source 46 reg <383:376> matrix out : io15 output enable 47 reg <391:384> matrix out: io 16 digital output source 48 reg <399:392> matrix out : io16 output enable 49 reg <407:400> matrix out: io 17 digital output source 50 reg <415:408> matrix out: acmp0 pdb (power down) 51 reg <423:416> matrix out: acmp1 pdb (power down) 52 reg <431:424> matrix out: acmp2 pdb (power down) 53 reg <439:432> matrix out: acmp3 pdb (power down) 54 reg <447:440> matrix out: input of filter_0 with fixed time edge detector 55 reg <455:448> matrix out: input of filter_1 with fixed time edge detector 56 reg <463:456> matrix out: input of programmable delay & edge det ector 57 reg <471:464> matrix out: osc 25khz/2mhz pdb (power down) 58 reg <479:472> matrix out: os c 25mhz pdb (power down) 59 reg <487:480> matrix out: in0 o f lut2_0 or clock input of dff0 60 reg <495:488> matrix out: in1 o f lut2_0 or data input of dff0 61 reg <503:496> matrix out: in0 o f lut2_1 or clock input of dff1 62 reg <511:504> matrix out: in1 o f lut2_1 or data input of dff1 63 reg <519:512> matrix out: in0 o f lut2_2 or clock input of dff2 64 reg <527:520> matrix out: in1 o f lut2_2 or data input of dff2 65 reg <535:528> matrix out: in0 o f lut2_3 or clock input of pgen 66 reg <543:536> matrix out: in1 of lut2_3 or nrst of pgen 67 reg <551:544> matrix out: in0 o f lut3_0 or clock input of dff3 68 reg <559:552> matrix out: in1 o f lut3_0 or data input of dff3 69 reg <567:560> matrix out: in2 of l ut3_0 or nrst (nset) of dff3 70 reg <575:568> matrix out: in0 o f lut3_1 or clock input of dff4 71 reg <583:576> matrix out: in1 o f lut3_1 or data input of dff4 72 reg <591:584> matrix out: in2 of l ut3_1 or nrst (nset) of dff4 73 reg <599:592> matrix out: in0 o f lut3_2 or clock input of dff5 74 reg <607:600> matrix out: in1 o f lut3_2 or data input of dff5 75 reg <615:608> matrix out: in2 of l ut3_2 or nrst (nset) of dff5 76 table 40. matrix output table register bit address matrix output signal function note: for each address, the two m ost significant bits are unuse d) matrix output number SLG46533_ds_114 page 50 of 184 SLG46533 reg <623:616> matrix out: in0 o f lut3_3 or clock input of dff6 77 reg <631:624> matrix out: in1 o f lut3_3 or data input of dff6 78 reg <639:632> matrix out: in2 of l ut3_3 or nrst (nset) of dff6 79 reg <647:640> matrix out: in0 o f lut3_4 or clock input of dff7 80 reg <655:648> matrix out: in1 o f lut3_4 or data input of dff7 81 reg <663:656> matrix out: in2 of l ut3_4 or nrst (nset) of dff7 82 reg <671:664> matrix out: in0 of lut3_5 or delay2 input (or coun ter2 rst input) 83 reg <679:672> matrix out: in1 o f lut3_5 or external clock input of delay2 (or counter2) 84 reg <687:680> matrix out: in2 of lut3_5 85 reg <695:688> matrix out: in0 of lut3_6 or delay3 input (or coun ter3 rst input) 86 reg <703:696> matrix out: in1 o f lut3_6 or external clock input of delay3 (or counter3) 87 reg <711:704> matrix out: in2 of lut3_6 88 reg <719:712> matrix out: in0 of lut3_7 or delay4 input (or coun ter4 rst input) 89 reg <727:720> matrix out: in1 o f lut3_7 or external clock input of delay4 (or counter4) 90 reg <735:728> matrix out: in2 of lut3_7 91 reg <743:736> matrix out: in0 of lut3_8 or delay5 input (or coun ter5 rst input) 92 reg <751:744> matrix out: in1 o f lut3_8 or external clock input of delay5 (or counter5) 93 reg <759:752> matrix out: in2 of lut3_8 94 reg <767:760> matrix out: in0 of lut3_9 or delay6 input (or coun ter6 rst input) 95 reg <775:768> matrix out: in1 o f lut3_9 or external clock input of delay6 (or counter6) 96 reg <783:776> matrix out: in2 of lut3_9 97 reg <791:784> matrix out: in0 o f lut3_10 or input of pipe delay 9 8 reg <799:792> matrix out: in1 of l ut3_10 or nrst of pipe delay 99 reg <807:800> matrix out: in2 of lut3_10 or clock of pipe delay 1 00 reg <815:808> matrix out: in0 of lut4_0 or delay0 input (or coun ter0 rst/set input) 101 reg <823:816> matrix out: in1 o f lut4_0 or external clock input of delay0 (or counter0) 102 reg <831:824> matrix out: in2 o f lut4_0 or up input of fsm0 103 reg <839:832> matrix out: in3 o f lut4_0 or keep input of fsm0 104 reg <847:840> matrix out: in0 of lut4_1 or delay1 input (or coun ter1 rst/set input) 105 reg <855:848> matrix out: in1 o f lut4_1 or external clock input of delay1 (or counter1) 106 reg <863:856> matrix out: in2 o f lut4_1 or up input of fsm1 107 reg <871:864> matrix out: in3 o f lut4_1 or keep input of fsm1 108 reg <879:872> matrix out: pd of ei ther temp-output with bg and/o r crystal oscillator by reg<1268> 109 table 40. matrix output table register bit address matrix output signal function note: for each address, the two m ost significant bits are unuse d) matrix output number SLG46533_ds_114 page 51 of 184 SLG46533 8.3 connection matrix virtual inputs as mentioned previously, the conn ection matrix inputs come from the outputs of various digital m acrocells on the device. eight of the connection matrix inputs have the special characteristic that the state of these signal lines comes from a correspondin g data bit written as a register value via i 2 c. this gives the user the ability to write data via the serial channel, and have this information translated into sig nals that can be driven into the connection matrix and from the connection matrix to the digita l inputs of other macrocell s on the device. the i 2 c address for reading and writing these regist er values is at b yte 0244. six of the eight connection matr ix virtual inputs are dedicated to this virtual input function. an i 2 c write command to these register bits will set the signal values going into the connection matri x to the desired state. a read command to these register bits w ill read either the original data values coming from the nvm memory bits (that were loaded during the initial device startup), or the v alues from a previous write command (if that has happened). two of the eight connection matrix virtual inputs are shared wi th pin digital inputs, (io6 digi tal or i2c_virtual_0 input) and (io7 digital or i2c_virtual_1 input). if the virtual input mode is s elected, an i 2 c write command to these register bits will set the signal values going into the connection matrix to the desired state. t wo register bits select whether the connection matrix input com es from the pin input or fr om the virtual register: ? reg <1074> select scl & v irtual input 0 or io6 ? reg <1082> select sda & virtual input 1 or io7 see table below for connecti on matrix virtual inputs. 8.4 connection matrix virtual outputs the digital outputs of the various macrocells are routed to the connection matrix to enable interconnections to the inputs of other macrocells in the device. at the same time, it is possible to r ead the state of each of the macrocell outputs as a register va lue via i 2 c. this option, called connecti on matrix virtual outputs, allow s the user to remotely read the values of each macrocell output . the i 2 c addresses for reading these register values are at bytes 0240 to 0247. write commands to these same register values will be ignored (with the exception of the virtual input regist er bits at byte 0244). matrix input number matrix input signal function register bit addresses (d) 32 i2c_virtual_0 input reg<1952> 33 i2c_virtual_1 input reg<1953> 34 i2c_virtual_2 input reg<1954> 35 i2c_virtual_3 input reg<1955> 36 i2c_virtual_4 input reg<1956> 37 i2c_virtual_5 input reg<1957> 38 i2c_virtual_6 input reg<1958> 39 i2c_virtual_7 input reg<1959> SLG46533_ds_114 page 52 of 184 SLG46533 9.0 combination function macrocells the SLG46533 has twenty-four com bination function macrocells th at can serve more than one log ic or timing function. in each case, they can serve as a look up table (lut), or as another lo gic or timing function. see the list below for the functions th at can be implemented in these macrocells: ? three macrocells that can serve as either 2-bit luts or as d f lip flops; ? twelve macrocells that can serve as either 3-bit luts or as d flip flops with set/reset input; ? one macrocell that can serve as either 3-bit lut or as pipe de lay; ? one macrocell that can serve as either 2-bit lut or as program mable pattern generator (pgen); ? five macrocells that can serve as either 3-bit luts or as 8-bi t counter / delays; ? two macrocells that can serve as either 4-bit luts or as 16-bi t counter / delays. inputs/outputs for the 24 combi nation function macrocells are c onfigured from the connection matrix with specific logic functi ons being defined by the state of nvm bits. when used as a lut to implement combinatorial logic functions, the outputs of the luts can be configured to any user defined function, including th e following standard digital logic device s (and, nand, or, nor, xor, xnor). 9.1 2-bit lut or d flip flop macrocells there are three macrocells that c an serve as either 2-bit luts or as d flip flops. when used to implement lut functions, the 2-bit luts each take in two input signals from the connection m atrix and produce a single output, which goes back into the connection matrix. when used to implement d flip flop function, the two input signals from the connection matrix go to the dat a (d) and clock (clk) inputs for t he flip flop, with the output g oing back to the connection matrix. the operation of the d flip-flop and latch will follow the func tional descriptions below: dff: clk is rising edge triggered , then q = d; otherwise q will not change. latch: when clk is low, then q = d; otherwise q remains its pre vious value (input d has no effect on the output, when clk is h igh figure 10. 2-bit lut0 or dff0 dff0 clk d 2-bit lut0 out in0 in1 to connection matrix input <8> 4-bits nvm from connection matrix output <61> 1-bit nvm reg <1207:1204> reg <1191> from connection matrix output <60> q/nq reg <1207> dff or latch select reg <1206> output select (q or nq) reg <1205> dff initial polarity select lut truth table dff registers s0 s1 s0 s1 s0 s1 0: 2-bit lut0 in0 1: dff0 clk 0: 2-bit lut0 in1 1: dff0 data 0: 2-bit lut0 out 1: dff0 out SLG46533_ds_114 page 53 of 184 SLG46533 figure 11. 2-bit lut1 or dff1 figure 12. 2-bit lut2 or dff2 dff1 clk d 2-bit lut1 out in0 in1 to connection matrix input <9> 4-bits nvm from connection matrix output <63> 1-bit nvm reg <1203:1200> reg <1190> from connection matrix output <62> q/nq reg <1203> dff or latch select reg <1202> output select (q or nq) reg <1201> dff initial polarity select lut truth table dff registers s0 s1 s0 s1 s0 s1 0: 2-bit lut1 in0 1: dff1 clk 0: 2-bit lut1 in1 1: dff1 data 0: 2-bit lut1 out 1: dff1 out dff2 clk d 2-bit lut2 out in0 in1 to connection matrix input <10> 4-bits nvm from connection matrix output <65> 1-bit nvm reg <1215:1212> reg <1189> from connection matrix output <64> q/nq reg <1215> dff or latch select reg <1214> output select (q or nq) reg <1213> dff initial polarity select lut truth table dff registers s0 s1 s0 s1 s0 s1 0: 2-bit lut2 in0 1: dff2 clk 0: 2-bit lut2 in1 1: dff2 data 0: 2-bit lut2 out 1: dff2 out SLG46533_ds_114 page 54 of 184 SLG46533 9.1.1 2-bit lut or d flip flop macrocells used as 2-bit luts each macrocell, when programmed for a lut function, uses a 4-bi t register to define their output function: 2-bit lut0 is defined by reg<1207:1204> 2-bit lut1 is defined by reg<1203:1200> 2-bit lut2 is defined by reg<1215:1212> the table below shows the regist er bits for the standard digita l logic devices (and, nand, or , nor, xor, xnor) that can be created within each of the t wo 2-bit lut logic cells. table 44. 2-bit lut stand ard digital functions function msb lsb and-2 1000 nand-2 0 1 1 1 or-2 1110 nor-2 0 0 0 1 xor-2 0110 xnor-2 1001 table 41. 2-bit lut0 truth table in1 in0 out 0 0 reg <1204> lsb 0 1 reg <1205> 1 0 reg <1206> 1 1 reg <1207> msb table 42. 2-bit lut1 truth table in1 in0 out 0 0 reg <1200> lsb 0 1 reg <1201> 1 0 reg <1202> 1 1 reg <1203> msb table 43. 2-bit lut2 truth table in1 in0 out 0 0 reg <1212> lsb 0 1 reg <1213> 1 0 reg <1214> 1 1 reg <1215> msb SLG46533_ds_114 page 55 of 184 SLG46533 9.1.2 2-bit lut or d flip flop macrocells used as d flip flop register se ttings table 45. dff0 register settings signal function register bit address register definition lut2_0 or dff0 select reg <1191> 0: lut2_0 1: dff0 dff0 initial polarity select reg <1205> 0: low 1: high dff0 output select re g <1206> 0: q output 1: nq output dff0 or latch select reg <1207> 0: dff function 1: latch function table 46. dff1 register settings signal function register bit address register definition lut2_1 or dff1 select reg <1190> 0: lut2_1 1: dff1 dff1 initial polarity select reg <1201> 0: low 1: high dff1 output select re g <1202> 0: q output 1: nq output select or latch select reg <1203> 0: dff function 1: latch function table 47. dff2 register settings signal function register bit address register definition lut2_2 or dff2 select reg <1189> 0: lut2_2 1: dff2 dff2 initial polarity select reg <1213> 0: low 1: high dff2 output select re g <1214> 0: q output 1: nq output dff2 or latch select reg <1215> 0: dff function 1: latch function SLG46533_ds_114 page 56 of 184 SLG46533 9.2 3-bit lut or d flip flop with set/reset macrocells there are twelve macrocells that can serve as either 3-bit luts or as d flip flops with set/reset inputs. when used to impleme nt lut functions, the 3-bit luts each take in three input signals from the connection matrix and produce a single output, which g oes back into the connection matrix. when used to implement d flip flop function, the three input signals from the connection matr ix go to the data (d) and clock (clk) and set/reset (nrst/nset) in puts for the flip flop, with the output going back to the conne ction matrix. figure 13. dff polarity operations SLG46533_ds_114 page 57 of 184 SLG46533 figure 14. 3-bit lut0 or dff3 with rst/set figure 15. 3-bit lut1 or dff4 with rst/set dff3 clk d to connection matrix< input 12> 8-bits nvm from connection matrix output <70> 1-bit nvm 3-bit lut0 out in1 in2 in0 nrst/nset from connection matrix output <69> from connection matrix output <68> reg <1223:1216> reg <1187> reg <1471> selects output from one or two dff q/nq ddq q reg <1222> reg <1471> lut truth tab l e reg <1223> dff or latch select reg <1222> output select (q or nq) reg <1221> dff nrst or nset select reg <1220> dff initial polarity select 0: 3-bit lut0 in1 1: dff3 d 0: 3-bit lut0 in2 1: dff3 nrst/nset 0: 3-bit lut0 out 1: dff3 out 0: 3-bit lut0 in0 1: dff3 clk s0 s1 s0 s1 s0 s1 s0 s1 dff4 clk d 8-bits nvm 1-bit nvm 3-bit lut1 out in1 in2 in0 nrst/nset from connection matrix output <73> from connection matrix output <72> from connection matrix output <71> reg <1231:1224> reg <1186> to connection matrix input <13> q/nq reg <1231> dff or latch select reg <1230> output select (q or nq) reg <1229> dff nrst or nset select reg <1228> dff initial polarity select lut truth tab l e dff registers 0: 3-bit lut1 in1 1: dff4 d 0: 3-bit lut1 in2 1: dff4 nrst/nset 0: 3-bit lut1 out 1: dff4 out 0: 3-bit lut1 in0 1: dff4 clk s0 s1 s0 s1 s0 s1 s0 s1 SLG46533_ds_114 page 58 of 184 SLG46533 figure 16. 3-bit lut2 or dff5 with rst/set figure 17. 3-bit lut3 or dff6 with rst/set dff5 clk d to connection matrix input <14> 8-bits nvm from connection matrix output <76> 1-bit nvm 3-bit lut2 out in1 in2 in0 nrst/nset from connection matrix output <75> from connection matrix output <74> reg <1239:1232> reg <1185> q/nq reg <1239> dff or latch select reg <1238> output select (q or nq) reg <1237> dff nrst or nset select reg <1236> dff initial polarity select lut truth table dff registers 0: 3-bit lut2 in1 1: dff5 d 0: 3-bit lut2 in2 1: dff5 nrst/nset 0: 3-bit lut2 out 1: dff5 out 0: 3-bit lut2 in0 1: dff5 clk s0 s1 s0 s1 s0 s1 s0 s1 dff6 clk d 8-bits nvm 1-bit nvm 3-bit lut3 out in1 in2 in0 nrst/nset from connection matrix output <79> from connection matrix output <78> from connection matrix output <77> reg <1247:1240> reg <1184> to connection matrix input <15> q/nq reg <1247> dff or latch select reg <1246> output select (q or nq) reg <1245> dff nrst or nset select reg <1244> dff initial polarity select lut truth tab l e dff registers 0: 3-bit lut3 in1 1: dff6 d 0: 3-bit lut3 in2 1: dff6 nrst/nset 0: 3-bit lut3 out 1: dff6 out 0: 3-bit lut3 in0 1: dff6 clk s0 s1 s0 s1 s0 s1 s0 s1 SLG46533_ds_114 page 59 of 184 SLG46533 figure 18. 3-bit lut4 or dff7 with rst/set figure 19. 3-bit lut11 or dff8 with rst/set dff7 clk d to connection matrix input <16> 8-bits nvm from connection matrix output <82> 1-bit nvm 3-bit lut4 out in1 in2 in0 nrst/nset from connection matrix output <81> from connection matrix output <80> reg <1255:1248> reg <1199> q/nq reg <1255> dff or latch select reg <1254> output select (q or nq) reg <1253> dff nrst or nset select reg <1252> dff initial polarity select lut truth table dff registers 0: 3-bit lut4 in1 1: dff7 d 0: 3-bit lut4 in2 1: dff7 nrst/nset 0: 3-bit lut4 out 1: dff7 out 0: 3-bit lut4 in0 1: dff7 clk s0 s1 s0 s1 s0 s1 s0 s1 dff8 clk d to connection matrix input <40> 8-bits nvm from connection matrix output <2> 1-bit nvm 3-bit lut11 out in1 in2 in0 nrst/nset from connection matrix output <1> from connection matrix output <0> reg <1375:1368> reg <1367> q/nq reg <1375> dff or latch select reg <1374> output select (q or nq) reg <1373> dff nrst or nset select reg <1372> dff initial polarity select lut truth table dff registers 0: 3-bit lut11 in1 1: dff8 d 0: 3-bit lut11 in1 1: dff8 nrst/nset 0: 3-bit lut11 out 1: dff8 out 0: 3-bit lut11 in0 1: dff8 clk s0 s1 s0 s1 s0 s1 s0 s1 SLG46533_ds_114 page 60 of 184 SLG46533 figure 20. 3-bit lut12 or dff9 with rst/set figure 21. 3-bit lut13 or dff10 with rst/set dff9 clk d 8-bits nvm 1-bit nvm 3-bit lut12 out in1 in2 in0 nrst/nset from connection matrix output <5> from connection matrix output <4> from connection matrix output <3> reg <1383:1376> reg <1366> to connection matrix input <41> q/nq reg <1383> dff or latch select reg <1382> output select (q or nq) reg <1381> dff nrst or nset select reg <1380> dff initial polarity select lut truth tab l e dff registers 0: 3-bit lut12 in1 1: dff9 d 0: 3-bit lut12 in2 1: dff9 nrst/nset 0: 3-bit lut12 out 1: dff9 out 0: 3-bit lut12 in0 1: dff9 clk s0 s1 s0 s1 s0 s1 s0 s1 dff10 clk d to connection matrix input <42> 8-bits nvm from connection matrix output <8> 1-bit nvm 3-bit lut13 out in1 in2 in0 nrst/nset from connection matrix output <7> from connection matrix output <6> reg <1391:1384> reg <1365> q/nq reg <1391> dff or latch select reg <1390> output select (q or nq) reg <1389> dff nrst or nset select reg <1388> dff initial polarity select lut truth table dff registers 0: 3-bit lut13 in1 1: dff10 d 0: 3-bit lut13 in2 1: dff10 nrst/nset 0: 3-bit lut13 out 1: dff10 out 0: 3-bit lut13 in0 1: dff10 clk s0 s1 s0 s1 s0 s1 s0 s1 SLG46533_ds_114 page 61 of 184 SLG46533 figure 22. 3-bit lut14 or dff11with rst/set figure 23. 3-bit lut15 or dff12 with rst/set dff11 clk d to connection matrix input <43> 8-bits nvm from connection matrix output <11> 1-bit nvm 3-bit lut14 out in1 in2 in0 nrst/nset from connection matrix output <10> from connection matrix output <9> reg <1399:1392> reg <1364> q/nq reg <1399> dff or latch select reg <1398> output select (q or nq) reg <1397> dff nrst or nset select reg <1396> dff initial polarity select lut truth table dff registers 0: 3-bit lut14 in1 1: dff11 d 0: 3-bit lut14 in2 1: dff11 nrst/nset 0: 3-bit lut14 out 1: dff11 out 0: 3-bit lut14 in0 1: dff11 clk s0 s1 s0 s1 s0 s1 s0 s1 dff12 clk d to connection matrix input <44> 8-bits nvm from connection matrix output <14> 1-bit nvm 3-bit lut15 out in1 in2 in0 nrst/nset from connection matrix output <13> from connection matrix output <12> reg <1407:1400> reg <1363> q/nq reg <1407> dff or latch select reg <1406> output select (q or nq) reg <1405> dff nrst or nset select reg <1404> dff initial polarity select lut truth table dff registers 0: 3-bit lut15 in1 1: dff12 d 0: 3-bit lut15 in2 1: dff12 nrst/nset 0: 3-bit lut15 out 1: dff12 out 0: 3-bit lut15 in0 1: dff12 clk s0 s1 s0 s1 s0 s1 s0 s1 SLG46533_ds_114 page 62 of 184 SLG46533 figure 24. 3-bit lut16 or dff13 with rst/set figure 25. 3-bit lut17 or dff14 with rst/set dff13 clk d 8-bits nvm 1-bit nvm 3-bit lut16 out in1 in2 in0 nrst/nset from connection matrix output <17> from connection matrix output <16> from connection matrix output <15> reg <1415:1408> reg <1362> to connection matrix input <45> q/nq reg <1415> dff or latch select reg <1414> output select (q or nq) reg <1413> dff nrst or nset select reg <1412> dff initial polarity select lut truth tab l e dff registers 0: 3-bit lut16 in1 1: dff13 d 0: 3-bit lut16 in2 1: dff13 nrst/nset 0: 3-bit lut16 out 1: dff13 out 0: 3-bit lut16 in0 1: dff13 clk s0 s1 s0 s1 s0 s1 s0 s1 dff14 clk d to connection matrix input <46> 8-bits nvm from connection matrix output <20> 1-bit nvm 3-bit lut17 out in1 in2 in0 nrst/nset from connection matrix output <19> from connection matrix output <18> reg <1423:1416> reg <1361> q/nq reg <1423> dff or latch select reg <1422> output select (q or nq) reg <1421> dff nrst or nset select reg <1420> dff initial polarity select lut truth table dff registers 0: 3-bit lut17 in1 1: dff14 d 0: 3-bit lut17 in2 1: dff14 nrst/nset 0: 3-bit lut17 out 1: dff14 out 0: 3-bit lut17 in0 1: dff14 clk s0 s1 s0 s1 s0 s1 s0 s1 SLG46533_ds_114 page 63 of 184 SLG46533 9.2.1 3-bit lut or d flip flop macrocells used as 3-bit luts table 48. 3-bit lut0 truth table in2 in1 in0 out 0 0 0 reg <1216> lsb 0 0 1 reg <1217> 0 1 0 reg <1218> 0 1 1 reg <1219> 1 0 0 reg <1220> 1 0 1 reg <1221> 1 1 0 reg <1222> 1 1 1 reg <1223> msb table 49. 3-bit lut1 truth table in2 in1 in0 out 0 0 0 reg <1224> lsb 0 0 1 reg <1225> 0 1 0 reg <1226> 0 1 1 reg <1227> 1 0 0 reg <1228> 1 0 1 reg <1229> 1 1 0 reg <1230> 1 1 1 reg <1231> msb table 50. 3-bit lut2 truth table in2 in1 in0 out 0 0 0 reg <1232> lsb 0 0 1 reg <1233> 0 1 0 reg <1234> 0 1 1 reg <1235> 1 0 0 reg <1236> 1 0 1 reg <1237> 1 1 0 reg <1238> 1 1 1 reg <1239> msb table 51. 3-bit lut3 truth table in2 in1 in0 out 0 0 0 reg <1240> lsb 0 0 1 reg <1241> 0 1 0 reg <1242> 0 1 1 reg <1243> 1 0 0 reg <1244> 1 0 1 reg <1245> 1 1 0 reg <1246> 1 1 1 reg <1247> msb table 52. 3-bit lut4 truth table in2 in1 in0 out 0 0 0 reg <1248> lsb 0 0 1 reg <1249> 0 1 0 reg <1250> 0 1 1 reg <1251> 1 0 0 reg <1252> 1 0 1 reg <1253> 1 1 0 reg <1254> 1 1 1 reg <1255> msb table 53. 3-bit lut11 truth table in2 in1 in0 out 0 0 0 reg <1368> lsb 0 0 1 reg <1369> 0 1 0 reg <1370> 0 1 1 reg <1371> 1 0 0 reg <1372> 1 0 1 reg <1373> 1 1 0 reg <1374> 1 1 1 reg <1375> msb table 54. 3-bit l ut12 truth table in2 in1 in0 out 0 0 0 reg <1376> lsb 0 0 1 reg <1377> 0 1 0 reg <1378> 0 1 1 reg <1379> 1 0 0 reg <1380> 1 0 1 reg <1381> 1 1 0 reg <1382> 1 1 1 reg <1383> msb table 55. 3-bit l ut13 truth table in2 in1 in0 out 0 0 0 reg <1384> lsb 0 0 1 reg <1385> 0 1 0 reg <1386> 0 1 1 reg <1387> 1 0 0 reg <1388> 1 0 1 reg <1389> 1 1 0 reg <1390> 1 1 1 reg <1391> msb SLG46533_ds_114 page 64 of 184 SLG46533 each macrocell, when programmed for a lut function, uses a 8-bi t register to define their output function: 3-bit lut0 is defined by reg<1223:1216> 3-bit lut1 is defined by reg<1231:1324> 3-bit lut2 is defined by reg<1239:1232> 3-bit lut3 is defined by reg<1247:1240> 3-bit lut4 is defined by reg<1255:1248> 3-bit lut11 is defined by reg<1375:1368> 3-bit lut12 is defined by reg<1383:1376> 3-bit lut13 is defined by reg<1391:1384> 3-bit lut14 is defined by reg<1399:1392> 3-bit lut15 is defined by reg<1407:1400> 3-bit lut16 is defined by reg<1415:1408> 3-bit lut17 is defined by reg<1423:1416> table 56. 3-bit lut14 truth table in2 in1 in0 out 0 0 0 reg <1392> lsb 0 0 1 reg <1393> 0 1 0 reg <1394> 0 1 1 reg <1395> 1 0 0 reg <1396> 1 0 1 reg <1397> 1 1 0 reg <1398> 1 1 1 reg <1399> msb table 57. 3-bit lut15 truth table in2 in1 in0 out 0 0 0 reg <1400> lsb 0 0 1 reg <1401> 0 1 0 reg <1402> 0 1 1 reg <1403> 1 0 0 reg <1404> 1 0 1 reg <1405> 1 1 0 reg <1406> 1 1 1 reg <1407> msb table 58. 3-bit l ut16 truth table in2 in1 in0 out 0 0 0 reg <1408> lsb 0 0 1 reg <1409> 0 1 0 reg <1410> 0 1 1 reg <1411> 1 0 0 reg <1412> 1 0 1 reg <1413> 1 1 0 reg <1414> 1 1 1 reg <1415> msb table 59. 3-bit l ut17 truth table in2 in1 in0 out 0 0 0 reg <1416> lsb 0 0 1 reg <1417> 0 1 0 reg <1418> 0 1 1 reg <1419> 1 0 0 reg <1420> 1 0 1 reg <1421> 1 1 0 reg <1422> 1 1 1 reg <1423> msb SLG46533_ds_114 page 65 of 184 SLG46533 the table below shows the regist er bits for the standard digita l logic devices (and, nand, or , nor, xor, xnor) that can be created within each of the s ix 3-bit lut logic cells. 9.2.2 3-bit lut or d flip flop macrocells used as d flip flop register settings table 60. 3-bit lut stand ard digital functions function msb lsb and-3 10000000 nand-3 01111111 or-3 11111110 nor-3 00000001 xor-3 10010110 xnor-3 01101001 table 61. dff3 register settings signal function register bit address register definition lut3_0 or dff3 select reg<1187> 0: lut3_0 1: dff3 dff3 initial polarity select reg<1220> 0: low 1: high dff3 nrst/nset select reg<1221> 1: nset from matrix out 0: nrst from matrix out dff3 output select reg<1222> 0: q output 1: nq output dff3 or latch select reg<1223> 0: dff function 1: latch function table 62. dff4 register settings signal function register bit address register definition lut3_1 or dff4 select reg<1186> 0: lut3_1 1: dff4 dff4 initial polarity select reg<1128> 0: low 1: high dff4 nrst/nset select reg<1129> 1: nset from matrix out 0: nrst from matrix out dff4 output select reg<1130> 0: q output 1: nq output dff4 or latch select reg<1131> 0: dff function 1: latch function SLG46533_ds_114 page 66 of 184 SLG46533 table 63. dff5 register settings signal function register bit address register definition lut3_2 or dff5 select reg<1185> 0: lut3_2 1: dff5 dff5 initial polarity select reg<1236> 0: low 1: high dff5 nrst/nset select reg<1237> 1: nset from matrix out 0: nrst from matrix out dff5 output select reg<1238> 0: q output 1: nq output dff5 or latch select reg<1239> 0: dff function 1: latch function table 64. dff6 register settings signal function register bit address register definition lut3_3 or dff6 select reg<1184> 0: lut3_3 1: dff6 dff6 initial polarity select reg<1244> 0: low 1: high dff6 nrst/nset select reg<1245> 1: nset from matrix out 0: nrst from matrix out dff6 output select reg<1246> 0: q output 1: nq output dff6 or latch select reg<1247> 0: dff function 1: latch function table 65. dff7 register settings signal function register bit address register definition lut3_4 or dff7 select reg<1199> 0: lut3_4 1: dff7 dff7 initial polarity select reg<1252> 0: low 1: high dff7 nrst/nset select reg<1253> 1: nset from matrix out 0: nrst from matrix out dff7 output select reg<1254> 0: q output 1: nq output dff7 or latch select reg<1255> 0: dff function 1: latch function SLG46533_ds_114 page 67 of 184 SLG46533 table 66. dff8 register settings signal function register bit address register definition lut3_11 or dff8 select reg<1367> 0: lut3_2 1: dff8 dff8 initial polarity select reg<1372> 0: low 1: high dff8 nrst/nset select reg<1373> 1: nset from matrix out 0: nrst from matrix out dff8 output select reg<1374> 0: q output 1: nq output dff8 or latch select reg<1375> 0: dff function 1: latch function table 67. dff9 register settings signal function register bit address register definition lut3_12 or dff9 select reg<1366> 0: lut3_12 1: dff9 dff9 initial polarity select reg<1380> 0: low 1: high dff9 nrst/nset select reg<1381> 1: nset from matrix out 0: nrst from matrix out dff9 output select reg<1382> 0: q output 1: nq output dff9 or latch select reg<1383> 0: dff function 1: latch function table 68. dff10 register settings signal function register bit address register definition lut3_13 or dff10 select reg<1365> 0: lut3_13 1: dff10 dff10 initial polarity select reg<1388> 0: low 1: high dff10 nrst/nset select reg<1389> 1: nset from matrix out 0: nrst from matrix out dff10 output select reg<1390> 0: q output 1: nq output dff10 or latch select reg<1391> 0: dff function 1: latch function SLG46533_ds_114 page 68 of 184 SLG46533 table 69. dff11 register settings signal function register bit address register definition lut3_14 or dff11 select reg<1364> 0: lut3_2 1: dff11 dff11 initial polarity select reg<1396> 0: low 1: high dff11 nrst/nset select reg<1397> 1: nset from matrix out 0: nrst from matrix out dff11 output select reg<1398> 0: q output 1: nq output dff11 or latch select reg<1399> 0: dff function 1: latch function table 70. dff12 register settings signal function register bit address register definition lut3_15 or dff12 select reg<1363> 0: lut3_3 1: dff12 dff12 initial polarity select reg<1404> 0: low 1: high dff12 nrst/nset select reg<1405> 1: nset from matrix out 0: nrst from matrix out dff12 output select reg<1406> 0: q output 1: nq output dff12 or latch select reg<1407> 0: dff function 1: latch function table 71. dff13 register settings signal function register bit address register definition lut3_16 or dff13 select reg<1362> 0: lut3_4 1: dff13 dff13 initial polarity select reg<1412> 0: low 1: high dff13 nrst/nset select reg<1413> 1: nset from matrix out 0: nrst from matrix out dff13 output select reg<1414> 0: q output 1: nq output dff13 or latch select reg<1415> 0: dff function 1: latch function SLG46533_ds_114 page 69 of 184 SLG46533 table 72. dff14 register settings signal function register bit address register definition lut3_17 or dff14 select reg<1361> 0: lut3_17 1: dff14 dff14 initial polarity select reg<1420> 0: low 1: high dff14 nrst/nset select reg<1421> 1: nset from matrix out 0: nrst from matrix out dff14 output select reg<1422> 0: q output 1: nq output dff14 or latch select reg<1423> 0: dff function 1: latch function SLG46533_ds_114 page 70 of 184 SLG46533 9.3 initial polarity operations figure 26. dff polarity operations with nreset SLG46533_ds_114 page 71 of 184 SLG46533 figure 27. dff polarity operations with nset SLG46533_ds_114 page 72 of 184 SLG46533 9.4 3-bit lut or pipe delay macrocell there is one macrocell that can serve as either a 3-bit lut or as a pipe delay. when used to implement lut functions, the 3-bit lut take in thr ee input signals from the connection matrix and produces a sing le output, which goes back in to the connection matrix. when used as a pipe delay, there are three inputs signals from the matrix, input (in), clock (c lk) and reset (nrst). the pipe delay cell is built from 16 d flip-flop logic cells that provid e the three output opt ions, two of which ar e user selectable. t he dff cells are tied in series where the output (q) of each delay cel l goes to the next dff cell. the first delay option is fixed at the output of the first flip-flop stage. the other two outputs (out0 and o ut1) provide user selectable options for 1 C 16 stages of delay there are delay output points for each set of the out0 and out1 outputs to a 16-input mux that is controlled by reg <1259:1256 > for out0 and reg <1263:1260> for out1. the 16-input mux is used to select the amount of delay. the overall time of the delay is based on the clock used in the SLG46533 design. each dff cell has a time delay of the inverse of the clock time (either extern al clock or the r c oscillator w ithin the SLG46533). th e sum of the number of dff cells used wi ll be the total time delay of the pipe delay logic cell. note: clk is rising edge triggered. figure 28. 3-bit lut10 or pipe delay 3-bit lut10 out in1 in0 from connection matrix output <98> from connection matrix output <99> in2 from connection matrix output <100> 16 flip-flops nrst in clk from connection matrix output <98> from connection matrix output <99> from connection matrix output <100> reg <1263:1260> reg <1259:1256> to connection matrix input<26> to connection matrix input <25> out1 out0 reg <1271> to connection matrix input <24> 1 pipe out s0 s1 s0 s1 lut truth ta bl e reg <1263:1256> reg <1270> SLG46533_ds_114 page 73 of 184 SLG46533 9.4.1 3-bit lut or pipe delay macrocells used as 3-bit luts each macrocell, when programmed for a lut function, uses a 8-bi t register to define their output function: 3-bit lut10 is defined by reg<1263:1256> 9.4.2 3-bit lut or pipe delay macrocells used as pipe delay r egister settings table 74. pipe delay register settings signal function register bit address register definition lut3_10 or pipe delay output select reg<1270> 0: lut3_10 1: 1 pipe delay output out0 select reg<1259:1256> out1 select reg<1263:1260> pipe delay out1 polarity select bit reg<1271> 0: non-inverted 1: inverted table 73. 3-bit lut10 truth table in2 in1 in0 out 0 0 0 reg <1256> lsb 0 0 1 reg <1257> 0 1 0 reg <1258> 0 1 1 reg <1259> 1 0 0 reg <1260> 1 0 1 reg <1261> 1 1 0 reg <1262> 1 1 1 reg <1263> msb SLG46533_ds_114 page 74 of 184 SLG46533 9.5 3-bit lut or 8-bit counter / delay macrocells there are five macrocells that c an serve as either 3-bit luts o r as counter / delays. when used to implement lut function, the 3-bit lut takes in three input signals from the connection matr ix and produces a single output, which goes back into the conne c- tion matrix. when used to implem ent 8-bit counter / delay funct ion, two of the three input signal s from the connection matrix go to the external clock (ext_clk) and reset (dly_in/cnt_reset) fo r the counter/delay, with the output going back to the connecti on matrix. these macrocells can also opera te in a one-shot mode, which wil l generate an output puls e of user-defined width. these macrocells can also operate in a frequency detection or e dge detection mode. for timing diagrams refer to section 9.7 cnt/dly/fsm timing diagrams two of the five macrocells can have their active count value re ad via i 2 c (cnt4 and cnt6). see section 18.5.1.2 reading counter data via i2c for further details. 9.5.1 3-bit lut or 8- bi t cnt/dly block diagrams figure 29. 3-bit lut5 or cnt/dly2 cnt/dly2 out clk dly_in/cnt_reset 3-bit lut5 out in0 in1 8-bits nvm 1-bit nvm in2 reg <1543:1536> reg <1198> from connection matrix output <83> from connection matrix output <84> to connection matrix input <17> from connection matrix output <85> lut truth ta b l e cnt data s0 s1 s0 s1 s0 s1 0: 3-bit lut5 in1 1: cnt/dly2 clk 0: 3-bit lut5 out 1: cnt/dly2 out 0: 3-bit lut5 in0 1: cnt/dly2 rst SLG46533_ds_114 page 75 of 184 SLG46533 figure 30. 3-bit lut6 or cnt/dly3 figure 31. 3-bit lut7 or cnt/dly4 cnt/dly3 out clk dly_in/cnt_reset 3-bit lut6 out in0 in1 8-bits nvm 1-bit nvm in2 reg <1551:1554> reg <1197> from connection matrix output <86> from connection matrix output <87> to connection matrix input <18> from connection matrix output <88> lut truth ta b l e cnt data s0 s1 s0 s1 s0 s1 0: 3-bit lut6 in1 1: cnt/dly3 clk 0: 3-bit lut6 out 1: cnt/dly3 out 0: 3-bit lut6 in0 1: cnt/dly3 rst cnt/dly4 out clk dly_in/cnt_reset 3-bit lut7 out in0 in1 8-bits nvm 1-bit nvm in2 reg <1559:1592> reg <1196> from connection matrix output <89> from connection matrix output <90> to connection matrix input <19> from connection matrix output <91> lut truth ta b l e cnt data s0 s1 s0 s1 s0 s1 0: 3-bit lut7 in1 1: cnt/dly4 clk 0: 3-bit lut7 out 1: cnt/dly4 out 0: 3-bit lut7 in0 1: cnt/dly4 rst SLG46533_ds_114 page 76 of 184 SLG46533 figure 32. 3-bit lut8 or cnt/dly5 figure 33. 3-bit lut9 or cnt/dly6 cnt/dly5 out clk dly_in/cnt_reset 3-bit lut8 out in0 in1 8-bits nvm 1-bit nvm in2 reg <1567:1560> reg <1195> from connection matrix output <92> from connection matrix output <93> to connection matrix input <20> from connection matrix output <94> lut truth ta b l e cnt data s0 s1 s0 s1 s0 s1 0: 3-bit lut8 in1 1: cnt/dly5 clk 0: 3-bit lut8 out 1: cnt/dly5 out 0: 3-bit lut8 in0 1: cnt/dly5 rst cnt/dly6 out clk dly_in/cnt_reset 3-bit lut9 out in0 in1 8-bits nvm 1-bit nvm in2 reg <1575:1568> reg <1194> from connection matrix output <95> from connection matrix output <96> to connection matrix input <21> from connection matrix output <97> lut truth ta b l e cnt data s0 s1 s0 s1 s0 s1 0: 3-bit lut9 in1 1: cnt/dly6 clk 0: 3-bit lut9 out 1: cnt/dly6 out 0: 3-bit lut9 in0 1: cnt/dly6 rst SLG46533_ds_114 page 77 of 184 SLG46533 9.5.2 3-bit lut or cnt/d lys used as 3-bit luts each macrocell, when programmed for a lut function, uses a 8-bi t register to define their output function: 3-bit lut5 is defined by reg<1543:1536> 3-bit lut6 is defined by reg<1551:1544> 3-bit lut7 is defined by reg<1559:1552> 3-bit lut8 is defined by reg<1567:1560> 3-bit lut9 is defined by reg<1575:1568> table 75. 3-bit lut5 truth table in2 in1 in0 out 0 0 0 reg <1536> lsb 0 0 1 reg <1537> 0 1 0 reg <1538> 0 1 1 reg <1539> 1 0 0 reg <1540> 1 0 1 reg <1541> 1 1 0 reg <1542> 1 1 1 reg <1543> msb table 76. 3-bit lut6 truth table in2 in1 in0 out 0 0 0 reg <1544> lsb 0 0 1 reg <1545> 0 1 0 reg <1546> 0 1 1 reg <1547> 1 0 0 reg <1548> 1 0 1 reg <1549> 1 1 0 reg <1550> 1 1 1 reg <1551> msb table 77. 3-bit lut7 truth table in2 in1 in0 out 0 0 0 reg <1552> lsb 0 0 1 reg <1553> 0 1 0 reg <1554> 0 1 1 reg <1555> 1 0 0 reg <1556> 1 0 1 reg <1557> 1 1 0 reg <1558> 1 1 1 reg <1559> msb table 78. 3-bit lut8 truth table in2 in1 in0 out 0 0 0 reg <1560> lsb 0 0 1 reg <1561> 0 1 0 reg <1562> 0 1 1 reg <1563> 1 0 0 reg <1564> 1 0 1 reg <1565> 1 1 0 reg <1566> 1 1 1 reg <1567> msb table 79. 3-bit lut9 truth table in2 in1 in0 out 0 0 0 reg <1568> lsb 0 0 1 reg <1569> 0 1 0 reg <1570> 0 1 1 reg <1571> 1 0 0 reg <1572> 1 0 1 reg <1573> 1 1 0 reg <1574> 1 1 1 reg <1575> msb SLG46533_ds_114 page 78 of 184 SLG46533 9.5.3 3-bit lut or 8-bit count er / delay macrocells used as 8 -bit counter / delay register settings table 80. cnt/dly2 register settings signal function register bit address register d efinition lut3_5 or counter2 select reg<1198> 0: lut3_5 1: counter2 delay2 mode select or asynchronous counter reset reg<1273:1272> 00: on both falli ng and rising edges (for delay & counter reset) 01: on falling edge only (fo r delay & counter reset) 10: on rising edge only (fo r delay & counter reset) 11: no delay on either falling or rising edges / counter high l evel reset counter/delay2 clock source select reg<1276:1274> 000: internal osc clock 001: osc/4 010: osc/12 011: osc/24 100: osc/64 101: 25mhz osc clock 110: external clock 111: counter1 overflow counter/delay2 output selection for counter mode reg<1277> 0: default output 1: edge dete ctor output counter/delay2 mode selection reg<1279:1278> 00: delay mode 01: one shot 10: freq. detect 11: counter mode counter/delay2 control data reg<1543:1536> 1 C 255 table 81. cnt/dly3 register settings signal function register bit address register d efinition lut3_6 or counter3 select reg<1197> 0: lut3_6 1: counter3 delay3 mode select or asynchronous counter reset reg<1281:1280> 00: on both falli ng and rising edges (for delay & counter reset) 01: on falling edge only (fo r delay & counter reset) 10: on rising edge only (fo r delay & counter reset) 11: no delay on either falling or rising edges / counter high l evel reset counter/delay3 clock source select reg<1284:1282> 000: internal osc clock 001: osc/4 010: osc/12 011: osc/24 100: osc/64 101: 25 mhz osc clock 110: external clock 111: counter2 overflow counter/delay3 output selection for counter mode reg<1285> 0: default output 1: edge dete ctor output counter/delay2 mode selection reg<1287:1286> 00: delay mode 01: one shot 10: freq. detect 11: counter mode counter/delay3 control data reg<1551:1544> 1 C 255 SLG46533_ds_114 page 79 of 184 SLG46533 table 82. cnt/dly4 register settings signal function register bit address register definition lut3_7 or counter4 select reg<1196> 0: lut3_7 1: counter4 delay4 mode select or asynchronous counter reset reg<1289:1288> 00: on both falling and risi ng edges (for delay & counter reset) 01: on falling edge only (for delay & counter reset) 10: on rising edge only ( for delay & counter reset) 11: no delay on either falling or rising edges / counter high l evel reset counter/delay4 clock source select reg<1292:1290> 000: internal osc clock 001: osc/4 010: osc/12 011: osc/24 100: osc/64 101: 25mhz osc clock 110: external clock 111: counter3 overflow counter/delay4 output selection for counter mode reg<1293> 0: default output 1: edge dete ctor output counter/delay4 mode selection reg<1295:1294> 00: delay mode 01: one shot 10: freq. detect 11: counter mode counter/delay4 control data reg<1559:1552> 1 C 255 table 83. cnt/dly5 register settings signal function register bit address register definition lut3_8 or counter5 select reg<1195> 0: lut3_8 1: counter5 delay5 mode select or asynchronous counter reset reg<1297:1296> 00: on both falling and rising edges (for delay & counter reset) 01: on falling edge only (for delay & counter reset) 10: on rising edge only (fo r delay & counter reset) 11: no delay on either falling or r ising edges / counter high l evel reset counter/delay5 clock source select reg<1300:1298> 000: internal osc clock 001: osc/4 010: osc/12 011: osc/24 100: osc/64 101: 25 mhz osc clock 110: external clock 111: counter4 overflow counter/delay5 output selection for counter mode reg<1301> 0: default output 1: edge detector output counter/delay5 mode selection reg<1303:1302> 00: delay mode 01: one shot 10: freq. detect 11: counter mode counter/delay5 control data reg<1567:1560> 1 C 255 SLG46533_ds_114 page 80 of 184 SLG46533 table 84. cnt/dly6 register settings signal function register bit address register definition lut3_9 or counter5 select reg<1194> 0: lut3_9 1: counter6 delay6 mode select or asynchronous counter reset reg<1305:1304> 00: on both falling and rising edges (for delay & counter reset) 01: on falling edge only (for delay & counter reset) 10: on rising edge only (fo r delay & counter reset) 11: no delay on either falling or r ising edges / counter high l evel reset counter/delay6 clock source select reg<1308:1306> 000: internal osc clock 001: osc/4 010: osc/12 011: osc/24 100: osc/64 101: 25 mhz osc clock 110: external clock 111: counter5 overflow counter/delay6 output selection for counter mode reg<1309> 0: default output 1: edge detector output counter/delay6 mode selection reg<1311:1310> 00: delay mode 01: one shot 10: freq. detect 11: counter mode counter/delay6 control data reg<1575:1568> 1 C 255 SLG46533_ds_114 page 81 of 184 SLG46533 9.6 4-bit lut or 16-bit counter / delay macrocells there are two macrocells that can serve as either 4-bit luts or as 16-bit counter / delays. when used to implement lut functio n, the 4-bit lut takes in four input signals from the connection m atrix and produces a single output, which goes back into the connection matrix. when used to implement 16-bit counter / dela y function, four input signals fr om the connection matrix go to the external clock (ext_clk), reset (dly_in/cnt_reset), keep an d up for the counter/delay, wit h the output going back to the connection matrix. these two macrocells have an optional finite state machine (fsm ) function. there are two ma trix inputs for up and keep to support fsm functionality. any counter within green pak is coun ting down by default. in fsm mode (cnt/dly0 and cnt/dly1) it is possible to reverse counting by applying high level to up input. also, there is a possibility to pause counting by apply ing high level to keep input, after the level goes low, the counter will proceed counting. these macrocells can also opera te in a one-shot mode, which wil l generate an output puls e of user-defined width. these macrocells can also opera te in a frequency detection. delay time and output period c an be calculated us ing the follow ing formulas: ? delay time: [(counter data + 2) / clk in put frequency C offset *]; ? output period: [(count er data + 1) / clk i nput frequency C off set*]; one shot pulse width can be calculated us ing formula: ? pulse width = [(counter data + 2) / clk input frequency C offs et*]; *offset is the asynchronous time offset between the input signa l and the first clock pulse. for timing diagrams refer to section 9.7 cnt/dly/fsm timing diagrams both of these macrocells can hav e their active count value read via i 2 c. see section 18.5.1.2 reading counter data via i2c for further details SLG46533_ds_114 page 82 of 184 SLG46533 9.6.1 4-bit lut or 16-bi t cnt/dly block diagram figure 34. 4-bit lut0 or cnt/dly0 cnt/dly0 out clk dly_in/cnt_reset 4-bit lut0 out in0 in1 16-bits nvm 1-bit nvm in2 in3 reg <1591:1576> reg <1193> from connection matrix output <101> from connection matrix output <104> from connection matrix output <102> to connection matrix input <22> fsm up keep from connection matrix output <103> lut truth table cnt data 0: 4-bit lut0 in1 1: cnt/dly0 clk 0: 4-bit lut0 out 1: cnt/dly0 out 0: 4-bit lut0 in0 1: cnt/dly0 rst 0: 4-bit lut0 in2 1: fsm up 0: 4-bit lut0 in3 1: fsm keep s0 s1 s0 s1 s0 s1 s0 s1 s0 s1 SLG46533_ds_114 page 83 of 184 SLG46533 figure 35. 4-bit lut1 or cnt/dly1 cnt/dly1 out clk dly_in/cnt_reset 4-bit lut1 out in0 in1 16-bits nvm 1-bit nvm in2 in3 reg <1607:1592> reg <1192> from connection matrix output <105> from connection matrix output <108> from connection matrix output <106> to connection matrix input <23> fsm up keep from connection matrix output <107> lut truth table cnt data 0: 4-bit lut1 in1 1: cnt/dly1 clk 0: 4-bit lut1 out 1: cnt/dly1 out 0: 4-bit lut1 in0 1: cnt/dly1 rst 0: 4-bit lut1 in2 1: fsm up 0: 4-bit lut1 in3 1: fsm keep s0 s1 s0 s1 s0 s1 s0 s1 s0 s1 SLG46533_ds_114 page 84 of 184 SLG46533 9.6.2 4-bit lut or 16-bit coun ter / delay macrocells used as 4-bit luts each macrocell, when programmed for a lut function, uses a 16-b it register to define their output function: 4-bit lut0 is defined by reg<1591:1576> 4-bit lut1 is defined by reg<1607:1592> table 87. 4-bit lut stand ard digital functions function msb lsb and-4 1000000000000000 nand-40111111111111111 or-4 1111111111111110 nor-4 0000000000000001 xor-4 0110100110010110 xnor-41001011001101001 table 85. 4-bit lut0 truth table. in3 in2 in1 in0 out 0 0 0 0 reg <1576> lsb 0 0 0 1 reg <1577> 0 0 1 0 reg <1578> 0 0 1 1 reg <1579> 0 1 0 0 reg <1580> 0 1 0 1 reg <1581> 0 1 1 0 reg <1582> 0 1 1 1 reg <1583> 1 0 0 0 reg <1584> 1 0 0 1 reg <1585> 1 0 1 0 reg <1586> 1 0 1 1 reg <1587> 1 1 0 0 reg <1588> 1 1 0 1 reg <1589> 1 1 1 0 reg <1590> 1 1 1 1 reg <1591> msb table 86. 4-bit lut1 truth table. in3 in2 in1 in0 out 0 0 0 0 reg <1592> lsb 0 0 0 1 reg <1593> 0 0 1 0 reg <1594> 0 0 1 1 reg <1595> 0 1 0 0 reg <1596> 0 1 0 1 reg <1597> 0 1 1 0 reg <1598> 0 1 1 1 reg <1599> 1 0 0 0 reg <1600> 1 0 0 1 reg <1601> 1 0 1 0 reg <1602> 1 0 1 1 reg <1603> 1 1 0 0 reg <1604> 1 1 0 1 reg <1605> 1 1 1 0 reg <1606> 1 1 1 1 reg <1607> msb SLG46533_ds_114 page 85 of 184 SLG46533 9.6.3 4-bit lut or 16-bit coun ter / delay macrocells used as 16-bit counter / delay register settings table 88. cnt/dly0 register settings signal function register bit address register d efinition lut4_0 or counter0 select reg<1193> 0: lut4_0 1: counter0 delay0 mode select or asynchronous counter reset reg<1313:1312> 00: on both falli ng and rising edges (for delay & counter reset) 01: on falling edge only (fo r delay & counter reset) 10: on rising edge only (fo r delay & counter reset) 11: no delay on either falling or rising edges / counter high l evel reset counter/delay0 clock source select reg<1316:1314> 000: internal osc clock 001: osc/4 010: osc/12 011: osc/24 100: osc/64 101: 25 mhz osc clock 110: external clock 111: counter6 overflow c n t 0 / f s m 0 ' s q a r e set to data or reset to 0s selection reg<1317> 0: reset to 0s 1: set to control data counter/delay0 mode selection reg<1319:1318> 00: delay mode 01: one shot 10: freq. detect 11: counter mode counter/delay0 control data reg<1591:1576> 1 - 16535 table 89. cnt/dly1 register settings signal function register bit address register definition lut4_1 or counter1 select reg<1192> 0: lut4_1 1: counter1 delay1 mode select or asynchronous counter reset reg<1321:1320> 00: on both falling and risin g edges (for delay & counter reset) 01: on falling edge only (for delay & counter reset) 10: on rising edge only (for delay & counter reset) 11: no delay on either falling or rising edges / counter high l evel reset counter/delay1 clock source select reg<1324:1322> 000: internal osc clock 001: osc/4 010: osc/12 011: osc/24 100: osc/64 101: 25 mhz osc clock 110: external clock 111: counter0 overflow c n t 0 / f s m 0 ' s q a r e set to data or reset to 0s selection reg<1325> 0: reset to 0s 1: set to control data counter/delay1 mode selection reg<1327:1326> 00: delay mode 01: one shot 10: freq. detect 11: counter mode counter/delay1 control data reg<1607:1592> 1 - 16535 SLG46533_ds_114 page 86 of 184 SLG46533 9.7 cnt/dly/fsm timing diagrams 9.7.1 delay mode (edge select: both, counter data: 3) cnt/dly 2...cnt/dly6 9.7.2 count mode (co unt data: 3), counter reset (rising edge detect) cnt/dly2...cnt/dly6 figure 36. delay mode timing diagram figure 37. counter mode timing diagram delay in rc osc: force power on (always running) delay output asynchronous delay variable asynchronous delay variable delay = period x (counter data + 1) + variable variable is from 0 to 1 clock period delay = period x (counter data + 1) + variable variable is from 0 to 1 clock period delay in rc osc: auto power on (powers up from delay in) delay output offset offset delay = offset + period x (counter data + 1) see offset in table 3 delay = offset + period x (counter data + 1) see offset in table 3 reset_in clk counter out count start in 0 clk after reset 4 clk period pulse SLG46533_ds_114 page 87 of 184 SLG46533 9.7.3 one-shot mode cnt/dly0...cnt/dly6 this macrocell will generate a pulse whenever a selected edge i s detected on its input. register bits set the edge selection. the pulse width determines by counter data and clock selection prop erties. the output pulse polarity (non-inverted or inverted) is selected by register bit. see table 90. any incoming edges will be ignored during the pulse width gener ation. the following diagram shows one-shot functi on for non-inverted output. figure 38. one-shot function timing diagram one-shot/freq. det/delay in one-shot function rising edge detection one-shot function falling edge detection one-shot function both edge detection t t t t delay time delay time delay time delay time delay time delay time SLG46533_ds_114 page 88 of 184 SLG46533 this macrocell generates a high level pulse with a set width (d efined by counter data) when dete cting the respective edge. it does not restart while pulse is high. 9.7.4 frequency detection mode cnt/dly0...cnt/dly6 rising edge: the output goes high if the time between two succe ssive edges is less than the delay. the output goes low if the second rising edge has not come a fter the last rising edge in s pecified time. falling edge: the output goes high if the time between two fall ing edges is less than the set time. the output goes low if the second falling edge has not come after the last falling edge in specified time. both edge: the output goes high if the time betwe en the rising and falling edges is less than the set time, which is equivalen t to the length of the pulse. the output goes low if after the last rising/falling edge and specified time, the second edge has not come. table 90. dly/cntx one-shot / freq. detect output polarity address signal function register bit definition i 2 c interface byte register bit read write a6 reg<1329> select the polarity of dly/cnt6's one shot / freq. detect output 0: default output 1: inverted output valid valid reg<1330> select the polarity of dly/cnt5's one shot / freq. detect output 0: default output 1: inverted output valid valid reg<1331> select the polarity of dly/cnt4's one shot / freq. detect output 0: default output 1: inverted output valid valid reg<1332> select the polarity of dly/cnt3's one shot / freq. detect output 0: default output 1: inverted output valid valid reg<1333> select the polarity of dly/cnt2's one shot / freq. detect output 0: default output 1: inverted output valid valid reg<1334> select the polarity of dly/cnt1's one shot / freq. detect output 0: default output 1: inverted output valid valid reg<1335> select the polarity of dly/cnt0's one shot / freq. detect output 0: default output 1: inverted output valid valid SLG46533_ds_114 page 89 of 184 SLG46533 figure 39. frequency detection mode timing diagram one-shot/freq. det/delay in frequency detector function rising edge detection frequency detector function falling edge detection frequency detector function both edge detection t t t t delay time delay time delay time delay time delay time delay time SLG46533_ds_114 page 90 of 184 SLG46533 9.7.5 edge detection mode cnt/dly2...cnt/dly6 the macrocell generates high level short pulse when detecting t he respective edge. see table 4. expected delays and pulse widths (typical) . figure 40. edge detection mode timing diagram one-shot/freq. det/delay in edge detector function rising edge detection edge detector function falling edge detection edge detector function both edge detection t t t t delay time delay time delay time delay time delay time SLG46533_ds_114 page 91 of 184 SLG46533 9.7.6 delay mode cnt/dly0...cnt/dly6 the macrocell shifts the respective edge to a set time and rest arts by appropriate edge. it works as a filter if the input sig nal is shorter than the delay time. figure 41. delay mode timing diagram one-shot/freq. det/delay in delay function rising edge detection delay function falling edge detection delay function both edge detection t t t t delay time delay time delay time delay time delay time delay time SLG46533_ds_114 page 92 of 184 SLG46533 9.7.7 cnt/fsm mode c nt/dly0, cnt/dly1 figure 42. cnt/fsm timing diagra m (reset rising edge mode, oscil lator is forced on, up=0) for counter data = 3 figure 43. cnt/fsm timing diagram (set rising edge mode, oscilla tor is forced on, up=0) for counter data = 3 reset in clk 313210 q count end 321 0 0 keep 2 32 10 note: q = current counter value set in clk 312103 q count end 210 3 3 keep 2 21 03 note: q = current counter value SLG46533_ds_114 page 93 of 184 SLG46533 figure 44. cnt/fsm timing diagra m (reset rising edge mode, osci llator is forced on, up=1 ) for counter data = 3 figure 45. cnt/fsm timing diagra m (set rising edge mode, oscill ator is forced on, up=1) for counter data = 3 reseti n clk 3 5 1234 q count end 567 8 0 keep 4 9 16381 16382 3 45 note: q = current counter value 16383 set in clk 3 5 4567 q count end 8910 11 3 keep 4 12 16381 16382 16383 3 45 note: q = current counter value SLG46533_ds_114 page 94 of 184 SLG46533 9.7.8 difference in counter val ue for counter, delay, one-sho t and frequency detect modes there is a difference in counter value for counter and delay/on e-shot/frequency detect modes. the counter value is shifted for two rising edges of the clock signal in delay/one-shot/frequenc y detect modes compared to counter mode. see figure 46. 9.8 2-bit lut or progr ammable pattern generator the SLG46533 has one combination function macrocell that can se rve as a logic or timing function. this macrocell can serve as a look up table (lut), or progra mmable pattern generator (pgen) . when used to implement lut functions, the 2-bit lut takes in tw o input signals from the connection matrix and produce a single output, which goes back into the connection matrix. when used a s a lut to implement combinatorial logic functions, the outputs of the luts can be configured to any user defined function, inc luding the following standard digital logic devices (and, nand, or, nor, xor, xnor). the user can also define the combinatorial relationship between inputs and outputs to be any selectable function. when operating as a programmable pattern generator, the output of the macrocell with clock out a sequence of two to sixteen bits that are user selectable in their bit values, and user sel ectable in the number of bits (u p to sixteen) that are output b efore the pattern repeats. see figure figure 48. figure 46. counter value, counter data = 3 one-shot/freq.set/delay in clk cnt out delay data one-shot out one-shot data dly out cnt data 0 3 2 1 0 3 2 3 3 3 2 1 3 3 3 3 3 2 1 3 3 SLG46533_ds_114 page 95 of 184 SLG46533 figure 47. 2-bit lut2 or pgen figure 48. pgen timing diagram pgen out clk nrst 2-bit lut3 out to connection matrix input <11> from connection matrix output <66> reg <1211:1208> reg <1188> from connection matrix output <67> in0 in1 reg <1623:1608> lut truth table pattern data pgen size 0: 2-bit lut3 out 1: pgen out s0 s1 vdd out d15 clk d0 nrst 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 d14 d0 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d15 t t t t SLG46533_ds_114 page 96 of 184 SLG46533 9.9 wake and sleep controller (ws) the SLG46533 has a wake and sleep function for all acmps. the m acrocell cnt/dly0 can be reconfigured for this purpose reg<1319:1318>=11 and reg<1495>=1. the ws serves for power savi ng, it allows to switch on and off selected acmps on selected bit of 16-bit counter. to use any acmp under ws controller the following settings must be done: ? acmp power up input f rom matrix = 1 (for each acmp separately) ; ? cnt/dly0 must be set to wake an d sleep controller function (fo r all acmps); ? register ws => enable (for each acmp separately); ? cnt/dly0 set/reset inpu t = 0 (for all acmps); ? in case of using osc1 (25 mhz), osc0 must be set to force powe r on. as the osc any oscillator with any pre divider can be used. the user can select a period of time while the acmps are sleeping in a range of 1 - 65535 clock cycles. before they are sent to s leep their outputs are latched so the acmps remain their state (high or low) while sleeping. ws controller has the following settings: ? wake and sleep output state (high/low) figure 49. ws controller osc ck_osc ws_pd 000:/1 001:/4 010:/12 011:/24 100:/64 cnt_end ws out ws_pd power control from connection matrix output<58> analog control block reg<1316:1314> ws_pd to w&s out state selection block ws clock freq. selection reg<1591:1576> ws ratio control data reg<1494> ws out state for osc off acmps_pdb ws out bg/regulator pdb ws time selection reg<1489> acmp0..3 out to connection matrix input <60:57> from connection matrix output <54:51> reg<1493:1490> acmp ws enable ws out latchs note: ws_pd is high at ws osc (25 khz/2mhz osc) power down ws controller cnt0 out to connection matrix input <22> ck cnt 4 4 4 acmps_pdb + - ws SLG46533_ds_114 page 97 of 184 SLG46533 if osc is powered off (power down option is selected; power dow n input = 1) and wake and sleep output state = high, the acmp is continuously on if osc is powered off (power dow n option is selected; power dow n input = 1) and wake and sleep output state = low, the acmp is continuously off both cases ws func tion is turned off ? counter data (range: 1 - 65535) user can select wake and sleep ra tio of the acmp; counter data = sleep time, one clock = wake time ? q mode - defines the state of ws counter data when set/reset s ignal appears reset - when active signal appears, the ws counter will reset t o zero and high level signal on its output will turn the acmps on. when reset signal goes out, t he ws counter will go low and turn the acmps off until the c ounter counts up to the end set - when active signal appear s, the ws count er will stop and low level signal on it s output will turn the acmps off. when set signal goes out, the ws counter will go on counting and hig h level signal will turn the acmps on while counter is counting up to the end ? edge select defines the edge for q mode high level set/reset - switches mode set/reset when level is hi gh note: q mode operates only in ca se of "high le vel set/reset" ? wake time selection - time re quired for wake signal to turn th e acmps on normal wake time - when ws signal is high, it takes a bg time ( 100/550 s) to turn the acmps on they will stay on until ws signal is low again. wake time is one clock period. it shoul d be longer than bg turn on time and minimal required comparing time of the acmp short wake time - when ws signal is high, it takes a bg time (1 00/550 s) to turn the acmps on. they will stay on for 1 s and turn off regardless of ws si gnal. the ws signal width does not matter. ? keep - pauses counting while keep = 1 ? up - reverses counting if up = 1, cnt is counting up fr om user selected value to 65535 if up = 0, cnt is c ounting down from user selected value to 0 SLG46533_ds_114 page 98 of 184 SLG46533 9.9.1 ws register settings table 91. ws register settings signal function register bit address register definition counter/delay0 clock source select reg<1316:1314> 000: internal osc clock 001: osc/4 010: osc/12 011: osc/24 100: osc/64 101: 25mhz osc clock 110: external clock 111: counter6 overflow ws time selection reg<1489> 0: short wake time 1: normal wake time acmp0 wake & sleep function enable reg<1490> 0: disable 1: enable acmp1 wake & sleep function enable reg<1491> 0: disable 1: enable acmp2 wake & sleep function enable reg<1492> 0: disable 1: enable acmp3 wake & sleep function enable reg<1493> 0: disable 1: enable wake sleep output state when ws oscillator is power down if dly/cnt0 mode selection is "11" reg<1494> 0: low 1: high wake sleep ratio control mode selection if dly/cnt0 mode selection is "11" reg<1495> 0: default mode 1: wake sleep ratio control mode dly/cnt0 (16bits, <15:0> = <1591:1576>) control data reg<1591:1576> 1 - 65535 SLG46533_ds_114 page 99 of 184 SLG46533 10.0 analog comparators (acmp) there are four analog comparator (acmp) macrocells in the slg46 533. in order for the acmp ce lls to be used in a greenpak design, the power up signals (acmpx_pdb) need to be active. by connecting to signals coming fr om the connection matrix, it is possible to have each acmp be always on, always off, or power c ycled based on a digital signal coming from the connection matrix. when acmp is powered down, output is low. pwr up = 1 => acmp is powered up. pwr up = 0 => acmp is powered down. during acmp power up, its output will remain low, and then beco mes valid 1.03 ms (max) after acmp power up signal goes high, see figure 51 . if vdd is greater or equal to 2.7 v, it is possible to decrea se turn-on time by setting the bg delay to 100 s, see figure 52 . the acmp cells have an input "low bandwith" signal selection, which can be used to save power and reduce noise impact when lower bandwidth signals are being compared. to ensu re proper chip startup operation, it is recommended to enable the acmps with the por sig nal, and not the vdd signal. note: regulator and charge pump set to automatic on/off . figure 50. maximum power on delay vs. vdd, bg = auto-delay. 120 140 160 180 200 220 240 1.71 1.8 2.5 2.7 3 3.3 3.6 4.2 4.5 5 5.5 power on delay (s) vdd (v) -40?c +25?c +85?c SLG46533_ds_114 page 100 of 184 SLG46533 . each of the acmp cells has a positive input signal that can be provided by a variety of external sources. there is also a sele ctable gain stage (1x, 0.5x, 0.33x, 0.2 5x) before connec tion to the an alog comparator. the gain divider is unbuffered and consists of 250 k (typ.) resistors, see table 92 . for gain divider accuracy refer to table 93 . in- voltage range: 0 - 1.2 v. can use vref selection vdd/4 and vdd/3 to maintain this input range. input bias current < 1 na (typ). each cell also has a hysteresis selection, to offer hysteresis of 0 mv, 25 mv, 50 mv or 200 mv. the 50 mv and 200 mv hysteresi s options can be used with internal voltage reference only, while 25 mv hysteresis option can be used with both internal and ext ernal voltage reference. the 50 mv and 200 mv hysteresis options are one way hysteresis. it means t hat the actual thresholds will be vref (high threshold) and vref - hysteresis (low threshold). th e acmp output will retain its previous value, if the input volt age is within threshold window (between vref and vref - hysteresis). p lease note: for the 25 mv hysteresis option threshold levels wi ll be vref + hysteresis/2 (high th reshold) and vref C hysteresis/2 (low threshold). note: any acmp powered on enables the bandgap internal circuit as well. an analog voltage will appear on vref even when the force bandgap option is set as disabled. table 92. gain divider input resistance gain 1x 0.5x 0.33x 0.25x input resistance 100 m 1 m 0.75 m 1 m table 93. gain di vider accuracy gain x0.5 x0.33 x0.25 accuracy 0.51% 0.34% 0.25% figure 51. maximum power on delay vs. vdd, bg = 550 s. 600 650 700 750 800 850 900 950 1000 1050 1100 1.71 1.8 2.5 2.7 3 3.3 3.6 4.2 4.5 5 5.5 power on delay (s) vdd (v) -40?c +25?c +85?c figure 52. maximum powe r on delay vs. vdd, bg = 100 s. 120 130 140 150 160 170 180 190 200 210 220 1.71 1.8 2.5 2.7 3 3.3 3.6 4.2 4.5 5 5.5 power on delay (s) vdd (v) -40?c +25?c +85?c SLG46533_ds_114 page 101 of 184 SLG46533 for high input impedance when using the gain divider (x0.25, x0 .33, x0.5), it is possible to use the input buffer. however, th is will add some offset, see figure 53. it is not recommended to use acmp buffer when vdd < 2.5 v. note: when vdd < 1.8v voltage reference should not exceed 1100 mv. figure 53. typical buffer input voltage offset vs. voltage refer ence at t = (-40.... +85)c, buffer bandwidth = 1 khz, vhys = 0 mv, gain = 1. figure 54. typical input threshold variation (including vref var iation, acmp offset) vs. voltage reference at t = (-40.... +85)c, lmb mode - disable, v hys = 0 mv. -40 -30 -20 -10 0 10 20 30 40 50 250 600 850 1200 voffset (mv) voltage reference (mv) upper limit @ vdd2.7v lower limit @ vdd2.7v -25% -20% -15% -10% -5% 0% 5% 10% 15% 20% 50 150 250 350 450 550 650 750 850 950 1050 1150 input threshold variation (%) voltage reference (mv) upper limit lower limit SLG46533_ds_114 page 102 of 184 SLG46533 10.1 acmp0 block diagram table 94. built-in hysteres is tolerance at t = 25c vhys (mv) vdd=(1.7-1.8) v vdd=(1.89-5.5) v vref = (50-500) mv vref = (550-1000) mv vref = (1050-1200) mv vref = (50-500) mv vref = (550-1000) mv vref = (1050-1200) mv min max min max min max min max min max min max 25 8.6 32.2 8.6 32.3 7.0 32. 5 8.5 32.3 8.5 32.3 7.8 34.0 50 44.8 56.5 43.9 56.7 42.7 56.4 44.2 56.8 43.6 57.3 43.1 56.0 200 192.8 207.9 194.0 208.0 192.7 205.4 192.0 208.6 193.0 209.5 190.8 207.7 figure 55. acmp0 block diagram 11010 11011 11100 11101 internal vref io9: ext_vref io5: acmp0(-) 110 100 0x1 io4: acmp0(+) external vdd 1.71 v ~ 5.5 v external vdd 2.7 v ~ 5.5 v selectable gain reg <1630:1629> to acmp1, acmp2, ac- mp3s mux input vref + - from connection matrix output <51> pdb lbw selection reg <1631> hysteresis selection reg <1175:1174> l/s to connection matrix input<57> reg <1628:1624> *io4_aio_en; reg <1173>; reg <1172> *io4_aio_en: if reg <1062:1061>=11 then 1, otherwise: 0 bg_ok latch 0 1 reg <1490> io9: ext_vref/2 io5: acmp0(-)/2 11001- 00000 acmp0 wake & sleep function enable SLG46533_ds_114 page 103 of 184 SLG46533 10.2 acmp0 register settings table 95. acmp0 register settings signal function register bit address register definition acmp0 positive input source select reg<1172> 0: io4 1: vdd acmp0 analog buffer enable reg<1173> 0: disable analog buffer 1: enable analog buffer acmp0 hysteresis enable reg<1175:1174> 00: disabled (0 mv) 01: enabled (25 mv) 10: enabled (50 mv) 11: enabled (200 mv) (01: for both external & internal vref; 10 & 11: for only inter nal vref; external vref will not have 50 mv & 2 00 mv hysteresis.) acmp0 wake & sleep function enable reg<1490> 0: disable 1: enable acmp0 in voltage select reg<1628:1624> 00000: 50 mv 00001: 100 mv 00010: 150 mv 00011: 200 mv 00100: 250 mv 00101: 300 mv 00110: 350 mv 00111: 400 mv 01000: 450 mv 01001: 500 mv 01010: 550 mv 01011: 600 mv 01100: 650 mv 01101: 700 mv 01110: 750 mv 01111: 800 mv 10000: 850 mv 10001: 900 mv 10010: 950 mv 10011: 1 v 10100: 1.05 v 10101: 1.1 v 10110: 1.15 v 10111: 1.2 v 11000: vdd/3 11001: vdd/4 11010: io9: ext_vref 11011: io5: acmp0- 11100: io9: ext_vref/2 11101: io5: acmp0-/2 acmp0 positive input divider reg<1630:1629> 00: 1.00x 01: 0.50x 10: 0.33x 11: 0.25x acmp0 low bandwidth (max: 1 mhz) enable reg<1631> 0: off 1: on SLG46533_ds_114 page 104 of 184 SLG46533 10.3 acmp1 block diagram figure 56. acmp1 block diagram 11010 11011 11100 11101 internal vref io9: ext_vref io9: ext_vref 11x 10x 0x1 io8: acmp1(+) from acmp0's mux output external vdd 2.7 v ~ 5.5 v selectable gain reg <1638:1637> vref + - from connection matrix output <52> pdb lbw selection reg <1639> hysteresis selection avd = 1.8 v l/s to connection matrix input<58> reg <1636:1632> *io8_aio_en; reg <1169>; reg <1168> *io8_aio_en: if reg <1093:1092>=11 then 1, otherwise: 0 bg_ok latch 0 1 reg <1491> io9: ext_vref/2 io9: ext_vref/2 11101- 00000 100 a current source acmp1 wake & sleep function enable en reg <1183> note: when 100 a current source is enabled input voltage on io 8 should not exceed 1.8 v reg <1171:1170> SLG46533_ds_114 page 105 of 184 SLG46533 10.4 acmp1 register settings table 96. acmp1 register settings signal function register bit address register definition acmp1 100 a current source enable reg<1183> 0: disable 1: enable acmp1 positive input source select reg<1168> 0: io8 1: acmp0 in+ source acmp1 analog buffer enable (max. band width 1 mhz) reg<1169> 0: disable analog buffer 1: enable analog buffer acmp1 hysteresis enable reg<1171:1170> 00: disabled (0 mv) 01: enabled (25 mv) 10: enabled (50 mv) 11: enabled (200 mv) (01: for both external & internal vref; 10 & 11: for only inter nal vref; external vref will not have 50 mv & 2 00 mv hysteresis.) acmp1 wake & sleep function enable reg<1491> 0: disable 1: enable acmp1 in voltage select reg<1636:1632> 00000: 50 mv 00001: 100 mv 00010: 150 mv 00011: 200 mv 00100: 250 mv 00101: 300 mv 00110: 350 mv 00111: 400 mv 01000: 450 mv 01001: 500 mv 01010: 550 mv 01011: 600 mv 01100: 650 mv 01101: 700 mv 01110: 750 mv 01111: 800 mv 10000: 850 mv 10001: 900 mv 10010: 950 mv 10011: 1 v 10100: 1.05 v 10101: 1.1 v 10110: 1.15 v 10111: 1.2 v 11000: vdd/3 11001: vdd/4 11010: io9: ext_vref 11011: io9: ext_vref 11100: io9: ext_vref/2 11101: io9: ext_vref/2 acmp1 positive input divider reg<1638:1637> 00: 1.00x 01: 0.50x 10: 0.33x 11: 0.25x acmp1 low bandwidth (max: 1 mhz) enable reg<1639> 0: off 1: on SLG46533_ds_114 page 106 of 184 SLG46533 10.5 acmp2 block diagram figure 57. acmp2 block diagram internal vref io9: ext_vref io11: acmp2(-) 10 01 io10: acmp2(+) from acmp0s mux output selectable gain reg <1646:1645> vref + - from connection matrix output <53> pdb lbw selection reg <1647> hysteresis selection reg <1182:1181> l/s to connection matrix input<59> reg <1644:1640> *io10_aio_en; reg <1180> *io10_aio_en: if reg <1109:1108>=11 then 1, otherwise: 0 bg_ok latch 0 1 reg <1492> acmp2 wake & sleep function enable 11010 11011 11100 11101 io9: ext_vref/2 io11: acmp2(-)/2 11001- 00000 SLG46533_ds_114 page 107 of 184 SLG46533 10.6 acmp2 register settings table 97. acmp2 register settings signal function register bit address register definition acmp2 positive input source select reg<1180> 0: io10 1: acmp0 in+ source acmp2 hysteresis enable reg<1182:1181> 00: disabled (0 mv) 01: enabled (25 mv) 10: enabled (50 mv) 11: enabled (200 mv) (01: for both external & internal vref; 10 & 11: for only inter nal vref; external vref will not have 50 mv & 2 00 mv hysteresis.) acmp2 wake & sleep function enable reg<1492> 0: disable 1: enable acmp2 in voltage select reg<1644:1640> 00000: 50 mv 00001: 100 mv 00010: 150 mv 00011: 200 mv 00100: 250 mv 00101: 300 mv 00110: 350 mv 00111: 400 mv 01000: 450 mv 01001: 500 mv 01010: 550 mv 01011: 600 mv 01100: 650 mv 01101: 700 mv 01110: 750 mv 01111: 800 mv 10000: 850 mv 10001: 900 mv 10010: 950 mv 10011: 1 v 10100: 1.05 v 10101: 1.1 v 10110: 1.15 v 10111: 1.2 v 11000: vdd/3 11001: vdd/4 11010: io9: ext_vref 11011: io11: acmp2- 11100: io9: ext_vref /2 11101: io11: acmp2-/2 acmp2 positive input divider reg<1646:1645> 00: 1.00x 01: 0.50x 10: 0.33x 11: 0.25x acmp2 low bandwidth (max: 1 mhz) enable reg<1647> 0: off 1: on SLG46533_ds_114 page 108 of 184 SLG46533 10.7 acmp3 block diagram figure 58. acmp3 block diagram internal vref io9: ext_vref io11: acmp3(-) 100 010 001 io12: acmp3(+) io10: acmp2(+) selectable gain reg <1654:1653> vref + - from connection matrix output <54> pdb lbw selection reg <1655> hysteresis selection reg <1179:1178> l/s reg <1652:1648> *io12_aio_en; reg<1177>; reg<1176> *io12_aio_en: if reg <1126:1125>=11 then 1, otherwise: 0 from acmp0s mux output to connection matrix input<60> bg_ok latch 0 1 reg <1493> acmp3 wake & sleep function enable 11011 11010 11100 11101 io9: ext_vref/2 io11: acmp3(-)/2 11001- 00000 SLG46533_ds_114 page 109 of 184 SLG46533 10.8 acmp3 register settings table 98. acmp3 register settings signal function register bit address register definition acmp3 positive input source select reg<1177:1176> 0: io12 01: acmp2 in+ source 10: acmp0 in+ source 00: reserved acmp3 hysteresis enable reg<1179:1178> 00: disabled (0 mv) 01: enabled (25 mv) 10: enabled (50 mv) 11: enabled (200 mv) (01: for both external & internal vref; 10 & 11: for only inter nal vref; external vref will not have 50 mv & 2 00 mv hysteresis.) acmp3 wake & sleep function enable reg<1493> 0: disable 1: enable acmp3 in voltage select reg<1652:1648> 00000: 50 mv 00001: 100 mv 00010: 150 mv 00011: 200 mv 00100: 250 mv 00101: 300 mv 00110: 350 mv 00111: 400 mv 01000: 450 mv 01001: 500 mv 01010: 550 mv 01011: 600 mv 01100: 650 mv 01101: 700 mv 01110: 750 mv 01111: 800 mv 10000: 850 mv 10001: 900 mv 10010: 950 mv 10011: 1 v 10100: 1.05 v 10101: 1.1 v 10110: 1.15 v 10111: 1.2 v 11000: vdd/3 11001: vdd/4 11010: io9: ext_vref 11011: io11: acmp3- 11100: io9: ext_vref/2 11101: io11: acmp3-/2 acmp3 positive input divider reg<1654:1653> 00: 1.00x 01: 0.50x 10: 0.33x 11: 0.25x acmp3 low bandwidth (max: 1 mhz) enable reg<1655> 0: off 1: on SLG46533_ds_114 page 110 of 184 SLG46533 11.0 pipe delay (pd) the SLG46533 has a pipe delay logic cell that is shared with th e lut3_10 in one of the combination function macrocells. the user can select one of these func tions to use in a design, but not both. please see section 9.4 3-bit lut or pipe delay macrocell for the description of this combination function macrocell. SLG46533_ds_114 page 111 of 184 SLG46533 12.0 programmable delay / edge detector the SLG46533 has a programmable time delay logic cell available that can generate a delay that is selectable from one of four timings configured in the greenpak designer. the programmable t ime delay cell can generate one of four different delay pattern s: rising edge detection, falling edge detection, both edge detect ion and both edge delay. see the timing diagrams below for furt her information. note : the input signal must be longer than the delay, otherwise it will be filtered out. 12.1 programmable delay timing diagram - edge detector output please refer to table 4. expected delays and pulse widths (typical) figure 59. programmable delay figure 60. edge detector output programmable delay out in reg <1267:1266> from connection matrix output <57> to connection matrix input <61> reg <1265:1264> edge mode selection delay value selection time1 edge detector output in rising edge detector falling edge detector both edge detector both edge delay time1 time1 is a fixed value time2 delay value is selected via register time2 time2 width width SLG46533_ds_114 page 112 of 184 SLG46533 12.2 programmable dela y register settings table 99. programmable de lay register settings signal function register bit address register definition select the edge mode of programmable delay & edge detector reg<1265:1264> 00: rising edge detector 01: falling edge detector 10: both edge detector 11: both edge delay delay value select for programmable delay & edge detector (vdd = 3.3v, typical condition) reg<1267:1266> 00: 135 ns 01: 270 ns 10: 405 ns 11: 540 ns SLG46533_ds_114 page 113 of 184 SLG46533 13.0 additional logic functions the SLG46533 has two additional logic functions that are connec ted directly to the connection m atrix inputs and outputs. there are two deglitch filters, each with edge detector functions. 13.1 deglitch filter / edge detector 13.2 deglitch filter register settings figure 61. deglitch filter / edge detector table 100. programmable delay register settings signal function register bit address register definition filter_1/edge detector_1 edge select reg<1457:1456> 00: rising edge detector 01: fall edge detector 10: both edge detector 11: both edge delay filter_1/edge detector_1 output polarity select reg<1458> 0: filter_1 output 1: filter_1 out put inverted filter_1 or edge detector_1 select (typ. 30 ns @vdd=3.3v) reg<1459> 0: filter_1 1: edge detector_1 filter_0/edge detector_0 edge select reg<1461:1460> 00: rising edge detector 01: fall edge detector 10: both edge detector 11: both edge delay from connection matrix output <55> to connection matrix input <30> from connection matrix output <56> to connection matrix input <31> filter_0 filter_1 reg <1462> reg <1458> c c r r reg <1463> reg <1459> edge detect edge detect edge select reg <1457:1456> edge select reg <1461:1460> SLG46533_ds_114 page 114 of 184 SLG46533 filter_0/edge detector_0 output polarity select reg<1462> 0: filter_0 output 1: filter_0 out put inverted filter_0 or edge detector_0 select (typ. 47 ns @vdd=3.3v) reg<1463> 0: filter_0 1: edge detector_0 table 100. programmable delay register settings signal function register bit address register definition SLG46533_ds_114 page 115 of 184 SLG46533 14.0 voltage reference (vref) 14.1 voltage reference overview the SLG46533 has a voltage reference macrocell to provide refer ences to the four analog comparators. this macrocell can supply a user selectio n of fixed voltage references, /3 and /4 reference off of the v dd power supply to the dev ice, and externally supplied voltage references from ios 5, 9, and 11. the macrocel l also has the option to output reference voltages on ios 15 an d 16. see table below for the available selections for each analo g comparator. also see figure 62 below, which shows the reference output structure. 14.2 vref selection table table 101. vref selection table. sel<4:0> acmp0_vref acmp1_vref acmp2_vref acmp3_vref 11101 vref_ext_acmp0/2 vref_ext_acm p1/2 vref_ext_acmp2/2 vref_ext_a cmp2/2 11100 vref_ext_acmp1/2 vref_ext_acm p1/2 vref_ext_acmp1/2 vref_ext_a cmp1/2 11011 vref_ext_acmp0 vref_ext_acmp 1 vref_ext_acmp2 vref_ext_acmp2 11010 vref_ext_acmp1 vref_ext_acmp 1 vref_ext_acmp1 vref_ext_acmp1 11001 vdd / 4 vdd / 4 vdd / 4 vdd / 4 11000 vdd / 3 vdd / 3 vdd / 3 vdd / 3 10111 1.20 1.20 1.20 1.20 101101.151.151.151.15 10101 1.10 1.10 1.10 1.10 10100 1.05 1.05 1.05 1.05 100111.001.001.001.00 10010 0.95 0.95 0.95 0.95 10001 0.90 0.90 0.90 0.90 10000 0.85 0.85 0.85 0.85 01111 0.80 0.80 0.80 0.80 011100.750.750.750.75 01101 0.70 0.70 0.70 0.70 01100 0.65 0.65 0.65 0.65 010110.600.600.600.60 01010 0.55 0.55 0.55 0.55 01001 0.50 0.50 0.50 0.50 01000 0.45 0.45 0.45 0.45 00111 0.40 0.40 0.40 0.40 001100.350.350.350.35 00101 0.30 0.30 0.30 0.30 00100 0.25 0.25 0.25 0.25 000110.200.200.200.20 00010 0.15 0.15 0.15 0.15 00001 0.10 0.10 0.10 0.10 00000 0.05 0.05 0.05 0.05 vdd practical vref range note 2.0 v - 5.5 v 50 mv ~ 1.2 v 1.7 v - 2.0 v 50 mv ~ 1.0 v do not operate above 1.0 v SLG46533_ds_114 page 116 of 184 SLG46533 14.3 vref block diagram figure 62. voltage refe rence block diagram cmp0_vref cmp1_vref cmp2_vref cmp3_vref reg <1628:1624> reg <1636:1632> reg <1644:1640> reg <1652:1648> vdd / 3 vdd / 4 ext_vref_acmp2 (io11) ext_vref_acmp1 (io9) ext_vref_acmp0 (io5) reg <1476> 000 001 100 101 110 000 001 100 101 110 reg <1474> vdd / 2 vdd / 3 vdd / 4 reg <1486:1484> reg <1482:1480> vref out_0 (io16) io16_aio_en reg<1157:1156>=11 vref out_1 (io15) io15_aio_en reg<1149:1148>=11 SLG46533_ds_114 page 117 of 184 SLG46533 14.4 vref load regulation note 1: it is not recommended to use vr ef connected to external pin without buffer. note 2: vref buffer performance is not guaranteed at vdd < 2.7 v. figure 63. typical load regulatio n, vref = 600 mv, t = (-40...+8 5) c, buffer - enable figure 64. typical load regulatio n, vref = 1000 mv, t = (-40...+ 85) c, buffer - enable 350 400 450 500 550 600 650 0 50 100 150 200 250 300 350 400 450 500 v ref i ( u a) vdd=5.5v vdd=3.3v vdd=2.7v 700 750 800 850 900 950 1000 1050 0 50 100 150 200 250 300 350 400 450 500 v ref i ( u a) vdd=5.5v vdd=3.3v vdd=2.7v SLG46533_ds_114 page 118 of 184 SLG46533 figure 65. typical load regulatio n, vref = 1200 mv, t = (-40...+ 85) c, buffer - enable 850 900 950 1000 1050 1100 1150 1200 1250 0 50 100 150 200 250 300 350 400 450 500 v ref i ( u a) vdd=5.5v vdd=3.3v vdd=2.7v SLG46533_ds_114 page 119 of 184 SLG46533 15.0 rc oscillator (rc osc) the SLG46533 has three internal oscillators. rc oscillator tha t runs at 25 khz / 2 mhz (osc0), oscillator that runs at 25 mhz (osc1) and crystal oscillator. it is possible to use all three oscillators simultaneously. the fundamental frequency can also come from clock input (io15 or io17 fo r 25 khz / 2 mhz and io14 for 25 mhz or crystal osc), see section 20.0 external clocking . 15.1 25 khz/2 mhz and 25 mhz rc oscillators there are two divider stages that allow the user flexibility fo r introducing clock signals on various connection matrix input lines. the predivider allows the selection of /1, /2, /4 or /8 divide down frequency from the fundamental. the second stage divider ( only for 25 khz / 2 mhz oscillator) has an input of frequency from t he predivider, and outputs one of seven different frequencies o n connection matrix input lines <27> (out0) and <28> (out1). see figure 66 and figure 67 below for details. there are two modes of the power control pin, (reg<1658> for 25 khz / 2 mhz osc and reg<1657> for 25 mhz osc): ? power down <0> . if pwr control input of oscillator is low, the oscillator wil l be turned on. if pwr control input of oscillator is high the oscill ator will be turne d off and osc divider will reset. ? force on <1> . if pwr control input of oscilla tor is high, the oscillator wi ll be turned on. if pwr control input of oscillator is low the osci llator will be turned off. the pwr control signal has the highest priority. the SLG46533 has a 25 khz / 2 mhz osc fast start-up function re g<1338> (1 C on, 0 C off). it allows the osc to run immediately after power-up this decreases the settling time. no te that when osc fast start-up is on, the current consumption will rise. the user can select two osc powe r modes (reg<1343 for 25 khz / 2 mhz osc and reg<1341> for 25 mhz osc): ?if auto power on <0> is selected, the osc will run only when any macr ocell that use s osc is powered on. ?if force power on <1> is selected, the osc will run when the sl g46533 is powered on. osc can be turned on by: ? register control (force power on) ? delay mode, when delay requires osc ? cnt/fsm SLG46533_ds_114 page 120 of 184 SLG46533 figure 66. 25 khz / 2 mh z rc osc block diagram figure 67. 25 mhz rc osc block diagram internal rco reg <1342> 0: 25 khz 1: 2 mhz io17i ext. clock ext. clk sel reg <1358> / 2 / 3 / 4 / 8 / 12 / 24 / 64 0 1 2 3 4 5 6 7 to connection matrix input <27> reg <1349:1347> div /1 /2 /4 /8 reg <1340:1339> predivider second stage divider 0 1 from connection matrix output <58> pwr down to connection matrix input <28> reg <1346:1344> 0 1 io15 ext. clock ext. clk sel reg <1355> auto power on 0 1 force power on osc power mode reg <1343> out0 out1 internal rco 25 mhz osc io14 ext. clock ext. clk sel reg <1357> to connection matrix input <29> div /1 /2 /4 /8 reg <1337:1336> divider 0 1 from connection matrix output <59> pwr down auto power on 0 1 force power on osc power mode reg <1341> out SLG46533_ds_114 page 121 of 184 SLG46533 15.2 oscillator power on delay note 1: osc power mo de: ?auto power on?. note 2: ?osc enable? signal appears when any macrocell that uses osc is powered on . figure 68. oscillator startup diagram figure 69. rc oscillator maximum p ower on delay vs. vdd at room temperature, osc0 = 2 mhz clk osc enable power on delay 150 250 350 450 550 650 750 850 950 1,050 1.7 1.8 1.9 2.3 2.5 2.7 3.0 3.3 3.6 4.2 4.5 5.0 5.5 power on delay (ns) vdd (v) normal start-up mode fast start-up mode SLG46533_ds_114 page 122 of 184 SLG46533 figure 70. rc oscillator maximum power on delay vs. vdd at room temperature, osc0 = 25 khz figure 71. osc1 (25 mhz) maximum power on delay vs. vdd at room temperature 0 5 10 15 20 25 1.7 1.8 1.9 2.3 2.5 2.7 3.0 3.3 3.6 4.2 4.5 5.0 5.5 power on delay ( s) vdd (v) normal start-up mode fast start-up mode 0 1 2 3 4 5 6 7 8 9 1,71 1,8 1,89 2,3 2,5 2,7 3 3,3 3,6 4,2 4,5 5 5,5 power on delay (s) vdd (v) SLG46533_ds_114 page 123 of 184 SLG46533 15.3 oscillator accuracy note: osc power setting: force power on; clock to matrix input - enable; bandgap: turn on by register - enable. figure 72. rc oscillator frequency vs. temperature, rc osc0=2 mh z figure 73. rc oscillator frequency vs. temperature, rc osc0=25 k hz 1.75 1.8 1.85 1.9 1.95 2 2.05 2.1 2.15 2.2 -40 -20 0 20 40 60 80 f (mhz) t (c) fmax @ vdd=1.8 v fmin @ vdd=1.8 v fmax @ vdd=3.3 v fmin @ vdd=3.3 v fmax @ vdd=5.0 v fmin @ vdd=5.0 v 23.5 24 24.5 25 25.5 26 26.5 27 -40 -20 0 20 40 60 80 f (khz) t (c) fmax @ vdd=1.8 v fmin @ vdd=1.8 v fmax @ vdd=3.3 v fmin @ vdd=3.3 v fmax @ vdd=5.0 v fmin @ vdd=5.0 v SLG46533_ds_114 page 124 of 184 SLG46533 note 1: for more information see section 5.11 osc specifications. note 2: 25 mhz rc osc1 performance is not guaranteed at vdd < 2.5 v. figure 74. osc1 (25 mhz) frequency vs. temperature 17 19 21 23 25 27 29 31 -40 -20 0 20 40 60 80 f (mhz) t (c) fmax @ vdd=1.8 v fmin @ vdd=1.8 v fmax @ vdd=3.3 v fmin @ vdd=3.3 v fmax @ vdd=5.0 v fmin @ vdd=5.0 v SLG46533_ds_114 page 125 of 184 SLG46533 16.0 crystal oscillator the crystal osc provides high pr ecision and stability of the ou tput frequency. io14 and io13 are input and output, respectivel y, of an inverting amplifier which is configured for use as an on- chip oscillator, as shown in figure 76 . either a quartz crystal or a ceramic resonator may be used. c1 and c2 should always be equal for both crystals and resonator s. the optimal value of the capacitors depends on the crystal or resonator in use, the amou nt of stray capacitance, and the electromagnetic noise of the environment. refer to table 102 . for the ceramic re sonators, the c apacitor values given by the manufacturer should be used. it is possible to use an external c lock source, it must be connect ed to io14. in this case no exte rnal components are required. figure 75. crystal osc block diagram figure 76. external crystal connection table 102. external compo nents selection table f c1 c2 r1 r2 32.768 khz 10 pf 330 pf 20 m ? 20 k ? 4 - 40 mhz 12 pf 12 pf 1 m ? 0 ? crystal osc to connection matrix input <53> from connection matrix output <109> pwr down disable 0 1 enable osc power mode reg <1136> io14 io13 out crystal SLG46533 io14 io13 c2 c1 r1 r2 SLG46533_ds_114 page 126 of 184 SLG46533 17.0 power on reset (por) the SLG46533 has a power-on reset (por) macrocell to ensure cor rect device initialization and operation of all macrocells in the device. the purpose of the por circuit is to have consisten t behavior and predictable results when the vdd power is first ramping to the device, and also while the vdd is falling during power-down. to accomplish this goal, the por drives a defined sequence of internal events that trigger changes to the states of different macrocells inside th e device, and finally to the s tate of the i/o pins. 17.1 general operation to start the por sequence in the SLG46533, the voltage applied on the vdd should be higher than the power_on threshold (see note 2). the full operational vdd range for the SLG46533 i s 1.71v C 5.5v (1.8v 5% - 5v10%). this means that the vdd voltage must ramp up to the operational voltage value, but the por sequence will start earlier, as soon as the vdd voltage ris es to the power_on threshold. aft er the por sequence has started, the SLG46533 will have a typical period of time to go through all the steps in the sequence (noted in the datasheet for that device), and will be ready and completely operational after the por sequence is complete. the SLG46533 is guaranteed to be powered down and nonoperationa l when the vdd voltage (voltage on vdd) is less than power off threshold (see in electrical characteristics table), but not less than -0.6 v. another essential condition for the c hip to be powered down is that no voltage higher (see note 1) than the vdd voltage is applied to any other pin. for example, if vdd voltage is 0.3 v, applying a voltage higher than 0.3 v to any o ther pin is incorrect, and can lead to incorrect or unexpected device behavior. note 1. there is a 0.6 v margin due to forward drop voltage of the esd protection diodes. note 2. the power_on threshold is defined in electrical characteristics table. to power down the chip the vdd voltage should be lower than the operational and to guarantee that chip is powered down it should be less than power off threshold. all pins are in high impedance st ate when the chip is powered d own and while the por sequence is taking place. the last step in the por sequence releases the i/o structures from the high i mpedance state, at which time the device is operational. the pi n configuration at this point in time is defined by the design pr ogrammed into the chip. also as it was mentioned before the vol tage on pins cant be bigger than t he vdd, this rule also applies to the case when the chip is powered on. SLG46533_ds_114 page 127 of 184 SLG46533 17.2 por sequence the por system generat es a sequence of signa ls that enable cert ain macrocells. the sequence is shown in figure 77 . as can be seen from figure 77 after the vdd has start ramping up and crosses the power_on th reshold, first, the on-chip nvm memory is reset. next the chip reads the data from nvm, and tra nsfers this information to sram registers that serve to configu re each macrocell, and the connection matrix which routes signals between macrocells. the third stage causes the reset of the inp ut pins, and then to enable them. after that, the luts are reset a nd become active. after luts the delay cells, rc osc, dffs, latches, pipe delay and other mac rocells are initialized. only after all macrocells are initialized internal por signal (por macrocell output) goes from low to high. the last portion of th e device to be initialized are the output pins, which transitio n from high impedience to active at this point. the typical time that takes to complete the por sequence varies by device type in the greenpak family. it also depends on many environmental factors, such as: slew rate, vdd value, temperatu re and even will vary from chip to chip (process influence). figure 77. por sequence vdd por_nvm (reset for nvm) nvm_ready_out por_gpi (reset for input enable) por_lut (reset for lut output) por_core (reset for dly/rc osc/dff /latch/pipe dly/other macrocells por_out (generate low to high to matrix) por_gpo (reset for output enable) t t t t t t t t input: ignore transition output: initial state (determined by reg<1354:1352>) SLG46533_ds_114 page 128 of 184 SLG46533 17.3 macrocells output states during por sequence to have a full picture of SLG46533 operation during powering an d por sequence, review the overview the macrocell output states during the por sequence ( figure 78 describes the output signals states). first, before the nvm has been res et, all macrocells have their output set to logic low (exc ept the output pins which are in h igh impedance state). before the nv m is ready, all macrocell output s are unpredictable (except the output pins). on the next step, some of the macrocells start ini tialization: input pins output state becomes low; luts also output low. only p dly macrocell configured as edge detector becomes active at this time. after that input pins are enabled. next, only luts are configured. ne xt, all other macrocells are initialized. after macrocells are init ialized, internal por matrix signa l switches from low to high. the last are output pins that become active and determined by the i nput signals. figure 78. internal macrocell states during por sequence unpredictable unpredictable unpredictable unpredictable unpredictable unpredictable unpredictable unpredictable vdd input pin_out to matrix lut_out to matrix programmable delay_out to matrix prog. edge_detector_out to matrix dff/latch_out to matrix delay_out to matrix por_out to matrix ext. gpo vdd_out to matrix determined by input signals determined by input signals starts to detect input edges determined by input signals determined by input signals determined by input signals starts to detect input edges determined by input signals determined by external signal guaranteed high before por_gpi determined by input signals out = in without delay determined by initial state determined by input signals out = in without delay tri-state t t t t t t t t t t output state unpredictable SLG46533_ds_114 page 129 of 184 SLG46533 17.3.1 initialization all internal macrocells by default have initial low level. star ting from indicated powerup time of 1.15 v - 1.6 v, macrocells in gpak are powered on while forced to the reset state. all output s are in hi-z and chip starts loading data from nvm. then the reset signal is released for int ernal macrocells and they start to initialize according t o the following sequence: 1. i 2 c; 2. input pins, acmp , pull up/down; 3. luts; 4. dffs, delays/counters, pipe delay; 5. por output to matrix; 6. output pin corresponds to the internal logic. the vref output pin driving signa l can precede por output signa l going high by 3 ? s - 5 ? s. the por signal going high indicates the mentioned power-up sequence is complete. note: the maximum voltage applied to any pin should not be hi gher than the vdd level. t here are esd diodes between pin ? > vdd and pin ?> gnd on each pin. so if the input signal applied to pin is higher than vdd, then current will sink through the diode to vdd. exceeding vdd results in leakage current on the input pin, and vdd will be pulled up, following the voltage on the input pin.there is no ef fect from input pin when input voltage is applied at the same time as vdd. 17.3.2 power down during powerdown, macrocells in SLG46533 are powered off after vdd falling down below power off threshold. please note that during a slow rampdown, outp uts can possibly switch state during this time. figure 79. power down not guaranteed output state vdd (v) time 1.6 v 1.15 v 2 v 1 v 1 v vref out signal SLG46533_ds_114 page 130 of 184 SLG46533 18.0 i 2 c serial communications macrocell 18.1 i 2 c serial commu nications macrocell overview in the standard use case for t he greenpak devices, the configur ation choices made by the user are stored as bit settings in th e non-volatile memory (nvm), and this information is transferred at startup time to volatile ram registers that enable the confi gu- ration of the macrocells. other ram registers in the device are responsible for setting the connections in the connection matr ix to route signals in th e manner most appropri ate for the users application. the i 2 c serial communications macrocell in this device allows an i 2 c bus master to read and write this information via a serial channel directly to the ram registers, allowing the remote re-c onfiguration of macrocells, and remote changes to signal chains within the device. an i 2 c bus master is also able read and write other register bits th at are not associated with nvm memory. as an example, the input lines to the connection matrix can be read as digital reg ister bits. these are the signal outputs of each of the macroce lls in the device, giving an i 2 c bus master the capability to re motely read the current value of any macrocell. the user has the flexibility to control read access and write a ccess via registers bits reg<1832>, reg<1870>, and reg<1871>. s ee section 18.5 i2c serial command register protection for more details on i 2 c read/write memory protection. note: greenpak i 2 c is fully compatible with standard i 2 c protocol. 18.2 i 2 c serial communicati ons device addressing each command to the i 2 c serial communications macrocell begins with a control byte. t he bits inside this control byte are shown in figure 80 . after the start bit, the first four bits are a control code, which can be set by the user in reg<1867:1864>. this gives the user flexibility on the chip level addressing of this device and other devices on the same i 2 c bus. the block address is the next three bits (a10,a9, a8 ), which will define the most si gnificant bits in the addressing of the data to be read or writ ten by the command. the last bit in the control byte is the r/w bit, which selects whether a read command or write command is requested, with a 1 selecti ng for a read command, and a 0 s electing for a write command. this control byte will be followe d by an acknowledge bit (ack), whic h is sent by this device to in dicate successful communication of the control byte data. in the i 2 c-bus specification and user manual, there are two groups of ei ght addresses (0000 xxx and 1111 xxx) that are reserved for the special functions, such as a system general call addres s. if the user of this device choses to set the control code to either 1111 or 0000 in a system with other slave device, please co nsult the i 2 c-bus specification and user manual to understand the addressing and implementation o f these special functions, to in sure reliable operation. in the read and write command address structure, there are a to tal of 11 bits of addressing, each pointing to a unique byte of information, resulting in a tota l address space of 2k bytes. of this 2k byte address space, the valid addresses accessible to the i 2 c macrocell on the SLG46533 are in the range from 0 (0x00) to 2 55 (0xff). the msb address bits (a10, a9 and a8) will be 0 for all commands to the SLG46533. with the exception of the current address read command, all com mands will have the control byte followed by the word address. figure 80 shows this basic co mmand structure. figure 80. basic command structure x x x x a 1 0 a 9 a 8 r/w a 7 a 0 control byte word address control code block address read/write bit (1 = read, 0 = write) s ack acknowledge bit start bit n o t u s e d , s e t t o 0 SLG46533_ds_114 page 131 of 184 SLG46533 18.3 i 2 c serial general timing general timing characteristics for the i 2 c serial communications macrocell are shown in figure 81 . timing specifications can be found in the ac charac teristics section. 18.4 i 2 c serial communi cations commands 18.4.1 byte write command following the start condition from the master, the control code [4 bits], the block address [3 bits] and the r/w bit (set to 0), are placed onto the i 2 c bus by the master. after the SLG46533 sends an acknowledge bi t (ack), the next byte transmitted by the master is the word address. the block address (a10, a9, a8), co mbined with the word address (a7 through a0), together set the internal address pointer in the SLG46533 where the data byt e is to be written. after the SLG46533 sends another acknowledg e bit, the master will transmit the data byte to be written into the addressed memory location. the SLG46533 again provides an acknowledge bit and then the mas ter generates a stop condition. the internal write cycle for t he data will take place at the t ime that the SLG46533 generates the acknowledge bit. figure 81. i 2 c general timing characteristics figure 82. byte write command, r/w = 0 scl t f t r t su sto t buf t high t low t su dat t hd dat t hd sta t su sta t aa t dh sda in sda out x x x x a 1 0 a 9 a 8 w a 7 a 0 control byte word address control code block address r/w bit = 0 s ack acknowledge bit start bit ack d 7 d 0 data p stop bit acknowledge bit sda line bus activity acknowledge bit ack n o t u s e d , s e t t o 0 SLG46533_ds_114 page 132 of 184 SLG46533 18.4.2 sequential write command the write control byte, word a ddress and the first data byte ar e transmitted to the SLG46533 in the same way as in a byte writ e command. however, instead of generating a stop condition, the m aster continues to transmit data bytes to the SLG46533. each subsequent data byte will incre ment the internal address counte r, and will be written into the next higher byte in the command addressing. as in the case of the byte write command, the inter nal write cycle will take place at the time that the SLG46533 generates the acknowledge bit. 18.4.3 current address read command the current address read command reads from the current pointer address location. the address pointer is incremented at the first stop bit following any write control byte. for example, i f a write or random read (which contains a write control byte) writes or reads data up to address n, t he address pointer would get in cremented to n+1 upon the stop of that command. subsequently, a current address read that follows would start reading data at n+1. the current address read command contains the control byte sent by the master, with the r/w bit = 1. the SLG46533 will issue an acknowledge bit, and the n transmit eight data bits for the requested byte. the master will not issue an acknowledg e bit, and follow immediately with a stop condition. figure 83. sequential write command, r/w = 0 figure 84. current address read command, r/w = 1 x x x x a 1 0 a 9 a 8 w control byte word address (n) control code block address r/w bit = 0 s ack acknowledge bit start bit data (n) stop bit sda line bus activity ack data (n + 1) ack ack data (n + x) p acknowledge bit ack n o t u s e d , s e t t o 0 x x x x a 1 0 a 9 a 8 r control byte data (n) control code block address r/w bit = 1 s ack acknowledge bit start bit p stop bit no ack bit sda line bus activity n o t u s e d , s e t t o 0 nack SLG46533_ds_114 page 133 of 184 SLG46533 18.4.4 random read command the random read command starts with a control byte (with r/w bit set to 0, indicating a wr ite command) and word address to set the internal byte address, followed by a start bit, and then the control byte for the read (exactly the same as the byt e write command). the start bit in the middle of the command will halt the decoding of a write command, but will set the internal addr ess counter in preparation for the second half of the command. afte r the start bit, the master issu es a second control byte with t he r/w bit set to 1, after which t he SLG46533 issues an acknowledge bit, followed by the reque sted eight data bits. 18.4.5 sequential read command the sequential read command is initiated in the same way as a c urrent address read or random read command, except that once the SLG46533 transmits the first data byte, the master iss ues an acknowledge bit as opposed to a stop condition in a rand om read. the master can continue r eading sequential bytes of data, and will terminate the comma nd with a stop condition. figure 85. random read command figure 86. sequential read command x x x x a 1 0 a 9 a 8 w control byte word address (n) control code block address r/w bit = 0 s ack acknowledge bit start bit control byte stop bit sda line bus activity ack data (n) ack p xxxx a 1 0 a 9 a 8 r s r/w bit = 1 no ack bit n o t u s e d , s e t t o 0 control code x x x x a 1 0 a 9 a 8 r control byte data (n) control code block address r/w bit = 1 s ack acknowledge bit start bit data (n+1) stop bit sda line bus activity ack data (n + 2) ack ack data (n + x) p no ack bit n o t u s e d , s e t t o 0 SLG46533_ds_114 page 134 of 184 SLG46533 18.4.6 i 2 c serial command address space in the read and write command address structure, there are a to tal of 11 bits of addressing, each pointing to a unique byte of information, resulting in a tota l address space of 2k bytes. of this 2k byte address space, the valid addresses accessible to the i 2 c macrocell on the SLG46533 are in the range from 0 (0x00) to 2 55 (0xff). the msb address bits (a10, a9 and a8) will be 0 for all commands to the SLG46533. 18.4.6.1 i 2 c serial command register map these register addresses are broken down into four banks to giv e the user greater control on access to reading and writing information in each bank. each of the four banks is 512 bits (6 4 bytes) in length. writing information to register bits in the se banks will change the configuration of t he device, resulting in eithe r a change in the interconnection options provided by the conne ction matrix, or by changing the configuration of individual macrocel ls. during device use, all regist er bits can be read or written via i 2 c, unless protection bits are set to prevent this. see section 21.0 appendix a - SLG46533 register definition for detailed information on all register bits 18.5 i 2 c serial command register protection the memory space is divided into four banks, each of which has 512bits (64bytes). there are thr ee bits that allow the user to define rules for reading and writi ng bits in each of these bank s via i 2 c: ? reg<1832> i 2 c lock for read bits <1535:0> ( bank 0/1/2). if the system provi des any read commands to the addresses in these three banks, the device will res pond with ffh in data field. ? reg<1871> i 2 c lock for write bits <1535:0> ( bank 0/1/2). if the system prov ides any write commands to the addresses in these three banks, the device wi ll acknowledge these commands, but will not do internal write s to the register space. ? reg<1870> i 2 c lock for write all bits (bank 0/1/2/3). if the system provide s any write commands to the add resses in these four banks, the device will ack nowledge these commands, but wil l not do internal write s to the register space. note 1. reg<1870> is higher priority than reg<1871>, and if reg<1870> is set, than reg<1871> does not have any effect. note 2. if the user sets ios 6 and 7 function to a selection other than sda and scl, all access via i 2 c will be disabled. figure 87. register bank map byte 0 bank 0 bank 1 bank 2 bank 3 byte 63 byte 64 byte 127 byte 128 byte 191 byte 192 byte 255 SLG46533_ds_114 page 135 of 184 SLG46533 if reg <1870> is not set, register bits in bank 3 are open to r ead and write commands via i 2 c with the following exceptions: ? reg<1663> io latching enable during i 2 c write interface is a lways protected from i 2 c write, see note 3. ? reg<1871> bank 0/1/2 i 2 c-write protection bit i s always protected from i 2 c write ? reg<1867:1864> i 2 c control code bit [3:0] i s always protected from i 2 c write note 3. if reg<1663> = 1, all outputs are latched while inpu ts and internal macrocells retain their status during i 2 c write note 4. any write commands that come to the device via i 2 c that are not blocked, based on the protection bits, will change the contents of the ram register bits that mirror the nvm bits. these write commands will not change the nvm bits themselves, and a por event will restore the register bits to original programmed contents of the nvm. see section 21.0 appendix a - SLG46533 register definition for detailed information on all registers. 18.5.1 register read/write protection there are six read/write protec t modes for the design sequence from being corrupted or copied. see table 103 for details. table 103. read/write protection options bank byte bits description lock status unlocked locked for read bits <1535:0> locked for write bits <1535:0> locked for write all bits locked for read and write bits <1535:0> locked for read bits <1535:0> and write all bits reg <1832>=0, <1871>=0, <1870>=0 reg <1832>=1, <1871>=0, <1870>=0 reg <1832>=0, <1871>=0, <1870>=0 reg <1832>=0, <1871>=x, <1870>=1 reg <1832>=1, <1871>=1, <1870>=0 reg <1832>=1, <1871>=x, <1870>=1 0 0-63 511-0 connection matrix outputs configuration r/w w r r - - 1 64-109 879-512 r/w w r r - - 110-127 880-1023 reserved - - - - - - 2 128-186 1495-1024 function configuration for pins, luts/dffs, osc, asm and some configuration for dlys, acmp r/w w r r - - 187-191 1535-1496 reserved - - - - - - 3 192-206 1655-1536 cnt/dly counter data and some luts truth table, acmp vref r/w r/w r/w r r/w r 207 1663 io latching enable during i2c write interface r r r r r r 1662 i2c reset bit with reloading nvm into data register r/w r/w r/w r r/w r 1661-1659 reserved r r r r r r 1658-1656 osc power control r/w r/w r/w r r/w r SLG46533_ds_114 page 136 of 184 SLG46533 3 208-223 1791-1664 asm output ram and user configurable ram / otp r/w r/w r/w r r/w r 224-227 1823-1792 reserved - - - - - - 228 1831-1824 reserved r/w r/w r/w r r/w r 229 1839-1836 product family id r r r r r r 1835-1834 reserved - - - - - - 1833 reserved r r r r r r 1832 i2c lock for read bits<1535:0> r r r r r r 230 1847-1840 pattern id r/w r/w r/w r r/w r 231 1855-1848 reserved r r r r r r 232 1863-1856 reserved r r r r r r 233 1871 i2c lock for write bits<1535:0> r r r r r r 1870 i2c lock for write all bits r r r r r r 1869-1868 reserved - - - - - - 1867-1864 i2c control code r r r r r r 234-239 1919-1872 counter current value r r r r r r 240-243 1951-1920 macrocells output values (connection matrix inputs) r r r r r r 244 1959-1952 connection matrix virtual inputs r/w r/w r/w r r/w r 245-247 2007-1983 macrocells output values (connection matrix inputs) r r r r r r 248-250 2007-1984 reserved r r r r r r table 103. read/write protection options bank byte bits description lock status unlocked locked for read bits <1535:0> locked for write bits <1535:0> locked for write all bits locked for read and write bits <1535:0> locked for read bits <1535:0> and write all bits reg <1832>=0, <1871>=0, <1870>=0 reg <1832>=1, <1871>=0, <1870>=0 reg <1832>=0, <1871>=0, <1870>=0 reg <1832>=0, <1871>=x, <1870>=1 reg <1832>=1, <1871>=1, <1870>=0 reg <1832>=1, <1871>=x, <1870>=1 SLG46533_ds_114 page 137 of 184 SLG46533 18.5.1.1 i 2 c serial reset command if i 2 c serial communication is established with the device, it is po ssible to reset the device to initial power up conditions, incl uding configuration of all macrocells , and all connections provided b y the connection matrix. this is implemented by setting reg<166 2> i 2 c reset bit to 1, which causes the device to re-enable the po wer on reset (por) sequence, including the reload of all regist er data from nvm. during the por sequence, the outputs of the devi ce will be in tri-state. after the reset has taken place, the c ontents of reg<1662> will be set to 0 automatically. the timing diagr am shown below illustrates the s equence of events for this rese t function. note: i 2 c serial reset command is not available during emulation. 3 251 2015-2008 reserved r/w r/w r/w r r/w r 252-253 2031-2016 reserved r r r r r r 254 2039-2032 reserved r/w r/w r/w r r/w r 255 2047-2040 reserved r/w r/w r/w r r/w r r/w allow read and write data w allow write data only r allow read data only - the data is protected for read and write table 103. read/write protection options bank byte bits description lock status unlocked locked for read bits <1535:0> locked for write bits <1535:0> locked for write all bits locked for read and write bits <1535:0> locked for read bits <1535:0> and write all bits reg <1832>=0, <1871>=0, <1870>=0 reg <1832>=1, <1871>=0, <1870>=0 reg <1832>=0, <1871>=0, <1870>=0 reg <1832>=0, <1871>=x, <1870>=1 reg <1832>=1, <1871>=1, <1870>=0 reg <1832>=1, <1871>=x, <1870>=1 SLG46533_ds_114 page 138 of 184 SLG46533 18.5.1.2 reading counter data via i 2 c the current count value in four counters in the device can be r ead via i 2 c. the counters that have this additional functionality are 16-bit cnt0 and cnt1, and 8 -bit counters cnt4 and cnt6. 18.5.1.3 user ram and otp memory array there are eight bytes of ram memory that can be read and writte n remotely by i 2 c commands. the initial contents of this memory space can be selected by the u ser, and this information will be transferred from otp memory t o the ram memory space during the power-up sequence. the lowest order byte in this array (use r configurable ram/otp byte 0) is located at i 2 c address 0xd8, and the highest order byte i n this array is located at i 2 c address 0xdf. figure 88. reset command timing table 104. ram array table i2c address (hex) highest bit address lowest bit address memory byte d8 1735 1728 user configurable ram/otp byte 0 d9 1743 1736 user configurable ram/otp byte 1 da 1751 1744 user configurable ram/otp byte 2 db 1759 1752 user configurable ram/otp byte 3 dc 1767 1760 user configurable ram/otp byte 4 dd 1775 1768 user configurable ram/otp byte 5 de 1783 1776 user configurable ram/otp byte 6 df 1791 1784 user configurable ram/otp byte 7 x x x x a 1 0 a 9 a 8 w a 7 a 0 control byte word address control code block address write bit s ack acknowledge bit start bit ack d 7 d 0 data p stop bit acknowledge bit sda line bus activity acknowledge bit ack reset-bit register output reloading nvm into data register internal por internal reset bit by i 2 c stop signal reset-bit register (reg<1662>) is cleared by reloading nvm into data register 1) i 2 c write with reg<1662>=1 (i 2 c reset bit with reloading nvm into data register) 2) por go to low and reloading nvm into data register start aft er stop of i 2 c 3) por go to high after reloading nvm into data register n o t u s e d , s e t t o 0 SLG46533_ds_114 page 139 of 184 SLG46533 19.0 analog temperature sensor the SLG46533 has an analog temper ature sensor (ts) with an outp ut voltage linearly-proportional to the centigrade tempera- ture. the ts cell shares buffer with vref0, so it is impossible to use both cells simultaneously, its output can be connected directly to the io16. using buffer causes low-output impeda nce, linear o utput and makes interfacing to r eadout or control circuitry esp e- cially easy. the ts is rated to operate over a -40c to 180c t emperature range. the error in the whole temperature range does not exceed 10.3% (5.7% in a range from -40c to 100c). ts ou tput voltage variation over vdd at constant temperature is less than 10.3% (6.3% without buffer). for mor e detail refer to section 5.13 analog temperature s ensor (ts) specifications . figure 89. analog temperature sensor structure diagram + - vref0 reg <1464> vcp, reg <1474:1472>=100 (always cp should be on) reg<1470>=0 vref op amp offset chopper clock frequency 2 mhz reg<1469>=1 bandgap op amp offset chopper enable ts vdd 1 0 0 1 0 1 reg <1486:1484> vref select reg <1487> reg <1478> io16 closed ts_on reg<1464>=1 reg <1464>=1 ts_o open from connection matrix output <109> pwr down SLG46533_ds_114 page 140 of 184 SLG46533 figure 90. ts output vs tempe rature, vdd = (1.715.5) v table 105. ts register settings signal function register bit address register definition enable temp. sensor (separately, needs to turn on io16 vref buffer) reg<1464> 0: disable 1: enable cp function selection & power divider (vdd/3, vdd/4) on/off (must be set to auto on/off when using ts) reg<1474:1472> 100: cp a uto on/off (use for 1.71v SLG46533_ds_114 page 141 of 184 SLG46533 20.0 external clocking the SLG46533 supports several wa ys to use an external, higher a ccuracy clock as a reference so urce for internal operations 20.1 crystal mode when reg<1136> is set to 1, an ex ternal crystal can be connecte d to ios 13 and 14 for supplying an accurate clock source. see section 16.0 crystal oscillator . an external clocking signal on io14 can be used in place of t he crystal. the high and low limits for crystal frequency that can be s elected are 32. 768 khz and 4 0 mhz. 20.2 io17 or io15 source for 25 khz / 2 mhz clock when reg<1358> is set to 1, an external clocking signal on pins 18 or 20 will be routed in place of the internal rc oscillator derived 25 khz/2 mhz clock source. when reg<1355> is set to 0, io17 is in use, and when set to 1, io15 is in use. see figure 66 . the high and low lim its for external fr equency that can be se lected are 0 mh z and 77 mhz. 20.3 io14 source for 25 mhz clock when reg<1357> is set to 1, an external clocking signal on io14 will be routed in place of the internal rc oscillator derived 25 mhz clock source. see figure 67 . the high and low limits for e xternal frequen cy that can be se lected are 0 mhz and 84 mhz. SLG46533_ds_114 page 142 of 184 SLG46533 21.0 appendix a - SLG46533 register definition address signal function register bit definition i 2 c interface byte register bit read write note: for reg<0> to reg<1495>, i 2 c read is valid (assuming reg <1832> = 0), i 2 c write is valid (assuming reg <1871> = 0) matrix output 00 reg<5:0> matrix out in0 of lut3_11 o r clock input of dff8 valid valid reg<7:6> reserved valid valid 01 reg<13:8> matrix out in1 of lut3_11 or data input of dff8 valid val id reg<15:14> reserved valid valid 02 reg<21:16> matrix out in2 of lut3_11 or nrst (nset) of dff8 valid valid reg<23:22> reserved valid valid 03 reg<29:24> matrix out in0 of lut3_12 o r clock input of dff9 valid valid reg<31:30> reserved valid valid 04 reg<37:32> matrix out in1 of lut3_12 or data input of dff9 valid v alid reg<39:38> reserved valid valid 05 reg<45:40> matrix out in2 of lut3_12 or nrst (nset) of dff9 valid valid reg<47:46> reserved valid valid 06 reg<53:48> matrix out in0 of lut3_13 o r clock input of dff10 valid valid reg<55:54> reserved valid valid 07 reg<61:56> matrix out in1 of lut3_13 o r data input of dff10 valid valid reg<63:62> reserved valid valid 08 reg<69:64> matrix out in2 of lut3_13 or nrst (nset) of dff10 valid valid reg<71:70> reserved valid valid 09 reg<77:72> matrix out in0 of lut3_14 o r clock input of dff11 valid valid reg<79:78> reserved valid valid 0a reg<85:80> matrix out in1 of lut3_14 o r data input of dff11 valid valid reg<87:86> reserved valid valid 0b reg<93:88> matrix out in2 of lut3_14 or nrst (nset) of dff11 valid valid reg<95:94> reserved valid valid 0c reg<101:96> matrix out in0 of lut3_15 o r clock input of dff12 valid valid reg<103:102> reserved valid valid 0d reg<109:104> matrix out in1 of lut3_15 o r data input of dff12 valid valid reg<111:110> reserved valid valid SLG46533_ds_114 page 143 of 184 SLG46533 0e reg<117:112> matrix out in2 of lut3_15 or nrst (nset) of dff12 valid valid reg<119:118> reserved valid valid 0f reg<125:120> matrix out in0 of lut3_16 o r clock input of dff13 valid valid reg<127:126> reserved valid valid 10 reg<133:128> matrix out in1 of lut3_16 or data input of dff13 valid valid reg<135:134> reserved valid valid 11 reg<141:136> matrix out in2 of lut3_16 or nrst (nset) of dff13 valid valid reg<143:142> reserved valid valid 12 reg<149:144> matrix out in0 of lut3_17 o r clock input of dff14 valid valid reg<151:150> reserved valid valid 13 reg<157:152> matrix out in1 of lut3_17 or data input of dff14 valid valid reg<159:158> reserved valid valid 14 reg<165:160> matrix out in2 of lut3_17 or nrst (nset) of dff14 valid valid reg<167:166> reserved valid valid 15 reg<173:168> matrix out in0 of lut4_2 valid valid reg<175:174> reserved valid valid 16 reg<181:176> matrix out in1 of lut4_2 valid valid reg<183:182> reserved valid valid 17 reg<189:184> matrix ou in2 of lut4_2 valid valid reg<191:190> reserved valid valid 18 reg<197:192> matrix out in3 of lut4_2 valid valid reg<199:198> reserved valid valid 19 reg<205:200> matrix out io1 digital output source valid valid reg<207:206> reserved valid valid 1a reg<213:208> matrix out io1 output enable valid valid reg<215:214> reserved valid valid 1b reg<221:216> matrix out io2 digital output source valid valid reg<223:222> reserved valid valid 1c reg<229:224> matrix out io3 digital output source valid valid reg<231:230> reserved valid valid 1d reg<237:232> matrix out io3 output enable valid valid reg<239:238> reserved valid valid 1e reg<245:240> matrix out io4 digital output source valid valid reg<247:246> reserved valid valid 1f reg<253:248> matrix out io5 digital output source valid valid reg<255:254> reserved valid valid address signal function register bit definition i 2 c interface byte register bit read write SLG46533_ds_114 page 144 of 184 SLG46533 20 reg<261:256> matrix out io5 output enable valid valid reg<263:262> reserved valid valid 21 reg<269:264> matrix out io6 digital output source (scl with vi/input & nmos open-drain) valid valid reg<271:270> reserved valid valid 22 reg<277:272> matrix out io7 digital output source (sda with vi/input & nmos open-drain) valid valid reg<279:278> reserved valid valid 23 reg<285:280> matrix out io8 digital output source valid valid reg<287:286> reserved valid valid 24 reg<293:288> matrix out io8 output enable valid valid reg<295:294> reserved valid valid 25 reg<301:296> matrix out io9 digital output source valid valid reg<303:302> reserved valid valid 26 reg<309:304> matrix out io10 digital output source valid valid reg<311:310> reserved valid valid 27 reg<317:312> matrix out io10 output enable valid valid reg<319:318> reserved valid valid 28 reg<325:320> matrix out io11 dig ital output source valid valid reg<327:326> reserved valid valid 29 reg<333:328> matrix out io11 output enable valid valid reg<335:334> reserved valid valid 2a reg<341:336> matrix out io12 digital output source valid valid reg<343:342> reserved valid valid 2b reg<349:344> matrix out io13 digital output source valid valid reg<351:350> reserved valid valid 2c reg<357:352> matrix out io13 output enable valid valid reg<359:358> reserved valid valid 2d reg<365:360> matrix out io14 digital output source valid valid reg<367:366> reserved valid valid 2e reg<373:368> matrix out io15 digital output source valid valid reg<375:374> reserved valid valid 2f reg<381:376> matrix out io15 output enable valid valid reg<383:382> reserved valid valid 30 reg<389:384> matrix out io16 digital output source valid valid reg<391:390> reserved valid valid 31 reg<397:392> matrix out io16 output enable valid valid reg<399:398> reserved valid valid 32 reg<405:400> matrix out io17 digital output source valid valid reg<407:406> reserved valid valid 33 reg<413:408> matrix out acmp0 pdb (power down) valid valid reg<415:414> reserved valid valid address signal function register bit definition i 2 c interface byte register bit read write SLG46533_ds_114 page 145 of 184 SLG46533 34 reg<421:416> matrix out acmp1 pdb (power down) valid valid reg<423:422> reserved valid valid 35 reg<429:424> matrix out acmp2 pdb (power down) valid valid reg<431:430> reserved valid valid 36 reg<437:432> matrix out acmp3 pdb (power down) valid valid reg<439:438> reserved valid valid 37 reg<445:440> matrix out input of filter_0 with fixed time edge detector valid valid reg<447:446> reserved valid valid 38 reg<453:448> matrix out input of filter_1 with fixed time edge detector valid valid reg<455:454> reserved valid valid 39 reg<461:456> matrix out input of programmable delay & edge detector valid valid reg<463:462> reserved valid valid 3a reg<469:464> matrix out osc 25khz/2mhz pd (power down) valid valid reg<471:470> reserved valid valid 3b reg<477:472> matrix out osc 25mhz pd (power down) valid valid reg<479:478> reserved valid valid 3c reg<485:480> matrix out in0 of lut2_0 or clock input of dff0 valid valid reg<487:486> reserved valid valid 3d reg<493:488> matrix out in1 of lut2_0 or data input of dff0 valid v alid reg<495:494> reserved valid valid 3e reg<501:496> matrix out in0 of lut2_1 or clock input of dff1 vali dvalid reg<503:502> reserved valid valid 3f reg<509:504> matrix out in1 of lut2_1 or data input of dff1 valid v alid reg<511:510> reserved valid valid 40 reg<517:512> matrix out in0 of lut2_2 or clock input of dff2 valid valid reg<519:518> reserved valid valid 41 reg<525:520> matrix out in1 of lut2_2 or data input of dff2 valid v alid reg<527:526> reserved valid valid 42 reg<533:528> matrix out in0 of lut2_3 or clock input of pgen valid valid reg<535:534> reserved valid valid 43 reg<541:536> matrix out in1 of lut2_3 or nrst of pgen valid valid reg<543:542> reserved valid valid 44 reg<549:544> matrix out in0 of lut3_0 or clock input of dff3 vali dvalid reg<551:550> reserved valid valid 45 reg<557:552> matrix out in1 of lut3_0 or data input of dff3 valid v alid reg<559:558> reserved valid valid 46 reg<565:560> matrix out in2 of lut3_0 or nrst (nset) of dff3 valid valid reg<567:566> reserved valid valid address signal function register bit definition i 2 c interface byte register bit read write SLG46533_ds_114 page 146 of 184 SLG46533 47 reg<573:568> matrix out in0 of lut3_1 or clock input of dff4 valid valid reg<575:574> reserved valid valid 48 reg<581:576> matrix out in1 of lut3_1 or data input of dff4 valid v alid reg<583:582> reserved valid valid 49 reg<589:584> matrix out in2 of lut3_1 or nrst (nset) of dff4 valid valid reg<591:590> reserved valid valid 4a reg<597:592> matrix out in0 of lut3_2 or clock input of dff5 valid valid reg<599:598> reserved valid valid 4b reg<605:600> matrix out in1 of lut3_2 or data input of dff5 valid v alid reg<607:606> reserved valid valid 4c reg<613:608> matrix out in2 of lut3_2 or nrst (nset) of dff5 valid valid reg<615:614> reserved valid valid 4d reg<621:616> matrix out in0 of lut3_3 or clock input of dff6 vali dvalid reg<623:622> reserved valid valid 4e reg<629:624> matrix out in1 of lut3_3 or data input of dff6 valid v alid reg<631:630> reserved valid valid 4f reg<637:632> matrix out in2 of lut3_3 or nrst (nset) of dff6 valid valid reg<639:638> reserved valid valid 50 reg<645:640> matrix out in0 of lut3_4 or clock input of dff7 vali dvalid reg<647:646> reserved valid valid 51 reg<653:648> matrix out in1 of lut3_4 or data input of dff7 valid v alid reg<655:654> reserved valid valid 52 reg<661:656> matrix out in2 of lut3_4 or nrst (nset) of dff7 valid valid reg<663:662> reserved valid valid 53 reg<669:664> matrix out in0 of lut3_5 or d elay2 input (or counter2 rst input) valid valid reg<671:670> reserved valid valid 54 reg<677:672> matrix out in1 of lut3_5 or external clock input of delay2 (or counter2) valid valid reg<679:678> reserved valid valid 55 reg<685:680> matrix out in2 of lut3_5 valid valid reg<687:686> reserved valid valid 56 reg<693:688> matrix out in0 of lut3_6 or d elay3 input (or counter3 rst input) valid valid reg<695:694> reserved valid valid 57 reg<701:696> matrix out in1 of lut3_6 or external clock input of delay3 (or counter3) valid valid reg<703:702> reserved valid valid 58 reg<709:704> matrix out in2 of lut3_6 valid valid reg<711:710> reserved valid valid address signal function register bit definition i 2 c interface byte register bit read write SLG46533_ds_114 page 147 of 184 SLG46533 59 reg<717:712> matrix out in0 of lut3_7 or d elay4 input (or counter4 rst input) valid valid reg<719:718> reserved valid valid 5a reg<725:720> matrix out in1 of lut3_7 or external clock input of delay4 (or counter4) valid valid reg<727:726> reserved valid valid 5b reg<733:728> matrix out in2 of lut3_7 valid valid reg<735:734> reserved valid valid 5c reg<741:736> matrix out in0 of lut3_8 or d elay5 input (or counter5 rst input) valid valid reg<743:742> reserved valid valid 5d reg<749:744> matrix out in1 of lut3_8 or external clock input of delay5 (or counter5) valid valid reg<751:750> reserved valid valid 5e reg<757:752> matrix out in2 of lut3_8 valid valid reg<759:758> reserved valid valid 5f reg<765:760> matrix out in0 of lut3_9 or d elay6 input (or counter6 rst input) valid valid reg<767:766> reserved valid valid 60 reg<773:768> matrix out in1 of lut3_9 or external clock input of delay6 (or counter6) valid valid reg<775:774> reserved valid valid 61 reg<781:776> matrix out in2 of lut3_9 valid valid reg<783:782> reserved valid valid 62 reg<789:784> matrix out in0 of lut3_10 or input of pipe delay vali dvalid reg<791:790> reserved valid valid 63 reg<797:792> matrix out in1 of lut3_10 or nrst of pipe de- lay valid valid reg<799:798> reserved valid valid 64 reg<805:800> matrix out in2 of lut3_10 or clock of pipe delay vali dvalid reg<807:806> reserved valid valid 65 reg<813:808> matrix out in0 of lut4_0 or d elay0 input (or counter0 rst/set input) valid valid reg<815:814> reserved valid valid 66 reg<821:816> matrix out in1 of lut4_0 or external clock input of delay0 (or counter0) valid valid reg<823:822> reserved valid valid 67 reg<829:824> matrix out in2 of lut4_0 or up input of fsm0 valid val id reg<831:830> reserved valid valid 68 reg<837:832> matrix out in3 of lut4_0 or keep input of fsm0 valid v alid reg<839:838> reserved valid valid 69 reg<845:840> matrix out in0 of lut4_1 or d elay1 input (or counter1 rst/set input) valid valid reg<847:846> reserved valid valid address signal function register bit definition i 2 c interface byte register bit read write SLG46533_ds_114 page 148 of 184 SLG46533 6a reg<853:848> matrix out in1 of lut4_1 or external clock input of delay1 (or counter1) valid valid reg<855:854> reserved valid valid 6b reg<861:856> matrix out in2 of lut4_1 or up input of fsm1 valid val id reg<863:862> reserved valid valid 6c reg<869:864> matrix out in3 of lut4_1 or keep input of fsm1 valid v alid reg<871:870> reserved valid valid 6d reg<877:872> matrix out pd of crystal oscillator by reg<1268> val id valid reg<879:878> reserved valid valid reserved 6e reg<887:880> reserved valid valid 6f reg<895:888> reserved valid valid 70 reg<903:896> reserved valid valid 71 reg<911:904> reserved valid valid 72 reg<919:912> reserved valid valid 73 reg<927:920> reserved valid valid 74 reg<935:928> reserved valid valid 75 reg<943:936> reserved valid valid 76 reg<951:944> reserved valid valid 77 reg<959:952> reserved valid valid 78 reg<967:960> reserved valid valid 79 reg<975:968> reserved valid valid 7a reg<983:976> reserved valid valid 7b reg<991:984> reserved valid valid 7c reg<999:992> reserved valid valid 7d reg<1007:1000> reserved valid valid 7e reg<1015:1008> reserved valid valid 7f reg<1023:1016> reserved valid valid io0 80 reg<1024> reserved valid valid reg<1025> reserved valid valid reg<1027:1026> reserved valid valid reg<1029:1028> io0 pull down resistor value selection 00: floating 01: 10k 10: 100k 11: 1m valid valid reg<1031:1030> io0 mode control 00: digital input wit hout schmitt trig- ger 01: digital input with schmitt trigger 10: low voltage digital input 11: reserved valid valid address signal function register bit definition i 2 c interface byte register bit read write SLG46533_ds_114 page 149 of 184 SLG46533 io1 81 reg<1032> reserved valid valid reg<1033> io1 pull up/down resistor selection 0: pull down resistor 1: pull up resistor valid valid reg<1035:1034> io1 pull up/down resistor value selection 00: floating 01: 10k 10: 100k 11: 1m valid valid reg<1037:1036> io1 mode co ntrol (sig_io1_oe=0) 00: digital input wit hout schmitt trig- ger, 01: digital input with schmitt trigger, 10: low voltage digital input 11: reserved valid valid reg<1039:1038> io1 mode co ntrol (sig_io1_oe=1) 00: push pull 1x 01: push pull 2x 10: open drain nmos 1x 11: open drain nmos 2x valid valid io2 82 reg<:1040> reserved valid valid reg<:1041> io2 driver strength selection 0: 1x 1: 2x valid valid reg<:1042> io2 pull up/do wn resistor selection 0: pull down resistor 1: pull up resistor valid valid reg<1044:1043> io2 pull up/down resistor value selection 00: floating 01: 10k 10: 100k 11: 1m valid valid reg<1047:1045> io2 mode control 000: digital input without schmitt trig- ger 001: digital input wit h schmitt trigger 010: low voltage digital input 011: reserved 100: push pull 101: open drain nmos 110: open drain pmos 111: open drain nmos valid valid address signal function register bit definition i 2 c interface byte register bit read write SLG46533_ds_114 page 150 of 184 SLG46533 io3 83 reg<1048> reserved valid valid reg<1049> io3 pull up/down resistor selection 0: pull down resistor 1: pull up resistor valid valid reg<1051:1050> io3 pull up/down resistor value selection 00: floating 01: 10 k 10: 100 k 11: 1 m valid valid reg<1053:1052> io3 mode co ntrol (sig_io3_oe=0) 00: digital input wit hout schmitt trig- ger 01: digital input with schmitt trigger 10: low voltage digital input 11: reserved valid valid reg<1055:1054> io3 mode co ntrol (sig_io3_oe=1) 00: push pull 1x 01: push pull 2x 10: open drain nmos 1x 11: open drain nmos 2x valid valid io4 84 reg<:1056> reserved valid valid reg<:1057> io4 driver strength selection 0: 1x 1: 2x valid valid reg<:1058> io4 pull up/do wn resistor selection 0: pull down resistor 1: pull up resistor valid valid reg<1060:1059> io4 pull up/down resistor value selection 00: floating 01: 10 k 10: 100 k 11: 1 m valid valid reg<1063:1061> io4 mode control 000: digital input without schmitt trig- ger 001: digital input wit h schmitt trigger 010: low voltage digital input 011: analog input/output 100: push pull 101: open drain nmos 110: open drain pmos 111: analog input & open drain valid valid address signal function register bit definition i 2 c interface byte register bit read write SLG46533_ds_114 page 151 of 184 SLG46533 io5 85 reg<1064> reserved valid valid reg<1065> io5 pull up/down resistor selection 0: pull down resistor 1: pull up resistor valid valid reg<1067:1066> io5 pull up/down resistor value selection 00: floating 01: 10 k 10: 100 k 11: 1 m valid valid reg<1069:1068> io5 mode co ntrol (sig_io5_oe=0) 00: digital input wit hout schmitt trig- ger 01: digital input with schmitt trigger 10: low voltage digital input 11: analog input/output valid valid reg<1071:1070> io5 mode co ntrol (sig_io5_oe=1) 00: push pull 1x 01: push pull 2x 10: open drain nmos 1x 11: open drain nmos 2x valid valid io6 86 reg<1072> reserved valid valid reg<1073> io6 driver s trength selection 0: 1x 1: 2x valid valid reg<1074> select scl & virtual input 0 or io6 0: scl & virtual input 0 1: io6 valid valid reg<1076:1075> io6 (or scl) pull do wn resistor value selection 00: floating 01: 10k 10: 100k 11: 1m valid valid reg<1079:1077> io6 (or scl) m ode control (input mode is selected by reg at scl) 000: digital input without schmitt trig- ger 001: digital input wit h schmitt trigger 010: low voltage digital input 011: reserved 100: open drain nmos 101: open drain nmos 110: open drain nmos 111: reserved valid valid address signal function register bit definition i 2 c interface byte register bit read write SLG46533_ds_114 page 152 of 184 SLG46533 io7 87 reg<:1080> reserved valid valid reg<:1081> io7 (or sda) d river strength selection 0: 1x (i 2 c up to 400 khz) 1: 2x (i 2 c up to 1 mhz) valid valid reg<:1082> select sda & virtual input 1 or io7 0: sda & virtual input 1 1: io7 valid valid reg<1084:1083> io7 (or sda) pull down resistor value se- lection 00: floating 01: 10 k 10: 100 k 11: 1 m valid valid reg<1087:1085> io7 (or sda) mode control (input mode is selected by reg. but, output mode is fixed as od at sda.) 000: digital input without schmitt trig- ger 001: digital input wit h schmitt trigger 010: low voltage digital input 0 11 : r e s e r v e d 100: open drain nmos 101: open drain nmos 110: open drain nmos 111: reserved valid valid io8 88 reg<1088> io8 super drive (4x , nmos open drain) selection 0: super drive off 1: super drive on (if sig_io8_oe='1' & io8 mode control = '1x') valid valid reg<1089> io8 pull up/down resistor selection 0: pull down resistor 1: pull up resistor valid valid reg<1091:1090> io8 pull up/down resistor value selection 00: floating 01: 10 k 10: 100 k 11: 1 m valid valid reg<1093:1092> io8 mode co ntrol (sig_io8_oe=0) 00: digital input wit hout schmitt trig- ger 01: digital input with schmitt trigger 10: low voltage digital input 11: analog input/output valid valid reg<1095:1094> io8 mode co ntrol (sig_io8_oe=1) 00: push pull 1x 01: push pull 2x 10: open drain nmos 1x 11: open drain nmos 2x valid valid address signal function register bit definition i 2 c interface byte register bit read write SLG46533_ds_114 page 153 of 184 SLG46533 io9 89 reg<:1096> io9 super drive (4x , nmos open drain) selection 0: super drive off 1: super drive on (if io9 mode con- trol = '101') valid valid reg<:1097> io9 driver strength selection 0: 1x 1: 2x valid valid reg<:1098> io9 pull up/do wn resistor selection 0: pull down resistor 1: pull up resistor valid valid reg<1100:1099> io9 pull up/down resistor value selection 00: floating 01: 10 k 10: 100 k 11: 1 m valid valid reg<1103:1101> io 9 mode control 000: digital input without schmitt trig- ger 001: digital input wit h schmitt trigger 010: low voltage digital input 011: analog input/output 100: push pull 101: open drain nmos 110: open drain pmos 111: analog input & open drain valid valid io10 8a reg<1104> reserved valid valid reg<1105> io10 pull up/down resistor selection 0: pull down resistor 1: pull up resistor valid valid reg<1107:1106> io10 pull up/down resistor value selection 00: floating 01: 10k 10: 100k 11: 1m valid valid reg<1109:1108> io10 mode control (sig_io10_oe=0) 00: digital input wit hout schmitt trig- ger 01: digital input with schmitt trigger 10: low voltage digital input 11: analog input/output valid valid reg<1111:1110> io10 mode control (sig_io10_oe=1) 00: push pull 1x 01: push pull 2x 10: open drain nmos 1x 11: open drain nmos 2x valid valid address signal function register bit definition i 2 c interface byte register bit read write SLG46533_ds_114 page 154 of 184 SLG46533 io11 8b reg<1112> reserved valid valid reg<1113> io11 pull up/down resistor selection 0: pull down resistor 1: pull up resistor valid valid reg<1115:1114> io11 pull up/down resistor value selection 00: floating 01: 10 k 10: 100 k 11: 1 m valid valid reg<1117:1116> io11 mode control (sig_io11_oe=0) 00: digital input wit hout schmitt trig- ger 01: digital input with schmitt trigger 10: low voltage digital input 11: analog input/output valid valid reg<1119:1118> io11 mode control (sig_io11_oe=1) 00: push pull 1x 01: push pull 2x 10: open drain nmos 1x 11: open drain nmos 2x valid valid io12 8c reg<:1120> reserved valid valid reg<:1121> io12 driver strength selection 0: 1x 1: 2x valid valid reg<:1122> io12 pull up/do wn resistor selection 0: pull down resistor 1: pull up resistor valid valid reg<1124:1123> io12 pull up/down resistor value selection 00: floating 01: 10 k 10: 100 k 11: 1 m valid valid reg<1127:1125> io12 mode control 000: digital input without schmitt trig- ger 001: digital input wit h schmitt trigger 010: low voltage digital input 011: analog input/output 100: push pull 101: open drain nmos 110: open drain pmos 111: analog input & open drain valid valid address signal function register bit definition i 2 c interface byte register bit read write SLG46533_ds_114 page 155 of 184 SLG46533 io13 8d reg<1128> reserved valid valid reg<1129> io13 pull up/down resistor selection 0: pull down resistor 1: pull up resistor valid valid reg<1131:1130> io13 pull up/down resistor value selection 00: floating 01: 10 k 10: 100 k 11: 1 m valid valid reg<1133:1132> io13 mode control (sig_io13_oe=0) 00: digital input wit hout schmitt trig- ger 01: digital input with schmitt trigger 10: low voltage digital input 11: sel for xosc (x2) valid valid reg<1135:1134> io13 mode control (sig_io13_oe=1) 00: push pull 1x 01: push pull 2x 10: open drain nmos 1x 11: open drain nmos 2x valid valid io14 8e reg<:1136> x1 & x2 for crystal osc enable 0: disable 1: enable valid valid reg<:1137> io14 driver strength selection 0: 1x 1: 2x valid valid reg<:1138> io14 pull up/do wn resistor selection 0: pull down resistor 1: pull up resistor valid valid reg<1140:1139> io14 pull up/down resistor value selection 00: floating 01: 10k 10: 100k 11: 1m valid valid reg<1143:1141> io14 mode control 000: digital input without schmitt trig- ger 001: digital input wit h schmitt trigger 010: low voltage digital input 011: sel for xosc (x1) 100: push pull 101: open drain nmos 110: open drain pmos 111: open drain nmos valid valid address signal function register bit definition i 2 c interface byte register bit read write SLG46533_ds_114 page 156 of 184 SLG46533 io15 8f reg<1144> reserved valid valid reg<1145> io15 pull up/down resistor selection 0: pull down resistor 1: pull up resistor valid valid reg<1147:1146> io15 pull up/down resistor value selection 00: floating 01: 10 k 10: 100 k 11: 1 m valid valid reg<1149:1148> io15 mode control (sig_io15_oe=0) 00: digital input wit hout schmitt trig- ger 01: digital input with schmitt trigger 10: low voltage digital input 11: analog input/output valid valid reg<1151:1150> io15 mode control (sig_io15_oe=1) 00: push pull 1x 01: push pull 2x 10: open drain nmos 1x 11: open drain nmos 2x valid valid io16 io169 0 reg<1152> reserved valid valid reg<1153> io16 pull up/down resistor selection 0: pull down resistor 1: pull up resistor valid valid reg<1155:1154> io16 pull up/down resistor value selection 00: floating 01: 10 k 10: 100 k 11: 1 m valid valid reg<1157:1156> io16 mode control (sig_io16_oe=0) 00: digital input wit hout schmitt trig- ger 01: digital input with schmitt trigger 10: low voltage digital input 11: analog input/output valid valid reg<1159:1158> io16 mode cont rol (sig_ioio1616_oe=1) 00: push pull 1x 01: push pull 2x 10: open drain nmos 1x 11: open drain nmos 2x valid valid address signal function register bit definition i 2 c interface byte register bit read write SLG46533_ds_114 page 157 of 184 SLG46533 io17 91 reg<:1160> reserved valid valid reg<:1161> io17 driver strength selection 0: 1x 1: 2x valid valid reg<:1162> io17 pull up/do wn resistor selection 0: pull down resistor 1: pull up resistor valid valid reg<1164:1163> io17 pull up/down resistor value selection 00: floating 01: 10 k 10: 100 k 11: 1 m valid valid reg<1167:1165> io17 mode control 000: digital input without schmitt trig- ger 001: digital input wit h schmitt trigger 010: low voltage digital input 011: reserved 100: push pull 101: open drain nmos 110: open drain pmos 111: open drain nmos valid valid acmp1 92 reg<1168> acmp1 positive i nput source select 0: io8 1: acmp0 in+ source valid valid reg<1169> acmp1 analog buffer enable (max. bw 1mhz) 0: disable analog buffer 1: enable analog buffer valid valid reg<1171:1170> acmp1 hysteresis enable 00: 0 mv 01: 25 mv 10: 50 mv 11: 200 mv (01: for both external & internal vref; 10 & 11: for only internal vref; exter- nal vref will not have 50 mv & 200 mv hysteresis.) valid valid acmp0 92 reg<1172> acmp0 positive i nput source select 0: io4 1: vdd valid valid reg<1173> acmp0 analog buffer enable (max. bw 1mhz) 0: disable analog buffer 1: enable analog buffer valid valid reg<1175:1174> acmp0 hysteresis enable 00: 0 mv 01: 25 mv 10: 50 mv 11: 200 mv (01: for both external & internal vref; 10 & 11: for only internal vref; exter- nal vref will not have 50 mv & 200 mv hysteresis.) valid valid address signal function register bit definition i 2 c interface byte register bit read write SLG46533_ds_114 page 158 of 184 SLG46533 acmp3 93 reg<1177:1176> acmp3 positive i nput source select 0: io12 01: acmp2 in+ source 10: acmp0 in+ source 00: reserved valid valid reg<1179:1178> acmp3 hysteresis enable 00: 0 mv 01: 25 mv 10: 50 mv 11: 200 mv (01: for both external & internal vref; 10 & 11: for only internal vref; exter- nal vref will not have 50 mv & 200 mv hysteresis.) valid valid acmp2 93 reg<1180> acmp2 positive i nput source select 0: io10 1: acmp0 in+ source valid valid reg<1182:1181> acmp2 hysteresis enable 00: 0 mv 01: 25 mv 10: 50 mv, 11: 200 mv (01: for both external & internal vref; 10 & 11: for only internal vref; exter- nal vref will not have 50 mv & 200 mv hysteresis.) valid valid acmp1 100 ua current source enable 93 reg<1183> acmp1 100ua current source enable 0: disable 1: enable valid valid lut3_x function select 94 reg<1184> lut3_3 or dff6 with nrst/nset select 0: lut3_3 1: dff6 with nrst/nset valid valid reg<1185> lut3_2 or dff5 with nrst/nset select 0: lut3_2 1: dff5 with nrst/nset valid valid reg<1186> lut3_1 or dff4 with nrst/nset select 0: lut3_1 1: dff4 with nrst/nset valid valid reg<1187> lut3_0 or dff3 with nrst/nset select 0: lut3_0 1: dff3 with nrst/nset valid valid lut2_x function select 94 reg<1188> lut2_3 or pgen select 0: lut2_3 1: pgen valid valid reg<1189> lut2_2 or dff2 select 0: lut2_2 1: dff2 valid valid reg<1190> lut2_1 or dff1 select 0: lut2_1 1: dff1 valid valid reg<1191> lut2_0 or dff0 select 0: lut2_0 1: dff0 valid valid address signal function register bit definition i 2 c interface byte register bit read write SLG46533_ds_114 page 159 of 184 SLG46533 lut4_x function select 95 reg<1192> lut4_1 or dly/cnt1(16bits) select 0: lut4_1 1: dly/cnt1(16bits) valid valid reg<1193> lut4_0 or dly/cnt0(16bits) select 0: lut4_0 1: dly/cnt0(16bits) valid valid lut3_x function select 95 reg<1194> lut3_9 or dly/cnt6(8bits) select 0: lut3_9 1: dly/cnt6(8bits) valid valid reg<1195> lut3_8 or dly/cnt5(8bits) select 0: lut3_8 1: dly/cnt5(8bits) valid valid reg<1196> lut3_7 or dly/cnt4(8bits) select 0: lut3_7 1: dly/cnt4(8bits) valid valid reg<1197> lut3_6 or dly/cnt3(8bits) select 0: lut3_6 1: dly/cnt3(8bits) valid valid reg<1198> lut3_5 or dly/cnt2(8bits) select 0: lut3_5 1: dly/cnt2(8bits) valid valid reg<1199> lut3_4 or dff7 with nrst/nset select 0: lut3_4 1: dff7 with nrst/nset valid valid lut2_1 / dff1 96 reg<1200> lut2_1 <0> valid valid reg<1201> lut2_1 <1> / dff1 initial polarity select 0: low 1: high valid valid reg<1202> lut2_1 <2> / dff1 output select 0: q output 1: qb output valid valid reg<1203> lut2_1 <3> / dff1 or latch select 0: dff function 1: latch function valid valid lut2_0 / dff0 96 reg<1204> lut2_0 <0> valid valid reg<1205> lut2_0 <1> / dff0 initial polarity select 0: low 1: high valid valid reg<1206> lut2_0 <2> / dff0 output select 0: q output 1: qb output valid valid reg<1207> lut2_0 <3> / dff0 or latch select 0: dff function 1: latch function valid valid lut2_3 / pgen 97 reg<1211:1208> lut2_3<3:0> or pgen 4bit counter da- ta<3:0> valid valid lut2_2 / dff2 97 reg<1212> lut2_2 <0> valid valid reg<1213> lut2_2 <1> / dff2 initial polarity select 0: low 1: high valid valid reg<1214> lut2_2 <2> / dff2 output select 0: q output 1: qb output valid valid reg<1215> lut2_2 <3> / dff2 or latch select 0: dff function 1: latch function valid valid address signal function register bit definition i 2 c interface byte register bit read write SLG46533_ds_114 page 160 of 184 SLG46533 lut3_0 / dff3 98 reg<1219:1216> lut3_0 <3:0> valid valid reg<1220> lut3_0 <4> / dff3 initial polarity select 0: low 1: high valid valid reg<1221> lut3_0 <5> / dff3 nrst or nset select 0: nrst from matrix output 1: nset from matrix output valid valid reg<1222> lut3_0 <6> / dff3 output select 0: q output 1: qb output valid valid reg<1223> lut3_0 <7> / dff3 or latch select 0: dff function 1: latch function valid valid lut3_1 / dff4 99 reg<1227:1224> lut3_1 <3:0> valid valid reg<1228> lut3_1 <4> / dff4 initial polarity select 0: low 1: high valid valid reg<1229> lut3_1 <5> / dff4 nrst or nset select 0: nrst from matrix output 1: nset from matrix output valid valid reg<1230> lut3_1 <6> / dff4 output select 0: q output 1: qb output valid valid reg<1231> lut3_1 <7> / dff4 or latch select 0: dff function 1: latch function valid valid lut3_2 / dff5 9a reg<1235:1232> lut3_2 <3:0> valid valid reg<1236> lut3_2 <4> / dff5 initial polarity select 0: low 1: high valid valid reg<1237> lut3_2 <5> / dff5 nrst or nset select 0: nrst from matrix output 1: nset from matrix output valid valid reg<1238> lut3_2 <6> / dff5 output select 0: q output 1: qb output valid valid reg<1239> lut3_2 <7> / dff5 or latch select 0: dff function 1: latch function valid valid lut3_3 / dff6 9b reg<1243:1240> lut3_3 <3:0> valid valid reg<1244> lut3_3 <4> / dff6 initial polarity select 0: low 1: high valid valid reg<1245> lut3_3 <5> / dff6 nrst or nset select 0: nrst from matrix output 1: nset from matrix output valid valid reg<1246> lut3_3 <6> / dff6 output select 0: q output 1: qb output valid valid reg<1247> lut3_3 <7> / dff6 or latch select 0: dff function 1: latch function valid valid address signal function register bit definition i 2 c interface byte register bit read write SLG46533_ds_114 page 161 of 184 SLG46533 lut3_4 / dff7 9c reg<1251:1248> lut3_4 <3:0> valid valid reg<1252> lut3_4 <4> / dff7 initial polarity select 0: low 1: high valid valid reg<1253> lut3_4 <5> / dff7 nrst or nset select 0: nrst from matrix output 1: nset from matrix output valid valid reg<1254> lut3_4 <6> / dff7 output select 0: q output 1: qb output valid valid reg<1255> lut3_4 <7> / dff7 or latch select 0: dff function 1: latch function valid valid lut3_10 / pipe delay 9d reg<1259:1256> lut3_10 <3:0> / pipe delay out0 select valid valid reg<1263:1260> lut3_10 <7:4> / pipe delay out1 select valid valid 9e reg<1265:1264> select the edge mode of programmable de- lay & edge detector 00: rising edge detector 01: falling edge detector 10: both edge detector 11: both edge delay valid valid reg<1267:1266> delay value select for programmable delay & edge detector (vdd = 3.3v, typical) 00: 135 ns 01: 270 ns 10: 405 ns 11: 540 ns valid valid reg<1269:1268> crystal oscillator power down enable 00: no matrix pd 01: matrix pd for crystal oscillator 10: reserved 11: matrix pd for both crystal oscillator valid valid reg<1270> lut3_10 or pipe delay select 0: lut3_10 1: pipe delay valid valid reg<1271> pipe delay out1 polarity select 0: non-inverted 1: inverted valid valid address signal function register bit definition i 2 c interface byte register bit read write SLG46533_ds_114 page 162 of 184 SLG46533 dly/cnt2 9f reg<1273:1272> dly2 mode select or asynchronous cnt2 reset 00: on both falling and rising edges (for delay & counter reset) 01: on falling edge only (for delay & counter reset) 10: on rising edge only (for delay & counter reset) 11: no delay on eith er falling or ris- ing edges / high level reset valid valid reg<1276:1274> dly/cnt2 clock source select 000: interna l osc clock 001: osc/4 010: osc/12 011: osc/24 100: osc/64 101: 25 mhz osc clock 110: external clock 111: counter1 overflow valid valid reg<1277> dly/cnt2 output selection if dly/cnt2 mode selection is "11" 0: default output 1: edge detector output valid valid reg<1279:1278> dly/cnt2 mode selection 00: delay mode 01: one shot 10: freq. detect 11: counter mode valid valid dly/cnt3 a0 reg<1281:1280> dly3 mode select or asynchronous cnt3 reset 00: on both falling and rising edges (for delay & counter reset) 01: on falling edge only (for delay & counter reset) 10: on rising edge only (for delay & counter reset) 11: no delay on eith er falling or ris- ing edges / high level reset valid valid reg<1284:1282> dly/cnt3 clock source select 000: interna l osc clock 001: osc/4 010: osc/12 011: osc/24 100: osc/64 101: 25mhz osc clock 110: external clock 111: counter2 overflow valid valid reg<1285> dly/cnt3 output selection if dly/cnt3 mode selection is "11" 0: default output 1: edge detector output valid valid reg<1287:1286> dly/cnt3 mode selection 00: delay mode 01: one shot 10: freq. detect 11: counter mode valid valid address signal function register bit definition i 2 c interface byte register bit read write SLG46533_ds_114 page 163 of 184 SLG46533 dly/cnt4 a1 reg<1289:1288> dly4 mode select or asynchronous cnt4 reset 00: on both falling and rising edges (for delay & counter reset) 01: on falling edge only (for delay & counter reset) 10: on rising edge only (for delay & counter reset) 11: no delay on eith er falling or ris- ing edges / high level reset valid valid reg<1292:1290> dly/cnt4 clock source select 000: interna l osc clock 001: osc/4 010: osc/12 011: osc/24 100: osc/64 101: 25mhz osc clock 110: external clock 111: counter3 overflow valid valid reg<1293> dly/cnt4 output selection if dly/cnt4 mode selection is "11" 0: default output 1: edge detector output valid valid reg<1295:1294> dly/cnt4 mode selection 00: delay mode 01: one shot 10: freq. detect 11: counter mode valid valid dly/cnt5 a2 reg<1297:1296> dly5 mode select or asynchronous cnt5 reset 00: on both falling and rising edges (for delay & counter reset) 01: on falling edge only (for delay & counter reset) 10: on rising edge only (for delay & counter reset) 11: no delay on eith er falling or ris- ing edges / high level reset valid valid reg<1300:1298> dly/cnt5 clock source select 000: interna l osc clock 001: osc/4 010: osc/12 011: osc/24 100: osc/64 101: 25 mhz osc clock 110: external clock 111: counter4 overflow valid valid reg<1301> dly/cnt5 output selection if dly/cnt5 mode selection is "11" 0: default output 1: edge detector output valid valid reg<1303:1302> dly/cnt5 mode selection 00: delay mode 01: one shot 10: freq. detect 11: counter mode valid valid address signal function register bit definition i 2 c interface byte register bit read write SLG46533_ds_114 page 164 of 184 SLG46533 dly/cnt6 a3 reg<1305:1304> dly6 mode select or asynchronous cnt6 reset 00: on both falling and rising edges (for delay & counter reset) 01: on falling edge only (for delay & counter reset) 10: on rising edge only (for delay & counter reset) 11: no delay on eith er falling or ris- ing edges / high level reset valid valid reg<1308:1306> dly/cnt6 clock source select 000: interna l osc clock 001: osc/4 010: osc/12 011: osc/24 100: osc/64 101: 25mhz osc clock 110: external clock 111: counter5 overflow valid valid reg<1309> dly/cnt6 output selection if dly/cnt6 mode selection is "11". 0: default output 1: edge detector output valid valid reg<1311:1310> dly/cnt6 mode selection 00: delay mode 01: one shot 10: freq. detect 11: counter mode valid valid dly/cnt0 a4 reg<1313:1312> dly0 mode select or asynchronous cnt0 reset (16bits) 00: on both falling and rising edges (for delay & counter reset) 01: on falling edge only (for delay & counter reset) 10: on rising edge only (for delay & counter reset) 11: no delay on eith er falling or ris- ing edges / high level reset valid valid reg<1316:1314> dly/cnt0 clo ck source select (16bits) 000: interna l osc clock 001: osc/4 010: osc/12 011: osc/24 100: osc/64 101: 25 mhz osc clock 110: external clock 111: counter6 overflow valid valid reg<1317> cnt0/fsm0's q are set to data or reset to 0s selection (16bits) 0: reset to 0s 1: set to data (r eg<1583:1576, 1591:1584>) valid valid reg<1319:1318> dly/cnt0 mode selection (16bits) 00: delay mode 01: one shot 10: freq. detect 11: counter mode valid valid address signal function register bit definition i 2 c interface byte register bit read write SLG46533_ds_114 page 165 of 184 SLG46533 dly/cnt1 a5 reg<1321:1320> dly1 mode select or asynchronous cnt1 reset (16bits) 00: on both falling and rising edges (for delay & counter reset) 01: on falling edge only (for delay & counter reset) 10: on rising edge only (for delay & counter reset) 11: no delay on eith er falling or ris- ing edges / high level reset valid valid reg<1324:1322> dly/cnt1 clo ck source select (16bits) 000: interna l osc clock 001: osc/4 010: osc/12 011: osc/24 100: osc/64 101: 25 mhz osc clock 110: external clock 111: counter0 overflow valid valid reg<1325> cnt1/fsm1's q are set to data or reset to 0s selection (16bits) 0: reset to 0 s 1: set to data (r eg<1599:1592, 1607:1600>) valid valid reg<1327:1326> dly/cnt1 mode selection (16bits) 00: delay mode 01: one shot 10: freq. detect 11: counter mode valid valid dly/cntx one-shot / freq. detect output polarity a6 reg<1328> reserved valid valid reg<1329> select the polarity of dly/cnt6's one shot / freq. detect output 0: default output 1: inverted output valid valid reg<1330> select the polarity of dly/cnt5's one shot / freq. detect output 0: default output 1: inverted output valid valid reg<1331> select the polarity of dly/cnt4's one shot / freq. detect output 0: default output 1: inverted output valid valid reg<1332> select the polarity of dly/cnt3's one shot / freq. detect output 0: default output 1: inverted output valid valid reg<1333> select the polarity of dly/cnt2's one shot / freq. detect output 0: default output 1: inverted output valid valid reg<1334> select the polarity of dly/cnt1's one shot / freq. detect output 0: default output 1: inverted output valid valid reg<1335> select the polarity of dly/cnt0's one shot / freq. detect output 0: default output 1: inverted output valid valid address signal function register bit definition i 2 c interface byte register bit read write SLG46533_ds_114 page 166 of 184 SLG46533 oscillator a7 reg<1337:1336> osc clock pre-divider for 25 mhz 00: div1 01: div2 10: div4 11: div8 valid valid reg<1338> osc fast start-up enable for 25khz/2mhz 0: disable 1: enable valid valid reg<1340:1339> osc clock pre-divider for 25khz/2mhz 00: div1 01: div2 10: div4 11: div8 valid valid reg<1341> force 25 mhz oscillator on 0: auto power on (if any cnt/dly use 25 mhz source) 1: force power on valid valid reg<1342> oscillator (25 khz: ring osc, 2 m: rc-osc) select 0: 25 khz ring osc 1: 2 mhz rc-osc valid valid reg<1343> force 25 khz /2 mhz oscillator on 0: auto power on (if any cnt/dly use 25 k/2 mhz source) 1: force power on valid valid a8 reg<1346:1344> internal osc 25 khz/2 mhz frequency di- vider control for matrix input <28> 000: osc/1 001: osc/2 010: osc/3 011: osc/4 100: osc/8 101: osc/12 110: osc/24 111: osc/64 valid valid reg<1349:1347> internal osc 25 khz/2 mhz frequency di- vider control for matrix input <27> 000: osc/1 001: osc/2 010: osc/3 011: osc/4 100: osc/8 101: osc/12 110: osc/24 111: osc/64 valid valid reg<1350> osc clock 25 khz/2 mhz to matrix input <28> enable 0: disable 1: enable valid valid reg<1351> osc clock 25 khz/2 mhz to matrix input <27> enable 0: disable 1: enable valid valid a9 reg<1354:1352> reserved valid valid reg<1355> external oscillator pin selection for 25 khz/2 mhz 0: io17 1: io15 valid valid reg<1356> osc clock 25mhz to matrix input <29> en- able 0: disable 1: enable valid valid reg<1357> external clock source s elect instead of 25 mhz 0: internal oscillator 1: external clock from io14 valid valid reg<1358> external clock source s elect instead of 25 khz/2 mhz 0: internal oscillator 1: external clock from io15 or io17 valid valid reg<1359> dly/cnt1 stop & resta rting enable in cnt mode when new data is loaded. 0: disable 1: enable valid valid address signal function register bit definition i 2 c interface byte register bit read write SLG46533_ds_114 page 167 of 184 SLG46533 lut3 or dff aa reg<1360> reserved valid valid reg<1361> lut3_17 or dff14 with nrst/nset select 0: lut3_17 1: dff14 with nrst/nset valid valid reg<1362> lut3_16 or dff13 with nrst/nset select 0: lut3_16 1: dff13 with nrst/nset valid valid reg<1363> lut3_15 or dff12 with nrst/nset select 0: lut3_15 1: dff12 with nrst/nset valid valid reg<1364> lut3_14 or dff11 with nrst/nset select 0: lut3_14 1: dff11 with nrst/nset valid valid reg<1365> lut3_13 or dff10 with nrst/nset select 0: lut3_13 1: dff10 with nrst/nset valid valid reg<1366> lut3_12 or dff9 with nrst/nset select 0: lut3_12 1: dff9 with nrst/nset valid valid reg<1367> lut3_11 or dff8 with nrst/nset select 0: lut3_11 1: dff8 with nrst/nset valid valid ab reg<1371:1368> lut3_11 <3:0> valid valid reg<1372> lut3_11 <4> / dff8 initial polarity select 0: low 1: high valid valid reg<1373> lut3_11 <5> / dff8 nrst or nset select 0: nrst from matrix output 1: nset from matrix output valid valid reg<1374> lut3_11 <6> / dff8 output select 0: q output 1: qb output valid valid reg<1375> lut3_11 <7> / dff8 or latch select 0: dff function 1: latch function valid valid ac reg<1379:1376> lut3_12 <3:0> valid valid reg<1380> lut3_12 <4> / dff9 initial polarity select 0: low 1: high valid valid reg<1381> lut3_12 <5> / dff9 nrst or nset select 0: nrst from matrix output 1: nset from matrix output valid valid reg<1382> lut3_12 <6> / dff9 output select 0: q output 1: qb output valid valid reg<1383> lut3_12 <7> / dff9 or latch select 0: dff function 1: latch function valid valid ad reg<1387:1384> lut3_13 <3:0> valid valid reg<1388> lut3_13 <4> / dff10 initial polarity select 0: low 1: high valid valid reg<1389> lut3_13 <5> / dff10 nrst or nset select 0: nrst from matrix output 1: nset from matrix output valid valid reg<1390> lut3_13 <6> / dff10 output select 0: q output 1: qb output valid valid reg<1391> lut3_13 <7> / dff10 or latch select 0: dff function 1: latch function valid valid address signal function register bit definition i 2 c interface byte register bit read write SLG46533_ds_114 page 168 of 184 SLG46533 ae reg<1395:1392> lut3_14 <3:0> valid valid reg<1396> lut3_14 <4> / dff11 initial polarity select 0: low 1: high valid valid reg<1397> lut3_14 <5> / dff11 nrst or nset select 0: nrst from matrix output 1: nset from matrix output valid valid reg<1398> lut3_14 <6> / dff11 output select 0: q output 1: qb output valid valid reg<1399> lut3_14 <7> / dff11 or latch select 0: dff function 1: latch function valid valid af reg<1403:1400> lut3_15 <3:0> valid valid reg<1404> lut3_15 <4> / dff12 initial polarity select 0: low 1: high valid valid reg<1405> lut3_15 <5> / dff12 nrst or nset select 0: nrst from matrix output 1: nset from matrix output valid valid reg<1406> lut3_15 <6> / dff12 output select 0: q output 1: qb output valid valid reg<1407> lut3_15 <7> / dff12 or latch select 0: dff function 1: latch function valid valid b0 reg<1411:1408> lut3_16 <3:0> valid valid reg<1412> lut3_16 <4> / dff13 initial polarity select 0: low 1: high valid valid reg<1413> lut3_16 <5> / dff13 nrst or nset select 0: nrst from matrix output 1: nset from matrix output valid valid reg<1414> lut3_16 <6> / dff13 output select 0: q output 1: qb output valid valid reg<1415> lut3_16 <7> / dff13 or latch select 0: dff function 1: latch function valid valid b1 reg<1419:1416> lut3_17 <3:0> valid valid reg<1420> lut3_17 <4> / dff14 initial polarity select 0: low 1: high valid valid reg<1421> lut3_17 <5> / dff14 nrst or nset select 0: nrst from matrix output 1: nset from matrix output valid valid reg<1422> lut3_17 <6> / dff14 output select 0: q output 1: qb output valid valid reg<1423> lut3_17 <7> / dff14 or latch select 0: dff function 1: latch function valid valid b2 reg<1431:1424> lut4_2 <15:0> = <1439:1424> valid valid b3 reg<1439:1432> valid valid b4 reg<1442:1440> reserved valid valid reg<1443> reserved valid valid reg<1446:1444> reserved valid valid reg<1447> reserved valid valid b5 reg<1450:1448> reserved valid valid reg<1451> reserved valid valid reg<1454:1452> reserved valid valid reg<1455> reserved valid valid address signal function register bit definition i 2 c interface byte register bit read write SLG46533_ds_114 page 169 of 184 SLG46533 filter / edge detector b6 reg<1457:1456> select the edge mode of edge detector_1 00: rising edge 01: falling edge 10: both edge 11: delay valid valid reg<1458> filter_1/edge detector_1 output polarity se- lect 0: filter_1 output 1: filter_1 output inverted valid valid reg<1459> filter_1or edge detector_1 select (typ. 30 ns @vdd=3.3 v) 0: filter_1 1: edge detector_1 valid valid reg<1461:1460> select the edge mode of edge detector_0 00: rising edge 01: falling edge 10: both edge 11: delay valid valid reg<1462> filter_0/edge detector_0 output polarity se- lect 0: filter_0 output 1: filter_0 output inverted valid valid reg<1463> filter_0 or edge detector_0 select (typ. 47 ns @vdd=3.3 v) 0: filter_0 1: edge detector_0 valid valid vref / bandgap reg<1465:1464> reserved valid valid b7 reg<1466> bandgap ok for acmp output delay time select, the start time is "resetb_core go to high" 0: 500 us 1: 50 us valid valid reg<1467> reserved valid valid reg<1468> reserved valid valid reg<1469> reserved valid valid reg<1470> reserved valid valid reg<1471> two consecutive dffs enable for sm 0: disable 1: enable valid valid address signal function register bit definition i 2 c interface byte register bit read write SLG46533_ds_114 page 170 of 184 SLG46533 b8 reg<1474:1472> power divider (vdd/3, vdd/4) on/off 0xx: power divider off (if there is no use of vdd/3, vdd/4 @ acmp nega- tive in) 100: reservedb x10: reserved xx1:reserved valid valid reg<1475> vdd bypass enable when device power is 1.8 v 0: regulator auto on 1: regulator off (vdd bypass) valid valid reg<1476> force bandgap on 0: auto-mode 1: enable (if chip i s power down, the bandgap will power down even if it is set to 1). valid valid reg<1477> nvm power down 0: none (or programming enable) 1: power down (or programming dis- able) valid valid reg<1478> temp output range contro l (temp. detector is not available) 0: 0.62 v ~ 0.99 v (typ) 1: 0.75 v ~ 1.2 v (typ) valid valid reg<1479> gpio quick charge enable 0: disable 1: enable valid valid b9 reg<1482:1480> vref1 output source select 000: acmp2 vref 001: acmp3 vref 100: vdd/2 101: vdd/3 110: vdd/4 111: hi-z valid valid reg<1483> reserved valid valid reg<1486:1484> vref0 output source select 000: acmp0 vref 001: acmp1 vref 100: vdd/2 101: vdd/3 110: vdd/4 111: hi-z valid valid reg<1487> reserved valid valid ba reg<1488> reserved valid valid reg<1489> wake time selection in wake sleep mode 0: short wake time 1: normal wake time valid valid reg<1490> acmp0 wake & sleep function enable 0: disable 1: enable valid valid reg<1491> acmp1 wake & sleep function enable 0: disable 1: enable valid valid reg<1492> acmp2 wake & sleep function enable 0: disable 1: enable valid valid reg<1493> acmp3 wake & sleep function enable 0: disable 1: enable valid valid reg<1494> wake sleep output state when ws oscilla- tor is off or dly/cnt0 high level set/reset at dly/cnt0 mode selection is "11" 0: low 1: high valid valid reg<1495> wake sleep ratio control mode selection if dly/cnt0 mode selection is "11" 0: default mode 1: wake sleep ratio control mode valid valid address signal function register bit definition i 2 c interface byte register bit read write SLG46533_ds_114 page 171 of 184 SLG46533 bb reg<1503:1496> reserved valid valid bc reg<1511:1504> reserved valid valid bd reg<1519:1512> reserved valid valid be reg<1527:1520> reserved valid valid bf reg<1535:1528> reserved valid valid lut / dly/cnt control data c0 reg<1543:1536> lut3_5 <7:0> or dly/cnt2 control data 1 - 255 (delay time = [counter control data + 1] / freq) valid valid c1 reg<1551:1544> lut3_6 <7:0> or dly/cnt3 control data 1 - 255 (delay time = [counter control data + 1] / freq) valid valid c2 reg<1559:1552> lut3_7 <7:0> or dly/cnt4 control data 1 - 255 (delay time = [counter control data + 1] / freq) valid valid c3 reg<1567:1560> lut3_8 <7:0> or dly/cnt5 control data 1 - 255 (delay time = [counter control data + 1] / freq) valid valid c4 reg<1575:1568> lut3_9 <7:0> or dly/cnt6 control data 1 - 255 (delay time = [counter control data + 1] / freq) valid valid c5 reg<1583:1576> lut4_0 <15:0> or dl y/cnt0 (16bits, <15:0> = <1591:1576>) control data 1 - 16535 (delay time = [counter control data + 2] / freq) valid valid c6 reg<1591:1584> c7 reg<1599:1592> lut4_1 <15:0> or dl y/cnt1 (16bits, <15:0> = <1607:1592>) control data 1 - 65535 (delay time = [counter control data + 2] / freq) valid valid c8 reg<1607:1600> c9 reg<1615:1608> pgen pattern data <15:0> = <1623:1608> valid valid ca reg<1623:1616> acmp0 cb reg<1628:1624> acmp0-in voltage select 00000: 50 mv 00001: 100 mv 00010: 150 mv 00011: 200 mv 00100: 250 mv 00101: 300 mv 00110: 350 mv 00111: 400 mv 01000: 450 mv 01001: 500 mv 01010: 550 mv 01011: 600 mv 01100: 650 mv 01101: 700 mv 01110: 750 mv 01111: 800 mv 10000: 850 mv 10001: 900 mv 10010: 950 mv 10011: 1 v 10100: 1.05 v 10101: 1.1 v 10110: 1.15 v 10111: 1.2 v 11000: vdd/3 11001: vdd/4 11010: io9: ext_vref 11011: io5: acmp0- 11100: io9: ext_vref/2 11101: io5: acmp0-/2 valid valid reg<1630:1629> acmp0 positive input divider 00: 1.0x 01: 0.5x 10: 0.33x 11: 0.25x valid valid reg<1631> acmp0 low bandwidth (max: 1mhz) en- a b l e 0: off 1: on valid valid address signal function register bit definition i 2 c interface byte register bit read write SLG46533_ds_114 page 172 of 184 SLG46533 acmp1 cc reg<1636:1632> acmp1-in voltage select 00000: 50 mv 00001: 100 mv 00010: 150 mv 00011: 200 mv 00100: 250 mv 00101: 300 mv 00110: 350 mv 00111: 400 mv 01000: 450 mv 01001: 500 mv 01010: 550 mv 01011: 600 mv 01100: 650 mv 01101: 700 mv 01110: 750 mv 01111: 800 mv 10000: 850 mv 10001: 900 mv 10010: 950 mv 10011: 1 v 10100: 1.05 v 10101: 1.1 v 10110: 1.15 v 10111: 1.2 v 11000: vdd/3 11001: vdd/4 11010: io9: ext_vref 11011: io9: ext_vref 11100: io9: ext_vref/2 11101: io9: ext_vref/2 valid valid reg<1638:1637> acmp1 positive input divider 00: 1.0x 01: 0.5x 10: 0.33x 11: 0.25x valid valid reg<1639> acmp1 low bandwidth (max: 1 mhz) en- a b l e 0: off 1: on valid valid acmp2 cd reg<1644:1640> acmp2-in voltage select 00000: 50 mv 00001: 100 mv 00010: 150 mv 00011: 200 mv 00100: 250 mv 00101: 300 mv 00110: 350 mv 00111: 400 mv 01000: 450 mv 01001: 500 mv 01010: 550 mv 01011: 600 mv 01100: 650 mv 01101: 700 mv 01110: 750 mv 01111: 800 mv 10000: 850 mv 10001: 900 mv 10010: 950 mv 10011: 1 v 10100: 1.05 v 10101: 1.1 v 10110: 1.15 v 10111: 1.2 v 11000: vdd/3 11001: vdd/4 11010: io9: ext_vref 11011: io11: acmp2- 11100: io9: ext_vref /2 11101: io11: acmp2-/2 valid valid reg<1646:1645> acmp2 positive input divider 00: 1.0x 01: 0.5x 10: 0.33x 11: 0.25x valid valid reg<1647> acmp2 low bandwidth (max: 1 mhz) en- a b l e 0: off 1: on valid valid address signal function register bit definition i 2 c interface byte register bit read write SLG46533_ds_114 page 173 of 184 SLG46533 acmp3 ce reg<1652:1648> acmp3-in voltage select 00000: 50 mv 00001: 100 mv 00010: 150 mv 00011: 200 mv 00100: 250 mv 00101: 300 mv 00110: 350 mv 00111: 400 mv 01000: 450 mv 01001: 500 mv 01010: 550 mv 01011: 600 mv 01100: 650 mv 01101: 700 mv 01110: 750 mv 01111: 800 mv 10000: 850 mv 10001: 900 mv 10010: 950 mv 10011: 1 v 10100: 1.05 v 10101: 1.1 v 10110: 1.15 v 10111: 1.2 v 11000: vdd/3 11001: vdd/4 11010: io9: ext_vref 11011: io11: acmp3- 11100: io9: ext_vref/2 11101: io11: acmp3-/2 valid valid reg<1654:1653> acmp3 positive input divider 00: 1.0x 01: 0.5x 10: 0.33x 11: 0.25x valid valid reg<1655> acmp3 low bandwidth (max: 1mhz) en- a b l e 0: off 1: on valid valid misc. cf reg<1656> reserved valid valid reg<1657> switch from matrix out: osc 25mhz pd to matrix out: osc 25 mhz force on 0: osc pd 1: osc force on (matrix output <59>) valid valid reg<1658> switch from matrix out: osc 25 khz/2 mhz pd to matrix out: osc 25 khz/2 mhz force on 0: osc pd 1: osc force on (matrix output <58>) valid valid reg<1659> reserved valid valid reg<1660> reserved valid valid reg<1661> reserved valid valid reg<1662> i 2 c reset bit with reloading nvm into data register 0: keep existing condition 1 : r e s e t e x e c u t i o n valid valid reg<1663> io latching enable during i 2 c write inter- face 0: disable 1: enable valid valid d0 reg<1671:1664> customer configurable ram8 valid valid d1 reg<1679:1672> customer configurable ram9 valid valid d2 reg<1687:1680> customer configurable ram10 valid valid d3 reg<1695:1688> customer configurable ram11 valid valid d4 reg<1703:1696> customer configurable ram12 valid valid d5 reg<1711:1704> customer configurable ram13 valid valid d6 reg<1719:1712> customer configurable ram14 valid valid d7 reg<1727:1720> customer configurable ram15 valid valid d8 reg<1735:1728> customer configurable ram0 invalid invalid d9 reg<1743:1736> customer configurable ram1 invalid invalid address signal function register bit definition i 2 c interface byte register bit read write SLG46533_ds_114 page 174 of 184 SLG46533 da reg<1751:1744> customer configurable ram2 invalid invalid db reg<1759:1752> customer configurable ram3 invalid invalid dc reg<1767:1760> customer configurable ram4 invalid invalid dd reg<1775:1768> customer configurable ram5 invalid invalid de reg<1783:1776> customer configurable ram6 invalid invalid df reg<1791:1784> customer configurable ram7 invalid invalid e0 reg<1799:1792> reserved invalid invalid e1 reg<1807:1800> reserved invalid invalid e2 reg<1815:1808> reserved invalid invalid e3 reg<1823:1816> reserved invalid invalid e4 reg<1831:1824> reserved valid valid e5 reg<1832> i 2 c lock for read bits < 1535:0> (bank 0/1/2) 0: disable (programmed data can be read.), 1: enable (programmed data can't be read.) valid invalid reg<1833> reserved valid invalid reg<1835:1834> reserved valid invalid reg<1839:1836> reserved valid invalid e6 reg<1847:1840> 8-bit pattern id byte 0 (from nvm): id[23:16] valid valid e7 reg<1855:1848> reserved valid invalid e8 reg<1863:1856> reserved valid invalid e9 reg<1867:1864> i 2 c control code bit [3:0] value for slave address valid invalid reg<1868> reserved valid valid reg<1869> reserved valid valid reg<1870> i 2 c lock for write all bits (bank 0/1/2/3) 0: writable 1: non-writable valid invalid reg<1871> i 2 c lock for write bits <1535:0> (bank 0/1/2) 0: writable 1: non-writable valid invalid ea reg<1879:1872> cnt4 counted value valid invalid eb reg<1887:1880> cnt0 (16bits) = <1895:1880> counted val- ue valid invalid ec reg<1895:1888> valid invalid ed reg<1903:1896> cnt6 counted value valid invalid ee reg<1911:1904> cnt1 (16bits) = <1919:1904> counted val- ue valid invalid ef reg<1919:1912> valid invalid address signal function register bit definition i 2 c interface byte register bit read write SLG46533_ds_114 page 175 of 184 SLG46533 matrix input f0 reg<1920> matrix input 0 gnd valid invalid reg<1921> matrix input 1 io0 digital input valid invalid reg<1922> matrix input 2 io1 digital input valid invalid reg<1923> matrix input 3 io2 digital input valid invalid reg<1924> matrix input 4 io3 digital input valid invalid reg<1925> matrix input 5 io4 digital input valid invalid reg<1926> matrix input 6 io5 digital input valid invalid reg<1927> matrix input 7 io8 digital input valid invalid f1 reg<1928> matrix input 8 lut2_ 0 / dff0 output valid invalid reg<1929> matrix input 9 lut2_ 1 / dff1 output valid invalid reg<1930> matrix input 10 lut2_2 / dff2 output valid invalid reg<1931> matrix input 11 lut2_3 / pgen output valid invalid reg<1932> matrix input 12 lut3_0 / dff3 output valid invalid reg<1933> matrix input 13 lut3_1 / dff4 output valid invalid reg<1934> matrix input 14 lut3_2 / dff5 output valid invalid reg<1935> matrix input 15 lut3_3 / dff6 output valid invalid f2 reg<1936> matrix input 16 lut3_4 / dff7 output valid invalid reg<1937> matrix input 17 lut3_5 / cnt_dly2(8bit) output valid inva lid reg<1938> matrix input 18 lut3_6 / cnt_dly3(8bit) output valid inva lid reg<1939> matrix input 19 lut3_7 / cnt_dly4(8bit) output valid inva lid reg<1940> matrix input 20 lut3_8 / cnt_dly5(8bit) output valid inva lid reg<1941> matrix input 21 lut3_9 / cnt_dly6(8bit) output valid inva lid reg<1942> matrix input 22 lut4_0 / cnt_dly0(16bit) output valid in valid reg<1943> matrix input 23 lut4_1 / cnt_dly1(16bit) output valid inv alid f3 reg<1944> matrix input 24 lut3_10 / pipe delay (1st stage) out- put valid invalid reg<1945> matrix input 25 pipe delay output0 valid invalid reg<1946> matrix input 26 pipe delay output1 valid invalid reg<1947> matrix input 27 fixed "l" output because it is osc clock. valid invalid reg<1948> matrix input 28 fixed "l" output because it is osc clock. valid invalid reg<1949> matrix input 29 fixed "l" output because it is osc clock. valid invalid reg<1950> matrix input 30 filter0 / edge detect0 output valid inva lid reg<1951> matrix input 31 filter1 / edge detect1 output valid inva lid address signal function register bit definition i 2 c interface byte register bit read write SLG46533_ds_114 page 176 of 184 SLG46533 f4 reg<1952> matrix input 32 vi rtual input <0> valid valid reg<1953> matrix input 33 vi rtual input <1> valid valid reg<1954> matrix input 34 vi rtual input <2> valid valid reg<1955> matrix input 35 vi rtual input <3> valid valid reg<1956> matrix input 36 vi rtual input <4> valid valid reg<1957> matrix input 37 vi rtual input <5> valid valid reg<1958> matrix input 38 vi rtual input <6> valid valid reg<1959> matrix input 39 virt ual input <7> valid valid f5 reg<1960> matrix input 40 lut3_11 / dff8 (set/rst) output valid inv alid reg<1961> matrix input 41 lut3_12 / dff9 (set/rst) output valid inv alid reg<1962> matrix input 42 lut3_13 / dff10 (set/rst) output valid in valid reg<1963> matrix input 43 lut3_14 / dff11 (set/rst) output valid in valid reg<1964> matrix input 44 lut3_15 / dff12 (set/rst) output valid in valid reg<1965> matrix input 45 lut3_16 / dff13 (set/rst) output valid in valid reg<1966> matrix input 46 lut3_17 / dff14 (set/rst) output valid in valid reg<1967> matrix input 47 lut4_2 output valid invalid f6 reg<1968> matrix input 48 io9 digital input valid invalid reg<1969> matrix input 49 io10 digital input valid invalid reg<1970> matrix input 50 io11 digital input valid invalid reg<1971> matrix input 51 io12 digital input valid invalid reg<1972> matrix input 52 io13 digital input valid invalid reg<1973> matrix input 53 io14 digital input valid invalid reg<1974> matrix input 54 io15 digital input valid invalid reg<1975> matrix input 55 io16 digital input valid invalid f7 reg<1976> matrix input 56 io17 digital input valid invalid reg<1977> matrix input 57 ac mp_0 output valid invalid reg<1978> matrix input 58 ac mp_1 output valid invalid reg<1979> matrix input 59 ac mp_2 output valid invalid reg<1980> matrix input 60 ac mp_3 output valid invalid reg<1981> matrix input 61 programmable del ay with edge de- tector output valid invalid reg<1982> matrix input 62 resetb_core valid invalid reg<1983> matrix input 63 vdd valid invalid reserved f8 reg<1991:1984> reserved valid invalid f9 reg<1999:1992> reserved valid invalid fa reg<2007:2000> reserved valid invalid fb reg<2015:2008> reserved valid valid fc reg<2023:2016> reserved valid invalid fd reg<2031:2024> reserved valid invalid fe reg<2039:2032> reserved valid valid ff reg<2047:2040> reserved valid valid address signal function register bit definition i 2 c interface byte register bit read write SLG46533_ds_114 page 177 of 184 SLG46533 22.0 package top marking system definition 22.1 stqfn 20l 2x3mm 0.4p col package 22.2 mstqfn 22l 2x2 .2 mm 0.4p package part code datecode lot revision ? part id field: identifies the specific device configuration ? date code field: coded date of manufacture ? lot code: designates lot # ? assembly site/coo: specifies assembly site/country of origin ? revision code: device revision xxxxx dd lll c rr coo p p a part code + assembly pin 1 identifier wwr date code + revision nn serial number code SLG46533_ds_114 page 178 of 184 SLG46533 23.0 package drawing and dimensions 23.1 stqfn 20l 2x3mm 0.4p col package jedec mo-220 ic net weight: 0.0090 g SLG46533_ds_114 page 179 of 184 SLG46533 23.2 mstqfn 22l 2x2 .2 mm 0.4p package jedec mo-220 ic net weight: 0.0058 g SLG46533_ds_114 page 180 of 184 SLG46533 24.0 tape and reel specifications 24.1 carrier tape drawing and dimensions package type # of pins nominal package size [mm] max units reel & hub size [mm] leader (min) trailer (min) tape width [mm] part pitch [mm] per reel per box pockets length [mm] pockets length [mm] stqfn 20l 2x3 mm 0.4p col 20 2 x 3 x 0.55 3,000 3,000 178 / 60 100 400 100 400 8 4 mstqfn 22l 2x2.2 mm 0.4p green 22 2 x 2.2x 0.55 3,000 3,000 178 / 60 100 400 100 400 8 4 package type pocket btm length pocket btm width pocket depth index hole pitch pocket pitch index hole diameter index hole to tape edge index hole to pocket center tape width a0 b0 k0 p0 p1 d0 e f w stqfn 20l 2x3 mm 0.4p col 2.2 3.15 0.76 4 4 1.5 1.75 3.5 8 mstqfn 22l 2x2.2 mm 0.4p green 2.2 2.35 0.8 4 4 1.5 1.75 3.5 8 refer to eia-481 specification SLG46533_ds_114 page 181 of 184 SLG46533 25.0 recommended land pattern 25.1 stqfn 20l 2x3mm 0.4p col package units: ? m SLG46533_ds_114 page 182 of 184 SLG46533 25.2 mstqfn 22l 2x2.2mm 0.4p green package 26.0 recommended reflow soldering profile please see ipc/jedec j-std-020: latest revision for reflow prof ile based on package volume of 3.30 mm 3 (nominal) for stqfn 20l package, and 2.42 mm 3 (nominal) for mstqfn 22l package . more inf ormation can be foun d at www.jedec.org. units: ? m SLG46533_ds_114 page 183 of 184 SLG46533 27.0 revision history date version change 10/12/2017 1.14 updated electrical spec fixed typos updated i2c specifications updated i2c serial command register protection added register read/write protection subsection 8/29/2017 1.13 updated vref block diagram updated subsection i2c serial reset command 5/24/2017 1.12 fixed typos updated reg<1831:1824> updated electrical characteristics 5/4/2017 1.11 fixed typos updated por section corrected table typical delay es timated for each block at t=25 c updated absolute maximum conditions 3/31/2017 1.10 fixed typos updated analog temperature se nsor (ts) specifications 2/16/2017 1.09 fixed quality of cnt timing diagrams updated section programmable delay / edge detector fixed typos 12/20/2016 1.08 corrected oscillator electrical spec updated silego w ebsite & support fixed typos corrected figure ws controller added table dly/cntx one-shot / freq. detect output polarity added data to table programma ble delay register settings updated figure deglitch filter / edge detector 11/15/2016 1.07 fixed typos corrected figure osc1 power on delay corrected table typical counter/delay offset measurements corrected table functional pin description added subsection difference in counter value for counter, delay , one-shot and frequency detect modes 10/20/2016 1.06 removed references to gpak families 10/11/2016 1.05 added temp sensor spec 10/10/2016 1.04 fixed typos updated vref electrical spec 9/27/2016 1.03 fixed typos updated figure 2-bit lut2 or pgen updated random read command diagram clarified pipe delay description added subsection vref load regulation 8/30/2016 1.02 reorgan ized and updated acmp electrical spec 8/22/2016 1.01 updated i 2 c serial command address space and write protection sections fixed typos and formatting updated section a nalog comparators added mstqfn package information reorganized subsections 3-bit lu t or 8- bit counter / delay mac rocells added subsection fsm timing diagrams added pgen timing diagram 7/14/2016 1.00 prod uction release SLG46533_ds_114 page 184 of 184 SLG46533 silego website & support silego technology website silego technology provides online support via our website at http://www.silego.com/ .this website is used as a means to make files and information easily available to customers. for more information regarding si lego green products, please vi sit our website. our green product lines feature: greenpak: programmable mixed signal matrix products greenfet1 / greenfet3 / hfet1: mos fet drivers and ultra-small, low rdson load switches greenclk1 / greenclk2 / greenclk 3: crystal replacement technolo gy products are also available for purchase directly from silego a t the silego on line store at http://www.silego.com /buy/ . silego technical support datasheets and errata, application notes and example designs, u ser guides, and hardware support documents and the latest software releases are available at the silego website or can be requested directly at info@silego.com . for specific greenpak design or applications questions and supp ort please send e-mail requests to greenpak@silego.com users of silego products can rec eive assistance through several channels: contact your local sales representative customers can contact their local sales representative or field application engineer (fae) for support. local sales offices ar e also available to help customers. more information regarding your lo cal representative is available at the silego website or send a request to info@silego.com contact silego directly silego can be contacted d irectly via e-mail at info@silego.com or user submission form, l ocated at the f ollowing url: http://support.silego.com/ other information the latest silego technology press releases, listing of seminar s and events, listings of world wide silego technology offices and representatives are all available at http://www.silego.com/ this product has been designed an d qualified for the consumer m arket. applications or uses as critical components in life support devices or systems are n ot authorized. silego technolog y does not assume any liability arising out of such applica- tions or uses of its products. silego technology reserves the r ight to improve product design , functions and reliability without notice . |
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