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| 2 1 - s3 - ck215/fk215 - 092002 user's manual s3ck215/fk215 calmrisc 8-bit cmos microcontroller revision 1
s3ck215/fk215 produ ct overview 1- 1 1 product overview overview the s3ck215/fk215 single-chip cmos microcontroller is designed for high performance using samsung's new 8-bit cpu core, calmrisc. calmrisc is an 8-bit low power risc microcontroller. its basic architecture follows harvard style, that is, it has separate program memory and data memory. both instruction and data can be fetched simultaneously without causing a stall, using separate paths for memory access. represented below is the top block diagram of the calmrisc microcontroller. product overview s 3ck215/fk215 1- 2 bbus[7:0] 20 program memory address generation unit pc[19:0] hardware stack hs[0] hs[15] 8 8 r0 r3 r1 r2 alu abus[7:0] alul alur pa[19:0] pd[15:0] idl0 idl1 sr0 sr1 ilh ilx ill spr idh do[7:0] di[7:0] gpr data memory address generation unit da[15:0] 20 flag rbus tbh tbl figure 1-1. top block diagram s3ck215/fk215 produ ct overview 1- 3 the calmrisc building blocks consist of: ? an 8-bit alu ? 16 general purpose registers (gpr) ? 11 special purpose registers (spr) ? 16-level hardware stack ? program memory address generation unit ? data memory address generation unit sixteen gprs are grouped into four banks (bank0 to bank3), and each bank has four 8-bit registers (r0, r1, r2, and r3). sprs, designed for special purposes, include status registers, link registers for branch-link instructions, and data memory index registers. the data memory address generation unit provides the data memory address (denoted as da[15:0] in the top block diagram) for a data memory access instruction. data memory contents are accessed through di[7:0] for read operations and do[7:0] for write operations. the program memory address generation unit contains a program counter, pc[19:0], and supplies the program memory address through pa[19:0] and fetches the corresponding instruction through pd[15:0] as the result of the program memory access. calmrisc has a 16-level hardware stack for low power stack operations as well as a temporary storage area. instruction fetch (if) instruction decode/ data memory access (id/mem) execution/writeback (exe/wb) figure 1-2. calmrisc pipeline diagram calmrisc has a 3-stage pipeline as described below: as can be seen in the pipeline scheme, calmrisc adopts a register-memory instruction set. in other words, data memory where r is a gpr can be one operand of an alu instruction as shown below: the first stage (or cycle) is the instruction fetch stage (if for short), where the instruction pointed by the program counter, pc[19:0] , is read into the instruction register (ir for short). the second stage is the instruction decode and data memory access stage (id/mem for short), where the fetched instruction (stored in ir) is decoded and data memory access is performed, if necessary. the final stage is the execute and write-back stage (exe/wb), where the required alu operation is executed and the result is written back into the destination registers. since calmrisc instructions are pipelined, the next instruction fetch is not postponed until the current instruction is completely finished but is performed immediately after completing the current instruction fetch. the pipeline stream of instructions is illustrated in the following diagram. product overview s 3ck215/fk215 1- 4 exe/wb if if if if if if if id/mem id/mem id/mem id/mem id/mem id/mem exe/wb exe/wb exe/wb exe/wb exe/wb / 1 / 2 / 3 / 4 / 6 / 5 figure 1-3. calmrisc pipeline stream diagram most calmrisc instructions are 1-word instructions, while same branch instructions such as long ?call? and ?jp? instructions are 2-word instructions. in figure 1-3, the instruction, i4 , is a long branch instruction, and it takes two clock cycles to fetch the instruction. as indicated in the pipeline stream, the number of clocks per instruction (cpi) is 1 except for long branches, which take 2 clock cycles per instruction. s3ck215/fk215 produ ct overview 1- 5 features cpu calmrisc core (8-bit risc architecture) memory rom: 8k-word (16k-byte) ram: 1024-byte (excluding lcd data ram) stack size: maximum 16 word-level 39 i/o pins 39 configurable i/o pins basic timer overflow signal makes a system reset watchdog function 16-bit timer/counter 0 programmable 16-bit timer interval, capture, pwm mode match/capture, overflow interrupt 16-bit timer/counter 1 programmable 16-bit timer match interrupt generator 8-bit timer/counter 2 programmable 8-bit timer interval, capture, pwm mode match/capture, overflow interrupt 8-bit timer/counter 3 programmable 8-bit timer match interrupt/carrier frequency generator watch timer real-time and interval time measurement clock generation for lcd four frequency outputs for buzzer sound (0.5/1/2/4 khz at 32.768 khz) lcd controller/driver 30 segments and 4 common terminals static, 1/2 duty, 1/3 duty, 1/4 duty voltage regulator and booster lcd display voltage supply capacitor/resistor bias selectable 3.0 v drive battery level detector programmable detection voltage (2.4 v, 3.0 v, 4.0 v) 8-bit serial i/o interface 8-bit transmit/receive mode 8-bit receive mode lsb-first/msb-first transmission selectable internal/external clock source a/d converter eight analog input channels 25 m s conversion speed at 8 mhz 10-bit conversion resolution operating voltage: 2.7 v to 5.5 v d/a converter one analog output channel 9-bit c onversion resolution (r-2r) operating voltage: 2.7 v to 5.5 v oscillation sources crystal, ceramic, rc for main clock crystal for sub clock main clock frequency 0.4?8 mhz sub clock frequency: 32.768 khz cpu clock divider circuit (divided by 1, 2, 4, 8, 16, 32, 64 or 128) product overview s 3ck215/fk215 1- 6 two power-down modes idle (only cpu clock stops) stop (system clock stops) interrupts 2 vectors, 13 interrupts instruction execution times 125 ns at 8 mhz (main clock) 30.5 m s at 32.768 khz (sub clock) operating temperature range - 25 c to 85 c operating voltage range 2.0 v to 5.5 v at 2 mhz (2mips) 2.4 v to 5.5 v at 4 mhz (4mips) 3.0 v to 5.5 v at 8 mhz (8mips) two amplifiers microphone and filter 8 8 multiplication signed by signed, unsigned by unsigned package type 80-pin qfp-1420 s3ck215/fk215 produ ct overview 1- 7 block diagram reset osc, reset lcd driver voltage detector cb ca v bldin p4.0-p4.7/ seg16-seg23 16-bit timer/ counter 0 10-bit a/d converter p0.0-p0.3/ int0-int3 i/o port 1 x in , xt in com0-com3 seg0-seg15 seg16-seg29/ p4.0-p5.5 16-bit timer/ counter 1 8-bit timer/ counter 2 8-bit timer/ counter 3 i/o port 0 i/o port 2 i/o port 3 9-bit d/a converter t0out/t0pwm/p1.0 t0clk/p1.1 t0cap/p1.2 t2out/t2pwm/p3.1 t2clk/p3.2 t2cap/p3.3 t3pwm/p3.0 p1.0-p1.7 av ref av ss p2.0-p2.7/ ad0-ad7 p3.0-p3.3 p3.4 (clkout) dao i/o port and interrupt control calm8 risc cpu 1024 byte register file 16-kbyte rom basic timer watch timer x out , xt out buz/p1.4 voltage booster serial i/o port i/o port 4 i/o port 5 8 8 multiplication two amplifiers v lc0 -v lc2 filin, micin, vref filout, micout p5.0-p5.5/ seg24-seg29 so/p1.5 sck/p1.6 si/p1.7 figure 1-4. block diagram product overview s 3ck215/fk215 1- 8 pin assignment seg24/p5.0 seg25/p5.1 seg26/p5.2 seg27/p5.3 seg28/p5.4 seg29/p5.5 p3.0/t3pwm p3.1/t2out/t2pwm p3.2/t2clk p3.3/t2cap p3.4/clkout v dd v ss x out x in test xt in xt out reset dao filin filout vref micin seg23/p4.7 seg22/p4.6 seg21/p4.5 seg20/p4.4 seg19/p4.3 seg18/p4.2 seg17/p4.1 seg16/p4.0 seg15 seg14 seg13 seg12 seg11 seg10 seg9 seg8 micout p0.0/int0 p0.1/int1 p0.2/int2 p0.3/int3 p1.0/t0out/t0pwm p1.1/t0clk p1.2/t0cap p1.3 p1.4/buz p1.5/so p1.6/sck p1.7/si p2.0/ad0 p2.1/ad1 p2.2/ad2 seg7 seg6 seg5 seg4 seg3 seg2 seg1 seg0 com3 com2 com1 com0 v lc2 v lc1 v lc0 ca cb av ss av ref p2.7/ad7/v bldin p2.6/ad6 p2.5/ad5 p2.4/ad4 p2.3/ad3 s3ck215/S3FK215 (80-qfp) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 figure 1-5. pin assignment (80-qfp) s3ck215/fk215 produ ct overview 1- 9 pin descriptions table 1-1. pin descriptions pin names pin type pin description circuit type pin numbers share pins p0.0 p0.1 p0.2 p0.3 i/o i/o port with bit programmable pins; schmitt trigger input or output mode selected by software; software assignable pull-up resistors. (with noise filter and interrupt control). d-4 26 27 28 29 int0 int1 int2 int3 p1.0 p1.1 p1.2 p1.3 p1.4 p1.5 p1.6 p1.7 i/o i/o port with bit programmable pins; schmitt trigger input or output mode selected by software; open-drain output mode can be selected by software; software assignable pull-up resistors. e-4 30 31 32 33 34 35 36 37 t0out/t0pwm t0clk t0cap - buz so sck si p2.0-p2.6 p2.7 i/o i/o port with bit programmable pins; normal input or output mode selected by software; software assignable pull-up resistors. f-10 f-18 38-44 45 ad0-ad6 v bldin /ad7 p3.0 p3.1 p3.2 p3.3 p3.4 i/o i/o port with bit programmable pins; schmitt trigger input or push-pull output with software assignable pull-up resistors. d-3 7-11 t3pwm t2out/t2pwm t2clk t2cap clkout p4.0-p4.7 i/o i/o port with bit programmable pins; push-pull or open-drain output and input with software assignable pull-up resistors. h-14 73-80 seg16-seg23 p5.0-p5.5 i/o have the same characteristic as port 4. h-14 1-6 seg24-seg29 ad0-ad6 ad7 i/o a/d converter analog input channels f-10 f-18 38-44 45 p2.0-p2.6 p2.7/v bldin av ref ? a/d converter reference voltage ? 46 ? av ss ? a/d converter ground ? 47 ? int0-int3 i/o external interrupt input pins d-4 26-29 p0.0-p0.3 reset i system reset pin b 19 ? test i test signal input (must be connected to v ss ) ? 16 ? product overview s 3ck215/fk215 1- 10 table 1-1. pin descriptions (continued) pin names pin type pin description circuit type pin numbers share pins v dd , v ss ? main power supply and ground ? 12,13 ? x out , x in ? main oscillator pins ? 14,15 ? so, sck, si i/o serial i/o interface clock signal e-4 35-37 p1.5-p1.7 v bldin i/o voltage detector reference voltage input f-18 45 p2.7/ad7 t3pwm i/o timer 3 pwm output d-3 7 p3.0 t2out/t2pwm i/o timer 2 output and pwm output d-3 8 p3.1 t2clk i/o timer 2 external clock input d-3 9 p3.2 t2cap i/o timer 2 capture input d-3 10 p3.3 t0out/t0pwm i/o timer 0 output and pwm output e-4 30 p1.0 t0clk i/o timer 0 external clock input e-4 31 p1.1 t0cap i/o timer 0 capture input e-4 32 p1.2 com0-com3 o lcd common signal output h 53-56 ? seg0-seg15 o lcd segment output h 57-72 ? seg16-seg23 i/o lcd segment output h-14 73-80 p4.0-p4.7 seg24-seg29 i/o lcd segment output h-14 1-6 p5.0-p5.5 v lc0 -v lc2 o lcd power supply ? 50-52 ? buz i/o 0.5,1,2 or 4 khz frequency output for buzzer sound with 4.19 mhz main system clock or 32768 hz subsystem clock e-4 34 p1.4 ca, cb ? capacitor terminal for voltage booster ? 48, 49 ? clkout i/o main oscillator clock output d-3 11 p3.4 dao ? da converter output ? 20 ? filin, filout ? filter amp input and output ? 21,22 ? micin, micout ? mic amp input and output ? 24,25 ? vref ? reference voltage input for filter amp and mic amp ? 23 ? s3ck215/fk215 produ ct overview 1- 11 pin circuits in v dd figure 1-6. pin circuit type b ( reset reset ) i/o output disable data circuit type c pull-up enable v dd p-channel figure 1-7. pin circuit type d-3 (p3) p-ch n-ch v dd out output disable data figure 1-8. pin circuit type c i/o output disable data circuit type c pull-up enable v dd noise filter ext. int input normal figure 1-9. pin circuit type d-4 (p0) product overview s 3ck215/fk215 1- 12 v dd output disable data pull-up resistor v dd i/o p-ch n-ch open drain enable figure 1-10. pin circuit type e-4 (p1) i/o output disable data circuit type c pull-up enable v dd adc enable to adc data figure 1-11. pin circuit type f-10 (p2.0-p2.6) i/o output disable data circuit type c pull-up enable v dd adc&vld enable to adc data v bldin figure 1-12. pin circuit type f-18 (p2.7/v bldin ) out v l c1 seg/ com v lc0 v lc2 figure 1-13. pin circuit type h (seg/com) s3ck215/fk215 produ ct overview 1- 13 out seg v lc2 v lc1 v lc0 output disable figure 1-14. pin circuit type h-4 v dd output disable data pull-up enable v dd i/o p-ch n-ch open drain enable circuit type h-14 seg lcd out enable figure 1-15. pin circuit type h-14 (p4, p5) product overview s 3ck215/fk215 1- 14 notes s3ck215/fk215 addre ss spaces 2- 1 2 address spaces overview calmrisc has 20-bit program address lines, pa[19:0] , which supports up to 1m words of program memory. the 1m word program memory space is divided into 256 pages and each page is 4k word long as shown in the next page. the upper 8 bits of the program counter, pc[19:12], points to a specific page and the lower 12 bits, pc[11:0], specify the offset address of the page. calmrisc also has 16-bit data memory address lines, da[15:0], which supports up to 64k bytes of data memory. the 64k byte data memory space is divided into 256 pages and each page has 256 bytes. the upper 8 bits of the data address, da[15:8], points to a specific page and the lower 8 bits, da[7:0], specify the offset address of the page. program memory (rom) 000h fffh 256 page 1 mword 4 kword fffh 000h figure 2-1. program memory organization address spaces s3c k215/fk215 2- 2 for example, if pc[19:0] = 5f79ah, the page index pointed to by pc is 5fh and the offset in the page is 79ah. if the current pc[19:0] = 5efffh and the instruction pointed to by the current pc, i.e., the instruction at the address 5efffh is not a branch instruction, the next pc becomes 5e000h, not 5f000h. in other words, the instruction sequence wraps around at the page boundary, unless the instruction at the boundary (in the above example, at 5efffh) is a long branch instruction. the only way to change the program page is by long branches (lcall, llnk, and ljp), where the absolute branch target address is specified. for example, if the current pc[19:0] = 047ach (the page index is 04h and the offset is 7ach) and the instruction pointed to by the current pc, i.e., the instruction at the address 047ach, is "ljp a507fh" (jump to the program address a507fh), then the next pc[19:0] = a507fh, which means that the page and the offset are changed to a5h and 07fh, respectively. on the other hand, the short branch instructions cannot change the page indices. suppose the current pc is 6fffeh and its instruction is "jr 5h" (jump to the program address pc + 5h). then the next instruction address is 6f003h, not 70003h. in other words, the branch target address calculation also wraps around with respect to a page boundary. this situation is illustrated below: 000h 001h 002h 003h 004h 005h ffeh fffh page 6fh jr 5h figure 2-2. relative jump around page boundary programmers do not have to manually calculate the offset and insert extra instructions for a jump instruction across page boundaries. the compiler and the assembler for calmrisc are in charge of producing appropriate codes for it. s3ck215/fk215 addre ss spaces 2- 3 00000h fffffh vector and option area ~ ~ ~ ~ 00020h 0001fh program memory area (4k words x 256 page = 1 mword) 8k words (16k bytes) note: for s3ck215, total size of program memory area is 8k words (16k bytes). 1fffh figure 2-3. program memory layout from 00000h to 00004h addresses are used for the vector address of exceptions, and 0001eh, 0001fh are used for the option only. aside from these addresses others are reserved in the vector and option area. program memory area from the address 00020h to fffffh can be used for normal programs. the program memory size of s3ck215 is 8k word (16k byte), so from the address 00020h to 1fffh are the program memory area. address spaces s3c k215/fk215 2- 4 rom code option (rcod_opt) just after power on, the rom data located at 0001eh and 0001fh is used as the rom code option. s3ck215 has rom code options like the reset value of basic timer and watchdog timer enable. for example, if you program as below: rcod_opt 1eh, 0x0000 rcod_opt 1fh, 0xbfff ? fxx/32 is used as reset value of basic timer (by bit.14, 13, 12) ? watchdog timer is enabled (by bit.11) if you don't program any values in these option areas, then the default value is "1". in these cases, the address 0001eh would be the value of "ffffh". s3ck215/fk215 addre ss spaces 2- 5 rom_code option (rcod_opt) rom address: 0001fh reset value of basic timer clock selection bits (wdtcon.6, .5, .4): 000 = fxx/2 001 = fxx/4 010 = fxx/16 011 = fxx/32 100 = fxx/128 101 = fxx/256 110 = fxx/1024 111 = fxx/2048 not used watchdog timer enable selection bit: 0 = disable wdt 1 = enable wdt .7 .6 .5 .4 .3 .2 .1 .0 msb lsb not used .7 .6 .5 .4 .3 .2 .1 .0 msb lsb not used .15 .14 .13 .12 .11 .10 .9 .8 msb lsb rom address: 0001eh .15 .14 .13 .12 .11 .10 .9 .8 msb lsb not used not used figure 2-4. rom code option (rcod_opt) address spaces s3c k215/fk215 2- 6 data memory organization the total data memory address space is 64k bytes, addressed by da[15:0], and divided into 256 pages, each page consists of 256 bytes as shown below. 00h ffh 256 page 64k bytes 00h fffh 256 byte ffh 00h ffh 4 page figure 2-5. data memory map the data memory page is indexed by spr and idh. in data memory index addressing mode, 16-bit data memory address is composed of two 8-bit sprs, idh[7:0] and idl0[7:0] (or idh[7:0] and idl1[7:0]). idh[7:0] points to a page index, and idl0[7:0] (or idl1[7:0]) represents the page offset. in data memory direct addressing mode, an 8-bit direct address, adr[7:0], specifies the offset of the page pointed to by idh[7:0] (see the details for direct addressing mode in the instruction sections). unlike the program memory organization, data memory address does not wrap around. in other words, data memory index addressing with modification performs an addition or a subtraction operation on the whole 16-bit address of idh[7:0] and idl0[7:0] (or idl1[7:0]) and updates idh[7:0] and idl0[7:0] (or idl1[7:0]) accordingly. suppose idh[7:0] is 0fh and idl0[7:0] is fch and the modification on the index registers, idh[7:0] and idl0[7:0], is increment by 5h, then, after the modification (i.e., 0ffch + 5 = 1001h), idh[7:0] and idl0[7:0] become 10h and 01h, respectively. s3ck215/fk215 addre ss spaces 2- 7 the s3ck215 has 1024 bytes of data register address from 0080h to 047fh. the area from 0000h to 007fh is for peripheral control, and lcd ram area is from 0480h to 008eh. data memory control register page 0 7fh 80h 80h ffh in byte 7fh 00h lcd ram 8 bits 8eh page 4 page1 page 2 page 3 00h figure 2-6. data memory map address spaces s3c k215/fk215 2- 8 notes s3ck215/fk215 regis ters 3- 1 3 registers overview the registers of calmrisc are grouped into 2 parts: general purpose registers and special purpose registers. table 3-1. general and special purpose registers registers mnemonics description reset value general purpose r0 general register 0 unknown registers (gpr) r1 general register 1 unknown r2 general register 2 unknown r3 general register 3 unknown special purpose group 0 (spr0) idl0 lower byte of index register 0 unknown registers (spr) idl1 lower byte of index register 1 unknown idh higher byte of index register unknown sr0 status register 0 00h group 1 (spr1) ilx instruction pointer link register for extended byte unknown ilh instruction pointer link register for higher byte unknown ill instruction pointer link register for lower byte unknown sr1 status register 1 unknown gpr ' s can be used in most instructions such as alu instructions, stack instructions, load instructions, etc (see the instruction set sections). from the programming standpoint, they have almost no restriction whatsoever. calmrisc has 4 banks of gpr ' s and each bank has 4 registers, r0, r1, r2, and r3. hence, 16 gpr ' s in total are available. the gpr bank switching can be done by setting an appropriate value in sr0[4:3] (see sr0 for details). the alu operations between gpr ' s from different banks are not allowed. spr ' s are designed for their own dedicated purposes. they have some restrictions in terms of instructions that can access them. for example, direct alu operations cannot be performed on spr ' s. however, data transfers between a gpr and an spr are allowed and stack operations with spr ' s are also possible (see the instruction sections for details). registers s3ck215/ fk215 3- 2 index registers: idh, idl0 and idl1 idh in concatenation with idl0 (or idl1) forms a 16-bit data memory address. note that calmrisc ' s data memory address space is 64 k byte (addressable by 16-bit addresses). basically, idh points to a page index and idl0 (or idl1) corresponds to an offset of the page. like gpr ' s, the index registers are 2-way banked. there are 2 banks in total, each of which has its own index registers, idh, idl0 and idl1. the banks of index registers can be switched by setting an appropriate value in sr0[2] (see sr0 for details). normally, programmers can reserve an index register pair, idh and idl0 (or idl1), for software stack operations. link registers: ilx, ilh and ill the link registers are specially designed for link-and-branch instructions (see lnk and lret instructions in the instruction sections for details). when an lnk instruction is executed, the current pc[19:0] is saved into ilx, ilh and ill registers, i.e., pc[19:16] into ilx[3:0], pc[15:8] into ilh [7:0], and pc[7:0] into ill[7:0], respectively. when an lret instruction is executed, the return pc value is recovered from ilx, ilh, and ill, i.e., ilx[3:0] into pc[19:16], ilh[7:0] into pc[15:8] and ill[7:0] into pc[7:0], respectively. these registers are used to access program memory by ldc/ldc+ instructions. when an ldc or ldc+ instruction is executed, the (code) data residing at the program address specified by ilx:ilh:ill will be read into tbh:tbl. ldc+ also increments ill after accessing the program memory. there is a special core input pin signal, np64kw , which is reserved for indicating that the program memory address space is only 64 k word. by grounding the signal pin to zero, the upper 4 bits of pc, pc[19:16], is deactivated and therefore the upper 4 bits, pa[19:16], of the program memory address signals from calmrisc core are also deactivated. by doing so, power consumption due to manipulating the upper 4 bits of pc can be totally eliminated (see the core pin description section for details). from the programmer ? s standpoint, when np64kw is tied to the ground level, then pc[19:16] is not saved into ilx for lnk instructions and ilx is not read back into pc[19:16] for lret instructions. therefore, ilx is totally unused in lnk and lret instructions when np64kw = 0. s3ck215/fk215 registers 3- 3 status register 0: sr0 sr0 is mainly reserved for system control functions and each bit of sr0 has its own dedicated function. table 3-2. status register 0 configuration flag name bit description eid 0 data memory page selection in direct addressing ie 1 global interrupt enable idb 2 index register banking selection grb[1:0] 4,3 gpr bank selection exe 5 stack overflow/underflow exception enable ie0 6 interrupt 0 enable ie1 7 interrupt 1 enable sr0[0] (or eid) selects which page index is used in direct addressing. if eid = 0, then page 0 (page index = 0) is used. otherwise ( eid = 1), idh of the current index register bank is used for page index. sr0[1] (or ie) is the global interrupt enable flag. as explained in the interrupt/exception section, calmrisc has 3 interrupt sources (non- maskable interrupt, interrupt 0, and interrupt 1) and 1 stack exception. both interrupt 0 and interrupt 1 are masked by setting sr0[1] to 0 (i.e., ie = 0). when an interrupt is serviced, the global interrupt enable flag ie is automatically cleared. the execution of an iret instruction (return from an interrupt service routine) automatically sets ie = 1. sr0[2] (or idb) and sr0[4:3] (or grb[1:0]) selects an appropriate bank for index registers and gpr's, respectively as shown below: r3 r0 r2 r1 r3 r0 r2 r1 r3 r0 r2 r1 r3 r0 r2 r1 idh idl0 idl1 idh idl0 idl1 bank 0 bank 1 bank 2 bank 3 11 10 01 00 grb [1:0] 0 1 idb figure 3-1. bank selection by setting of grb bits and idb bit sr0[5] (or exe) enables the stack exception, that is, the stack overflow/underflow exception. if exe = 0, the stack exception is disabled. the stack exception can be used for program debugging in the software development stage. sr0[6] (or ie0) and sr0[7] (or ie1) are enabled, by setting them to 1. even though ie0 or ie1 are enabled, the interrupts are ignored (not serviced) if the global interrupt enable flag ie is set to 0. registers s3ck215/ fk215 3- 4 status register 1: sr1 sr1 is the register for status flags such as alu execution flag and stack full flag. table 3-3. status register 1: sr1 flag name bit description c 0 carry flag v 1 overflow flag z 2 zero flag n 3 negative flag sf 4 stack full flag ? 5,6,7 reserved sr1[0] (or c) is the carry flag of alu executions. sr1[1] (or v) is the overflow flag of alu executions. it is set to 1 if and only if the carry-in into the 8-th bit position of addition/subtraction differs from the carry-out from the 8-th bit position. sr1[2] (or z) is the zero flag, which is set to 1 if and only if the alu result is zero. sr1[3] (or n) is the negative flag. basically, the most significant bit (msb) of alu results becomes n flag. note a load instruction into a gpr is considered an alu instruction. however, if an alu instruction touches the overflow flag (v) like add, sub, cp, etc , n flag is updated as exclusive-or of v and the msb of the alu result. this implies that even if an alu operation results in overflow, n flag is still valid. sr1[4] (or sf) is the stack overflow flag. it is set when the hardware stack is overflowed or under flowed. programmers can check if the hardware stack has any abnormalities by the stack exception or testing if sf is set (see the hardware stack section for great details). note when an interrupt occurs, sr0 and sr1 are not saved by hardware, so sr0, and sr1 register values must be saved by software. s3ck215/fk215 memor y map 4- 1 4 memory map overview to support the control of peripheral hardware, the address for peripheral control registers are memory-mapped to page 0 of the ram. memory mapping lets you use a mnemonic as the operand of an instruction in place of the specific memory location. in this section, detailed descriptions of the control registers are presented in an easy-to-read format. you can use this section as a quick-reference source when writing application programs. this memory area can be accessed with the whole method of data memory access. ? if sr0 bit 0 is "0" then the accessed register area is always page 0. ? if sr0 bit 0 is "1" then the accessed register page is controlled by the proper idh register's value. so if you want to access the memory map area, clear the sr0.0 and use the direct addressing mode. this method is used for most cases. this control register is divided into five areas. here, the system control register area is same in every device. 7fh 00h control register system control register area port data register area peripheral control register (4 x 8) peripheral control register ( 1x 16 or 2 x 8) 0fh 10h port control register area (4 x 8) 1fh 20h 3fh 40h 6fh 70h standard exhortative area standard area figure 4-1. memory map area memory map s3ck215 /fk215 4- 2 table 4-1. registers register name mnemonic decimal hex reset r/w locations 16h-1fh are not mapped port 5 data register p5 21 15h 00h r/w port 4 data register p4 20 14h 00h r/w port 3 data register p3 19 13h 00h r/w port 2 data register p2 18 12h 00h r/w port 1 data register p1 17 11h 00h r/w port 0 data register p0 16 10h 00h r/w locations 0eh-0fh are not mapped. watchdog timer control register wdtcon 13 0dh x0h r/w basic timer counter btcnt 12 0ch 00h r interrupt id register 1 iir1 11 0bh ? r/w interrupt priority register 1 ipr1 10 0ah ? r/w interrupt mask register 1 imr1 9 09h 00h r/w interrupt request register 1 irq1 8 08h ? r interrupt id register 0 iir0 7 07h ? r/w interrupt priority register 0 ipr0 6 06h ? r/w interrupt mask register 0 imr0 5 05h 00h r/w interrupt request register 0 irq0 4 04h ? r oscillator control register osccon 3 03h 00h r/w power control register pcon 2 02h 04h r/w locations 00h-01h are not mapped. notes: 1. '?' means undefined. 2. if you want to clear the bit of irqx, then write the number that you want to clear to iirx. for example, when clear irq0.4 then ld rx, #04h and ld iir0, rx. s3ck215/fk215 memor y map 4- 3 table 4-1. registers (continued) register name mnemonic decimal hex reset r/w timer 2 counter t2cnt 82 52h ? r timer 2 data register t2data 81 51h ffh r/w timer 2 control register t2con 80 50h 00h r/w locations 4dh-4fh are not mapped timer 1 counter (low byte) t1cntl 76 4ch ? r timer 1 counter (high byte) t1cnth 75 4bh ? r timer 1 data register (low byte) t1datal 74 4ah ffh r/w timer 1 data register (high byte) t1datah 73 49h ffh r/w timer 1 count register t1con 72 48h 00h r/w locations 45h-47h are not mapped timer 0 counter (low byte) t0cntl 68 44h ? r timer 0 counter (high byte) t0cnth 67 43h ? r timer 0 data register (low byte) t0datal 66 42h ffh r/w timer 0 data register (high byte) t0datah 65 41h ffh r/w timer 0 count register t0con 64 40h 00h r/w location 36h-3fh are not mapped port 5 control register (low byte) p5conl 53 35h 00h r/w port 5 control register (high byte) p5conh 52 34h 00h r/w location 32h-33h are not mapped port 4 control register (low byte) p4conl 49 31h 00h r/w port 4 control register (high byte) p4conh 48 30h 00h r/w locations 2eh-2fh are not mapped port 3 control register (low byte) p3conl 45 2dh 00h r/w port 3 control register (high byte) p3conh 44 2ch 00h r/w locations 2ah-2bh are not mapped port 2 control register (low byte) p2conl 41 29h 00h r/w port 2 control register (high byte) p2conh 40 28h 00h r/w locations 24h-27h are not mapped port 1 pull-up register p1pur 35 23h 00h r/w port 1 control register (low byte) p1conl 34 22h 00h r/w port 1 control register (high byte) p1conh 33 21h 00h r/w port 0 control register p0con 32 20h 00h r/w memory map s3ck215 /fk215 4- 4 table 4-1. registers (continued) register name mnemonic decimal hex reset r/w locations 7dh-7fh are not mapped multiplication result (low byte) mrl 124 7ch 00h r multiplication result (high byte) mrh 123 7bh 00h r multiplier y input register myinp 122 7ah 00h r/w multiplier x input register mxinp 121 79h 00h r/w multiplier control register mulcon 120 78h 00h r/w op amp control register opcon 119 77h 00h r/w d/a converter data register (low byte) dadatal 118 76h 00h r/w d/a converter data register (high byte) dadatah 117 75h 00h r/w d/a converter control register dacon 116 74h 00h r/w locations 73h is not mapped main system clock output control register clocon 114 72h 00h r/w battery level detector register bldcon 113 71h 00h r/w watch timer control register wtcon 112 70h 00h r/w location 62h-6fh are not mapped lcd mode register lmod 97 61h 00h r/w lcd control register lcon 96 60h 00h r/w location 5fh is not mapped a/d converter data register (low byte) addatal 94 5eh ? r a/d converter data register (high byte) addatah 93 5dh ? r a/d converter control register adcon 92 5ch 00h r/w locations 5bh is not mapped serial i/o data register siodata 90 5ah 00h r/w serial i/o pre-scale register siops 89 59h 00h r/w serial i/o control register siocon 88 58h 00h r/w timer 3 counter t3cnt 87 57h ? r timer 3 data register (low byte) t3datal 86 56h ffh r/w timer 3 data register (high byte) t3datah 85 55h ffh r/w timer 3 control register t3con 84 54h 00h r/w locations 53h is not mapped s3ck215/fk215 hardw are stack 5- 1 5 hardware stack overview the hardware stack in calmrisc has two usages: ? to save and restore the return pc[19:0] on lcall, calls, ret, and iret instructions. ? temporary storage space for registers on push and pop instructions. when pc[19:0] is saved into or restored from the hardware stack, the access should be 20 bits wide. on the other hand, when a register is pushed into or popped from the hardware stack, the access should be 8 bits wide. hence, to maximize the efficiency of the stack usage, the hardware stack is divided into 3 parts: the extended stack bank (xstack, 4-bits wide), the odd bank (8-bits wide), and the even bank (8-bits wide). 3 0 7 0 7 0 level 0 level 1 level 2 level 14 level 15 xstack odd bank even bank hardware stack 0 1 5 stack pointer sptr [5:0] odd or even bank selector stack level pointer figure 5-1. hardware stack hardware stack s3ck 215/fk215 5- 2 the top of the stack (tos) is pointed to by a stack pointer, called sptr[5:0] . the upper 5 bits of the stack pointer, sptr[5:1], points to the stack level into which either pc[19:0] or a register is saved. for example, if sptr[5:1] is 5h or tos is 5, then level 5 of xstack is empty and either level 5 of the odd bank or level 5 of the even bank is empty. in fact, sptr[0], the stack bank selection bit, indicates which bank(s) is empty. if sptr[0] = 0, both level 5 of the even and the odd banks are empty. on the other hand, if sptr[0] = 1, level 5 of the odd bank is empty, but level 5 of the even bank is occupied. this situation is well illustrated in the figure below. level 0 level 1 level 2 level 15 xstack odd bank even bank 0 1 5 sptr [5:0] bank selector stack level pointer level 3 level 4 level 5 0 0 1 1 0 0 level 0 level 1 level 2 level 15 xstack odd bank even bank 0 1 5 sptr [5:0] bank selector stack level pointer level 3 level 4 level 5 0 0 1 1 1 0 figure 5-2. even and odd bank selection example as can be seen in the above example, sptr[5:1] is used as the hardware stack pointer when pc[19:0] is pushed or popped and sptr[5:0] as the hardware stack pointer when a register is pushed or popped. note that xstack is used only for storing and retrieving pc[19:16]. let us consider the cases where pc[19:0] is pushed into the hardware stack (by executing lcall/calls instructions or by interrupts/exceptions being served) or is retrieved from the hardware stack (by executing ret/iret instructions). regardless of the stack bank selection bit ( sptr[0]), tos of the even bank and the odd bank store or return pc[7:0] or pc[15:8], respectively. this is illustrated in the following figures. s3ck215/fk215 hardw are stack 5- 3 level 0 level 15 xstack odd bank even bank 1 5 sptr [5:0] bank selector level 5 0 0 1 1 0 0 level 6 0 level 0 level 15 xstack odd bank even bank 1 5 sptr [5:0] bank selector stack level pointer level 5 0 1 1 0 0 0 level 6 0 pc[7:0] stack level pointer level 0 level 15 xstack odd bank even bank 1 5 sptr [5:0] bank selector level 5 1 0 1 1 0 0 level 6 0 level 0 level 15 xstack odd bank even bank 1 5 sptr [5:0] bank selector level 5 1 1 1 0 0 0 level 6 0 by executing ret, iret by executing call, calls or interrupts/exceptions stack level pointer stack level pointer pc[19:16] pc[15:8] pc[15:8] pc[19:16] pc[7:0] by executing ret, iret by executing call, calls or interrupts/exceptions figure 5-3. stack operation with pc [19:0] as can be seen in the figures, when stack operations with pc[19:0] are performed, the stack level pointer sptr[5:1] ( not sptr[5:0]) is either incremented by 1 (when pc[19:0] is pushed into the stack) or decremented by 1 (when pc[19:0] is popped from the stack). the stack bank selection bit ( sptr[0]) is unchanged. if a calmrisc core input signal np64kw is 0, which signifies that only pc[15:0] is meaningful, then any access to xstack is totally deactivated from the stack operations with pc. therefore, xstack has no meaning when the input pin signal, np64kw , is tied to 0. in that case, xstack doesn ? t have to even exist. as a matter of fact, xstack is not included in calmrisc core itself and it is interfaced through some specially reserved core pin signals ( npush, nstack , xhsi[3:0] , xsho[3:0] ), if the program address space is more than 64 k words (see the core pin signal section for details). with regards to stack operations with registers, a similar argument can be made. the only difference is that the data written into or read from the stack are a byte. hence, the even bank and the odd bank are accessed alternately as shown below. hardware stack s3ck 215/fk215 5- 4 level 0 level 15 xstack odd bank even bank 1 5 sptr [5:0] bank selector level 5 0 0 1 1 0 0 level 6 0 level 0 level 15 xstack odd bank even bank 1 5 sptr [5:0] bank selector stack level pointer level 5 1 0 1 1 0 0 level 6 0 register stack level pointer level 0 level 15 xstack odd bank even bank 1 5 sptr [5:0] bank selector level 5 1 0 1 1 0 0 level 6 0 level 0 level 15 xstack odd bank even bank 1 5 sptr [5:0] bank selector level 5 0 1 1 0 0 0 level 6 0 register pop register push register stack level pointer stack level pointer pop register push register figure 5-4. stack operation with registers when the bank selection bit ( sptr[0]) is 0, then the register is pushed into the even bank and the bank selection bit is set to 1. in this case, the stack level pointer is unchanged. when the bank selection bit ( sptr[0]) is 1, then the register is pushed into the odd bank, the bank selection bit is set to 0, and the stack level pointer is incremented by 1. unlike the push operations of pc[19:0], any data are not written into xstack in the register push operations. this is illustrated in the example figures. when a register is pushed into the stack, sptr[5:0] is incremented by 1 ( not the stack level pointer sptr[5:1]). the register pop operations are the reverse processes of the register push operations. when a register is popped out of the stack, sptr[5:0] is decremented by 1 ( not the stack level pointer sptr[5:1]). hardware stack overflow/underflow happens when the msb of the stack level pointer, sptr[5], is 1. this is obvious from the fact that the hardware stack has only 16 levels and the following relationship holds for the stack level pointer in a normal case. suppose the stack level pointer sptr[5:1] = 15 (or 01111b in binary format) and the bank selection bit sptr[0] = 1. here if either pc[19:0] or a register is pushed, the stack level pointer is incremented by 1. therefore, sptr[5:1] = 16 (or 10000b in binary format) and sptr[5] = 1, which implies that the stack is overflowed. the situation is depicted in the following. s3ck215/fk215 hardw are stack 5- 5 level 0 level 15 xstack odd bank even bank push register 1 1 1 1 1 0 1 5 sptr [5:0] 0 level 1 level 14 level 0 level 15 xstack odd bank even bank 0 0 0 0 0 1 1 5 sptr [5:0] 0 level 1 level 14 level 0 level 15 1 0 0 0 0 1 1 5 sptr [5:0] 0 level 1 level 14 xstack odd bank even bank push pc [19:0] register pc[19:16] pc[15:8] pc[7:0] figure 5-5. stack overflow hardware stack s3ck 215/fk215 5- 6 the first overflow happens due to a register push operation. as explained earlier, a register push operation increments sptr[5:0] (not sptr[5:1]) , which results in sptr[5] = 1, sptr[4:1] = 0 and sptr[0] = 0. as indicated by sptr[5] = 1, an overflow happens. note that this overflow doesn ? t overwrite any data in the stack. on the other hand, when pc[19:0] is pushed, sptr[5:1] is incremented by 1 instead of sptr[5:0], and as expected, an overflow results. unlike the first overflow, pc[7:0] is pushed into level 0 of the even bank and the data that has been there before the push operation is overwritten . a similar argument can be made about stack underflows. note that any stack operation, which causes the stack to overflow or underflow, doesn ? t necessarily mean that any data in the stack are lost, as is observed in the first example. in sr1, there is a status flag, sf (stack full flag), which is exactly the same as sptr[5]. in other words, the value of sptr[5] can be checked by reading sf (or sr1[4]). sf is not a sticky flag in the sense that if there was a stack overflow/underflow but any following stack access instructions clear sptr[5] to 0, then sf = 0 and programmers cannot tell whether there was a stack overflow/underflow by reading sf. for example, if a program pushes a register 64 times in a row, sptr[5:0] is exactly the same as sptr[5:0] before the push sequence. therefore, special attention should be paid. another mechanism to detect a stack overflow/underflow is through a stack exception. a stack exception happens only when the execution of any stack access instruction results in sf = 1 (or sptr[5] = 1). suppose a register push operation makes sf = 1 (the sf value before the push operation doesn ? t matter). then the stack exception due to the push operation is immediately generated and served if the stack exception enable flag (exe of sr0) is 1. if the stack exception enable flag is 0, then the generated interrupt is not served but pending. sometime later when the stack exception enable flag is set to 1, the pending exception request is served even if sf = 0. more details are available in the stack exception section. s3ck215/fk215 excep tions 6- 1 6 exceptions overview exceptions in calmrisc are listed in the table below. exception handling routines, residing at the given addresses in the table, are invoked when the corresponding exception occurs. the start address of each exception routine is specified by concatenation 0h (leading 4 bits of 0) and the 16-bit data in the exception vector listed in the table. for example, the interrupt service routine for irq[0] starts from 0h:pm[00002h]. note that ":"means concatenation and pm[*] stands for the 16-bit content at the address * of the program memory. aside from the exception due to reset release, the current pc is pushed in the stack on an exception. when an exception is executed due to irq[1:0]/iexp, the global interrupt enable flag, ie bit (sr0[1]), is set to 0, whereas ie is set to 1 when iret or an instruction that explicitly sets ie is executed. table 6-1. exceptions name address priority description reset 00000h 1st exception due to reset release. ? 00001h ? reserved irq[0] 00002h 3rd exception due to nirq[0] signal. maskable by setting ie/ie0. irq[1] 00003h 4th exception due to nirq[1] signal. maskable by setting ie/ie1. iexp 00004h 2nd exception due to stack full. maskable by setting exe. ? 00005h ? reserved. ? 00006h ? reserved. ? 00007h ? reserved. note: break mode due to bkreq has a higher priority than all the exceptions above. that is, when bkreq is active, even the exception due to reset release is not executed. hardware reset when hardware reset is active (the reset input signal pin nres = 0), the control pins in the calmrisc core are initialized to be disabled, and sr0 and sptr (the hardware stack pointer) are initialized to be 0. additionally, the interrupt sensing block is cleared. when hardware reset is released ( nres = 1), the reset exception is executed by loading the jp instruction in ir (instruction register) and 0h:0000h in pc. therefore, when hardware reset is released, the "jp {0h:pm[00000h]}" instruction is executed. exceptions s3ck215 /fk215 6- 2 irq[0] exception when a core input signal nirq[0] is low, sr0[6] (ie0) is high, and sr0[1] ( ie) is high, irq[0] exception is generated, and this will load the call instruction in ir (instruction register) and 0h:0002h in pc. therefore, on an irq[0] exception, the "call {0h:pm[00002h]}" instruction is executed. when the irq[0] exception is executed, sr0[1] ( ie) is set to 0. irq[1] exception (level-sensitive) when a core input signal nirq[1] is low, sr0[7] (ie1) is high, and sr0[1] ( ie) is high, irq[1] exception is generated, and this will load the call instruction in ir (instruction register) and 0h:0003h in pc. therefore, on an irq[1] exception, the "call {0h:pm[00003h]}" instruction is executed. when the irq[1] exception is executed, sr0[1] ( ie) is set to 0. hardware stack full exception a stack full exception occurs when a stack operation is performed and as a result of the stack operation sptr[5] (sf) is set to 1. if the stack exception enable bit, exe (sr0[5]), is 1, the stack full exception is served. one exception to this rule is when nnmi causes a stack operation that sets sptr[5] (sf), since it has higher priority. handling a stack full exception may cause another stack full exception. in this case, the new exception is ignored. on a stack full exception, the call instruction is loaded in ir (instruction register) and 0h:0004h in pc. therefore, when the stack full exception is activated, the "call {0h:pm[00004h]}" instruction is executed. when the exception is executed, sr0[1] ( ie) is set to 0. break exception break exception is reserved only for an in-circuit debugger. when a core input signal, bkreq , is high, the calmrisc core is halted or in the break mode, until bkreq is deactivated. another way to drive the calmrisc core into the break mode is by executing a break instruction, break. when break is fetched, it is decoded in the fetch cycle (if stage) and the calmrisc core output signal nbkack is generated in the second cycle (id/mem stage). an in-circuit debugger generates bkreq active by monitoring nbkack to be active. break instruction is exactly the same as the nop (no operation) instruction except that it does not increase the program counter and activates nbkack in the second cycle (or id/mem stage of the pipeline). there, once break is encountered in the program execution, it falls into a deadlock. break instruction is reserved for in-circuit debuggers only, so it should not be used in user programs. s3ck215/fk215 excep tions 6- 3 exceptions ( or interrupts) timer 0 match/capture timer 0 overflow int 3 timer 2 overflow timer 3 match sio int ivec0 00002h ivec1 00003h watch timer int 0 int 1 int 2 stack full int 00004h sf_excep - h/w, s/w h/w, s/w h/w, s/w h/w, s/w h/w, s/w h/w, s/w h/w, s/w h/w, s/w h/w notes: 1. reset has the highest priority for an interrupt level, followed by sf_excep, ivec0 and ivec1. 2. in the case of ivec0 and ivec1, one interrupt vector has several interrupt sources. the priority of the sources is controlled by setting the ipr register. 3. external interrupts are triggered by rising or falling edge, depending on the corresponding control register setting. 4. after system reset, the ipr register is in unknown status, so user must set the ipr register with proper value. 5. the pending bit is cleared by hardware when cpu reads the iir registser value. h/w, s/w vector source level reset (clear) reset reset 00000h - timer 1 match timer 2 match/capture h/w, s/w h/w, s/w h/w, s/w 00001h not used nmi basic timer overflow h/w, s/w figure 6-1. interrupt structure exceptions s3ck215 /fk215 6- 4 ipr0 logic iir0 cpu ivec0 ipr0 imr0 logic imr0 stop & idle release imr1 logic imr1 ipr1 ipr1 logic ivec1 iir1 irq1.0 irq1.1 irq1.2 irq1.3 irq1.4 irq1.5 irq1.6 irq1.7 note: the irq register value is cleared by h/w when the iir register is read by the programmer in an interrupt service routine. however, if you want to clear by s/w, then write the proper value to the iir register like as in the example above. to clear all the bits of irqx register at one time write "#08h" to the iirx register. clear (when writing clear bit value to bit.2. 1. 0) clear (when writing clear bit value to bit.2. 1. 0) ld r0, #x5h ld iir0, r0 irq0.5 is cleared ex) ld r0, #x2h ld iir1, r0 irq1.2 is cleared ex) irq0.0 irq0.1 irq0.2 irq0.3 irq0.4 irq0.5 irq0.6 irq0.7 timer 0 overflow timer 0 match/capture timer 1 match timer 2 match/capture timer 3 match timer 2 overflow sio basic timer overflow not used int3 not used not used watch timer int0 int1 int2 figure 6-2. interrupt structure s3ck215/fk215 excep tions 6- 5 interrupt mask registers .7 .6 .5 .4 .3 .2 .1 .0 interrupt mask register0 (imr0) 05h, r/w, reset: 00h irq0.0 irq0.1 irq0.2 irq0.3 irq0.4 irq0.5 irq0.6 irq0.7 interrupt request enable bits: 0 = disable interrupt request 1 = enable interrupt request note: if you want to change the value of the imr register, then you first make disable global int by di instruction, and change the value of the imr register. .7 .6 .5 .4 .3 .2 .1 .0 interrupt mask register1 (imr1) 09h, r/w, reset: 00h irq1.0 irq1.1 irq1.2 irq1.3 irq1.4 not used not used not used figure 6-3. interrupt mask register exceptions s3ck215 /fk215 6- 6 interrupt priority register group a 0 = irq0 > irq1 1 = irq1 > irq0 interrupt priority registers (ipr0:06h,ipr1:0ah, r/w ) ipr group a note: if you want to change the value of the ipr register, then you first make disable global int by di instruction, and change the value of the ipr register. after reset, ipr register is unknown status, so user must set the ipr register with proper value. ipr group b ipr group c irq0 irq1 irq2 irq3 irq4 irq5 irq6 irq7 group b 0 = irq2 > (irq3,irq4) 1 = (irq3,irq4) > irq2 subgroup b 0 = irq3 > irq4 1 = irq4 > irq3 group c 0 = irq5 > (irq6,irq7) 1 = (irq6,irq7) > irq5 subgroup c 0 = irq6 > irq7 1 = irq7 > irq6 .7 .6 .5 .4 .3 .2 .1 .0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 not used b>c>a a>b>c b>a>c c>a>b c>b>a a>c>b not used .7 .4 .1 group priority: figure 6-4. interrupt priority register s3ck215/fk215 excep tions 6- 7 + + programming tip ? interrupt programming tip 1 jumped from vector 2 push sr1 push r0 ld r0, iir00 cp r0, #03h jr ule, lte03 cp r0, #05h jr ule, lte05 cp r0, #06h jp eq, irq6_srv jp t, irq7_srv lte05 cp r0, #04 jp eq, irq4_srv jp t, irq5_srv lte03 cp r0, #01 jr ule, lte01 cp r0, #02 jp eq, irq2_srv jp t, irq3_srv lte01 cp r0, #00h jp eq, irq0_srv jp t, irq1_srv irq0_srv ; ? service for irq0 pop r0 pop sr1 iret irq1_srv ; ? service for irq1 pop r0 pop sr1 iret irq7_srv ; ? service for irq7 pop r0 pop sr1 iret note if the sr0 register is changed in the interrupt service routine, then the sr0 register must be pushed and popped in the interrupt service routine. exceptions s3ck215 /fk215 6- 8 + + programming tip ? interrupt programming tip 2 jumped from vector 2 push sr1 push r0 push r1 ld r0, iir00 sl r0 ld r1, < tbl_intx add r0, > tbl_intx push r1 push r0 ret tbl_intx ljp irq0_svr ljp irq1_svr ljp irq2_svr ljp irq3_svr ljp irq4_svr ljp irq5_svr ljp irq6_svr ljp irq7_svr irq0_srv ; ? service for irq0 pop r1 pop r0 pop sr1 iret irq1_srv ; ? service for irq1 pop r1 pop r0 pop sr1 iret irq7_srv ; ? service for irq7 pop r1 pop r0 pop sr1 iret note 1. if the sr0 register is changed in the interrupt service routine, then the sr0 register must be pushed and popped in the interrupt service routine. 2. above example is assumed that rom size is less than 64k-word and all the ljp instructions in the jump table ( tbl_intx) is in the same page. s3ck215/fk215 instr uction set 7- 1 7 instruction set overview glossary this chapter describes the calmrisc instruction set and the details of each instruction are listed in alphabetical order. the following notations are used for the description. table 7-1. instruction notation conventions notation interpretation < opn> operand n. n can be omitted if there is only one operand. typically, instruction set s3c k215/fk215 7- 2 instruction set map table 7-2.overall instruction set map ir [12:10]000 001 010 011 100 101 110 111 [15:13,7:2] 000 xxxxxx add gpr, #imm:8 sub gpr, #imm:8 cp gpr, #imm8 ld gpr, #imm:8 tm gpr, #imm:8 and gpr, #imm:8 or gpr, #imm:8 xor gpr, #imm:8 001 xxxxxx add gpr, @ idm sub gpr, @ idm cp gpr, @ idm ld gpr, @ idm ld @ idm, gpr and gpr, @ idm or gpr, @ idm xor gpr, @ idm 010 xxxxxx add gpr, adr:8 sub gpr, adr:8 cp gpr, adr:8 ld gpr, adr:8 bitt adr:8.bs bits adr:8.bs 011 xxxxxx adc gpr, adr:8 sbc gpr, adr:8 cpc gpr, adr:8 ld adr:8, gpr bitr adr:8.bs bitc adr:8.bs 100 000000 add gpr, gpr sub gpr, gpr cp gpr, gpr bms/bm c ld spr0, #imm:8 and gpr, adr:8 or gpr, adr:8 xor gpr, adr:8 100 000001 adc gpr, gpr sbc gpr, gpr cpc gpr, gpr invalid 100 000010 invalid invalid invalid invalid 100 000011 and gpr, gpr or gpr, gpr xor gpr, gpr invalid 100 00010x sla/sl/ rlc/rl/ sra/sr/ rrc/rr/ gpr inc/incc /dec/ decc/ com/ com2/ comc gpr invalid invalid 100 00011x ld spr, gpr ld gpr, spr swap gpr, spr ld tbh/tbl, gpr 100 00100x push spr pop spr invalid invalid 100 001010 push gpr pop gpr ld gpr, gpr ld gpr, tbh/tbl s3ck215/fk215 instr uction set 7- 3 table 7-2. overall instruction set map (continued) ir [12:10]000 001 010 011 100 101 110 111 100 001011 pop invalid ldc invalid ld spr0, #imm:8 and gpr, adr:8 or gpr, adr:8 xor gpr, adr:8 100 00110x ret/lret/ iret/nop/ break invalid invalid invalid 100 00111x invalid invalid invalid invalid 100 01xxxx ld gpr:bank, gpr:bank and sr0, #imm:8 or sr0, #imm:8 bank #imm:2 100 100000 100 110011 invalid invalid invalid invalid 100 1101xx lcall cc:4, imm:20 (2-word instruction) 100 1110xx llnk cc:4, imm:20 (2-word instruction) 100 1111xx ljp cc:4, imm:20 (2-word instruction) [15:10] 101 xxx jr cc:4, imm:9 110 0xx calls imm:12 110 1xx lnks imm:12 111 xxx cld gpr, imm:8 / cld imm:8, gpr / jnzd gpr, imm:8 / sys #imm:8 / cop #imm:12 note: ? invalid ? - invalid instruction. instruction set s3c k215/fk215 7- 4 table 7-3. instruction encoding instruction 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 add gpr, #imm:8 000 000 gpr imm[7:0] sub gpr, #imm:8 001 cp gpr, #imm:8 010 ld gpr, #imm:8 011 tm gpr, #imm:8 100 and gpr, #imm:8 101 or gpr, #imm:8 110 xor gpr, #imm:8 111 add gpr, @ idm 001 000 gpr idx mod offset[4:0] sub gpr, @ idm 001 cp gpr, @ idm 010 ld gpr, @ idm 011 ld @ idm, gpr 100 and gpr, @ idm 101 or gpr, @ idm 110 xor gpr, @ idm 111 add gpr, adr:8 010 000 gpr adr[7:0] sub gpr, adr:8 001 cp gpr, adr:8 010 ld gpr, adr:8 011 bitt adr:8.bs 10 bs bits adr:8.bs 11 adc gpr, adr:8 011 000 gpr adr[7:0] sbc gpr, adr:8 001 cpc gpr, adr:8 010 ld adr:8, gpr 011 bitr adr:8.bs 10 bs bitc adr:8.bs 11 s3ck215/fk215 instr uction set 7- 5 table 7-3. instruction encoding (continued ) instruction 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 add gprd, gprs 100 000 gprd 000000 gprs sub gprd, gprs 001 cp gprd, gprs 010 bms/bmc 011 adc gprd, gprs 000 000001 sbc gprd, gprs 001 cpc gprd, gprs 010 invalid 011 invalid ddd 000010 and gprd, gprs 000 000011 or gprd, gprs 001 xor gprd, gprs 010 invalid 011 aluop1 000 gpr 00010 aluop1 aluop2 001 gpr aluop2 invalid 010?011 xx xxx ld spr, gpr 000 gpr 00011 spr ld gpr, spr 001 gpr spr swap gpr, spr 010 gpr spr ld tbl, gpr 011 gpr x 0 x ld tbh, gpr x 1 x push spr 000 xx 00100 spr pop spr 001 xx spr invalid 010?011 xx xxx push gpr 000 gpr 001010 gpr pop gpr 001 gpr gpr ld gprd, gprs 010 gprd gprs ld gpr, tbl 011 gpr 0 x ld gpr, tbh 1 x pop 000 xx 001011 xx ldc @il 010 0 x ldc @il+ 1 x invalid 001, 011 xx note: "x" means not applicable. instruction set s3c k215/fk215 7- 6 table 7-3. instruction encoding (concluded ) instruction 15-13 12 11 10 9 8 7 6 5 4 3 2 1 0 2 nd word modop1 100 000 xx 00110 modop1 ? invalid 001?011 xx xxx invalid 000 xx 01 xxxxxx and sr0, #imm:8 001 imm[7:6] imm[5:0] or sr0, #imm:8 010 imm[7:6] bank #imm:2 011 xx x imm [1:0] xxx invalid 0 xxxx 10000000-11001111 lcall cc, imm:20 cc 1101 imm[19:16] imm[15:0] llnk cc, imm:20 ljp cc, imm:20 ld spr0, #imm:8 1 00 spr0 imm[7:0] ? and gpr, adr:8 01 gpr adr[7:0] or gpr, adr:8 10 xor gpr, adr:8 11 jr cc, imm:9 101 imm [8] cc imm[7:0] calls imm:12 110 0 imm[11:0] lnks imm:12 1 cld gpr, imm:8 111 0 00 gpr imm[7:0] cld imm:8, gpr 01 gpr jnzd gpr, imm:8 10 gpr sys #imm:8 11 xx cop #imm:12 1 imm[11:0] notes: 1. "x" means not applicable. 2. there are several modop1 codes that can be used, as described in table 7-9. 3. the operand 1(gpr) of the instruction jnzd is bank 3?s register. s3ck215/fk215 instr uction set 7- 7 table 7-4. index code information (? idx?) symbol code description id0 0 index 0 idh:idl0 id1 1 index 1 idh:idl1 table 7-5. index modification code information (?mod?) symbol code function @ idx + offset:5 00 dm[ idx], idx ? idx + offset @[ idx - offset:5] 01 dm[ idx + (2?s complement of offset:5)], idx ? idx + (2?s complement of offset:5) @[ idx + offset:5]! 10 dm[ idx + offset], idx ? idx @[ idx - offset:5]! 11 dm[ idx + (2?s complement of offset:5)], idx ? idx note: carry from idl is propagated to idh. in case of @[ idx - offset:5] or @[ idx - offset:5]!, the assembler should convert offset:5 to the 2?s complement format to fill the operand field (offset[4:0]). furthermore, @[ idx - 0] and @[ idx - 0]! are converted to @[ idx + 0] and @[ idx + 0]!, respectively. table 7-6. condition code information (?cc?) symbol (cc:4) code function blank 0000 always nc or ult 0001 c = 0, unsigned less than c or uge 0010 c = 1, unsigned greater than or equal to z or eq 0011 z = 1, equal to nz or ne 0100 z = 0, not equal to ov 0101 v = 1, overflow - signed value ule 0110 ~c | z, unsigned less than or equal to ugt 0111 c & ~z, unsigned greater than zp 1000 n = 0, signed zero or positive mi 1001 n = 1, signed negative pl 1010 ~n & ~z, signed positive zn 1011 z | n, signed zero or negative sf 1100 stack full ec0-ec2 1101-1111 ec[0] = 1/ec[1] = 1/ec[2] = 1 note: ec[2:0] is an external input ( calmrisc core?s point of view) and used as a condition. instruction set s3c k215/fk215 7- 8 table 7-7. ?aluop1? code information symbol code function sla 000 arithmetic shift left sl 001 shift left rlc 010 rotate left with carry rl 011 rotate left sra 100 arithmetic shift right sr 101 shift right rrc 110 rotate right with carry rr 111 rotate right table 7-8. ?aluop2? code information symbol code function inc 000 increment incc 001 increment with carry dec 010 decrement decc 011 decrement with carry com 100 1?s complement com2 101 2?s complement comc 110 1?s complement with carry ? 111 reserved table 7-9. ?modop1? code information symbol code function lret 000 return by il ret 001 return by hs iret 010 return from interrupt (by hs) nop 011 no operation break 100 reserved for debugger use only ? 101 reserved ? 110 reserved ? 111 reserved s3ck215/fk215 instr uction set 7- 9 quick reference operation op1 op2 function flag # of word / cycle and or xor add sub cp gpr adr:8 #imm:8 gpr @ idm op1 ? op1 & op2 op1 ? op1 | op2 op1 ? op1 ^ op2 op1 ? op1 + op2 op1 ? op1 + ~op2 + 1 op1 + ~op2 + 1 z,n z,n z,n c,z,v,n c,z,v,n c,z,v,n 1w1c adc sbc cpc gpr gpr adr:8 op1 ? op1 + op2 + c op1 ? op1 + ~op2 + c op1 + ~op2 + c c,z,v,n c,z,v,n c,z,v,n tm gpr #imm:8 op1 & op2 z,n bits bitr bitc bitt r3 adr:8.bs op1 ? (op2[bit] ? 1) op1 ? (op2[bit] ? 0) op1 ? ~(op2[bit]) z ? ~(op2[bit]) z z z z bms/bmc ? ? tf ? 1 / 0 ? push pop gpr ? hs[ sptr] ? gpr, ( sptr ? sptr + 1) gpr ? hs[ sptr - 1], ( sptr ? sptr - 1) ? z,n push pop spr ? hs[ sptr] ? spr, ( sptr ? sptr + 1) spr ? hs[ sptr - 1], ( sptr ? sptr - 1) ? pop ? ? sptr ? sptr ? 2 ? sla sl rlc rl sra sr rrc rr inc incc dec decc com com2 comc gpr ? c ? op1[7], op1 ? {op1[6:0], 0} c ? op1[7], op1 ? {op1[6:0], 0} c ? op1[7], op1 ? {op1[6:0], c} c ? op[7], op1 ? {op1[6:0], op1[7]} c ? op[0], op1 ? {op1[7],op1[7:1]} c ? op1[0], op1 ? {0, op1[7:1]} c ? op1[0], op1 ? {c, op1[7:1]} c ? op1[0], op1 ? {op1[0], op1[7:1]} op1 ? op1 + 1 op1 ? op1 + c op1 ? op1 + 0ffh op1 ? op1 + 0ffh + c op1 ? ~op1 op1 ? ~op1 + 1 op1 ? ~op1 + c c,z,v,n c,z,n c,z,n c,z,n c,z,n c,z,n c,z,n c,z,n c,z,v,n c,z,v,n c,z,v,n c,z,v,n z,n c,z,v,n c,z,v,n instruction set s3c k215/fk215 7- 10 quick reference ( continued ) operation op1 op2 function flag # of word / cycle ld gpr :bank gpr :bank op1 ? op2 z,n 1w1c ld spr0 #imm:8 op1 ? op2 ? ld gpr gpr spr adr:8 @ idm #imm:8 tbh/tbl op1 ? op2 z,n ld spr tbh/tbl gpr op1 ? op2 ? ld adr:8 gpr op1 ? op2 ? ld @ idm gpr op1 ? op2 ? ldc @il @il+ ? (tbh:tbl) ? pm[(ilx:ilh:ill)], ill++ if @il+ ? 1w2c and or sr0 #imm:8 sr0 ? sr0 & op2 sr0 ? sr0 | op2 ? 1w1c bank #imm:2 ? sr0[4:3] ? op2 ? swap gpr spr op1 ? op2, op2 ? op1 (excluding sr0/sr1) ? lcall cc imm:20 ? if branch taken, push xstack, hs[15:0] ? {pc[15:12],pc[11:0] + 2} and pc ? op1 else pc[11:0] ? pc[11:0] + 2 ? 2w2c llnk cc imm:20 ? if branch taken, il[19:0] ? {pc[19:12], pc[11:0] + 2} and pc ? op1 else pc[11:0] ? pc[11:0] + 2 ? calls imm:12 ? push xstack, hs[15:0] ? {pc[15:12], pc[11:0] + 1} and pc[11:0] ? op1 ? 1w2c lnks imm:12 ? il[19:0] ? {pc[19:12], pc[11:0] + 1} and pc[11:0] ? op1 ? jnzd rn imm:8 if ( rn == 0) pc ? pc[delay slot] - 2?s complement of imm:8, rn-- else pc ? pc[delay slot]++, rn-- ? ljp cc imm:20 ? if branch taken, pc ? op1 else pc[11:0] < pc[11:0] + 2 ? 2w2c jr cc imm:9 ? if branch taken, pc[11:0] ? pc[11:0] + op1 else pc[11:0] ? pc[11:0] + 1 ? 1w2c note: op1 - operand1, op2 - operand2, 1w1c - 1-word 1-cycle instruction, 1w2c - 1-word 2-cyc le instruction, 2w2c - 2-word 2-cycle instruction. the rn of instruction jnzd is bank 3?s gpr. s3ck215/fk215 instr uction set 7- 11 quick reference ( concluded ) operation op1 op2 function flag # of word / cycle lret ret iret nop break ? ? pc ? il[19:0] pc ? hs[ sptr - 2], ( sptr ? sptr - 2) pc ? hs[ sptr - 2], ( sptr ? sptr - 2) no operation no operation and hold pc ? 1w2c 1w2c 1w2c 1w1c 1w1c sys #imm:8 ? no operation but generates syscp[7:0] and nsysid ? 1w1c cld imm:8 gpr op1 ? op2, generates syscp[7:0], ncldid, and cldwr ? cld gpr imm:8 op1 ? op2, generates syscp[7:0], ncldid, and cldwr z,n cop #imm:12 ? generates syscp[11:0] and ncopid ? notes: 1. op1 - operand1, op2 - operand2, sptr - stack pointer register, 1w1c - 1-word 1-cycle instruction, 1w2c - 1-word 2-cycle instruction 2. pseudo instructions ? scf/rcf carry flag set or reset instruction ? stop/idle mcu power saving instructions ? ei/di exception enable and disable instructions ? jp/lnk/call if jr/lnks/calls commands (1 word instructions) can access the target address, there is no conditional code in the case of call/lnk, and the jp/lnk/call commands are assembled to jr/lnks/calls in linking time, or else the jp/lnk/call commands are assembled to ljp/llnk/lcall (2 word instructions) inst ructions. instruction set s3c k215/fk215 7- 12 instruction group summary alu instructions ?alu instructions? refer to the operations that use alu to generate results. alu instructions update the values in status register 1 (sr1), namely carry (c), zero (z), overflow (v), and negative (n), depending on the operation type and the result. aluop gpr, adr:8 performs an alu operation on the value in gpr and the value in dm[adr:8] and stores the result into gpr. aluop = add, sub, cp, and, or, xor for sub and cp, gpr+(not dm[adr:8])+1 is performed. adr:8 is the offset in a specific data memory page. the data memory page is 0 or the value of idh (index of data memory higher byte register), depending on the value of eid in status register 0 (sr0). operation gpr ? gpr aluop dm[00h:adr:8] if eid = 0 gpr ? gpr aluop dm[idh:adr8] if eid = 1 note that this is an 7-bit operation. example add r0, 80h // assume eid = 1 and idh = 01h // r0 ? r0 + dm[0180h] aluop gpr, #imm:8 stores the result of an alu operation on gpr and an 7-bit immediate value into gpr. aluop = add, sub, cp, and, or, xor for sub and cp, gpr+(not #imm:8)+1 is performed. #imm:8 is an 7-bit immediate value. operation gpr ? gpr aluop #imm:8 example add r0, #7ah // r0 ? r0 + 7ah s3ck215/fk215 instr uction set 7- 13 aluop gprd, gprs store the result of aluop on gprs and gprd into gprd. aluop = add, sub, cp, and, or, xor for sub and cp, gprd + (not gprs) + 1 is performed. gprs and gprd need not be distinct. operation gprd ? gprd aluop gprs gprd - gprs when aluop = cp (comparison only) example add r0, r1 // r0 ? r0 + r1 aluop gpr, @ idm performs aluop on the value in gpr and dm[id] and stores the result into gpr. index register id is idh:idl (idh:idl0 or idh:idl1). aluop = add, sub, cp, and, or, xor for sub and cp, gpr+(not dm[ idm])+1 is performed. idm = idx+off:5, [idx-offset:5], [idx+offset:5]!, [idx-offset:5]! ( idx = id0 or id1) operation gpr - dm[ idm] when aluop = cp (comparison only) gpr ? gpr aluop dm[ idx], idx ? idx + offset:5 when idm = idx + offset:5 gpr ? gpr aluop dm[ idx - offset:5], idx ? idx - offset:5 when idm = [ idx - offset:5] gpr ? gpr aluop dm[ idx + offset:5] when idm = [ idx + offset:5]! gpr ? gpr aluop dm[ idx - offset:5] when idm = [ idx - offset:5]! when carry is generated from idl (on a post-increment or pre-decrement), it is propagated to idh. example add r0, @id0+2 // assume id0 = 02ffh // r0 ? r0 + dm[02ffh], idh ? 03h and idl0 ? 01h add r0, @[id0-2] // assume id0 = 0201h // r0 ? r0 + dm[01ffh], idh ? 01h and idl0 ? ffh add r0, @[id1+2]! // assume id1 = 02ffh // r0 ? r0 + dm[0301], idh ? 02h and idl1 ? ffh add r0, @[id1-2]! // assume id1 = 0200h // r0 ? r0 + dm[01feh], idh ? 02h and idl1 ? 00h instruction set s3c k215/fk215 7- 14 aluopc gprd, gprs performs aluop with carry on gprd and gprs and stores the result into gprd. aluopc = adc, sbc, cpc gprd and gprs need not be distinct. operation gprd ? gprd + gprs + c when aluopc = adc gprd ? gprd + (not gprs) + c when aluopc = sbc gprd + (not gprs) + c when aluopc = cpc (comparison only) example add r0, r2 // assume r1:r0 and r3:r2 are 16-bit signed or unsigned numbers. adc r1, r3 // to add two 16-bit numbers, use add and adc. sub r0, r2 // assume r1:r0 and r3:r2 are 16-bit signed or unsigned numbers. sbc r1, r3 // to s ubtract two 16-bit numbers, use sub and sbc. cp r0, r2 // assume both r1:r0 and r3:r2 are 16-bit unsigned numbers. cpc r1, r3 // to compare two 16-bit unsigned numbers, use cp and cpc. aluopc gpr, adr:8 performs aluop with carry on gpr and dm[adr:8]. operation gpr ? gpr + dm[adr:8] + c when aluopc = adc gpr ? gpr + (not dm[adr:8]) + c when aluopc = sbc gpr + (not dm[adr:8]) + c when aluopc = cpc (comparison only) cplop gpr (complement operations ) cplop = com, com2, comc operation com gpr not gpr (logical complement) com2 gpr not gpr + 1 (2?s complement of gpr) comc gpr not gpr + c (logical complement of gpr with carry) example com2 r0 // assume r1:r0 is a 16-bit signed number. comc r1 // com2 and comc can be used to get the 2?s complement of it. s3ck215/fk215 instr uction set 7- 15 incdec gpr (increment/decrement operations) incdec = inc, incc, dec, decc operation inc gpr increase gpr, i.e., gpr ? gpr + 1 incc gpr i ncrease gpr if carry = 1, i.e., gpr ? gpr + c dec gpr decrease gpr, i.e., gpr ? gpr + ffh decc gpr decrease gpr if carry = 0, i.e., gpr ? gpr + ffh + c example inc r0 // assume r1:r0 is a 16-bit number incc r1 // to increase r1:r0, use inc and incc. dec r0 // assume r1:r0 is a 16-bit number decc r1 // to decrease r1:r0, use dec and decc. instruction set s3c k215/fk215 7- 16 shift/rotate instructions shift (rotate) instructions shift (rotate) the given operand by 1 bit. depending on the operation performed, a number of status register 1 (sr1) bits, namely carry (c), zero (z), overflow (v), and negative (n), are set. sl gpr operation c 7 0 0 gpr carry (c) is the msb of gpr before shifting, negative (n) is the msb of gpr after shifting. overflow (v) is not affected. zero (z) will be 1 if the result is 0. sla gpr operation c 7 0 0 gpr carry (c) is the msb of gpr before shifting, negative (n) is the msb of gpr after shifting. overflow (v) will be 1 if the msb of the result is different from c. z will be 1 if the result is 0. rl gpr operation c 7 0 gpr carry (c) is the msb of gpr before rotating. negative (n) is the msb of gpr after rotatin/g. overflow (v) is not affected. zero (z) will be 1 if the result is 0. rlc gpr operation c 7 0 gpr carry (c) is the msb of gpr before rotating, negative (n) is the msb of gpr after rotating. overflow (v) is not affected. zero (z) will be 1 if the result is 0. s3ck215/fk215 instr uction set 7- 17 sr gpr operation c 7 0 0 gpr carry (c) is the lsb of gpr before shifting, negative (n) is the msb of gpr after shifting. overflow (v) is not affected. zero (z) will be 1 if the result is 0. sra gpr operation c 7 0 gpr carry (c) is the lsb of gpr before shifting, negative (n) is the msb of gpr after shifting. overflow (v) is not affected. z will be 1 if the result is 0. rr gpr operation c 7 0 gpr carry (c) is the lsb of gpr before rotating. negative (n) is the msb of gpr after rotating. overflow (v) is not affected. zero (z) will be 1 if the result is 0. rrc gpr operation c 7 0 gpr carry (c) is the lsb of gpr before rotating, negative (n) is the msb of gpr after rotating. overflow (v) is not affected. zero (z) will be 1 if the result is 0. instruction set s3c k215/fk215 7- 18 load instructions load instructions transfer data from data memory to a register or from a register to data memory, or assigns an immediate value into a register. as a side effect, a load instruction placing a value into a register sets the zero (z) and negative (n) bits in status register 1 (sr1), if the placed data is 00h and the msb of the data is 1, respectively. ld gpr, adr:8 loads the value of dm[adr:8] into gpr. adr:8 is offset in the page specified by the value of eid in status register 0 (sr0). operation gpr ? dm[00h:adr:8] if eid = 0 gpr ? dm[idh:adr:8] if eid = 1 note that this is an 7-bit operation. example ld r0, 80h // assume eid = 1 and idh= 01h // r0 ? dm[0180h] ld gpr, @ idm loads a value from the data memory location specified by @ idm into gpr. idm = idx+off:5, [idx-offset:5], [idx+offset:5]!, [idx-offset:5]! ( idx = id0 or id1) operation gpr ? dm[ idx], idx ? idx + offset:5 when idm = idx + offset:5 gpr ? dm[ idx - offset:5], idx ? idx - offset:5 when idm = [ idx - offset:5] gpr ? dm[ idx + offset:5] when idm = [ idx + offset:5]! gpr ? dm[ idx - offset:5] when idm = [ idx - offset:5]! when carry is generated from idl (on a post-increment or pre-decrement), it is propagated to idh. example ld r0, @[id0 + 03h]! // assume idh:idl0 = 0270h // r0 ? dm[0273h], idh:idl0 ? 0270h s3ck215/fk215 instr uction set 7- 19 ld reg, #imm:8 loads an 7-bit immediate value into reg. reg can be either gpr or an spr0 group register - idh (index of data memory higher byte register), idl0 (index of data memory lower byte register)/ idl1, and status register 0 (sr0). #imm:8 is an 7-bit immediate value. operation reg ? #imm:8 example ld r0 #7ah // r0 ? 7ah ld idh, #03h // idh ? 03h ld gpr:bs:2, gpr:bs:2 loads a value of a register from a specified bank into another register in a specified bank. example ld r0:1, r2:3 // r0 in bank 1, r2 in bank 3 ld gpr, tbh/tbl loads the value of tbh or tbl into gpr. tbh and tbl are 7-bit long registers used exclusively for ldc instructions that access program memory. therefore, after an ldc instruction, ld gpr, tbh/tbl instruction will usually move the data into gprs, to be used for other operations. operation gpr ? tbh (or tbl) example ldc @il // gets a program memory item residing @ ilx:ilh:ill ld r0, tbh ld r1, tbl ld tbh/tbl, gpr loads the value of gpr into tbh or tbl. these instructions are used in pair in interrupt service routines to save and restore the values in tbh/tbl as needed. operation tbh (or tbl) ? gpr ld gpr, spr loads the value of spr into gpr. operation gpr ? spr example ld r0, idh // r0 ? idh instruction set s3c k215/fk215 7- 20 ld spr, gpr loads the value of gpr into spr. operation spr ? gpr example ld idh, r0 // idh ? r0 ld adr:8, gpr stores the value of gpr into data memory (dm). adr:8 is offset in the page specified by the value of eid in status register 0 (sr0). operation dm[00h:adr:8] ? gpr if eid = 0 dm[idh:adr:8] ? gpr if eid = 1 note that this is an 7-bit operation. example ld 7ah, r0 // assume eid = 1 and idh = 02h. // dm[027ah] ? r0 ld @ idm, gpr loads a value into the data memory location specified by @ idm from gpr. idm = idx+off:5, [idx-offset:5], [idx+offset:5]!, [idx-offset:5]! ( idx = id0 or id1) operation dm[ idx] ? gpr, idx ? idx + offset:5 when idm = idx + offset:5 dm[ idx - offset:5] ? gpr, idx ? idx - offset:5 when idm = [ idx - offset:5] dm[ idx + offset:5] ? gpr when idm = [ idx + offset:5]! dm[ idx - offset:5] ? gpr when idm = [ idx - offset:5]! when carry is generated from idl (on a post-increment or pre-decrement), it is propagated to idh. example ld @[id0 + 03h]!, r0 // assume idh:idl0 = 0170h // dm[0173h] ? r0, idh:idl0 ? 0170h s3ck215/fk215 instr uction set 7- 21 branch instructions branch instructions can be categorized into jump instruction, link instruction, and call instruction. a jump instruction does not save the current pc, whereas a call instruction saves (?pushes?) the current pc onto the stack and a link instruction saves the pc in the link register il. status registers are not affected. each instruction type has a 2-word format that supports a 20-bit long jump. jr cc:4, imm:9 imm:9 is a signed number (2?s complement), an offset to be added to the current pc to compute the target (pc[19:12]:(pc[11:0] + imm:9)). operation pc[11:0] ? pc[11:0] + imm:9 if branch taken (i.e., cc:4 resolves to be true) pc[11:0] ? pc[11:0] + 1 otherwise example l18411: // assume current pc = 18411h. jr z, 107h // next pc is 18518 (18411h + 107h) if zero (z) bit is set. ljp cc:4, imm:20 jumps to the program address specified by imm:20. if program size is less than 64k word, pc[19:16] is not affected. operation pc[15:0] ? imm[15:0] if branch taken and program size is less than 64k word pc[19:0] ? imm[19:0] if branch taken and program size is equal to 64k word or more pc [11:0] ? pc[11:0] + 1 otherwise example l18411: // assume current pc = 18411h. ljp z, 10107h // next instruction?s pc is 10107h if zero (z) bit is set jnzd rn, imm:8 jumps to the program address specified by imm:8 if the value of the bank 3 register rn is not zero. jnzd performs only backward jumps, with the value of rn automatically decreased. there is one delay slot following the jnzd instruction that is always executed, regardless of whether jnzd is taken or not. operation if ( rn == 0) pc ? pc[delay slot] (-) 2?s complement of imm:8, rn ? rn - 1 else pc ? pc[delay slot] + 1, rn ? rn - 1. instruction set s3c k215/fk215 7- 22 example loop_a: // start of loop body jnzd r0, loop_a // jump back to loop_a if r0 is not zero add r1, #2 // delay slot, always executed (you must use one cycle instruction only) calls imm:12 saves the current pc on the stack (?pushes? pc) and jumps to the program address specified by imm:12. the current page number pc[19:12] is not changed. since this is a 1-word instruction, the return address pushed onto the stack is (pc + 1). if np64kw is low when pc is saved, pc[19:16] is not saved in the stack. operation hs[ sptr][15:0] ? current pc + 1 and sptr ? sptr + 2 (push stack) if np64kw = 0 hs[ sptr][19:0] ? current pc + 1 and sptr ? sptr + 2 (push stack) if np64kw = 1 pc[11:0] ? imm:12 example l18411: // assume current pc = 18411h. calls 107h // call the subroutine at 18107h, with the current pc pushed // onto the stack (hs ? 18412h) if np64kw = 1. lcall cc:4, imm:20 saves the current pc onto the stack (pushes pc) and jumps to the program address specified by imm:20. since this is a 2-word instruction, the return address saved in the stack is (pc + 2). if np64kw, a core input signal is low when pc is saved, 0000111111pc[19:16] is not saved in the stack and pc[19:16] is not set to imm[19:16]. operation hs[ sptr][15:0] ? current pc + 2 and sptr + 2 (push stack) if branch taken and np64kw = 0 hs[ sptr][19:0] ? current pc + 2 and sptr + 2 (push stack) if branch taken and np64kw = 1 pc[15:0] ? imm[15:0] if branch taken and np64kw = 0 pc[19:0] ? imm[19:0] if branch taken and np64kw = 1 pc[11:0] ? pc[11:0] + 2 otherwise example l18411: // assume current pc = 18411h. lcall nz, 10107h // call the subroutine at 10107h with the current pc pushed // onto the stack (hs ? 18413h) s3ck215/fk215 instr uction set 7- 23 lnks imm:12 saves the current pc in il and jumps to the program address specified by imm:12. the current page number pc[19:12] is not changed. since this is a 1-word instruction, the return address saved in il is (pc + 1). if the program size is less than 64k word when pc is saved, pc[19:16] is not saved in ilx. operation il[15:0] ? current pc + 1 if program size is less than 64k word il[19:0] ? current pc + 1 if program size is equal to 64k word or more pc[11:0] ? imm:12 example l18411: // assume current pc = 18411h. lnks 107h // call the subroutine at 18107h, with the current pc saved // in il (il[19:0] ? 18412h) if program size is 64k word or more. llnk cc:4, imm:20 saves the current pc in il and jumps to the program address specified by imm:20. since this is a 2-word instruction, the return address saved in il is (pc + 2). if the program size is less than 64k word when pc is saved, pc[19:16] is not saved in ilx. operation il[15:0] ? current pc + 2 if branch taken and program size is less than 64k word il[19:0] ? current pc + 2 if branch taken and program size is 64k word or more pc[15:0] ? imm[15:0] if branch taken and program size is less than 64k word pc[19:0] ? imm[19:0] if branch taken and program size is 64k word or more pc[11:0] ? pc[11:0] + 2 otherwise example l18411: // assume current pc = 18411h. llnk nz, 10107h // call the subroutine at 10107h with the current pc saved // in il (il[19:0] ? 18413h) if program size is 64k word or more ret, iret returns from the current subroutine. iret sets ie (sr0[1]) in addition. if the program size is less than 64k word, pc[19:16] is not loaded from hs[19:16]. operation pc[15:0] ? hs[ sptr - 2] and sptr ? sptr - 2 (pop stack) if program size is less than 64k word pc[19:0] ? hs[ sptr - 2] and sptr ? sptr - 2 (pop stack) if program size is 64k word or more example ret // assume sptr = 3h and hs[1] = 18407h. // the next pc will be 18407h and sptr is set to 1h instruction set s3c k215/fk215 7- 24 lret returns from the current subroutine, using the link register il. if the program size is less than 64k word, pc[19:16] is not loaded from ilx. operation pc[15:0] ? il[15:0] if program size is less than 6 4k word pc[19:0] ? il[19:0] if program size is 64k word or more example lret // assume il = 18407h. // the next instruction to execute is at pc = 18407h // if program size is 64k word or more jp/lnk/call jp/lnk/call instructions are pseudo instructions. if jr/lnks/calls commands (1 word instructions) can access the target address, there is no conditional code in the case of call/lnk and the jp/lnk/call commands are assembled to jr/lnks/calls in linking time or else the jp/lnk/call commands are assembled to ljp/llnk/lcall (2 word instructions) instructions. s3ck215/fk215 instr uction set 7- 25 bit manipulation instructions bitop adr:8.bs performs a bit operation specified by op on the value in the data memory pointed by adr:8 and stores the result into r3 of current gpr bank or back into memory depending on the value of tf bit. bitop = bits, bitr, bitc, bitt bits: bit set bitr: bit reset bitc: bit complement bitt: bit test (r3 is not touched in this case) bs: bit location specifier, 0 - 7. operation r3 ? dm[00h:adr:8] bitop bs if eid = 0 r3 ? dm[idh:adr:8] bitop bs if eid = 1 (no register transfer for bitt) set the zero (z) bit if the result is 0. example bits 25h.3 // assume eid = 0. set bit 3 of dm[00h:25h] and store the result in r3. bitt 25h.3 // check bit 3 of dm[00h:25h] if eid = 0. bmc/bms clears or sets the tf bit, which is used to determine the destination of bitop instructions. when tf bit is clear, the result of bitop instructions will be stored into r3 (fixed); if the tf bit is set, the result will be written back to memory. operation tf ? 0 (bmc) tf ? 1 (bms) tm gpr, #imm:8 performs and operation on gpr and imm:8 and sets the zero (z) and negative (n) bits. no change in gpr. operation z, n flag ? gpr & #imm:8 bitop gpr.bs performs a bit operation on gpr and stores the result in gpr. since the equivalent functionality can be achieved using or gpr, #imm:8, and gpr, #imm:8, and xor gpr, #imm:8, this instruction type doesn?t have separate op codes. instruction set s3c k215/fk215 7- 26 and sr0, #imm:8/or sr0, #imm:8 sets/resets bits in sr0 and stores the result back into sr0. operation sr0 ? sr0 & #imm:8 sr0 ? sr0 | #imm:8 bank #imm:2 loads sr0[4:3] with # imm[1:0]. operation sr0[4:3] ? # imm[1:0] miscellaneous instruction swap gpr, spr swaps the values in gpr and spr. sr0 and sr1 can not be used for this instruction. no flag is updated, even though the destination is gpr. operation temp ? spr spr ? gpr gpr ? temp example swap r0, idh // assume idh = 00h and r0 = 08h. // after this, idh = 08h and r0 = 00h. push reg saves reg in the stack (pushes reg into stack). reg = gpr, spr operation hs[ sptr][7:0] ? reg and sptr ? sptr + 1 example push r0 // assume r0 = 08h and sptr = 2h // then hs[2][7:0] ? 08h and sptr ? 3h s3ck215/fk215 instr uction set 7- 27 pop reg pops stack into reg. reg = gpr, spr operation reg ? hs[sptr-1][7:0] and sptr ? sptr ? 1 example pop r0 // assume sptr = 3h and hs[2] = 18407h // r0 ? 07h and sptr ? 2h pop pops 2 bytes from the stack and discards the popped data. nop does no work but increase pc by 1. break does nothing and does not increment pc. this instruction is for the debugger only. when this instruction is executed, the processor is locked since pc is not incremented. therefore, this instruction should not be used under any mode other than the debug mode. sys #imm:8 does nothing but increase pc by 1 and generates syscp[7:0] and nsysid signals. cld gpr, imm:8 gpr ? (imm:8) and generates syscp[7:0], ncldid, and ncldwr signals. cld imm:8, gpr (imm:8) ? gpr and generates syscp[7:0], ncldid, and ncldwr signals. cop #imm:12 generates syscp[11:0] and ncopid signals. instruction set s3c k215/fk215 7- 28 ldc loads program memory item into register. operation [tbh:tbl] ? pm[ilx:ilh:ill] (ldc @il) [tbh:tbl] ? pm[ilx:ilh:ill], ill++ (ldc @il+) tbh and tbl are temporary registers to hold the transferred program memory items. these can be accessed only by ld gpr and tbl/tbh instruction. example ld ilx, r1 // assume r1:r2:r3 has the program address to access ld ilh, r2 ld ill, r3 ldc @il // get the program data @(ilx:ilh:ill) into tbh:tbl s3ck215/fk215 instr uction set 7- 29 pseudo instructions ei/di exceptions enable and disable instruction. operation sr0 ? or sr0,#00000010b (ei) sr0 ? and sr0,#11111101b (di) exceptions are enabled or disabled through this instruction. if there is an ei instruction, the sr0.1 is set and reset, when di instruction. example di ei scf/rcf carry flag set and reset instruction. operation cp r0,r0 (scf) and r0,r0 (rcf) carry flag is set or reset through this instruction. if there is an scf instruction, the sr1.0 is set and reset, when rcf instruction. example scf rcf stop/idle mcu power saving instruction. operation sys #0ah (stop) sys #05h (idle) the stop instruction stops the both cpu clock and system clock and causes the microcontroller to enter stop mode. the idle instruction stops the cpu clock while allowing system clock oscillation to continue. example stop(or idle) nop nop nop instruction set s3c k215/fk215 7- 30 adc ? add with carry format: adc s3ck215/fk215 instr uction set 7- 31 add ? add format: add instruction set s3c k215/fk215 7- 32 and ? bit-wise and format: and s3ck215/fk215 instr uction set 7- 33 and sr0 ? bit-wise and with sr0 format: and sr0, #imm:8 operation: sr0 ? sr0 & imm:8 and sr0 performs the bit-wise and operati on on the value of sr0 and imm:8 and stores the result in sr0. flags: ? example: given: sr0 = 11000010b nie equ ~02h nie0 equ ~40h nie1 equ ~80h and sr0, # nie | nie0 | nie1 and sr0, #11111101b in the first example, the statement ?and sr0, #nie|nie0|nie1? clear all of bits of the global interrupt, interrupt 0 and interrupt 1. on the contrary, cleared bits can be set to ?1? by instruction ?or sr0, #imm:8?. refer to instruction or sr0 for more detailed explanation about enabling bit. in the second example, the statement ?and sr0, #11111101b? is equal to instruction di, which is disabling interrupt globally. instruction set s3c k215/fk215 7- 34 bank ? gpr bank selection format: bank #imm:2 operation: sr0[4:3] ? imm:2 flags: ? note: for explanation of the calmrisc banked register file and its usage, please refer to chapter 3. example: bank #1 // select register bank 1 ld r0, #11h // bank1?s r0 ? 11h bank #2 // select register bank 2 ld r1, #22h // bank2?s r1 ? 22h s3ck215/fk215 instr uction set 7- 35 bitc ? bit complement format: bitc adr:8.bs bs: 3-digit bit specifier operation: r3 ? ((adr:8) ^ (2**bs)) if (tf == 0) (adr:8) ? ((adr:8) ^ (2**bs)) if (tf == 1) bitc complements the specified bit of a value read from memory and stores the result in r3 or back into memory, depending on the value of tf. tf is set or clear by bms/bmc instruction. flags: z: set if result is zero. reset if not. note: since the destination register r3 is fixed, it is not specified explicitly. example: given: idh = 01, dm[0180h] = ffh, eid = 1 bmc // tf ? 0 bitc 80h.0 // r3 ? feh, dm[0180h] = ffh bms // tf ? 1 bitc 80h.1 // dm[0180h] ? fdh instruction set s3c k215/fk215 7- 36 bitr ? bit reset format: bitr adr:8.bs bs: 3-digit bit specifier operation: r3 ? ((adr:8) & ((11111111) 2 - (2**bs))) if (tf == 0) (adr:8) ? ((adr:8) & ((11111111) 2 - (2**bs))) if (tf == 1) bitr resets the specified bit of a value read from memory and stores the result in r3 or back into memory, depending on the value of tf. tf is set or clear by bms/bmc instruction. flags: z: set if result is zero. reset if not. note: since the destination register r3 is fixed, it is not specified explicitly. example: given: idh = 01, dm[0180h] = ffh, eid = 1 bmc // tf ? 0 bitr 80h.1 // r3 ? fdh, dm[0180h] = ffh bms // tf ? 1 bitr 80h.2 // dm[0180h] ? fbh s3ck215/fk215 instr uction set 7- 37 bits ? bit set format: bits adr:8.bs bs: 3-digit bit specifier. operation: r3 ? ((adr:8) | (2**bs)) if (tf == 0) (adr:8) ? ((adr:8) | (2**bs)) if (tf == 1) bits sets the specified bit of a value read from memory and stores the result in r3 or back into memory, depending on the value of tf. tf is set or clear by bms/bmc instruction. flags: z: set if result is zero. reset if not. note: since the destination register r3 is fixed, it is not specified explicitly. example: given: idh = 01, dm[0180h] = f0h, eid = 1 bmc // tf ? 0 bits 80h.1 // r3 ? 0f2h, dm[0180h] = f0h bms // tf ? 1 bits 80h.2 // dm[0180h] ? f4h instruction set s3c k215/fk215 7- 38 bitt ? bit test format: bitt adr:8.bs bs: 3-digit bit specifier. operation: z ? ~((adr:8) & (2**bs)) bitt tests the specified bit of a value read from memory. flags: z: set if result is zero. reset if not. example: given: dm[0080h] = f7h, eid = 0 bitt 80h.3 // z flag is set to ?1? jr z, %1 // jump to label %1 because condition is true. %1 bits 80h.3 nop s3ck215/fk215 instr uction set 7- 39 bmc/bms ? tf bit clear/set format: bms/bmc operation: bmc/bms clears (sets) the tf bit. tf ? 0 if bmc tf ? 1 if bms tf is a single bit flag which determines the destination of bit operations, such as bitc, bitr, and bits. flags: ? note: bmc/bms are the only instructions that modify the content of the tf bit. example: bms // tf ? 1 bits 81h.1 bmc // tf ? 0 bitr 81h.2 ld r0, r3 instruction set s3c k215/fk215 7- 40 call ? conditional subroutine call (pseudo instruction) format: call cc:4, imm:20 call imm:12 operation: if calls can access the target address and there is no conditional code (cc:4), call command is assembled to calls (1-word instruction) in linking time, else the call is assembl ed to lcall (2-word instruction). example: call c, wait // hs[ sptr][15:0] ? current pc + 2, sptr ? sptr + 2 // 2-word instruction call 0088h // hs[ sptr][15:0] ? current pc + 1, sptr ? sptr + 2 // 1-word instruction wait: nop // address at 0088h nop nop nop nop ret s3ck215/fk215 instr uction set 7- 41 calls ? call subroutine format: calls imm:12 operation: hs[ sptr][15:0] ? current pc + 1, sptr ? sptr + 2 if the program size is less than 64k word. hs[ sptr][19:0] ? current pc + 1, sptr ? sptr + 2 if the program size is equal to or over 64k word. pc[11:0] ? imm:12 calls unconditionally calls a subroutine residing at the address specified by imm:12. flags: ? example: calls wait wait: nop nop nop ret because this is a 1-word instruction, the saved returning address on stack is (pc + 1). instruction set s3c k215/fk215 7- 42 cld ? load into coprocessor format: cld imm:8, s3ck215/fk215 instr uction set 7- 43 cld ? load from coprocessor format: cld instruction set s3c k215/fk215 7- 44 com ? 1's or bit-wise complement format: com s3ck215/fk215 instr uction set 7- 45 com2 ? 2's complement format: com2 instruction set s3c k215/fk215 7- 46 comc ? bit-wise complement with carry format: comc s3ck215/fk215 instr uction set 7- 47 cop ? coprocessor format: cop #imm:12 operation: cop passes imm:12 to the coprocessor by generating syscp[11:0] and ncopid signals. flags: ? example: cop #0d01h // generate 1 word instruction code(fd01h) cop #0234h // generate 1 word instruction code(f234h) the above two instructions are equal to statement ?eld a, #1234h? for mac816 operation. the microcode of mac instruction ?eld a, #1234h? is ?fd01f234?, 2-word instruction. in this, code ?f? indicates ?cop? instruction. instruction set s3c k215/fk215 7- 48 cp ? compare format: cp s3ck215/fk215 instr uction set 7- 49 cpc ? compare with carry format: cpc instruction set s3c k215/fk215 7- 50 dec ? decrement format: dec s3ck215/fk215 instr uction set 7- 51 decc ? decrement with carry format: decc instruction set s3c k215/fk215 7- 52 di ? disable interrupt (pseudo instruction) format: di operation: disables interrupt globally. it is same as ?and sr0, #0fdh? . di instruction sets bit1 ( ie: global interrupt enable) of sr0 register to ?0? flags: ? example: given: sr0 = 03h di // sr0 ? sr0 & 11111101b di instruction clears sr0[1] to ?0?, disabling interrupt processing. s3ck215/fk215 instr uction set 7- 53 ei ? enable interrupt (pseudo instruction) format: ei operation: enables interrupt globally. it is same as ?or sr0, #02h? . ei instruction sets the bit1 ( ie: global interrupt enable) of sr0 register to ?1? flags: ? example: given: sr0 = 01h ei // sr0 ? sr0 | 00000010b the statement ?ei? sets the sr0[1] to ?1?, enabling all interrupts. instruction set s3c k215/fk215 7- 54 idle ? idle operation (pseudo instruction) format: idle operation: the idle instruction stops the cpu clock while allowing system clock oscillation to continue. idle mode can be released by an interrupt or reset operation. the idle instruction is a pseudo instruction. it is assembled as ?sys #05h?, and this generates the syscp[7-0] signals. then these signals are decoded and the decoded signals execute the idle operation. flags: ? note: the next instruction of idle instruction is executed, so please use the nop instruction after the idle instruction. example: idle nop nop nop the idle instruction stops the cpu clock but not the system clock. s3ck215/fk215 instr uction set 7- 55 inc ? increment format: inc instruction set s3c k215/fk215 7- 56 incc ? increment with carry format: incc s3ck215/fk215 instr uction set 7- 57 iret ? return from interrupt handling format: iret operation: pc ? hs[ sptr - 2], sptr ? sptr - 2 iret pops the return address (after interrupt handling) from the hardware stack and assigns it to pc. the ie (i.e., sr0[1]) bit is set to allow further interrupt generation. flags: ? note: the program size (indicated by the np64kw signal) determines which portion of pc is updated. when the program size is less than 64k word, only the lower 16 bits of pc are updated (i.e., pc[15:0] ? hs[ sptr ? 2] ) . when the program size is 64k word or more, the action taken is pc[19:0] ? hs[ sptr - 2]. example: sf_excep: nop // stack full exception service routine iret instruction set s3c k215/fk215 7- 58 jnzd ? jump not zero with delay slot format: jnzd s3ck215/fk215 instr uction set 7- 59 jp ? conditional jump (pseudo instruction) format: jp cc:4 imm:20 jp cc:4 imm:9 operation: if jr can access the target address, jp command is assembled to jr (1 word instruction) in linking time, else the jp is assembled to ljp (2 word instruction) instruction. there are 16 different conditions that can be used, as described in table 7-6. example: %1 ld r0, #10h // assume address of label %1 is 020dh jp z, %b1 // address at 0264h jp c, %f2 // address at 0265h %2 ld r1, #20h // assume address of label %2 is 089ch in the above example, the statement ?jp z, %b1? is assembled to jr instruction. assuming that current pc is 0264h and condition is true, next pc is made by pc[11:0] ? pc[11:0] + offset, offset value is ?64h + a9h? without carry. ?a9? means 2?s complement of offset value to jump backward. therefore next pc is 020dh. on the other hand, statement ?jp c, %f2? is assembled to ljp instruction because offset address exceeds the range of imm:9. instruction set s3c k215/fk215 7- 60 jr ? conditional jump relative format: jr cc:4 imm:9 cc:4: 4-bit condition code operation: pc[11:0] ? pc[11:0] + imm:9 if condition is true. imm:9 is a signed number, which is sign- extended to 12 bits when added to pc. there are 16 different conditions that can be used, as described in table 7-6. flags: ? note: unlike ljp, the target address of jr is pc-relative. in the case of jr, imm:9 is added to pc to compute the actual jump address, while ljp directly jumps to imm:20, the target. example: jr z, %1 // assume current pc = 1000h %1 ld r0, r1 // address at 10a5h after the first instruction is executed, next pc has become 10a5h if z flag bit is set to ?1?. the range of the relative address is from +255 to ?256 because imm:9 is signed number. s3ck215/fk215 instr uction set 7- 61 lcall ? conditional subroutine call format: lcall cc:4, imm:20 operation: hs[ sptr][15:0] ? current pc + 2, sptr ? sptr + 2, pc[15:0] ? imm[15:0] if the condition holds and the program size is less than 64k word. hs[ sptr][19:0] ? current pc + 2, sptr ? sptr + 2, pc[19:0] ? imm:20 if the condition holds and t he program size is equal to or over 64k word. pc[11:0] ? pc[11:0] + 2 otherwise. lcall instruction is used to call a subroutine whose starting address is specified by imm:20. flags: ? example: lcall l1 lcall c, l2 label l1 and l2 can be allocated to the same or other section. because this is a 2-word instruction, the saved returning address on stack is (pc + 2). instruction set s3c k215/fk215 7- 62 ld adr:8 ? load into memory format: ld adr:8, s3ck215/fk215 instr uction set 7- 63 ld @ idm ? load into memory indexed format: ld @ idm, instruction set s3c k215/fk215 7- 64 ld ? load register format: ld s3ck215/fk215 instr uction set 7- 65 ld ? load gpr:bankd, gpr:banks format: ld instruction set s3c k215/fk215 7- 66 ld ? load gpr, tbh/tbl format: ld s3ck215/fk215 instr uction set 7- 67 ld ? load tbh/tbl, gpr format: ld instruction set s3c k215/fk215 7- 68 ld spr ? load spr format: ld s3ck215/fk215 instr uction set 7- 69 ld spr0 ? load spr0 immediate format: ld spr0, #imm:8 operation: spr0 ? imm:8 ld spr0 loads an 7-bit immediate value into spr0. flags: ? example: given: eid = 1, idb = 0 (index register bank 0 selection) ld idh, #80h // idh point to page 80h ld id l1, #44h ld idl0, #55h ld sr0, #02h the last instruction set ie (global interrupt enable) bit to ?1?. special register group 1 (spr1) registers are not supported in this addressing mode. instruction set s3c k215/fk215 7- 70 ldc ? load code format: ldc s3ck215/fk215 instr uction set 7- 71 ljp ? conditional jump format: ljp cc:4, imm:20 cc:4: 4-bit condition code operation: pc[15:0] ? imm[15:0] if condition is true and the program size is less than 64k word. if the program is equal to or larger than 64k word, pc[19:0] ? imm[19:0] as long as the condition is true. there are 16 different conditions that can be used, as described in table 7-6. flags: ? note: ljp cc:4 imm:20 is a 2-word instruction whose immediate field directly specifies the target address of the jump. example: ljp c, %1 // assume current pc = 0812h %1 ld r0, r1 // address at 10a5h after the first instruction is executed, ljp directly jumps to address 10a5h if condition is true. instruction set s3c k215/fk215 7- 72 llnk ? linked subroutine call conditional format: llnk cc:4, imm:20 cc:4: 4-bit condition code operation: if condition is true, il[19:0] ? {pc[19:12], pc[11:0] + 2}. further, when the program is equal to or larger than 64k word, pc[19:0] ? imm[19:0] as long as the condition is true. if the program is smaller than 64k word, pc[15:0] ? imm[15:0]. there are 16 different conditions that can be used, as described in table 7-6. flags: ? note: llnk is used to conditionally to call a subroutine with the return address saved in the link register (il) without stack operation. this is a 2-word instruction. example: llnk z, %1 // address at 005ch, ilx:ilh:ill ? 00:00:5eh nop // address at 005eh %1 ld r0, r1 lret s3ck215/fk215 instr uction set 7- 73 lnk ? linked subroutine call (pseudo instruction) format: lnk cc:4, imm:20 lnk imm:12 operation: if lnks c an access the target address and there is no conditional code (cc:4), lnk command is assembled to lnks (1 word instruction) in linking time, else the lnk is assembled to llnk (2 word instruction). example: lnk z, link1 // equal to ?llnk z, link1? lnk link2 // equal to ?lnks link2? nop link2: nop lret subroutines section code, abs 0a00h subroutines link1: nop lret instruction set s3c k215/fk215 7- 74 lnks ? linked subroutine call format: lnks imm:12 operation: il[19:0] ? {pc[19:12], pc[11:0] + 1} and pc[11:0] ? imm:12 lnks saves the current pc in the link register and jumps to the address specified by imm:12. flags: ? note: lnks is used to call a subroutine with the return address saved in the link register (il) without stack operation. example: lnks link1 // address at 005ch, ilx:ilh:ill ? 00:00:5dh nop // address at 005dh link1: nop lret s3ck215/fk215 instr uction set 7- 75 lret ? return from linked subroutine call format: lret operation: pc ? il[19:0] lret returns from a subroutine by assigning the saved return address in il to pc. flags: ? example: lnk link1 link1: nop lret ; pc[19:0] ? ilx:ilh:ill instruction set s3c k215/fk215 7- 76 nop ? no operation format: nop operation: no operation. when the instruction nop is executed in a program, no operation occurs . instead, the instruction time is delayed by approximately one machine cycle per each nop instruction encountered. flags: ? example: nop s3ck215/fk215 instr uction set 7- 77 or ? bit-wise or format: or instruction set s3c k215/fk215 7- 78 or sr0 ? bit-wise or with sr0 format: or sr0, #imm:8 operation: sr0 ? sr0 | imm:8 or sr0 pe rforms the bit-wise or operation on sr0 and imm:8 and stores the result in sr0. flags: ? example: given: sr0 = 00000000b eid equ 01h ie equ 02h idb1 equ 04h ie0 equ 40h ie1 equ 80h or sr0, #ie | ie0 | ie1 or sr0, #00000010b in the first example, the statement ?or sr0, #eid|ie|ie0? set global interrupt( ie), interrupt 0(ie0) and interrupt 1(ie1) to ?1? in sr0. on the contrary, enabled bits can be cleared with instruction ?and sr0, #imm:8?. refer to instruction and sr0 for more detailed explanation about disabling bit. in the second example, the statement ?or sr0, #00000010b? is equal to instruction ei, which is enabling interrupt globally. s3ck215/fk215 instr uction set 7- 79 pop ? pop format: pop operation: sptr ? sptr ? 2 pop decrease sptr by 2. the top two bytes of the hardware stack are therefore invalidated. flags: ? example: given: sptr[5:0] = 001010b pop this pop instruction decrease sptr[5:0] by 2. therefore sptr[5:0] is 001000b. instruction set s3c k215/fk215 7- 80 pop ? pop to register format: pop s3ck215/fk215 instr uction set 7- 81 push ? push register format: push instruction set s3c k215/fk215 7- 82 ret ? return from subroutine format: ret operation: pc ? hs[ sptr - 2], sptr ? sptr ? 2 ret pops an address on the hardware stack into pc so that control returns to the subroutine call site. flags: ? example: given: sptr[5:0] = 001010b calls wait // address at 00120h wait: nop // address at 01000h nop nop nop nop ret after the first instruction calls execution, ?pc+1?, 0121h is loaded to hs[5] and hardware stack pointer sptr[5:0] have 001100b and next pc became 01000h. the instruction ret pops value 0121h on the hardware stack hs[sptr-2] and load to pc then stack pointer sptr[[5:0] became 001010b. s3ck215/fk215 instr uction set 7- 83 rl ? rotate left format: rl instruction set s3c k215/fk215 7- 84 rlc ? rotate left with carry format: rlc s3ck215/fk215 instr uction set 7- 85 rr ? rotate right format: rr instruction set s3c k215/fk215 7- 86 rrc ? rotate right with carry format: rrc s3ck215/fk215 instr uction set 7- 87 sbc ? subtract with carry format: sbc instruction set s3c k215/fk215 7- 88 sl ? shift left format: sl s3ck215/fk215 instr uction set 7- 89 sla ? shift left arithmetic format: sla |