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tmp04ch01fxxx(jtmp04ch01xxxs) 2002-12-11 1 toshiba cmos digital integrated circuit silicon monolithic tmp04ch01fxxx (jtmp04ch01xxxs) cmos 4 bit ll microcontroller (ll: low power consumption & low voltage operation) the tmp04ch00fxxx is a high-performance microcontroller designed to be in a variety of low-voltage products. it is a 4 bit cmos ll microcontroller with integrated a 4 bit high-performance cpu, memory (static work ram and program rom). lcd display ll controller driver, and a multi-function timer into a single chip. the basic features are as follows. features ? number of instructions: 56 ? minimum instruction execution time: 61 s (at 32.768 khz) 1 s (2 mhz/3.0 v) ? oscillating circuit : low speed-crystal oscillator (32.768 khz)/internal cr (33 khz at 1.5 v) high speed-crystal oscillator (2 mhz at 3.0 v)/external cr (200 khz at 1.5 v) ? built-in rom size : 16 k words (1 word = 16 bits) ? built-in ram size : work ram : 512 4 bits ? input pins : 4 pins (with interrupts) ? i/o pins : 12 pins (with 4 interrupts and mask option) ? output pins : 1 pin (buzzer) ? interruption : 2 external system (input pins, general purpose i/o pin) 2 internal system (timer/counter, timings) ? timer : 8 bits 2 ch or 16 bits 1 ch (software-selectable) ? lcd display driver controller: 52 seg 16 com ? built-in lcd driver power circuit ? watchdog timer : timer/counter can be used as watch dog timer ? power supply voltage : 1.5/3.0 v (typ.) mask option weight: 1.65 g (typ.)
tmp04ch01fxxx(jtmp04ch01xxxs) 2002-12-11 2 figure 1 block diagram seg1 to seg 52 com1 to com16 v 4 v 3 v 2 v 1 c 1 c 2 v xt v ss v dd bz test xh in xh out xl in xl out breset oscillator control test circuit reset work ram (2 k bits) interrupt control timer (8 bit/16 bit) i/n port i/o port display ram lcd control quadrupler voltage reglater bz control v 1 in1 to in4 io01 to io04 io11 to io14 io21 to io24 t4x core rom (16 k words)
tmp04ch01fxxx(jtmp04ch01xxxs) 2002-12-11 3 pin configuration 1. pin assignment pin no. pin name pin no. pin name pin no. pin name pin no. pin name 1 ? v 1 26 ? io21 51 ? s 22 76 ? s 47 2 ? c 1 27 ? io22 52 ? s 23 77 ? s 48 3 ? c 2 28 ? io23 53 ? s 24 78 ? s 49 4 ? v ss 29 ? io24 54 ? s 25 79 ? s 50 5 ? v xt 30 ? s 1 55 ? s 26 80 ? s 51 6 ? breset 31 ? s 2 56 ? s 27 81 ? s 52 7 ? xl in 32 ? s 3 57 ? s 28 82 ? com16 8 ? xl out 33 ? s 4 58 ? s 29 83 ? com15 9 ? v dd 34 ? s 5 59 ? s 30 84 ? com14 10 ? xh in 35 ? s 6 60 ? s 31 85 ? com13 11 ? xh out 36 ? s 7 61 ? s 32 86 ? com12 12 ? test 37 ? s 8 62 ? s 33 87 ? com11 13 ? bz 38 ? s 9 63 ? s 34 88 ? com10 14 ? in1 39 ? s 10 64 ? s 35 89 ? com9 15 ? in2 40 ? s 11 65 ? s 36 90 ? com8 16 ? in3 41 ? s 12 66 ? s 37 91 ? com7 17 ? in4 42 ? s 13 67 ? s 38 92 ? com6 18 ? io01 43 ? s 14 68 ? s 39 93 ? com5 19 ? io02 44 ? s 15 69 ? s 40 94 ? com4 20 ? io03 45 ? s 16 70 ? s 41 95 ? com3 21 ? io04 46 ? s 17 71 ? s 42 96 ? com2 22 ? io11 47 ? s 18 72 ? s 43 97 ? com1 23 ? io12 48 ? s 19 73 ? s 44 98 ? v 4 24 ? io13 49 ? s 20 74 ? s 45 99 ? v 3 25 ? io14 50 ? s 21 75 ? s 46 100 ? v 2 80 qfp100 81 51 100 1 30 50 31
tmp04ch01fxxx(jtmp04ch01xxxs) 2002-12-11 4 2. pin description pin name function v dd ? power supply ( + ) v ss ? power supply ( ? ) v xt ? voltage regulator1 output (output for only the mask option 3.0 v type) v 1 ? voltage regulator2 output v 2 to v 4 ? boosted voltage output c 1, c 2 ? capacitor pin for lcd booster xh in , xh out ? crystal/resister connection pin for high-speed oscillator xl in , xl out ? crystal connection pin for low-speed oscillator in1 to in4 ? input port (with interruption) io01 to io04 ? i/o port (with interruption) io11 to io14 ? i/o port io21 to io24 ? i/o port seg1 to seg52 ? lcd segment output com1 to com16 ? lcd common output bz ? buzzer output breset ? reset input (low active) test ? test input
tmp04ch01fxxx(jtmp04ch01xxxs) 2002-12-11 5 memory map 1. program rom program rom consists of 16 bits 1 word. op-code and operand are executed in one word units. program rom consists of 4 k words per page. the internal program rom area is 4 pages (16 k words). this program rom area can be used for constant data rom. in this case, it can be used in byte units (1 byte = 8 bits). ? note: use the call instruction to write the interrupt entry address. write nop for unused interrupts. example: call a ; int0 nop ; int1 call b ; int2 nop ; int3 nop ; int4 nop ; int5 nop ; int6 ? page 0 000h 0001h 0002h 0003h 0004h 0005h 0006h 0007h 0fffh 1000h 3fffh 15 8 7 0 upper 8 bit lower 8 bit 1 word page 1 to 3 reset start int0 int1 int2 int3 int4 int. entry address figure 2 program memory map
tmp04ch01fxxx(jtmp04ch01xxxs) 2002-12-11 6 2. work ram figure 3 work ram 7 15 23 31 39 47 55 63 6 14 22 30 38 46 54 62 5 13 21 29 37 45 53 61 4 12 20 28 36 44 52 60 3 11 19 27 35 43 51 59 2 10 18 26 34 42 50 58 1 9 17 25 33 41 49 57 0 8 16 24 32 40 48 56 f d b 9 7 5 3 1 e c a 8 6 4 2 0 f e d c b a 9 8 7 6 5 4 3 2 1 0 address page bank 0 bank 1 no. stack area
tmp04ch01fxxx(jtmp04ch01xxxs) 2002-12-11 7 work ram consists of 512 4 bits. r/w is performed at the address specified by bellows. (1) indirectly addressing mode (figure 4 (a)) dmb in f-reg, h, l-reg specify the work ram address. (dmb: bank, h-reg : page, l-reg: address) ld a, m: a ram (hl) (2) directly addressing mode (figure 4 (b)) immediate data (8 bits) in instruction specify the work ram page and address. bank is specified by dmb in f-reg. ldi 2ch, 0ah: ram (2ch) ah (3) index addressing mode (figure 4 (c) ) address (l-reg) is specified by the immediate data (4 bits) in instruction, and the other immediate data specify page. ldri 4h, 3h: ram (hl + 4h) ram (3h, l) l l + 1, a a ? 1 bank0, page8 to f area can be used as stack area. when using the ?call/calls? instruction or start the interruption routine, the data of program counter and program memory bank are stored in stack area. then, using ?ret? instruction, program return according to those data. and, using ?push? instruction, 8 bits data in a pair register can be stored in stack area. then, using ?pop? instruction, those data are returned to the register. maximum stack area is 64 (0 to 63), and each stack area consist of 8 bits. figure 4 addressing mode dmb hr lr ram address (a) indirectly addressing or xxxx xxxx instruction field xxxx xxxx dmb xxxx xxxx ram address (b) directly addressing yyyy + lr zzzz ram address instruction field (c) index addressing
tmp04ch01fxxx(jtmp04ch01xxxs) 2002-12-11 8 3. data ram tmp04ch01fxxx has display ram, and addressing and data read/write is decided by register file, as follows. when the data is read from/written into display ram. drce (pc6-bit2) is needed to be 1. addressing is decided by drr1 to drr4 (pd4) and drc1 to drc3 (pd5) (lsb is drr1, and msb is drc3) data is read/written by 8 bits which is set in drd1 to drd8 (pd6, pd7). to read from/written into display, only 8 bits transference instruction can be used. caution: 1. when ?halt? instruction is executed for the next instruction of the transference the data to display ram, the data of display ram is broken. 2. when ?halt? instruction is executed during drce is 1, the data of display ram is broken. therefore, be sure to set drce to 0 before executing the halt instruction. drd1 to 8 (pd6, pd7) are valid for only 8-bit transfer instructions. ? pc6 msb 3 drce 2 don 1 ce1 0 lsb drr4 pd4 drr3 drr2 drr1 ? pd5 msb 3 drc3 2 drc2 1 drc1 0 lsb drd4 pd6 drd3 drd2 drd1 drd8 pd7 msb 3 drd7 2 drd6 1 drd5 0 lsb
tmp04ch01fxxx(jtmp04ch01xxxs) 2002-12-11 9 figure 5 display ram drd 8 com4 1 1 1 1 com5 1 1 1 1 com6 1 1 1 1 com7 1 1 1 1 com1 1 1 1 1 com8 1 1 1 1 com2 1 1 1 1 com3 1 1 1 1 00h 01h 02h 32h 33h 34h 3fh 40h 41h 72h 73h 74h 7fh com9 1 1 1 1 com10 1 1 1 1 drd 7 drd 6 drd 5 drd 4 drd 3 drd 2 drd 1 s 1 s 2 s 3 s 51 s 52 s 1 s 2 s 51 s 52 com11 1 1 1 1 com12 1 1 1 1 com13 1 1 1 1 com14 1 1 1 1 com15 1 1 1 1 com16 1 1 1 1
tmp04ch01fxxx(jtmp04ch01xxxs) 2002-12-11 10 figure 6 lcd driver read data from pd6/pd7 (8-bit transfer). write data to pd6/pd7 (8-bit transfer). drd8 latch drd7 drd6 drd5 drd4 drd3 drd2 drd1 pd7 pd6 d0 d7 d6 d5 d4 d3 d2 d1 data ? drc3 drc2 drc1 drr4 drr3 drr2 drr1 pd5 pd4 a0 a6 a5 a4 a3 a2 a1 address latch latch latch latch latch latch read write latch dsta don drce ? pc6 latch latch ce s 52 out s 51 out s 50 out s 3 out s 2 out s 1 out output gate segment driver52 segment driver51 segment driver50 common driver1 common driver2 common driver14 common driver15 common driver16 display ram common select segment driver3 segment driver2 segment driver1 s 2 s 1 s 3 s 50 com2 com14 com1 v 4 v 3 v 2 c 1 c 2 v 1 v dd v ss seg/com = v ss 4 khz f l (low-speed clock) common/segment driver timing generator circuit voltage regulator booster clock on booster circuit for lcd bias s 51 s 52 com15 com16
tmp04ch01fxxx(jtmp04ch01xxxs) 2002-12-11 11 register file register files consist of (1) general-purpose registers, (2) system registers, and (3) peripheral i/o registers. figure 6 shows the overall configuration of register files. 1. general register 1. flag register: f-register (page/ad = 0/0) cf : carry flag zf : zero flag (0) : not use dmb : work ram bank 2. accumulater register: a-register ? ? ? ? (page/ad = 0/1) accumulator for arithmetic operations. when consecutive instructions are executed, used as a counter register. 3. h.l register (page/ad = 0/3 to 2) h.l register are used for work ram address setting with dmb. 4. bank register (page/ad = 0/7): b-register b-register is used for rom page. 0000 = page 0 0001 = page 1 0010 = page 2 0011 = page 3 5. e-register, d-register, p-register (b-register) (page/ad = 0/4, 0/5, 0/6, 0/7) general purpose register. when using rom as data table function, b, p, d, e-register are used for rom address setting. (data table function: user can use rom area for store the constant, and can access those constant by ldbl and ldbh instruction.) r07 3 msb 3 2 2 1 1 0 0 lsb r00 dmb msb 3 (0) 2 zf 1 cf 0 lsb f-register r03 hr3 msb 3 hr2 2 hr1 1 hr0 0 lsb h-register work ram page lr3 msb 3 lr2 2 lr1 1 lr0 0 lsb l-register work ram address r02
tmp04ch01fxxx(jtmp04ch01xxxs) 2002-12-11 12 2. system registers 1. stack pointer (page/ad = 1/0, 1/1) the stack pointer shows the location (63 to 0) in the stack area in work ram. 2. interrupt enable/disable registers (page/ad = 1/2, 1/3) enable/disable interrupts. there are five interrupt vectors (int0 to int4). writing data in the bit corresponding to an interrupt enables/disables the interrupt. the details are described in the section on peripheral circuits. 3. input/output registers (page/ad = 1/4, 1/5) used for the input/output pins (io11 to io14, io21 to io24). using the bit that corresponds to a pin, output data can be set or input data can be read. the details are described in the section on peripheral circuits. ? r11 sp32 sp16 sp8 sp4 r10 msb 3 sp2 2 sp1 1 ? 0 msb 3 2 1 0 ? r13 ? int4 int3 int2 r12 msb 3 int1 2 int0 1 (0) 0 msb 3 2 1 0 io24 r15 io23 io22 io21 io14 r14 msb 3 io13 2 io12 1 io11 0 msb 3 2 1 0
tmp04ch01fxxx(jtmp04ch01xxxs) 2002-12-11 13 3. peripheral i/o registers registers used to control peripheral circuits specific to the product are allocated to pages 2 to 7. the details are described in the section on peripheral circuits. note: a precaution relating to writes to system registers/peripheral i/o registers. writing to system register and i/o registers is performed in synchronization with w. because rising edges of w coincides with the timing at which write data is output on the data bus, it is possible that incorrect data is output to the peripheral circuits for a very short period of time. please take this into account when programming. peripheral circuits data bus w d q latch c d q latch c d q latch c d q latch c clk f0 f1 f2 f3 register write timing ( w) outputs incorrect data. write data
tmp04ch01fxxx(jtmp04ch01xxxs) 2002-12-11 14 address 0 1 2 3 4 5 6 7 0 2 4 6 8 bit address lower4bit upper4bit l4bit h4bit l4bit h4bit l4bit h4bit page (rfb) r/w read write read write read write read write read write read write read write read write bit 3 bit 2 bit 1 0 msb lsb bit 0 f register a register l register h register e register d register p register b register bit 3 0 int2 iod14 ioo14 iod24 ioo24 bit 2 int1 iod13 ioo13 iod23 ioo23 bit 1 stack pointer (sp) int0 int4 iod12 ioo12 iod22 ioo22 1 (p1x) msb lsb bit 0 0 0 int3 iod11 ioo11 iod21 ioo21 bit 3 ind4 iod04 ioo04 rst4 bit 2 ind3 iod03 ioo03 lowcp rst3 bit 1 ind2 iod02 ioo02 cpmode2 rst2 2 (pax) msb lsb bit 0 ind1 iod01 ioo01 cpmode1 rst1 bit 3 bit 2 bit 1 3 (pbx) msb lsb bit 0 bit 3 iin4 iie4 bit 2 eselt iin3 iie3 drce bit 1 eselio iin2 iie2 don p2 4 (pcx) msb lsb bit 0 eseli iin1 iie1 ioie0 dsta p1 bit 3 ti4 1/2 tir4 tie4 drr4 drd4 drd8 bit 2 ti3 4/8 tir3 tie3 drr3 drc3 drd3 drd7 bit 1 ti2 16/32 tir2 tie2 drr2 drc2 drd2 drd6 5 (pdx) msb lsb bit 0 ti1 128/256 tir1 tie1 drr1 drc1 drd1 drd5 bit 3 tcr14 set14 tcr18 set18 tc1en 2/4 k bit 2 tcr13 set13 tcr17 set17 cks13 tc1r bz3 bit 1 tcr12 set12 tcr16 set16 cks12 cmpen1 tci1e bz2 6 (pex) msb lsb bit 0 tcr11 set11 tcr15 set15 cks11 wdt1 tci1r bz1 bit 3 tcr24 set24 tcr28 set28 tcps tc2en bit 2 tcr23 set23 tcr27 set27 cks23 tc2r bit 1 tcr22 set22 tcr26 set26 cks22 cmpen2 tci2e 7 (pfx) msb lsb bit 0 tcr21 set21 tcr25 set25 cks21 tci2r figure 7 register file note: blank columns are indeterminate.
tmp04ch01fxxx(jtmp04ch01xxxs) 2002-12-11 15 peripheral circuit each peripheral circuits can be accessed (read/write/circuit setting) by register files. 1. oscillator block the cpu clock is generated by the asynchronous oscillator switching circuit which has low-speed and high-speed clock oscillator circuit. this block also provides the clock for the timer circuit, lcd driver, quadrupler. oscillation mode is controlled by register files ?cpmode1? and ?cpmode2? (page/ad = 2/6), as follows. cpmode 1 ? cpmode 2 ? low- speed osc high- speed osc system cp ? mode name 0 ? 0 ? off ? off ? off ? (cpm0) 1 ? 0 ? on ? off ? low-speed ? (cpm1) 0 ? 1 ? off ? on ? high-speed ? (cpm2) 1 ? 1 ? on ? on ? high-speed ? (cpm3) cpmode 1, 2 are initially 1 (cpm3). ?lowcp? is the display clock control bit. when ?lowcp? is set to 1, low-speed osc clock is supplied to lcd circuit. ?lowcp? is initially ?0?. even if lowcp is set to 1, clock cannot be occupied to display circuit during low-speed osc stopped, and display cannot be shown. low-speed osc circuit can select x?tal or internal cr oscillation by mask option. high-speed osc circuit can select x?tal or external cr oscillation by mask option. setting a register to cpm1 and executing a halt instruction sets the mode to halt (system cp off, high-speed oscillator off, low-speed oscillator on). setting a register to cpm0 and executing a halt instruction sets the mode to stop (system cp off, high-speed oscillator and low-speed oscillators off). even if, mode is changed to mode 0 from mode 1/2/3, there are no changing until use ?halt? instruction. the high/low-speed osc circuit has warm up function. the warm-up function disables the crystal oscillator as the system clock from when the crystal oscillator starts oscillation to when the frequency stabilizes. the warm-up circuit in the high-speed crystal oscillator circuit consists of a 15-stage binary counter. the warm-up time is 16,384 pulses of the high-speed clock. the warm-up circuit in the low-speed crystal oscillator circuit consists of a 9-stage binary counter. the warm-up time is 256 pulses of the high-speed clock. the low-speed oscillation does not have enough warm-up time, therefore, when the oscillation is started, software need to make warming up time enoughly. set the warm-up time by software to approx. 500 ms as standard. when the system cp is changed between low and high (cpm1 cpm2/3 or cpm2 cpm1), changing system cp waits to finish the warming up time. also that until the system cp is changed, instructions are executed with the previous system cp. if the cr oscillator is selected as the high- or low-speed oscillator circuit, the warm-up function is disabled. msb 3 lowcp 2 cpmode2 1 cpmode1 0 lsb ? pa6
tmp04ch01fxxx(jtmp04ch01xxxs) 2002-12-11 16 tmp04ch01fxxx has 21 bits divider. the divider circuit of bits 1 to 6 generates a clock from 1 mhz to 32 khz by dividing the high-speed clock (2 mhz). the divider circuit of bits 7 to 21 generates a clock from 16 khz to 1 hz by dividing the 32 khz clock. when the low-speed oscillator circuit is on (cpm1/cpm3), a low-speed clock (32 mhz) is supplied to the divider circuit of bits 7 to 21. when the low-speed oscillator circuit is off (cpm2), output from bit 6 is supplied. figure 9 divider circuit 1 mhz system cp generator circuit 1 2 3 4 5 6 512 khz 256 khz 128 khz 16 khz 16 khz 7 8 9 10 11 12 8 khz 4 khz 2 khz 1 khz 256 hz 13 14 15 16 17 18 128 hz 64 hz 32 hz 16 hz 19 20 21 8 hz 4 hz 2 hz 512 hz 32 khz binary counter f h high-speed clock (2 mhz) f l low-speed clock (32 khz) 1 hz binary counter automatically shifts to cpm3 mode. (note 2) high-speed clock warm-up set the oscillation mode to cpm2. reset start mode high-speed clock: on low-speed clock: on system clock: stop cpm0 (stop mode) high-speed clock: off low-speed clock: off system clock: stop cpm1 high-speed clock: off low-speed clock: on system clock: low-speed halt mode high-speed clock: off low-speed clock: on system clock: stop cpm2 high-speed clock: on low-speed clock: off system clock: high-speed cpm3 mode high-speed clock: on low-speed clock: on system clock: high-speed interrupt set the oscillation mode to cpm0, then execute halt instruction. set the oscillation mode to cpm3. (note 2) high-speed clock warm-up set the oscillation mode to cpm1 (note 1) low-speed clock warm-u p set the oscillation mode to cpm2. (note 2) high-speed clock warm-up interrupt executes halt instruction. set the oscillation mode to cpm3. set the oscillation mode to cpm1. (note1) low-speed clock warm-up note 1: low-speed clock warm-up if x?tal oscillation circuit is selected for low-speed oscillation, it takes some time before low-speed oscillation is used for system clock. note 2: high-speed clock warm-up if x?tal oscillation circuit is selected for high-speed oscillation, it takes some time before high-speed oscillation is used for system clock. figure 8 mode transition
tmp04ch01fxxx(jtmp04ch01xxxs) 2002-12-11 17 the reset for this divider circuit is done by register file rst1 to rst4 (pa7w). rst1: binary counter 1 to 6 (2 m to 32 khz) reset rst2: binary counter 7 to 12 (16 k to 512 hz) reset rst3: binary counter 13 to 17 (256hz to 16 hz) reset rst4: binary counter 18 to 21 (8hz to 1 hz) reset (when using 2 mhz, 32 khz crystal) caution: 1. do not set system cp to low speed when the low-speed osc is not in operation or before stable. 2. do not set system cp to high speed when the high-speed osc is not in operation or before stable. 3. and, when low-speed osc is on, low-speed frequency is supplied from 7th bit divider circuit (when use 2 mhz crystal for high-speed osc and 32 khz crystal for low-speed osc and the mode is cpm3, 1 mhz to 32 khz are made by 2 mhz crystal, 16 khz to 1 hz are made by 32 khz crystal. and when the mode is cpm2, all frequency are made by 2 mhz crystal. therefore if the mode change between cpm1 and cpm2 or cpm2 and cpm3, the frequency which is supplied by binary counter 7 to 21 shift the timing). 4. when operated with a 1.5 v power supply, the oscillation frequency on the high-speed side is 200 khz (max), so that the output of binary counter 6 is 3.125 khz (max). consequently, if the mode is changed from cpm1 or cpm3 to cpm2 or from cpm2 to cpm1 or cpm3, the generated timing changes greatly. 5. when the crystal oscillator circuit is used for low-speed oscillation, a long time is required from oscillation stop to oscillation start. the lcd circuit operates using a low-speed clock. lcd cannot be performed until oscillation starts. after power on, operate the low-speed oscillator circuit at all times and do not change to stop mode. example 1 start mode (after warming up, program start at address 0000.) cpm3 (high/low speed on, syscp = high, lowcp off) ld 26o, 7h cpm3 (high/low speed on, syscp = high, lowcp on) ld 26o, 4h cpm0 (high/low speed on, syscp = high, lowcp on) (there are no change after shift to cpm0) halt stop mode (high/low-speed osc, stop, syscp off, lowcp off) when an interruption occurs, the mode is changed to start mode and program start at the address which is decided by each interruption (refer to figure 2). example 2 start mode (after warming up, program start at address 0000.) cpm3 (high/low speed on, syscp = high, lowcp off) ld 26o, 5h cpm1 (low speed on, syscp = low, lowcp on) halt halt mode (high speed osc off, low-speed osc on, syscp off, lowcp on) when an interruption occurs, the mode is changed to slow mode (cpm1) and program start at the address which is decided by each interruption. rst4 msb 3 rst3 2 rst2 1 rst1 0 lsb pa7w
tmp04ch01fxxx(jtmp04ch01xxxs) 2002-12-11 18 example 3 start mode (after warming up, program start at address 0000.) cpm3 (high/low speed on, syscp = high, lowcp off) ld 26o, 7h cpm3 (high/low speed on, syscp = high, lowcp on) ld 26o, 4h cpm0 (high/low speed on, syscp = high, lowcp on) (there are no change after shift to cpm0.) ld 26o, 7h cpm3 (high/low speed on, syscp = high, lowcp on) example 4 (after reset) breset f h f l system cp unstable osc unstable osc stop mode warming up for high-speed osc (16384 clock, 7.8 ms/2 mhz) warming up for low-speed osc (256 clock, 7.8 ms/32 khz) 2.86 s/2 mhz cpu on (cpm3)
tmp04ch01fxxx(jtmp04ch01xxxs) 2002-12-11 19 example 5 (cpm3 1) example 6 (cpm1 2) note: no warm-up is provided for high-speed and low-speed rc oscillations by mask options. f h f l system cp cpm3 max 64 s/32 khz command cpm3 1 cpm1 cpm1 2 f h f l system cp max 1.43 s/2 mhz unstable osc cpm1 16384 clock (7.8 ms/2 mhz) cpm2 command warming up for high-speed osc max 15 s/ 32 khz
tmp04ch01fxxx(jtmp04ch01xxxs) 2002-12-11 20 system reset by watchdog timer release from halt/stop mode breset 16 h z q tff ? c q r 8 h z 4 h z 2 h z 1 h z 512 h z 256 h z 128 h z 64 h z 32 h z 16 kh z oschstop locpen osclstop hicpen timing control set cpm3 cpstop set cpm1/cpm3 cp mode1 cp mode2 lowcp ? pa6 latch latch latch low-speed (cr) oscillator circuit ?h? to lcd driver timing generator syscp f0 f1 f2 f3 basic timing high-speed (cr) oscillator circuit xh in xh out 1 mh z q tff ? c q r rst1 rst2 rst3 rst4 pa7w 512 kh z 256 kh z 128 kh z 64 kh z q tff ? c q r 8 kh z 4 kh z 2 kh z 1 kh z q tff ? c q r r r 32 kh z figure 10 oscillator circuit/divider circuit
tmp04ch01fxxx(jtmp04ch01xxxs) 2002-12-11 21 2. interruption block interruption is supplied by in1to in4, io01 to io04, timer/counter, timing. (interruption priority) interruption priority can be selected by register file p1 and p2. interrupt priority is valid only when multiple interrupts occur simultaneously. p1 and p2 are initially 0. p1 ? p2 ? int0 ? int1 ? int2 ? int3 ? int4 0 ? 0 ? iin ? ioin ? tin ? tcin1 ? tcin2 1 ? 0 ? ioin ? iin ? tin ? tcin1 ? tcin2 0 ? 1 ? tin ? iin ? ioin ? tcin1 ? tcin2 1 ? 1 ? tcin1 ? iin ? ioin ? tin ? tcin2 iin: in1 to in4, ioin: io01 to io04, tin: timing, tcin1/2: timer/counter1/2 (interruption enable/disable) each interruption (iin, ioin, tin, tcin1, tcin2) is decided enable/disable as follows. iin : iie1 to iie4 (r42-bit 0 to 3) ioin : ioie0 (r43-bit 0) tin : tie1 to tie4 (r53-bit 0 to 3) tcin1 : tci1e (r64-bit 1) tcin2 : tci2e (r74-bit 1) after deciding priority by p1, p2 each interruption is decided enable/disable by int0 to int4. disable the unnecessary interrupts in your application by initial settings of iie1-4, ioie, tie1-4, and tci1e/2e. int0 to int4 are initially 0 (disable) int0 to int4 = 0 int0 to int4 disable = 1 int0 to int4 enable (interrupt reset) after an interrupt occurs, reset the interrupt following the procedures described below. first, reset in1 to in4 interrupt/io01 to io04 interrupt/timing interrupt/timer counter 1 interrupt/timer counter 2 interrupt. then reset the signal ?release from halt/stop mode? by executing a transfer instruction to r12 or r13. (re-enable interrupts by executing a transfer instruction to r12 or r13, as you need.) how to deactivate respective interrupts will be explained in the sections which describe each of the interrupts. ? r13 ? int4 int3 int2 r12 msb 3 int1 2 int0 1 (0) 0 lsb ? pc7 msb 3 ? 2 p2 1 p1 0 lsb (higher) priority (lower)
tmp04ch01fxxx(jtmp04ch01xxxs) 2002-12-11 22 figure 11 interruption circuit block int3 int4 ? ? r13 ? int0 int1 int2 r12 p1 p2 ? ? pc7 int0 in1 to in4 interrupt io01 to io04 interrupt timing interrupt timer counter 1 interrupt timer counter 2 interrupt priority selector s q rsff ? r executes transfer instructions to r12/r13 release from halt/stop mode. interrupt generation ?
09*<0; interrupt request interrupt vector executes ret instruction. int1 int2 int3 int4 iint0 iint1 iint2 iint3 iint4 iin ioin tin tcin1 tcin2 input output p2 p1 int4 int3 int2 int1 int0 0 0 tcin2 tcin1 tin ioin iin 0 1 tcin2 tcin1 tin iin ioin 1 0 tcin2 tcin1 ioin iin tin 1 1 tcin2 tin ioin iin tcin1 p1 p2 r latch latch latch latch latch latch latch
tmp04ch01fxxx(jtmp04ch01xxxs) 2002-12-11 23 2-1. iuput/inoutput interruption (interruption enable/disable) iie1 = 0 in1 interruption disable 1 in1 interruption enable iie2 = 0 in2 interruption disable 1 in2 interruption enable iie3 = 0 in3 interruption disable 1 in3 interruption enable iie4 = 0 in4 interruption disable 1 in4 interruption enable iie1 to iie4 are initially 0 (in1 to in4 interruption disable). ioie0 = 0 io01 to io04 interruption disable 1 io01 to io04 interruption enable ioie0 is initially 0 (disable). interruption enable/disable bit can use as interruption reset. when the interruption occurs and after recognizing the interruption, it can be resetted int latch by setting iie1 to iie4 or ioie0. (interruption data read) interruption data of in1 to in4 can be read by register file iin1 to iin4. example ld 42o, 0fh (set enable to in1 to in4 interruption) ld m, 41o (read in1 to in4 interruption) ld 42o, 0eh (reset in1 interruption) ld 12o, 0fh (set enable to int0 to int2) ld 13o, 0fh (set enable to int3 to int4) ld 42o, 0fh (set enable to in1 to in4 interruption) iie4 pc2 msb 3 iie3 2 iie2 1 iie1 0 lsb iin4 pc1r msb 3 iin3 2 iin2 1 iin1 0 lsb ? pc3 msb 3 ? 2 ? 1 ioie0 0 lsb in1 interruption occurs. program goes to the address which is decided by each interruption. recognize which interruption is occurred. (recognize in1 interruption is occurred.)
tmp04ch01fxxx(jtmp04ch01xxxs) 2002-12-11 24 figure 12 in1 to in4 interrupts h in1 h in2 h in3 h in4 in1 to in4 interrupt (iin) iie1 iie2 iie3 iie4 pc2 latch latch latch latch eseli eselo eselt ? pc0 latch latch latch iin1 iin2 iin3 iin4 pc1r to timing interrupt circuit to io01 to io04 ports ind1 ind2 ind3 ind4 pa0r r r r r d q dff c r d q dff c r d q dff c r d q dff c r latch latch latch latch latch latch latch
tmp04ch01fxxx(jtmp04ch01xxxs) 2002-12-11 25 note: disabling input or input/output interrupts using pc2 or pc3 is valid only when a rising edge interrupt (see 4, input/output ports) is selected. if a level interrupt is selected, disabling interrupts using pc2 or pc3 is invalid. figure 13 io01 to io04 interrupts h io01 h io02 h io03 h io04 io01 to io04 interrupt (ioin) ioie ? ? ? pc3 latch eseli eselo eselt ? pc0 latch latch latch to timing interrupt circuit to in1 to in4 ports iod01 iod02 iod03 iod04 pa1r d q dff c r d q dff c r d q dff c r d q dff c r h mask option r h r h r h r ioo01 ioo02 iod03 ioo04 pa1w latch latch latch latch
tmp04ch01fxxx(jtmp04ch01xxxs) 2002-12-11 26 2-2. timing interruption (timing interruption selecting) timing interruptions are selectable by register file (pd1) 128/256, 16/32, 4/8, 1/2. 128/256, 16/32, 4/8 and 1/2 are initially 0 (1 hz, 4 hz, 16 hz, 128 hz is selected). 128/256 = 0 128 hz int. select 1 256 hz int. select 16/32 = 0 16 hz int. select 1 32 hz int. select 4/8 = 0 4 hz int. select 1 8 hz int. select 1/2 = 0 1 hz int. select 1 2 hz int. select (timing interruption enable/disable) selected timing interruption can be controlled enable/disable by register file (pd3) tie1 to tie4 (r53). tie1 to tie4 are initially 0 (disable). tie1 = 0 1 hz or 2 hz int. disable ? 1 1 hz or 2 hz int. enable tie2 = 0 4 hz or 8 hz int. disable 1 4 hz or 8 hz int. enable tie3 = 0 16 hz or 32 hz int. disable 1 16 hz or 32 hz int. enable tie4 = 0 128 hz or 256 hz int. disable 1 128 hz or 256 hz int. enable 1/2 pd1 msb 3 4/8 2 16/32 1 128/256 0 lsb tie4 pd3 msb 3 tie3 2 tie2 1 tie1 0 lsb
tmp04ch01fxxx(jtmp04ch01xxxs) 2002-12-11 27 (timing interruption reset) the timing interruption for the selected timing interruption is reset by register files tir1 to tir4 (pd2w). tir1 to tir4 are initially 0 (disable). tir1 = 1 1 hz or 2 hz interruption reset tir2 = 1 4 hz or 8 hz interruption reset tir3 = 1 16 hz or 32 hz interruption reset tir4 = 1 128 hz or 256 hz interruption reset (timing interruption read) selected timing interruption can be read by register file ti1 to ti4 (pd0r). ti1: interruption data of 1 hz or 2 hz ti2: interruption data of 4 hz or 8 hz ti3: interruption data of 16 hz or 32 hz ti4: interruption data of 128 hz or 256 hz (interruption edge selection) tin interruption can be selected the reading point ( or ) by register file eselt. estlt is initially 0 (rising edge). eselt = 0: interruption at rising edge of timing int. 1: interruption at down edge of timing int. example ld 51o, 01h (256 hz, 16 hz, 4 hz and 1 hz select) ld 53o, 07h (256 hz disable, 16 hz, 4 hz, 1 hz enable) when the 1hz interruption occurs. ld m, 50o (read timing interruption) recognize 1hz interruption. ld 52o, 01h (reset 1hz interruption) note: a mode transition from cpm1 or cpm3 to cpm2 or from cpm2 to cpm1 or cpm3 causes the timings of binary counters 7-21 to change. therefore, the timing interrupts also have their timings changed. tir4 pd2w msb 3 tir3 2 tir2 1 tir1 0 lsb ti4 pd0r msb 3 ti3 2 ti2 1 ti1 0 lsb ? pc0 msb 3 eselt 2 (eslio) 1 (eseli) 0 lsb
tmp04ch01fxxx(jtmp04ch01xxxs) 2002-12-11 28 figure 14 timing interrupt circuit h timing interrupt (tin) 1/2 4/8 16/32 128/256 pd1 latch eseli eselo eselt ? pc0 latch latch latch to in1 to in4 ports d q dff c r ti1 ti2 ti3 ti4 pd0r tie1 tie2 tie3 tie4 pd3 latch to io01 to io04 ports latch latch latch h d q dff c r h d q dff c r h d q dff c r h h d q dff c r h h d q dff c r tim1 2 h z tir1 tir2 tir3 tir4 pd2w 1 h z tim2 8 h z 4 h z tim3 32 h z 16 h z tim4 256 h z 128 h z latch latch latch d q dff c r d q dff c r
tmp04ch01fxxx(jtmp04ch01xxxs) 2002-12-11 29 2-3. 8 bits/16 bits timer counter interruption when timer/counter1, 2 overflow or coincide with setting time/count each interruption occurs. tci1e/tci2e = 0 timer/counter1, 2 interruption disable = 1 timer/counter1, 2 interruption enable tci1r/tci2r = 1 timer/counter1, 2 interruption reset tci1e, tci2e and tci2r are initially 0 (disable). ? pe4 msb 3 ? 2 tci1e 1 tci1r 0 lsb ? pf4 msb 3 ? 2 tci2e 1 tci2r 0 lsb r/w w r/w w
tmp04ch01fxxx(jtmp04ch01xxxs) 2002-12-11 30 3. timer/counter the timer/counter circuit can use as 8 bit 2ch or 16 bit 1ch timer/counter. and there time/counter can be use as general timer/counter, watch dog timer, or multi interruption timer. 8 bits/16 bits can be changed by register file tcps. and input frequency also can be changed by register cks11 to cks13 and cks21 to cks23, as follows. cks 11 ? cks 12 ? cks 13 ? input frequency for timer counter1 (f h = 2 mhz z f l = 32 khz) 0 ? 0 ? 0 ? f h /2 21 (f l /2 15 ) ? 1 hz (1.0 s) 1 ? 0 ? 0 ? f h /2 12 (f l /2 6 ) ? 512 hz (19.5 ms) 0 ? 1 ? 0 ? f h /2 8 (f l /2 2 ) ? 2 13 hz (122 s) 1 ? 1 ? 0 ? f h /2 3 ? 2 18 hz (3.81 s) ? ? ? ? 1 ? off ? cks 21 ? cks 22 ? cks 23 ? input frequency for timer counter2 (f h = 2 mhz z f l = 32 khz) 0 ? 0 ? 0 ? f h /2 15 (f l /2 9 ) ? 64 hz (15.6 ms) 1 ? 0 ? 0 ? f h /2 9 (f l /2 3 ) ? 2 12 hz (244 s) 0 ? 1 ? 0 ? f h /2 5 ? 2 16 hz (15.2 s) 1 ? 1 ? 0 ? f h /2 2 ? 2 19 hz (1.90 s) ? ? ? ? 1 ? off ? tcps = 0 8 bit 2 ch timer/counter = 1 16 bit 1 ch timer/counter when timer/counter is used as 16 bits timer, timer2 is used as lower bits. and cks11 to cks13 are ignored. input frequency is decided by cks21 to cks23. cks11 to cks13, cks21 to cks23 and tcps are initially 0. (timer/counter1 : 1hz, timer/counter2: 64 hz, 8 bit 2 ch) caution: 256 khz of timer/counter1, 512 khz, 64 khz of timer/counter2 can be used when high-speed osc is on. ? pe2 msb 3 cks13 2 cks12 1 cks11 0 lsb tcps pf2 msb 3 cks23 2 cks22 1 cks21 0 lsb
tmp04ch01fxxx(jtmp04ch01xxxs) 2002-12-11 31 timer function can be selected by register file/wdt1 and cmpen1, 2. timer/counter1 can be used as watch dog timer. and input frequency can be controlled by register file tc1en and tc2en. timer/counter is resetted by register file tc1r, tc2r. timer/counter1 setting is made in pe3. timer/counter2 setting is made in pf3. all the bits of pe3 and pf3 are initially 0. pe3 wdt1 = 0: used as 8-bit timer/counter. = 1: used as watchdog timer. cmpen1 = 0: an interrupt is generated if timer/counter1 overflows. (the entire system is reset if wdt1 = 1.) = 1: an interrupt is generated if timer/counter1 values match time/count set values (the entire system is reset if wdt1 = 1.) tc1r = 1: timer/counter1 is reset (cleared). timer/counter1 resumes counting up after reset. (refer to the timing chart below.) tc1en = 0: reference clock input on timer/counter1 is stopped. = 1: reference clock input on timer/counter1 is started. pf3 bit 0 = 1: timer/counter2 cannot be used as 8-bit timer/counter. = 0: timer/counter2 is used as 8-bit timer/counter. cmpen2 = 0: an interrupt occurs if timer/counter2 overflows. = 1: an interrupt occurs if timer/counter2 values match time/count set values. tc2r = 1: timer/counter2 is reset (cleared). timer/counter2 resumes counting up after reset. (refer to the timing chart below.) tc2en = 0: reference clock input on timer/counter2 is stopped. = 1: reference clock input on timer/counter2 is started. timing chart for timer/counter 1/2 reset pe3 pf3 tc1en msb 3 tc1r 2 cmpen1 1 wdt1 0 lsb tc2en msb 3 tc2r 2 cmpen2 1 (note) 0 lsb r/w r/w r/w r/w w r/w w note: writing 1 invalidates tc2 interrupts. tc1r/tc2r syscp f0 f2 count up count up timer/counter reset write reset count up starts
tmp04ch01fxxx(jtmp04ch01xxxs) 2002-12-11 32 timer/counter1,2 data can read from register file tcr11 to tcr18 and tcr21 to tcr28. timer/counter1, 2 comparison data is set by register file set11 to set18 and set21 to set28. set11 to set18 and set21 to set28 are initially 0. caution: 1. when generating an interrupt for the timer/counter by comparing it with the setup value (set11 to set18, set21 to set28) or resetting the system, set the setup values in register files set11 to set18 and set21 to set28 before enabling cmpen1 and cmpen2. 2. when generating an interrupt by a 16-bit timer by comparing it with the setup value, enable all of cmpen1, cmpen2, tc1en, and tc2en using instructions. 3. since the setup values and timer/counter values both are 0 after initialization, an interrupt is generated or the system is reset immediately when cmpen1 is enabled. 4. since a mode transition from cpm1 or cpm3 to cpm2 or from cpm2 to cpm1 or cpm3 causes the timing of the binary counters 7-21 to change, the timer/counters also have their timings changed. 5. do not change the timer/counter from 8 bits to 16 bits in the middle of operation after the timer/counter has started counting, because such a change could cause the data to be destroyed. tcr18 pe1r tcr17 tcr16 tcr15 tcr14 pe0r msb 3 tcr13 2 tcr12 1 tcr11 0 lsb tcr28 pf1r tcr27 tcr26 tcr25 tcr24 pf0r tcr23 tcr22 tcr21 set18 pe1w set17 set16 set15 set14 pe0w msb 3 set13 2 set12 1 set11 0 lsb set28 pf1w set27 set26 set25 set24 pf0w set23 set22 set21
tmp04ch01fxxx(jtmp04ch01xxxs) 2002-12-11 33 figure 15 timer/counter cks11 cks12 cks13 ? pe2 latch latch latch 1 hz 256 khz 512 hz 8 khz set11 set12 set13 set14 pe0w latch latch latch latch set15 set16 set17 set18 pe1w latch latch latch latch clock out multiplexer a1 a2 a3 a4 a5 a6 a7 a8 b1 b2 b3 b4 b5 b6 b7 b8 a = b in a < b in q1 q2 q3 q4 q5 q6 q7 q8 q1 q2 q3 q4 q5 q6 q7 q8 reset clock pe3 d q latch c r wdt1 cmp en1 tc1r tc1en latch latch latch a = b out (1) a < b out (1) 8-bit magnitude comparator (1) h d q dff c r tcr11 tcr12 tcr13 tcr14 tcr15 tcr16 tcr17 tcr18 pe0r pe1r s q rsff h r tcin1 system reset by watchdog timer tci1r tci1e ? ? pe4 latch 8-bit counter (1) cks21 cks22 cks23 tcps pe2 latch latch latch 64 hz 512 khz 4 khz 64 khz set21 set22 set23 set24 pe0w latch latch latch latch set25 set26 set27 set28 pe1w latch latch latch latch clock out multiplexer a1 a2 a3 a4 a5 a6 a7 a8 b1 b2 b3 b4 b5 b6 b7 b8 q1 q2 q3 q4 q5 q6 q7 q8 q1 q2 q3 q4 q5 q6 q7 q8 reset clock pf3 d q latch c r ? cmp en2 tc2r tc2en latch latch latch a = b out (2) a < b out (2) 8-bit magnitude comparator (2) h d q dff c r tcr21 tcr22 tcr23 tcr24 tcr25 tcr26 tcr27 tcr28 pf0r pf1r s q rsff h r tcin2 tci2r tci2e ? ? pf4 latch 8-bit counter (2) latch
tmp04ch01fxxx(jtmp04ch01xxxs) 2002-12-11 34 4. input/io ports (refer to figure 21) tmp04ch01fxxx has 4 inputs and 12 i/o ports. 4 input and 4 i/o ports have interruption. also, these ports have a mask option available. ? 4-1. input (in1 to in4) each input data can be read by register file ind1 to ind4. ? ? each input interruption function can be set enable/disable by register file iie1 to iie4. ? ? iie1 to iie 4 = 0 in1 to in4 each interruption disable = 1 in1 to in4 each interruption enable ? note 1: iie1 to iie4 interrupt disable/enables are register files that are effective when rising-edge interrupts are selected. when level interrupts are selected, interrupts are disabled/enabled by the data input from ports. in this case, therefore, interrupts cannot be disabled/enabled by the register files. after the level-triggered interrupt is selected, do not apply 61- s or less pulse (low speed, two cycles) to the in pin. malfunction may occur. 4 inputs (in1 to in4) interruption data can be read by register file iin1 to iin4. ? note 2 interrupt data io01 to io04 cannot be read out. only the data input form ports can be read out. (refer to figure 13.) interrupt timings (rising edge/evel) can be selected using register file eseli. ? ? eseli = 0 in1 to in4: interruption at rising edge of input int. 1 in1 to in4: high level of input int. ? input level-triggered interrupts are possible when eseli = 1. in this case, if interrupts have been enabled by register files int0-4, the interrupt remain asserted while the input level is high. ? ? ind4 pa0r msb 3 ind3 2 ind2 1 ind1 0 lsb iie4 pc2 msb 3 iie3 2 iie2 1 iie1 0 lsb iin4 pc1r msb 3 iin3 2 iin2 1 iin1 0 lsb int0 to int4 enable/disable int in figure 16 interruption by high level-read ? pc0 msb 3 (eselt) 2 (eselio) 1 eseli 0 lsb
tmp04ch01fxxx(jtmp04ch01xxxs) 2002-12-11 35 4-2. i/o ports (io01 to io04, io11 to io14, io21 to io24) each input data can be read by following register file, when using input port. iod01 to iod04 have interruption, each interruption can be disable/enable by register file ioie0. (four interrupt sources are collectively disabled/enabled by ioie0.) ioie0 = 0 io01 to io04 are disabled. 1 io01 to io04 are enabled. note: the io01 to io04 interrupt disable/enables are the register files that are effective when rising-edge interrupts are selected. when level interrupts are selected, interrupts are disabled/enabled by the data input from ports. in this case, therefore, interrupts cannot be disabled/enabled by the register files. after the level-triggered interrupt is selected, do not apply 61- s or less pulse (low speed, two cycles) to the io0 pin. malfunction may occur. io01 to io04 interruption recoginized timing (rising edge/high level) can be selected by register file eselio. eselio = 0 interruptions io01 to io04 are rising edge-triggered. 1 interruptions io01 to io04 level-triggered. output data can be read by following register file, when using each i/o ports as output. iod24 r15r iod23 iod22 iod21 iod14 r14r msb 3 iod13 2 iod12 1 iod11 0 lsb iod04 pa1r iod03 iod02 iod01 ? pc3 msb 3 ? 2 ? 1 ioie0 0 lsb ? pc0 msb 3 (eselt) 2 eselio 1 (eseli) 0 lsb ioo14 r14w ioo13 ioo12 ioo11 ioo04 ra1w msb 3 ioo03 2 ioo02 1 ioo01 0 lsb ioo24 r15w ioo23 ioo22 ioo21
tmp04ch01fxxx(jtmp04ch01xxxs) 2002-12-11 36 figure 17 io11 to io14, io21 to io24 ioo24 ioo23 ioo22 ioo21 r15w ioo14 ioo13 ioo12 ioo11 r14w iod14 iod13 iod12 iod11 r14r iod24 iod23 iod22 iod21 r15r d q latch io21 ?h? r d q latch io11 ?h? r d q latch io22 ?h? r d q latch io12 ?h? r d q latch io23 ?h? r d q latch io13 ?h? r d q latch io24 ?h? r d q latch io14 ?h? r mask option mask option
tmp04ch01fxxx(jtmp04ch01xxxs) 2002-12-11 37 5. buzzer circuit buzzer sound can be selected by register file bz1, bz2, bz3 and 2k/4k. 2 k/4 k = 0 basic frequency 2 khz = 1 basic frequency 4 khz buzzer sound can be made by software using (000), (001) or (000), (111) setting, as above. when the register file r67 is set the above ((bz3, bz2, bz1) = ( 010) to (110)), each buzzer sound is continuously released setting (bz3, bz2, bz1) to (000). note: the above buzzer sounds are shown with respect to timings in the cpm2 mode where the high-speed oscillation frequency is 2 mhz, the cpm1/3 mode where the low-speed oscillation frequency is 32 khz, and in the halt mode. 2 k/4 k pe7 msb 3 bz3 2 bz2 1 bz1 0 lsb figure 18 buzzer sound bz bz bz 3 2 1 8 hz 4 hz 2 hz 1 hz 0 1 0 0 1 1 1 1 0 1 1 1 bz h (v dd ) 1 0 1 1 0 0 0 0 0 (bz l (v ss )) off (000) on (001) off (000) 2 k/4 khz on (001) 0 0 1 (bz on)
tmp04ch01fxxx(jtmp04ch01xxxs) 2002-12-11 38 figure 19 buzzer circuit bz ?h? input output bz3 bz2 bz1 8 hz 4 hz 2 hz 1 hz out 0 0 1 * * * * 1 0 1 0 * * * 0 1 0 1 1 * * 0 * 1 1 0 0 * 1 0 * 1 1 0 1 * 1 * 0 1 1 1 0 1 * * * 1 other than above 0 bz1 bz3 bz2 1 hz 2 hz 4 hz 8 hz out * : d?ont care 4 khz 2 khz bz1 bz2 bz3 2 k/4 k pe7 latch latch latch latch 1 hz 2 hz 4 hz 8 hz
tmp04ch01fxxx(jtmp04ch01xxxs) 2002-12-11 39 6. lcd circuit the lcd driver circuit has common signals and segment signals to drive 4.5 v, 1/16 duty, 1/4 bias lcd. duty frame frequency common segment 1/16 ? 97.5 hz ? com1 to com16 ? s 1 to s 52 the lcd driver circuit is controlled by register file both dsta and don, and display ram is enable on drce = 1 don ? dsta ? behavior of lcd driver 0 0 the booster circuit (quadrupler) is turned off and all common & segment is fixed to v ss level. lcd shows full off display. 1 1 the booster circuit (quadrupler) is turned on and lcd driver is enabled to display the data on display ram. other than above ? the setting other than above can cause mal-function. do not set. drce = 0 disable display ram = 1 enable display ram caution: 1. display signals from segment and common are made by the clock which come from low- speed oscillation. even though the high-speed oscillator may be operating no display is output unless the low-speed oscillator is operating. 2. register file don and dsta are read to display driver circuit by the clock which is made by lowcp. when the lowcp is needed off it is needs max. 103 ms after changing the data of don and dsta. ? pc6w msb 3 drce 2 don 1 dsta 0 lsb
tmp04ch01fxxx(jtmp04ch01xxxs) 2002-12-11 40 figure 20 lcd drive waveform (1/16 duty) com1 com2 com3 com4 com5 com6 com7 com8 v 4 v 3 v 2 v 1 v ss v 4 v 3 v 2 v 1 v ss v 4 v 3 v 2 v 1 v ss v 4 v 3 v 2 v 1 v ss v 4 v 3 v 2 v 1 v ss v 4 v 3 v 2 v 1 v ss v 4 v 3 v 2 v 1 v ss v 4 v 3 v 2 v 1 v ss v 4 v 3 v 2 v 1 v ss v 4 v 3 v 2 v 1 v ss v 4 v 3 v 2 v 1 v ss v 4 v 3 v 2 v 1 v ss v 4 v 3 v 2 v 1 v ss v 4 v 3 v 2 v 1 v ss v 4 v 3 v 2 v 1 v ss v 4 v 3 v 2 v 1 v ss 21/2,048 s 21/32,768 s segment- com1 to com16 = off segment- com1 = on com2 to com16 = off segment- com1 = off com2 = on com3 to com16 = off segment- com1, com2 = on com3 to com16 = off segment- com1, com2 = off com3 = on com4 to com16 = off segment- com1 to com15 = on com16 = off *: f l = 32,768 hz segment- com1 to com16 = on com9 com10 com11 com12 com13 com14 com15 com16
tmp04ch01fxxx(jtmp04ch01xxxs) 2002-12-11 41 7. mask option tmp04ch01fxxx has 8 mask option. mask code battery in ? i00 i01 i02 high-speed osc low-speed osc remark a11f1 ? 1.5 v ? in (1) ? i/o (1) ? i/o (1) i/o (2) cr ? x?tal ? (*) a11f3 ? 1.5 v ? in (1) ? i/o (1) ? i/o (1) i/o (2) cr ? cr ? (*) a32f0 ? 3.0 v ? in (1) ? i/o (2) ? i/o (2) i/o (2) x?tal ? x?tal ? (*) a32f1 ? 3.0 v ? in (1) ? i/o (2) ? i/o (2) i/o (2) cr ? x?tal ? (*) a32f3 ? 3.0 v ? in (1) ? i/o (2) ? i/o (2) i/o (2) cr ? cr ? (*) a33f0 ? 3.0 v ? in (1) ? i/o (1) ? i/o (1) i/o (1) x?tal ? x?tal ? (*) a33f1 ? 3.0 v ? in (1) ? i/o (1) ? i/o (1) i/o (1) cr ? x?tal ? ? a33f3 ? 3.0 v ? in (1) ? i/o (1) ? i/o (1) i/o (1) cr ? cr ? (*) (*) under development (1) supply voltage either 1.5 v or 3.0 v can be selected as the supply voltage. when 3.0 v is used, the low-speed oscillator circuit is driven by output from the internal constant voltage circuit (v reg2 ) thus reducing current dissipation. low-speed (crystal) oscillator circuit 32 khz 3.0 v 0 v v dd v ss xl in xl out rout rfb when 3.0 v selected 3.0 v v xt constant voltage circuit vreg2 1.8 v 1.5 v when 1.5 v selected low-speed (crystal) oscillator circuit 32 khz 1.5 v 0 v v dd v ss xl in xl out rout rfb
tmp04ch01fxxx(jtmp04ch01xxxs) 2002-12-11 42 (2) input/output port types either cmos output or p-channel open drain can be selected in units of four bits for the input/output pins: io01 to io04, io11 to io14, io21 to io24. for port types, see the diagram of input/output port types. (3) high-speed oscillator circuit either the crystal or the cr oscillator circuit can be selected as the high-speed oscillator circuit. note: after a reset, the cpu starts operating using the high-speed clock as the system clock. therefore, even if only a low-speed clock is used for the following processes, the high-speed oscillator circuit must operate normally at startup. select either the crystal or the cr oscillator circuit and correctly connect the external component (crystal oscillator or resistor) to the xh in /xh out pin. (4) low-speed oscillator circuit either the crystal or the cr oscillator circuit can be selected as the low-speed oscillator circuit. note: a low-speed clock is used in the lcd driver circuit. to display the lcd, the low-speed oscillator circuit must be operated. when the cr oscillator circuit is selected, because both resistor and capacitor are built in, an external component is not required. connect the xl in pin to v ss . if the pin is left open, the internal circuit gates become unstable, possibly allowing surge current to flow. f h xh in xh out r f when cr oscillator circuit is selected external resisto r internal capacitor f h xh in xh out rout rfb when crystal oscillator circuit is selected crystal oscillato r f l xl in xl out rout rfb when crystal oscillator circuit is selected crystal oscillato r f l xl in xl out when cr oscillator circuit is selected internal resistor internal capacitor r
tmp04ch01fxxx(jtmp04ch01xxxs) 2002-12-11 43 ? input/output circuit in1 (1) i/o (1) i/o (2) rin : internal pull-down resistor, 400 k ? (typ.) r : input protective resistor, 100 ? (typ.) rin r r rin r figure 21 i/o port
tmp04ch01fxxx(jtmp04ch01xxxs) 2002-12-11 44 electrical characteristics absolute maximam ratings ? ? ? ? (v ss = = = = 0 v) characteristics symbol rating unit power supply voltage v dd ? ? 0.3 to 6.0 ? v input voltage v in ? ? 0.3 to v dd + 0.3 ? v power dissipation (t opr = 80c) p d ? 350 ? mw solder temperature ? t sol ? 260 (10 s) ? c storage temperature ? t stg ? ? 55 to 125 ? c operating temperature ? t opr ? 0 to 40 ? c recommended operating condition 1.5v version (unless otherwise specified, v ss = = = = 0 v, t opr = = = = 0c to 40c) characteristics symbol test condition min typ. max unit power supply voltage ? v dd ? f xth = 200 khz ? 1.2 ? 1.5 ? 1.8 ? v f xtl1 ? v dd = 1.2 v to 1.8 v (note 1) ? ? ? 32.768 ? ? ? f xtl2 ? v dd = 1.5 v (note 2) ? 20 ? 33 ? 55 ? oscillation frequency ? f xth1 ? v dd = 1.5 v (note 3) ? ? ? 200 ? ? ? khz v dd = 1.3 v ? v dd 0.8 ? ? ? v dd ? ?h? level v ih ? v dd = 1.7 v ? v dd 0.7 ? ? ? v dd ? v dd = 1.3 v ? 0 ? ? ? v dd 0.2 ? input voltage ? ?l? level v il ? v dd = 1.7 v ? 0 ? ? ? v dd 0.3 ? v quadrupler capacitance ? c 1 , c 2 ? ? ? ? 1.0 ? ? f v 1 ? ? ? ? 1.0 ? ? v 2 ? ? ? ? 1.0 ? ? ? v 3 ? ? ? ? 1.0 ? ? ? voltage capacitance ? v 4 ? ? ? ? 1.0 ? ? ? f note 1: crystal oscillation circuit is used for low-speed oscillator. note 2: internal cr oscillator is used for low-speed oscillator. note 3: an cr oscillating circuit configured with an external r is used for the high-speed oscillator. oscillation characteristics symbol test condition min typ. max unit osc starting voltage v sta ? t sta = 10 s, t opr = 25c (note 4) ? 1.4 ? ? ? ? ? v osc holding voltage v hold ? (note 4) ? 1.2 ? ? ? ? ? v frequency of internal cr osc f osc1 ? v dd = 1.5 v (note 5) ? 20 ? 33 ? 55 ? khz frequency of high-speed osc f osc2 ? v dd = 1.5 v r f = 150 k ? ? (note 6) ? ? ? 200 ? ? ? khz note 4: crystal oscillation circuit for low-speed oscillator. input 1.4 v or more at power-on. note 5: internal cr oscillator for low-speed oscillator. note 6: an cr oscillating circuit configured with an external r is used for the high-speed oscillator.
tmp04ch01fxxx(jtmp04ch01xxxs) 2002-12-11 45 dc characteristics characteristics symbol test condition min typ. max unit i ih1 ? v dd = 1.8 v, v in = 0 v ? ? 500 ? ? ? 500 ? na input current (1) (in1 to in4, io01 to io04, io11 to io14,) ? i il1 v dd = 1.8 v, v in = 1.8 v ? 3.21 ? 4.5 ? 7.5 a i ih1 ? v dd = 1.8 v, v in = 0 v ? ? 500 ? ? ? 500 ? input current (1-2) (io21 to 24) i il1 v dd = 1.8 v, v in = 1.8 v ? ? 500 ? ? ? 500 na i ih2l (note) ? v dd = 1.8 v, v in = 0 v low resistor side ? ? 60 ? ? 36 ? ? 25.7 input current (2) (breset) ? i ih2h v dd = 1.8 v, v in = 0 v high resistor side ? ? 6 ? ? 3.6 ? ? 2.57 ? a input current (3) (test) ? i il3 ? v dd = 1.8 v, v in = 1.8 v ? 6.43 ? 9.0 ? 15.0 a i oh1 ? v dd = 1.2 v, v oh = 0.7 v ? ? ? ? ? ? 150 output current (1) (io01 to 04, io11 to 14) ? i ol1 v dd = 1.2 v, v ol = 0.5 v ? 0.89 ? 1.25 ? 2.08 ? a output current (1-2) (io21 to 24) i oh1 ? v dd = 1.2 v, v oh = 0.7 v ? ? ? ? ? ? 150 a i oh2 ? v dd = 1.2 v, v oh = 0.7 v ? ? ? ? ? ? 500 output current (2) (bz) ? i ol2 v dd = 1.2 v, v ol = 0.5 v ? 500 ? ? ? ? ? a i oh3 ? v oh = v 4 ? 0.5 v ? ? ? ? ? ? 100 i ol3 v ol = 0.5 v ? 100 ? ? ? ? ? output current (3) (segment) ? i om3 v 1 = 1.125 v, v 2 = 2.25 v, v 3 = 3.375 v, v 4 = 4.5 v ? v om = v 2 ? 0.5 v ? ? ? ? ? ? 50 ? a i oh4 ? v oh = v 4 ? 0.5 v ? ? ? ? ? ? 100 i ol4 v ol = 0.5 v ? 100 ? ? ? ? ? i om4 v om = v 3 ? 0.5 v ? ? ? ? ? ? 50 ? output current (4) (common) ? i om4 v 1 = 1.125 v, v 2 = 2.25 v, v 3 = 3.375 v, v 4 = 4.5 v ? v om = v 1 + 0.5 v ? 50 ? ? ? ? ? a v 1 ? 1.075 ? 1.125 ? 1.175 ? v 2 2.05 ? 2.25 ? 2.45 ? v 3 3.175 ? 3.375 ? 3.575 ? quadrupler output ? v 4 v 1 = 1.125 v, ta = 25c ? 4.3 ? 4.5 ? 4.7 ? v display on ? ? ? 48 ? 77 i ddop ? v dd = 1.5 v, f h = 200 khz f l = 32 khz at high-speed operation ? display off ? ? ? ? ? 73 ? display on ? ? ? 9.5 ? 12 ? i ddslow v dd = 1.5 v, f l = 32 khz at low-speed operation ? display off ? ? ? ? ? 11 ? display on ? ? ? 4 ? 7 ? i ddhold v dd = 1.5 v, f l = 32 khz in hold mode ? display off ? ? ? ? ? 6 ? power supply current (1) (low-speed crystel oscillation circuit) ? i ddstop v dd = 1.5 v, in stop mode ? ? ? 0.4 ? 1 ? a display on ? ? ? 50 ? 77 i ddop ? v dd = 1.5 v, f = 200 khz f l = internal at high-speed operation ? display off ? ? ? ? ? 73 ? display on ? ? ? 12 ? 17 ? i ddslow v dd = 1.5 v, f l = internal at low-speed operation ? display off ? ? ? ? ? 16 ? display on ? ? ? 5 ? 7.5 ? i ddhold v dd = 1.5 v, f l = internal in hold mode ? display off ? ? ? ? ? 6.5 ? power supply current (2) (low-speed cr oscillation circuit) ? i ddstop v dd = 1.5 v, in stop mode ? ? ? 0.4 ? 1 ? a
tmp04ch01fxxx(jtmp04ch01xxxs) 2002-12-11 46 note: the breset pin is connected to v dd (high level) via two resistors as shown below. to minimize the current that flows at reset, the low resistance consists of a p-channel fet. when the input level is v ss (low level), the fet is off. the resistance is . the specified input current (2), i ih2l , is the current that flows when the low resistance = p-channel fet is on. however, the low-resistance is off when vi n = 0 v, so actual measurement is impossible. typical operating condition 3.0 v version (unless otherwise specified, v ss = = = = 0 v, t opr = = = = 0c to 40c) characteristics symbol test condition min typ. max unit power supply voltage ? v dd ? f xth = 2 mhz ? 2.4 ? 3.0 ? 3.6 ? v f xtl1 ? v dd = 2.4 v to 3.6 v (note 1) ? ? ? 32.768 ? ? ? f xtl2 ? v dd = 3.0 v (note 2) ? 20 ? 35 ? 60 ? khz f xth1 ? v dd = 2.4 v to 3.6 v (note 3) ? ? ? 2.0 ? ? ? oscillation frequency ? f xth2 ? v dd = 3.0 v (note 4) ? ? ? 2.0 ? ? ? mhz v dd = 2.4 v ? v dd 0.8 ? ? ? v dd ? ?h? level v ih ? v dd = 3.6 v ? v dd 0.7 ? ? ? v dd ? v dd = 2.4 v ? 0 ? ? ? v dd 0.2 ? input voltage ? ?l? level v il ? v dd = 3.6 v ? 0 ? ? ? v dd 0.3 ? v quadrupler capacitance ? c 1 , c 2 ? ? ? ? ? 1.0 ? ? f v 2 ? ? ? ? ? 1.0 ? ? v 3 ? ? ? ? ? 1.0 ? ? v 4 ? ? ? ? ? 1.0 ? ? voltage capacitance ? v xt ? ? ? ? ? 1.0 ? ? f note 1: crystal oscillation circuit is used for low-speed oscillator. note 2: internal cr oscillator is used for low-speed oscillator. note 3: crystal oscillation circuit is used for high-speed oscillator. note 4: an cr oscillating circuit configured with an external r is used for the high-speed oscillator. ? reset breset r v dd = ?high? level high resistance low resistance
tmp04ch01fxxx(jtmp04ch01xxxs) 2002-12-11 47 oscillation characteristics symbol test condition min typ. max unit osc starting voltage (low-speed) ? v sta1 ? t sta = 10 s, t opr = 25c ? 1.85 ? ? ? ? ? v osc starting voltage (high-speed) ? v sta2 ? t sta = 8 ms ? 2.10 ? ? ? ? ? v osc holding voltage (low-speed) ? v hold1 ? ? ? 1.65 ? ? ? ? ? v osc holding voltage (high-speed) ? v hold2 ? ? ? 1.90 ? ? ? ? ? v frequency of internal cr osc f osc1 ? v dd = 3.0 v (note 5) ? 20 ? 35 ? 60 ? khz frequency of high-speed osc f osc2 ? v dd = 3.0 v, r f = 13.0 k ? (note 6) ? ? ? 2.0 ? ? ? mhz note 5: internal cr oscillator for low-speed oscillator. note 6: an cr oscillating circuit configured with an external r is used for the high-speed oscillator.
tmp04ch01fxxx(jtmp04ch01xxxs) 2002-12-11 48 dc characteristics characteristics symbol test condition min typ. max unit i ih1 ? v dd = 3.6 v, v in = 0 v ? ? 500 ? ? ? 500 ? na input current (1) (in1 to in4) ? i il1 v dd = 3.6 v, v in = 3.6 v ? 6.43 ? 9.0 ? 15.0 a i ih1 ? v dd = 3.6 v, v in = 0 v ? ? 500 ? ? ? 500 ? na input current (1-2) (io01 to io04, io11 to io14, io21 to io24) (note 1) i il1 v dd = 3.6 v, v in = 3.6 v ? 6.43 ? 9.0 ? 15.0 a i ih1 ? v dd = 3.6 v, v in = 0 v ? ? 500 ? ? ? 500 ? na input current (1-3) (io01 to io04, io11 to io14, io21 to io24) (note 2) i il1 v dd = 3.6 v, v in = 3.6 v ? 500 ? ? ? 500 ? na i ih2l ? v dd = 3.6 v, v in = 0 v low resistor side ? ? 120 ? ? 72 ? ? 51.4 input current (2) (breset) ? i ih2h v dd = 3.6 v, v in = 0 v high resistor side ? ? 12 ? ? 7.2 ? ? 5.14 ? a input current (3) (test) ? i il3 ? v dd = 3.6 v, v in = 3.6 v ? 12.9 ? 18.0 ? 30.0 a i oh1 ? v dd = 2.4 v, v oh = 1.9 v ? ? ? ? ? ? 1.5 ma output current (1) (io01 to io04, io11 to io14, io21 to io24) ? i ol1 (note 1) v dd = 2.4 v, v ol = 0.5 v ? 0.89 ? 1.25 ? 2.08 ? a i oh2 ? v dd = 2.4 v, v oh = 1.9 v ? ? ? ? ? ? 2.0 output current (2) (bz) ? i ol2 v dd = 2.4 v, v ol = 0.5 v ? 2.0 ? ? ? ? ? ma i oh3 ? v oh = v 4 ? 0.5 v ? ? ? ? ? ? 100 i ol3 v ol = 0.5 v ? 100 ? ? ? ? ? output current (3) (segment) ? i om3 v dd = 3.0 v, v reg = 1.125 v, v 2 = 2.25 v, v 3 = 3.375 v, v 4 = 4.5 v ? v om = v 2 ? 0.5 v ? ? ? ? ? ? 50 ? a i oh4 ? v oh = v 4 ? 0.5 v ? ? ? ? ? ? 100 i ol4 v ol = 0.5 v ? 100 ? ? ? ? ? i om4 v om = v 3 ? 0.5 v ? ? ? ? ? ? 50 ? output current (4) (common) ? i om4 v dd = 3.0 v, v reg = 1.125 v, v 2 = 2.25 v, v 3 = 3.375 v, v 4 = 4.5 v ? v om = v 1 + 0.5 v ? 50 ? ? ? ? ? a v reg1 v dd = 3.0 v, ta = 25c (note 3) 1.075 1.125 1.175 voltage regulater output v reg2 v dd = 3.0 v, ta = 25c (note 4) ? 1.8 ? v v 2 2.05 2.25 2.45 v 3 3.175 3.375 3.575 quadrupler output v 4 v dd = 3.0 v, v reg = 1.125 v, ta = 25c 4.3 4.5 4.7 v note 1: mask code: a33f0, a33f1, a33f3 note 2: mask code : a32f0, a32f1, a32f3 note 3: voltage regulator for quadrupler note 4: voltage output regulator for low-speed oscillator
tmp04ch01fxxx(jtmp04ch01xxxs) 2002-12-11 49 characteristics symbol test condition min typ. max unit display on ? ? ? 0.85 ? 1.2 ? i ddop ? v dd = 3.0 v, f h = 2 mhz, f l = 32 khz at high-speed operation ? display off ? ? ? ? ? 1.2 ma display on ? ? ? 17.0 ? 24.0 ? i ddslow ? v dd = 3.0 v, f l = 32 khz at low-speed operation ? display off ? ? ? ? ? 23.0 ? display on ? ? ? 5.5 ? 11.0 ? i ddhold ? v dd = 3.0 v, f l = 32 khz in hold mode ? display off ? ? ? ? ? 10.0 ? power supply current (1) (high-speed crystal oscillation circuit) (low-speed crystal oscillation circuit) ? i ddstop ? v dd = 3.0 v in stop mode ? ? ? 0.8 ? 1.2 ? a display on ? ? ? 0.85 ? 1.5 ? i ddop ? v dd = 3.0 v, f h = 2 mhz, f l = 32 khz at high-speed operation ? display off ? ? ? ? ? 1.5 ma display on ? ? 17.0 24.0 i ddslow v dd = 3.0 v, f l = 32 khz at low-speed operation ? display off ? ? ? 23.0 display on ? ? ? 5.5 ? 11.0 ? i ddhold ? v dd = 3.0 v, f l = 32 khz in hold mode ? display off ? ? ? ? ? 10.0 ? power supply current (2) (high-speed cr oscillation circuit) (low-speed crystal oscillation circuit) ? i ddstop v dd = 3.0 v in stop mode ? ? ? 0.8 ? 1.2 ? a display on ? ? ? 0.85 ? 1.5 ? i ddop ? v dd = 3.0 v, f h = 2 mhz, f l = internal at high-speed operation ? display off ? ? ? ? ? 1.5 ma display on ? ? ? 23.0 40.0 ? i ddslow ? v dd = 3.0 v f l = internal at low-speed operation ? display off ? ? ? ? ? 39.0 ? display on ? ? ? 6.5 ? 14.0 ? i ddhold ? v dd = 3.0 v, f l = internal in hold mode ? display off ? ? ? ? ? 12.0 ? power supply current (3) (high-speed cr oscillation circuit) (low-speed cr oscillation circuit) ? i ddstop ? v dd = 3.0 v in stop mode ? ? ? 0.8 ? 1.4 ? a
tmp04ch01fxxx(jtmp04ch01xxxs) 2002-12-11 50 example of application circuit note 1: either 1.5 v or 3 v can be selected as the supply voltage. note 2: recommended high-speed oscillator circuit capacitor: 22 pf note 3: recommended low-speed oscillator circuit capacitor: 15 pf note 4: insert a 0.1 f capacitor between breset and v ss . note 5: high-speed cr oscillator circuit (optional) note 6: low-speed cr oscillator circuit (optional) note 7: adjust between 0.1 to 1.0 f depending on the size of the lcd panel used. (note 2) (note 3) (note 1) (note 4) in 1 in 2 in 3 in 4 io 01 io 02 io 03 io 04 io 11 io 12 io 13 io 14 io 21 io 22 io 23 io 24 xh in xh out xl in xl out breset v ss v dd bz (note 5) (note 6) v 4 v 3 v 2 v 1 v xt c 1 c 2 test (note 7) (note 7) (note 7) (note 7) (note 7) (note 7) lcd tmp04ch01fxxx seg1 to seg52/com1 to com16 150 k ? (200 khz@1.5 v) xh in xh out 13 k ? (2 mhz@3.0 v) xl in xl out c and r are built in. connect xl in to v ss .
tmp04ch01fxxx(jtmp04ch01xxxs) 2002-12-11 51 package dimensions weight: 1.65 g (typ.)
tmp04ch01fxxx(jtmp04ch01xxxs) 2002-12-11 52 bare chip 1. pad assignment chip size 5.04 5.78 (mm) chip thickness 450 30 ( m) substrate voltage v ss s 50 s 49 s 48 s 47 s 46 s 45 s 44 s 43 s 42 s 41 s 40 s 39 s 38 s 37 s 36 s 35 s 34 s 33 s 32 s 31 s 30 s 29 s 28 s 27 s 26 s 25 s 24 s 23 s 51 s 52 com16 com15 com14 com13 com12 com11 com10 com9 com8 com7 com6 com5 com4 com3 com2 com1 v 4 v 3 v 2 v 1 c 1 c 2 v ss v xt breset xl in xl out v dd xh in xh out test bz in1 in2 in3 in4 io01 io02 io03 io04 io11 io12 io13 io14 io21 io22 io23 io24 s 22 s 21 s 20 s 19 s 18 s 17 s 16 s 15 s 14 s 13 s 12 s 11 s 10 s 9 s 8 s 7 s 6 s 5 s 4 s 3 s 2 s 1 jtmp04ch01xxxs (top view)
tmp04ch01fxxx(jtmp04ch01xxxs) 2002-12-11 53 2. pad location table ( 10 ? 3 mm) no. ? pad name x point y point no. ? pad name x point y point 1 ? v 1 ? ? 1957 ? 2653 37 ? s 8 ? ? 599 ? 2653 2 ? c 1 ? ? 2253 ? 2375 38 ? s 9 ? ? 431 ? 2653 3 ? c 2 ? ? 2253 ? 2201 39 ? s 10 ? ? 256 ? 2653 4 ? v ss ? ? 2253 ? 2038 40 ? s 11 ? ? 85 ? 2653 5 ? v xt ? ? 2253 ? 1871 41 ? s 12 ? 85 ? 2653 6 ? breset ? ? 2253 ? 1699 42 ? s 13 ? 258 ? 2653 7 ? xl in ? ? 2253 ? 1519 43 ? s 14 ? 428 ? 2653 8 ? xl out ? ? 2253 ? 1345 44 ? s 15 ? 601 ? 2653 9 ? v dd ? ? 2253 ? 1144 45 ? s 16 ? 771 ? 2653 10 ? xh in ? ? 2253 ? 944 46 ? s 17 ? 944 ? 2653 11 ? xh out ? ? 2253 ? 772 47 ? s 18 ? 1114 ? 2653 12 ? test ? ? 2253 ? 592 48 ? s 19 ? 1287 ? 2653 13 ? bz ? ? 2253 ? 410 49 ? s 20 ? 1457 ? 2653 14 ? in1 ? ? 2253 ? 227 50 ? s 21 ? 1630 ? 2653 15 ? in2 ? ? 2253 ? 59 51 ? s 22 ? 1959 ? 2653 16 ? in3 ? ? 2253 ? ? 112 52 ? s 23 ? 2253 ? 2283 17 ? in4 ? ? 2253 ? ? 280 53 ? s 24 ? 2253 ? 2112 18 ? io01 ? ? 2253 ? ? 468 54 ? s 25 ? 2253 ? 1945 19 ? io02 ? ? 2253 ? ? 639 55 ? s 26 ? 2253 ? 1774 20 ? io03 ? ? 2253 ? ? 815 56 ? s 27 ? 2253 ? 1607 21 ? io04 ? ? 2253 ? ? 986 57 ? s 28 ? 2253 ? 1436 22 ? io11 ? ? 2253 ? ? 1162 58 ? s 29 ? 2253 ? 1269 23 ? io12 ? ? 2253 ? ? 1333 59 ? s 30 ? 2253 ? 1098 24 ? io13 ? ? 2253 ? ? 1509 60 ? s 31 ? 2253 ? 931 25 ? io14 ? ? 2253 ? ? 1680 61 ? s 32 ? 2253 ? 760 26 ? io21 ? ? 2253 ? ? 1856 62 ? s 33 ? 2253 ? 593 27 ? io22 ? ? 2253 ? ? 2027 63 ? s 34 ? 2253 ? 422 28 ? io23 ? ? 2253 ? ? 2203 64 ? s 35 ? 2253 ? 255 29 ? io24 ? ? 2253 ? ? 2374 65 ? s 36 ? 2253 ? 84 30 ? s 1 ? ? 1960 ? ? 2653 66 ? s 37 ? 2253 84 31 ? s 2 ? ? 1628 ? ? 2653 67 ? s 38 ? 2253 255 32 ? s 3 ? ? 1460 ? ? 2653 68 ? s 39 ? 2253 422 33 ? s 4 ? ? 1285 ? ? 2653 69 ? s 40 ? 2253 593 34 ? s 5 ? ? 1117 ? ? 2653 70 ? s 41 ? 2253 760 35 ? s 6 ? ? 942 ? ? 2653 71 ? s 42 ? 2253 931 36 ? s 7 ? ? 774 ? ? 2653 72 ? s 43 ? 2253 1098
tmp04ch01fxxx(jtmp04ch01xxxs) 2002-12-11 54 no. ? pad name x point y point 73 ? s 44 ? 2253 1269 74 ? s 45 ? 2253 1436 75 ? s 46 ? 2253 1607 76 ? s 47 ? 2253 1774 77 ? s 48 ? 2253 1945 78 ? s 49 ? 2253 2112 79 ? s 50 ? 2253 2283 80 ? s 51 ? 1959 2653 81 ? s 52 ? 1629 2653 82 ? com16 1459 2653 83 ? com15 1286 2653 84 ? com14 1116 2653 85 ? com13 943 2653 86 ? com12 773 2653 87 ? com11 600 2653 88 ? com10 ? 430 2653 89 ? com9 ? 257 2653 90 ? com8 ? 87 2653 91 ? com7 ? ? 87 2653 92 ? com6 ? ? 257 2653 93 ? com5 ? ? 430 2653 94 ? com4 ? ? 600 2653 95 ? com3 ? ? 773 2653 96 ? com2 ? ? 943 2653 97 ? com1 ? ? 1116 2653 98 ? v 4 ? ? 1291 2653 99 ? v 3 ? ? 1468 2653 100 ? v 2 ? ? 1638 2653
tmp04ch01fxxx(jtmp04ch01xxxs) 2002-12-11 55 ? toshiba is continually working to improve the quality and reliability of its products. nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. it is the responsibility of the buyer, when utilizing toshiba products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such toshiba products could cause loss of human life, bodily injury or damage to property. in developing your designs, please ensure that toshiba products are used within specified operating ranges as set forth in the most recent toshiba products specifications. also, please keep in mind the precautions and conditions set forth in the ?handling guide for semiconductor devices,? or ?toshiba semiconductor reliability handbook? etc.. ? the toshiba products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). these toshiba products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (?unintended usage?). unintended usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. unintended usage of toshiba products listed in this document shall be made at the customer?s own risk. ? the products described in this document are subject to the foreign exchange and foreign trade laws. ? the information contained herein is presented only as a guide for the applications of our products. no responsibility is assumed by toshiba corporation for any infringements of intellectual property or other rights of the third parties which may result from its use. no license is granted by implication or otherwise under any intellectual property or other rights of toshiba corporation or others. ? the information contained herein is subject to change without notice. 000707eb a restrictions on product use

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