silego technology, inc. rev 1.0 000-007nt614-10 revised july 3, 2013 ultra-small 22 m 4 a load switch with reverse current blocking slg7nt614v block diagram general description the slg7nt614v is a 22 m 4 a single-channel load switch that is able to switch 1 to 5 v power rails. the product is pack- aged in an ultra-small 1.5 x 2.0 mm package. features ? 1.5 x 2.0 mm fc-tdfn 8l package (2 fused pins for drain and 2 fused pins for source) ? logic level on pin capable of supporting 0.85 v cmos logic ? user selectable ramp rate with external capacitor ? 22 m rds on while supporting 4 a ? two over current protection modes ? short circuit current limit ? active current limit ? over temperature protection ? pb-free / halogen-free / rohs compliant ? operating temperature: -40 c to 85 c ? operating voltage: 2.5 v to 5.5 v pin configuration applications ? notebook power rail switching ? tablet power rail switching ? smartphone power rail switching 8-pin fc-tdfn (top view) vdd 1 cap gnd vin on 2 3 7 8 slg7nt614v vin 4 vout vout 5 6 vin vout linear ramp control cmos input on charge pump +2.5 to 5.5 v cap over current and over temperature protection reverse blocking 4 a @ 22 m
000-007nt614-10 page 2 of 10 slg7nt614v pin description ordering information pin # pin name type pin description 1 vdd pwr vdd power for load switch control (2.5 v to 5.5 v) 2 on input turns mosfet on (4 m pull down resistor) cmos input with vil < 0.3 v, vih > 0.85 v 3 vin mosfet drain of power mosfet (fused with pin 4) 4 vin mosfet drain of power mosfet (fused with pin 3) 5 vout mosfet source of power mosfet (fused with pin 6) 6 vout mosfet source of power mosfet (fused with pin 5) 7 cap input capacitor for controlling power rail ramp rate 8 gnd gnd ground part number type production flow slg7nt614v fc-tdfn 8l industrial, -40 c to 85 c SLG7NT614VTR fc-tdfn 8l (tape and reel) industrial, -40 c to 85 c
000-007nt614-10 page 3 of 10 slg7nt614v absolute maximum ratings electrical characteristics parameter description conditions min. typ. max. unit v dd power supply -- -- 7 v t s storage temperature -65 -- 150 c esd hbm esd protection human body model 2000 -- -- v w dis package power dissipation -- -- 1 w mosfet ids pk peak current from drain to source for no more than 1 ms with 1% duty cycle -- -- 6 a note: stresses greater than those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a s tress rating only and functional operation of the device at these or any other conditions above t hose indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating condition s for extended periods may affect reliability. t a = -40 c to 85 c (unless otherwise stated) parameter description conditions min. typ. max. unit v dd power supply voltage -40 c to 85 c 2.5 -- 5.5 v i dd power supply current (pin 1) when off -- -- 1 a when on, no load -- 70 100 a rds on static drain to source on resistance t a 25c @ 100 ma -- 22 28 m t a 70c @ 100 ma -- 25 30 m t a 85c @ 100 ma -- 27 31 m ids operating current v in = 1.0 v to 5.5 v -- -- 4 a v in drain voltage 1.0 -- v dd v t on_delay on pin delay time 50% on to ramp begin 0 300 500 s t to ta l _ o n total turn on time 50% on to 90% v out configurable 1 ms example: cap (pin 7) = 4 nf, v dd = v in = 5 v, source_cap = 10 f, ids = 100 ma -- 1.96 -- ms t slewrate slew rate 10% v out to 90% v out configurable 1 v/ms example: cap (pin 7) = 4 nf, v dd = v in = 5 v, source_cap = 10 f, ids = 100 ma -- 3.0 -- v/ms i reverse reverse blocking current v out = 5.0, v in = 0 v -- 1 -- a cap source source cap source to gnd -- -- 500 f on_v ih high input voltage on on pin 0.85 -- v dd v on_v il low input voltage on on pin -0.3 0 0.3 v i limit active current limit mosfet will automatically limit cur- rent when v out > 250 mv -- 6.0 -- a short circuit current limit mosfet will automatically limit cur- rent when v out < 250 mv -- 0.5 -- a therm on thermal shutoff turn-on temperature -- 125 -- c therm off thermal shutoff turn-off temperature -- 100 -- c therm time thermal shutoff time -- -- 1 ms t off_delay off delay time 50% on to v out fall, v dd = v in = 5 v -- 7.5 15 s notes: 1. refer to table for configuration details.
000-007nt614-10 page 4 of 10 slg7nt614v slg7nt614v turn on the normal power on sequence is first vdd, with vin only being applied after vdd is > 1 v, and then on after vin is at least 90% of final value. the normal power off s equence is the power on sequence in reverse. if vdd and vin are turned on at the same time then it is possibl e that a voltage glitch will appear on vout before vdd achieves 1v which is the vt of the main mosfet. the size of the glitch is dependent on source and drain capacitance loading and the ramp rate of vdd & vin. slg7nt614v turn on the vout ramp follows a linear path, not an rc limitation provided the ramp is slow enough to not be current limited by load capacitance. slg7nt614v current limiting the slg7nt614v has two forms of current limiting. standard current limiting mode current is measured by mirroring the current through the main mosfet. the mirrored current is then sent through a resistor creating a voltage v(i) proportional to the mosfet current. the v(i) is then compared with a band gap voltage v(bg). if v(i) exceeds the band gap voltage then the voltage v(g) on the gate of the main mosfet is reduced. the v(g) continues to drop until v(i) < v(bg). this response is a closed loop response and is therefore very fast and current limits in less than a few micro-seconds. there is no difference between peak or cons tant current limit. temperature cutoff however, as the v(g) drops the rds(on) of the main mosfet will increase, thus limit ing the current, but also increasing the power dissipation of the ic. the ic is very small and cannot di ssipate much power. therefore, if a current limit condition is sustained the ic will heat up. if the temperature exceeds approxi mately 120c, then v(g) will be brought low completely shuttin g off the main mosfet. as the die cools the mosfet will be turned back on at 100c. if the current limiting condition has not been mitigated then the die will again heat up to 120c and the process will repeat. short circuit current limiting mode when v(vout) < 250 mv, which is the case if there is a solder bridge during the manufacturing process or a hard short on the power rail, then the current is limited to approximately 500 ma. this current limit is accomplished in the same manner as the standard current limiting mode with the exce ption that the current mirror is 15x great er. because the current mirror is so much larger, a 15x smaller main mosfet current is required to gener ate the same v(i). if v(vout) rises above approximately 250 mv, then this mode is au tomatically switched out.
000-007nt614-10 page 5 of 10 slg7nt614v t total_on vs. cap @ v dd = 3.3 v t total_on vs. cap @ v dd = 5.0 v slg7nt614v t to t a l _ o n : on (50%) - v out (90%) v dd = 3.3 v, t a = 25 c. c l = 10 f, ids = 100 ma slg7nt614v t to t a l _ o n : on (50%) - v out (90%) v dd = 5.0 v, t a = 25 c. c l = 10 f, ids = 100 ma 2 3 4 5 6 ttotal_on (ms) vd = 1.5v vd = 2.5v vd = 3.3v 0 1 0 2000 4000 6000 8000 10000 12000 14000 16000 cap (pf) 2 3 4 5 6 ttotal_on (ms) vd = 1.50v vd = 2.50v vd = 3.30v vd = 5.00v 0 1 0 2000 4000 6000 8000 10000 12000 14000 16000 cap (pf)
000-007nt614-10 page 6 of 10 slg7nt614v t slew vs. cap @ v dd = 3.3 v t slew vs. cap @ v dd = 5.0 v slg7nt614v t slew : v out (10%) - v out (90%) v dd = 3.3 v, t a = 25 c. c l = 10 f, ids = 100 ma slg7nt614v t slew : v out (10%) - v out (90%) v dd = 5.0 v, t a = 25 c. c l = 10 f, ids = 100 ma 5 6 7 8 9 10 11 12 13 14 15 v/ms vd = 1.50v vd = 2.50v vd = 3.30v 0 1 2 3 4 0 1000 2000 3000 4000 5000 6000 7000 8000 9000 10000 11000 12000 13000 14000 15000 16000 cap (pf) 5 6 7 8 9 10 11 12 13 14 15 v/ms vd = 1.50v vd = 2.50v vd = 3.30v vd = 5.00v 0 1 2 3 4 0 1000 2000 3000 4000 5000 6000 7000 8000 9000 10000 11000 12000 13000 14000 15000 16000 cap (pf)
000-007nt614-10 page 7 of 10 slg7nt614v t total_on , t on_delay and slew rate measurement 90% v out 50% on t on_delay slew rate (v/ms) on v out t to t a l _ o n 10% v out 50% on 10% v out t off_delay t fall 90% v out
000-007nt614-10 page 8 of 10 slg7nt614v package top marking system definition xxa ddr ll date code + revision part code + assembly site lot traceability pin 1 identifier
000-007nt614-10 page 9 of 10 slg7nt614v package drawing and dimensions 8 lead tdfn package 1.5 x 2.0 mm (fused lead) jedec mo-252, variation w2015d symbol a a1 a2 b d e l l1 l2 s symbol min nom. max unit: mm min nom. max 0.70 0.75 0.80 1.95 2.00 2.05 0.005 - 0.060 1.45 1.50 1.55 0.15 0.20 0.25 0.35 0.40 0.45 0.515 0.565 0.615 0.15 0.20 0.25 a indexarea(d/2xe/2) l l1 e l2 d e a1 a2 0.135 0.185 0.235 8 1 e 0.50 bsc s 0.37 ref b (8x)
000-007nt614-10 page 10 of 10 slg7nt614v tape and reel specifications carrier tape drawing and dimensions recommended reflow soldering profile please see ipc/jedec j-std-020: late st revision for reflow profile based on package volume of 2.25 mm 3 (nominal). more information can be found at www.jedec.org. package type # of pins nominal package size [mm] max units reel & hub size [mm] leader (min) trailer (min) tape width [mm] part pitch [mm] per reel per box pockets length [mm] pockets length [mm] tdfn 8l fc green 8 1.5 x 2.0 x 0.75 3000 3000 178 / 60 100 400 100 400 8 4 package type pocket btm length pocket btm width pocket depth index hole pitch pocket pitch index hole diameter index hole to tape edge index hole to pocket center tape width a0 b0 k0 p0 p1 d0 e f w tdfn 8l fc green 1.68 2.18 0.9 4 4 1.5 1.75 3.5 8 p1 w e p0 a0 d0 y y b0 k0 section y-y c l f refer to eia-481 specification
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