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? semiconductor components industries, llc, 2016 july, 2017 ? rev. 1 1 publication order number: noip1sn0480a/d PYTHON480 python 0.48 megapixel global shutter cmos image sensor features ? 808 x 608 active pixels, 1/3.6? optical format ? 4.8 m x 4.8 m low noise global shutter pixels with in-pixel cds ? monochrome (sn, sp), color (se, sf) ? wide cra options (sp, sf) ? frame rate up to 120 fps at full resolution ? on ? chip 10 ? bit analog ? to ? digital converter (adc) ? 10 ? bit output mode ? one low voltage differential signaling (lvds) high speed serial output or parallel cmos output ? random programmable region of interest (roi) readout ? serial peripheral interface (spi) ? automatic exposure control (aec) ? phase locked loop (pll) ? dual power supply (3.3 v and 1.8 v) ? ? 40 c to +85 c operational temperature range ? 67 pin csp ? 265 mw / 185 mw power dissipation (lvds 120 fps / 60 fps) ? these devices are pb ? free and are rohs compliant applications ? machine vision ? motion monitoring ? security ? bar code scanning description the python 480 image sensor utilizes high sensitivity 4.8 m x 4.8 m pixels that support low noise ?pipelined? and ?triggered? global shutter readout modes. in global shutter mode, the sensors support correlated double sampling (cds) readout, reducing noise and increasing dynamic range. the image sensors have on ? chip programmable gain amplifiers and 10 ? bit a/d converters. the integration time and gain parameters can be reconfigured without any visible image artifact. optionally the on ? chip automatic exposure control loop (aec) controls these parameters dynamically. the image?s black level is either calibrated automatically or can be adjusted by a user programmable offset. a high level of programmability using a four wire serial peripheral interface enables the user to read out specific regions of interest. up to four regions can be programmed, achieving even higher frame rates. the image data interface consist s of one l vds data lane, facilitating frame rate up to 120 frames per second. a separate synchronization channel containing payload information is provided to facilitate the image reconstruction at the receiving end. the device also provides a parallel cmos output interface at the same frame rate. the python 480 is packaged in a 67 ? pin csp package and is available in monochrome and bayer color configurations with standard and wide cra options. www. onsemi.com
python 480 www. onsemi.com 2 ordering information part number description prod. status mpq package noip1sn0480a ? sti 0.48 megapixel, monochrome, cra 1.65 production 100 67 ? ball csp noip1se0480a ? sti 0.48 megapixel, bayer color, cra 1.65 production noip1sp0480a ? sti 0.48 megapixel, monochrome, cra 23.59 engineering noip1sf0480a ? sti 0.48 megapixel, bayer color, cra 23.59 engineering noip1sn0480a ? sti1 0.48 megapixel, monochrome, cra 1.65 production 10 noip1se0480a ? sti1 0.48 megapixel, bayer color, cra 1.65 production noip1sp0480a ? sti1 0.48 megapixel, monochrome, cra 23.59 engineering noip1sf0480a ? sti1 0.48 megapixel, bayer color, cra 23.59 engineering note: more details on the part coding can be found at http://www.onsemi.com/pub_link/collateral/tnd310 ? d.pdf production mark part number 10 ? digit package mark noip1sn0480a ? sti/sti1 sn480 ym nnn noip1se0480a ? sti/sti1 se480 ym nnn noip1sp0480a ? sti/sti1 sp480 ym nnn noip1sf0480a ? sti/sti1 sf480 ym nnn where y is 1 ? digit year, m is the 1 ? digit month, nnn is the 3 ? digit serial number for wafer identification
python 480 www. onsemi.com 3 specifications key specifications table 1. general specifications parameter specification pixel type in ? pixel cds. global shutter pixel architecture shutter type pipelined and triggered global shutter frame rate up to 120fps (full frame readout) master clock lvds mode: 68 mhz when pll is used, 340 mhz (10 ? bit) / 272 mhz (8 ? bit) when pll is not used cmos mode: 68 mhz windowing 4 randomly programmable windows. normal, sub ? sampled and binned readout modes adc resolution 10 ? bit lvds outputs data + sync + clock cmos outputs 10 ? bit parallel output, frame_valid, line_valid, clock data rate lvds mode: 1 x 680 mbps (10 ? bit) cmos mode: 68 mhz power dissipation lvds mode: 265 mw, cmos mode: 185 mw package type 67 ? pin csp note: all numbers listed are for 1x gain condition unless otherwise noted. table 2. electro ? optical specifications parameter specification active pixels 808 (h) x 608 (v) pixel size 4.8 m x 4.8 m conversion gain 0.096 lsb10/e ? 140 v/e ? dark temporal noise < 11 e ? responsivity at 550 nm 7.7 v/lux.s parasitic light sensitivity (pls) <1/6300 full well charge 10000 e ? quantum efficiency at 550 nm 56% pixel fpn < 1.0 lsb10 prnu < 1% mtf 62% @ 535 nm ? x ? dir & y ? dir psnl at 20 c 200 lsb10/s, 2000 e ? /s dark signal at 20 c 5 e ? /s, 0.5 lsb10/s dynamic range > 59 db signal to noise ratio (snr max) 40 db note: all numbers listed are for 1x analog gain condition unless otherwise noted. table 3. recommended operating ratings (note 1) symbol description min max unit t j operating temperature range ? 40 85 c functional operation above the stresses listed in the recommended operating ranges is not implied. extended exposure to stresse s beyond the recommended operating ranges limits may affect device reliability. 1. performance parameters may degrade above 60 c. table 4. absolute maximum ratings (note 4) symbol parameter min max unit abs (1.8 v supply group) abs rating for 1.8 v supply group ?0.5 2.2 v abs (3.3 v supply group) abs rating for 3.3 v supply group ?0.5 3.8 v t s abs storage temperature range ? 40 150 c abs storage humidity range at 85 c 85 %rh electrostatic discharge (esd) human body model (hbm): js ? 001 500 v charged device model (cdm): jesd22 ? c101 500 lu latch ? up: jesd ? 78 100 ma stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected. 2. the adc is 11 ? bit, down ? scaled to 10 ? bit. the python uses a larger word ? length internally to provide 10 ? bit on the output. 3. operating ratings are conditions in which operation of the device is intended to be functional. 4. on semiconductor recommends that customers become familiar with, and follow the procedures in jedec standard jesd625 ? a. refer to application note an52561. long term exposure toward the maximum storage temperature will accelerate color filter degradation .
python 480 www. onsemi.com 4 table 5. electrical specifications boldface limits apply for t j = t min to t max , all other limits t j = +30 c. (notes 5, 6, 7, 8) parameter description min typ max unit power supply parameters ? lvds (note: all ground pins (gnd_18, gnd_33, gnd_colpc) should be connected to an external 0 v ground reference.) vdd_33 supply voltage, 3.3 v 3.2 3.3 3.4 v idd_33 current consumption 3.3 v supply 48 ma vdd_18 supply voltage, 1.8 v 1.7 1.8 1.9 v idd_18 current consumption 1.8 v supply 59 ma vdd_pix supply voltage, pixel 3.25 3.3 3.35 v idd_pix current consumption pixel supply 0.04 ma ptot total power consumption at vdd_33 = 3.3 v, vdd_18 = 1.8 v 265 mw pstby_lp power consumption in low power standby mode < 1 mw popt power consumption at lower pixel rates configurable power supply parameters ? cmos vdd_33 supply voltage, 3.3 v 3.2 3.3 3.4 v idd_33 current consumption 3.3 v supply 33 ma vdd_18 supply voltage, 1.8 v 1.7 1.8 1.9 v idd_18 current consumption 1.8 v supply 37 ma vdd_pix supply voltage, pixel 3.25 3.3 3.35 v idd_pix current consumption pixel supply 3 ma ptot total power consumption 185 mw pstby_lp power consumption in low power standby mode < 0.5 mw popt power consumption at lower pixel rates configurable i/o ? lvds (eia/tia ? 644): conforming to standard/additional specifications and deviations listed fserdata data rate on data channels ddr signaling ? 1 data channel, 1 synchronization channel 680 mbps fserclock clock rate of output clock clock output for mesochronous signaling 340 mhz vicm lvds input common mode level 0.3 1.25 1.8 v tccsk channel to channel skew (training pattern allows per channel skew correction) 50 ps i/o ? cmos 1.8 v signal levels (note 9) fpardata data rate on parallel channels (10 ? bit) 68 mbps vil cmos input low level ? 0.2 0.8 v vih cmos input high level 1.2 3.6 v electrical interface ? lvds fin input clock rate when pll used 68 mhz input clock rate when pll used 340 product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 5. all parameters are characterized for dc conditions after thermal equilibrium is established. 6. this device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. however, it is recommended that normal precautions be taken to avoid application of any voltages higher than the maximum rated voltages to this high impedance circuit. 7. minimum and maximum limits are guaranteed through test and design. 8. refer to acsPYTHON480 available at the image sensor portal for detailed acceptance criteria specifications. 9. cmos inputs are compatible with 3.3 v signal levels. 10. longer integration times are possible, but with possible image quality trade ? offs. 11. data is clocked on the rising edge of the output clock. this can be changed to the falling edge by register 130[8]
python 480 www. onsemi.com 5 table 5. electrical specifications (continued) boldface limits apply for t j = t min to t max , all other limits t j = +30 c. (notes 5, 6, 7, 8) parameter unit max typ min description electrical interface ? lvds tidc input clock duty cycle when pll used 45 50 55 % ratspi (= fin/fspi) 10 ? bit, pll used (fin = 68 mhz) 6 10 ? bit, lvds input used (fin = 340 mhz) 30 electrical interface ? cmos cout output load (only capacitive load) 10 pf tr output rise time 2.5 4.5 6.5 ns tf output fall time 2 3.5 5 ns fin input clock rate 68 mhz tidc input clock duty cycle 45 50 55 % ratspi (= fin/fspi) 10 ? bit (fin = 58 mhz) 6 todc clk_out duty cycle 40 50 60 % t cd clk_out to doutx (note 11) 4 ns t cfh clk_out to frame_valid high 4 ns t cfl clk_out to frame_valid low 4 ns t clh clk_out to line_valid high 4 ns t cll clk_out to line_valid low 4 ns frame specifications ? lvds t_int integration time range 0.035 100 (note 10) ms fps frame rate at full resolution (800 x 600 pixels) 120 fps fps_roi frame rate at 640 x 480 pixels resolution 180 fps fpix pixel rate 68 mpix/s frame specifications ? cmos fps frame rate at full resolution (800 x 600 pixels) 120 fps product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 5. all parameters are characterized for dc conditions after thermal equilibrium is established. 6. this device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. however, it is recommended that normal precautions be taken to avoid application of any voltages higher than the maximum rated voltages to this high impedance circuit. 7. minimum and maximum limits are guaranteed through test and design. 8. refer to acsPYTHON480 available at the image sensor portal for detailed acceptance criteria specifications. 9. cmos inputs are compatible with 3.3 v signal levels. 10. longer integration times are possible, but with possible image quality trade ? offs. 11. data is clocked on the rising edge of the output clock. this can be changed to the falling edge by register 130[8]
python 480 www. onsemi.com 6 color filter array the sensor is processed with a bayer rgb color pattern as shown in figure 1. pixel (0,0) has a red filter situated to the botto m left. figure 1. color filter array for the pixel array pixel (0;0) y x gb gr quantum efficiency figure 2. quantum efficiency curve for mono and color 0.0% 10.0% 20.0% 30.0% 40.0% 50.0% 60.0% 300 400 500 600 700 800 900 1000 1100 qe [%] wavelength [nm] red gr gb blue mono
python 480 www. onsemi.com 7 ray angle and microlens array information an array of microlenses is placed over the cmos pixel array in order to improve the absolute responsivity of the photodiodes. the combined microlens array and pixel array has two important properties: 1. angular dependency of photoresponse of a pixel the photoresponse of a pixel with microlens in the center of the array to a fixed optical power with varied incidence angle is as plotted in figure 3, where definitions of angles x and y are as described by figure 4. 2. microlens shift across array and cra the microlens array is fabricated with a slightly smaller pitch than the array of photodiodes. this difference in pitch creates a varying degree of shift of a pixel?s microlens with regards to its photodiode. a shift in microlens position versus photodiode position will cause a tilted angle of peak photoresponse, here denoted chief ray angle (cra). microlenses and photodiodes are aligned with 0 shift and cra in the center of the array, while the shift and cra increases radially towards its edges, as illustrated by figure 5. the purpose of the shifted microlenses is to improve the uniformity of photoresponse when camera lenses with a finite exit pupil distance are used. the cra varies nearly linearly with distance from the center as illustrated in figure 6, with a corner cra of approximately 1.65 degrees. this edge cra is matching a lens with exit pupil distance of ~ 60 mm. another cra option tar getting 23.59 degrees is available for both mono and color versions. the corresponding curves for this version is shown in figures 8 and 9. figure 3. central pixel photoresponse to a fixed optical power with incidence angle varied along x and y (low cra version) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 ? 30 ? 20 ? 100 102030 normalized response [degrees deviation from normal] incidence angle x , y note that the photoresponse peaks near normal incidence for center pixels. x = 0 y = 0
python 480 www. onsemi.com 8 figure 4. definition of angles used in figure 3. figure 5. principles of microlens shift shift center pixel (aligned) edge pixel (with shift) cra the center axes of the microlens and the photodiode coincide for the center pixels. for the edge pixels, there is a shift between the axes of the microlens and the photodiode causing a peak response incidence angle (cra) that deviates from the normal of the pixel array. figure 6. variation of peak responsivity angle (cra) as a function of distance from the center of the array (low cra version) cra [degrees] distance from center [mm] 0 0.5 1 1.5 2 2.5 0 0.5 1 1.5 2 2.5 x direction y direction diagonal 1.8 deg 2.3 deg 1.4 deg
python 480 www. onsemi.com 9 figure 7. central pixel photoresponse to a fixed optical power with incidence angle varied along x and y (high cra version) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 ? 30 ? 20 ? 100 102030 normalized response [degrees deviation from normal] incidence angle x , y note that the photoresponse peaks near normal incidence for center pixels. x = 0 y = 0 figure 8. variation of peak responsivity angle (cra) as a function of distance from the center of the array (high cra version) cra [degrees] distance from center [mm] 0 5 10 15 20 25 0 0.5 1 1.5 2 2.5 x direction y direction diagonal 19.4 deg 24.1 deg 14.4 deg
python 480 www. onsemi.com 10 figure 9. typical application diagram notes: ? vref_botplate power needs to allow source and sink; load is < 20 ma ? vdd_pix is 3.3 v low noise power supply. verify tolerance allowed in table 5. ? place low inductance bypass capacitors as close as possible to all power pins (10 f and 100 nf) ? lvds lines: route the differential output traces close together to maximize common ? mode rejection with the 100 termination resistor close to the receiver. user should pay attention to printed circuit board (pcb) trace lengths to minimize any delay skew. vdd_33 vdd_18 vdd_pix clock_outp clock_outn doutp doutn clk_pll lvds receiver lvds receiver reset_n 68 mhz vdd_1.8 v c1 c2 c3 c4 vdd_3.3 v vdd_pix vref_botplate vss_colpc vss_33 vss_18 vref_botplate lvds receiver syncp syncn lvds_clock_inp lvds_clock_inn 100 lvds clock input cmos output sck mosi ss_n miso trigger0 tr2 scan_en test_enable monitor0 line_valid monitor1 monitor2 lock_detect 47.7 k ibias_master mbsinout_1(h1) mbsinout_2 cp_calib cp_respd cp_sel_sample clk_out dout0 dout1 dout2 dout3 dout4 dout5 dout6 dout7 dout8 dout9 frame_valid tr1
python 480 www. onsemi.com 11 figure 10. recommended circuit for vref_botplate signal generation fb blm18ag601 lmv321 ? + 5 v 1.8 k 16 v 1.8 v vref_botplate 3.2 k 5 v 0.1 f 16 v 0.1 f 16 v 4.7 f
python 480 www. onsemi.com 12 overview figure 11 gives an overview of the major functional blocks of the sensor. figure 11. block diagram pixel array data formatting serializers & lvds interface spi interface lvds clock input lvds interface (data, sync, clock) 2 analog channels 2 x 10 bit digital channels 1 x 10 bit digital channels row decoder column structure image core bias image core automatic exposure control (aec) clock distribution external triggers reset cmos clock input lvds receiver pll control & registers cmos interface cmos interface (data, frame_valid, line_valid) analog front end (afe) image core the image core consists of: ? pixel array ? address decoders and row drivers ? pixel biasing the python 480 pixel array contains 808 (h) x 608 (v) readout pixels with a pixel pitch of 4.8 m, inclusive of 8 pixel rows and 8 pixel columns at every side to allow for reprocessing or color reconstruction. the sensors use in ? pixel cds architecture, which makes it possible to achieve a low noise read out of the pixel array in global shutter mode with cds. the function of the row drivers is to access the image array line by line, or all lines together, to reset or read the pixel data. the row drivers are controlled by the on ? chip sequencer and can access the pixel array. the pixel biasing block guarantees that the data on a pixel is transferred properly to the column multiplexer when the row drivers select a pixel line for readout. phase locked loop the pll accepts a (low speed) clock and generates the required high speed clock. input clock frequency is 68 mhz.
python 480 www. onsemi.com 13 lvds clock receiver the lvds clock receiver receives an lvds clock signal and distributes the required clocks to the sensor. input clock frequency is 340 mhz. the clock input needs to be terminated with a 100 resistor. column multiplexer all pixels of one image row are stored in the column sample ? and ? hold (s/h) stages. these stages store both the reset and integrated signal levels. the data stored in the column s/h stages is read out through 2 parallel differential outputs operating at a frequency of 34 mhz. at this stage, the reset signal and integrated signal values are transferred into an fpn ? corrected differential signal. a programmable gain of 1x, 2x, or 3.5x can be applied to the signal. the column multiplexer also supports read ? 1 ? skip ? 1 and read ? 2 ? skip ? 2 mode. enabling this mode increases the frame rate, with a decrease in resolution but same field of view. bias generator the bias generator generates all required reference voltages and bias currents used on chip. an external resistor of 47 k , connected between pin ibias_master and gnd_33, is required for the bias generator to operate properly. analog front end the afe contains 2 channels, each containing a pga and a 10 ? bit adc. for each of the 2 channels, a pipelined 10 ? bit adc is used to convert the analog image data into a digital signal, which is delivered to the data formatting block. a black calibration loop is implemented to ensure that the black level is mapped to match the correct adc input level. data formatting the data block receives data from two adcs and multiplexes this data to one data stream. a cyclic redundancy check (crc) code is calculated on the passing data. a frame synchronization data block transmits synchronization codes such as frame start, line start, frame end, and line end indications. the data block calculates a crc once per line for every channel. this crc code can be used for error detection at the receiving end. serializer and lvds interface (lvds mode only) the serializer and lvds interface block receives the formatted data from the data formatting block. this data is serialized and transmitted by the lvds 340 mhz output driver. the maximum output data rate is 680 mbps per channel. in addition to the lvds data outputs, two extra lvds outputs are available. one of these outputs carries the output clock, which is skew aligned to the output data channels. the second lvds output contains frame format synchronization codes to serve system ? level image reconstruction. cmos interface frame synchronization information is communicated by means of frame and line valid strobes. both cmos and lvds outputs are active at the same time. lvds channels can be powered down through spi control when using the cmos outputs. sequencer the sequencer: ? controls the image core. starts and stops integration and control pixel readout. ? operates the sensor in master or slave mode. ? applies the window settings. organizes readouts so that only the configured windows are read. ? controls the column multiplexer and analog core. applies gain settings and subsampling modes at the correct time, without corrupting image data. ? starts up the sensor correctly when leaving standby mode. automatic exposure control the aec block implements a control system to modulate the exposure of an image. both integration time and gains are controlled by this block to target a predefined illumination level.
python 480 www. onsemi.com 14 operating modes global shutter mode the python 480 operates in pipelined or triggered global shuttering modes. in this mode, light integration takes place on all pixels in parallel, although subsequent readout is sequential. figure 12 shows the integration and readout sequence for the global shutter. all pixels are light sensitive at the same period of time. the whole pixel core is reset simultaneously and after the integration time all pixel values are sampled together on the storage node inside each pixel. the pixel core is read out line by line after integration. note that the integration and readout can occur in parallel or sequentially. the integration starts at a certain period, relative to the frame start. figure 12. global shutter operation pipelined global shutter mode in pipelined global shutter mode, the integration and readout are done in parallel. images are continuously read and integration of frame n is ongoing during readout of the previous frame n ? 1. the readout of every frame starts with a frame overhead time (fot), during which the analog value on the pixel diode is transferred to the pixel memory element. after the fot, the sensor is read out line per line and the readout of each line is preceded by the row overhead time (rot). figure 13 shows the exposure and readout time line in pipelined global shutter mode. master mode in this mode, the integration time is set through the register interface and the sensor integrates and reads out the images autonomously. the sensor acquires images without any user interaction. figure 13. integration and readout for pipelined shutter reset n exposure time n reset n+1 exposure time n+1 readout frame n-1 fot fot readout frame n rot line readout fot fot slave mode the slave mode adds more manual control to the sensor. the integration time registers are ignored in this mode and the integration time is instead controlled by an external pin. as soon as the control pin is asserted, the pixel array goes out of reset and integration starts. the integration continues until the user or system deasserts the external pin. upon a falling edge of the trigger input, the image is sampled and the readout begins. figure 14 shows the relation between the external trigger signal and the exposure/readout timing.
python 480 www. onsemi.com 15 figure 14. pipelined shutter operated in slave mode reset n exposure time n reset n+1 exposure t im e n+1 readout n ? 1 fot fot readout n triggered global shutter mode in this mode, manual intervention is required to control both the integration time and the start of readout. after the integration time, indicated by a user controlled pin, the image core is read out. after this sequence, the sensor goes to an idle mode until a new user action is detected. the three main differences with the pipelined global shutter mode are: ? upon user action, one single image is read. ? normally, integration and readout are done sequentially. however, the user can control the sensor in such a way that two consecutive batches are overlapping, that is, having concurrent integration and readout. ? integration and readout is under user control through an external pin. this mode requires manual intervention for every frame. the pixel array is kept in reset state until requested. the triggered global mode can also be controlled in a master or in a slave mode. master mode in this mode, a rising edge on the synchronization pin is used to trigger the start of integration and readout. the integration time is defined by a register setting. the sensor autonomously integrates during this predefined time, after which the fot starts and the image array is readout sequentially. a falling edge on the synchronization pin does not have any impact on the readout or integration and subsequent frames are started again for each rising edge. figure 15 shows the relation between the external trigger signal and the exposure/readout timing. if a rising edge is applied on the external trigger before the exposure time and fot of the previous frame is complete, it is ignored by the sensor. figure 15. triggered shutter operated in master mode reset n exposure time n reset n+1 exposure time n+1 readout n-1 fot fot readout n rot line readout external trigger no effect on falling edge register controlled fot fot slave mode integration time control is identical to the pipelined shutter slave mode. an external synchronization pin controls the start of integration. when it is de ? asserted, the fot starts. the analog value on the pixel diode is transferred to the pixel memory element and the image readout can start. a request for a new frame is started when the synchronization pin is asserted again.
python 480 www. onsemi.com 16 sensor operation flowchart figure 16 shows the sensor operation flowchart. the sensor has six different ?states?. every state is indicated with the oval circle. these states are power off, low power standby, standby (1), standby (2), idle, running. figure 16. sensor operation flowchart power up sequence enable clock management - part 2 (first pass after hard reset) low-power standby required register upload standby (2) soft power-up idle enable sequencer running sensor (re-)configuration (optional) disable sequencer soft power-down disable clock management part 2 power off power down sequence intermediate standby enable clock management - part 2 (not first pass after hard reset) sensor (re-)configuration (optional) sensor (re-)configuration (optional) assertion of reset_n pin enable clock management - part 1 poll lock indication (only when pll is enabled) disable clock management part 1 standby (1)
python 480 www. onsemi.com 17 sensor states low power standby in low power standby state, all power supplies are on, but internally every block is disabled. no internal clock is running (pll / lvds clock receiver is disabled). only a subset of the spi registers is active for read/write in order to be able to configure clock settings and leave the low power standby state. the only spi registers that should be touched are the ones required for the ?enable clock management? action described in enable clock management ? part 1 on page 18 standby (1) in standby state, the pll/lvds clock receiver is running, but the derived logic clock signal is not enabled. standby (2) in standby state, the derived logic clock signal is running. all spi registers are active, meaning that all spi registers can be accessed for read or write operations. all other blocks are disabled. idle in the idle state, all internal blocks are enabled, except the sequencer block. the sensor is ready to start grabbing images as soon as the sequencer block is enabled. running in running state, the sensor is enabled and grabbing images. the sensor can be operated in global master/slave modes. user actions: power up functional mode sequences power up sequence figure 17 shows the power up sequence of the sensor. the figure indicates that the first supply to ramp ? up is the vdd_18 supply, followed by vdd_33 and vdd_pix respectively. it is important to comply with the described sequence. any other supply ramping sequence may lead to high current peaks and, as consequence, a failure of the sensor power up. the clock input should start running when all supplies are stabilized. when the clock frequency is stable, the reset_n signal can be de ? asserted. after a wait period of 10 s, the power up sequence is finished and the first spi upload can be initiated. note: the ?clock input? can be lvds clock input (lvds_clock_inn/p) in case the pll is bypassed. figure 17. power up sequence reset_n vdd_18 vdd_33 clock input vdd_pix > 10us > 10us > 10us > 10us spi upload > 10us enable clock management ? part 1 the ?enable clock management? action configures the clock management blocks and activates the clock generation and distribution circuits in a pre ? defined way. first, a set of clock settings must be uploaded through the spi register. these settings are dependent on the desired operation mode of the sensor. table 6 shows the spi uploads to be executed to configure the sensor for lvds 10 ? bit serial mode, with the pll. note that the spi uploads to be executed to configure the sensor for other supported modes are available to customers under nda at the on semiconductor image sensor portal: https://www.onsemi.com/powersolutions/myon/ercispfol der.do in the serial modes, if the pll is not used, the l vds clock input must be running. it is important to follow the upload sequence listed in table 6. use of phase locked loop if pll is used, the pll is started after the upload of the spi registers. the pll requires (dependent on the settings) some time to generate a stable output clock. a lock detect circuit detects if the clock is stable. when complete, this is flagged in a status register. note: since the pll is not used in cmos mode, the lock detect status must not be checked for the cmos mode sensor.
python 480 www. onsemi.com 18 check the pll_lock flag 24[0] by reading the spi register. when the flag is set, the ?enable clock management ? part 2? action can be continued. when pll is not used, this step can be bypassed as shown in figure 16 on page 16. table 6. enable clock management register upload: part 1 upload # address data description lvds mode with pll 1 2 0x0000 monochrome sensor 0x0001 color sensor 2 8 0x0000 release pll soft reset 3 16 0x0003 enable pll 4 17 0x2113 configure pll 5 20 0x0000 configure clock management 6 26 0x2280 configure pll lock detector 7 27 0x3d2d configure pll lock detector 8 32 0x7014 configure clock management enable clock management ? part 2 the next step to configure the clock management consists of spi uploads which enables all internal clock distribution. the required uploads are listed in table 4. note that it is important to follow the upload sequence listed in table 7. table 7. enable clock management register upload: part 2 upload # address data description lvds mode with pll 1 9 0x0000 release clock generator soft reset 2 32 0x7007 enable logic clock 3 34 0x0001 enable logic blocks required register upload in this phase, the ?reserved? register settings are uploaded through the spi register. different settings are not allowed and may cause the sensor to malfunction. the required uploads can be downloaded from the myon website.
python 480 www. onsemi.com 19 soft power up during the soft power up action, the internal blocks are enabled and prepared to start processing the image data stream. this action exists of a set of spi uploads. the soft power up uploads are listed in table 8. table 8. soft power up register upload upload # address data description lvds mode with pll 1 10 0x0000 release soft reset state 2 32 0x7007 enable analog clock 3 40 0x0003 enable column multiplexer 4 42 0x4113 configure image core 5 48 0x0001 enable afe 6 64 0x0001 enable biasing block 7 72 0x0127 enable charge pump 8 112 0x0007 enable lvds transmitters cmos mode with pll 1 10 0x0000 release soft reset state 2 32 0x7007 enable analog clock 3 40 0x0003 enable column multiplexer 4 42 0x4113 configure image core 5 48 0x0001 enable afe 6 64 0x0001 enable biasing block 7 72 0x0127 enable charge pump
python 480 www. onsemi.com 20 enable sequencer during the ?enable sequencer? action, the frame grabbing sequencer is enabled. the sensor starts grabbing images in the configured operation mode. refer to sensor states on page 17. the ?enable sequencer ? action consists of a set of register uploads. the required uploads are listed in table 9. table 9. enable sequencer register upload upload # address data (zrot) description 1 192 0x0803 enable sequencer user actions: functional modes to power down sequences disable sequencer during the ?disable sequencer? action, the frame grabbing sequencer is stopped. the sensor stops grabbing images and returns to the idle mode. the ?disable sequencer? action consists of a set of register uploads. as listed in table 10. table 10. disable sequencer register upload upload # address data (zrot) description 1 192 0x0802 disable sequencer soft power down during the soft power down action, the internal blocks are disabled and the sensor is put in standby state to reduce the current dissipation. this action exists of a set of spi uploads. the soft power down uploads are listed in table 12. table 11. soft power down register upload upload # address data description lvds mode with pll 1 112 0x0999 soft reset 2 72 0x7006 disable analog clock 3 64 0x0000 disable column multiplexer 4 48 0x4110 image core config 5 42 0x0000 disable afe 6 40 0x0000 disable biasing block 7 32 0x0010 disable charge pump 8 10 0x0000 disable lvds transmitters cmos mode with pll 1 72 0x0999 soft reset 2 64 0x7006 disable analog clock 3 48 0x0000 disable column multiplexer 4 42 0x4110 image core config 5 40 0x0000 disable afe 6 32 0x0000 disable biasing block 7 10 0x0010 disable charge pump
python 480 www. onsemi.com 21 disable clock management ? part 2 the ?disable clock management? action stops the internal clocking to further decrease the power dissipation. this action can be implemented with the spi uploads as shown in table 13. table 12. disable clock management register upload: part 2 upload # address data description lvds mode with pll 1 34 0x0000 soft reset clock generator 2 32 0x7004 disable logic clock 3 9 0x0000 disable logic blocks disable clock management ? part 1 the ?disable clock management? action stops the internal clocking to further decrease the power dissipation. this action can be implemented with the spi uploads as shown in table 13. table 13. disable clock management register upload: part 1 upload # address data description lvds mode with pll 1 16 0x0099 soft reset pll 2 8 0x0000 disable pll power down sequence figure 18 illustrates the timing diagram of the preferred power down sequence. it is important that the sensor is in reset before the clock input stops running. otherwise, the internal pll becomes unstable and the sensor gets into an unknown state. this can cause high peak currents. the same applies for the ramp down of the power supplies. the preferred order to ramp down the supplies is first vdd_pix, second vdd_33, and finally vdd_18. any other sequence can cause high peak currents. note: the ?clock input? can be the lvds clock input (lvds_clock_inn/p) in case the pll is bypassed. figure 18. power down sequence reset_n vdd_18 vdd_33 clock input vdd_pix > 10us > 10us > 10us > 10us
python 480 www. onsemi.com 22 sensor reconfiguration during the standby, idle, or running state several sensor parameters can be reconfigured. ? frame rate and exposure time: frame rate and exposure time changes can occur during standby, idle, and running states by modifying registers 199 to 203. refer to page 30 ? 32 for more information. ? signal path gain: signal path gain changes can occur during standby, idle, and running states by modifying registers 204/205. refer to page 37 for more information. ? windowing: changes with respect to windowing can occur during standby, idle, and running states. refer to multiple window readout on page 29 for more information. ? subsampling: changes of the subsampling mode can occur during standby, idle, and running states by modifying register 192. refer to subsampling on page 30 for more information. ? shutter mode: the shutter mode can only be changed during standby or idle mode by modifying register 192. reconfiguring the shutter mode during running state is not supported. sensor configuration this device contains multiple configuration registers. some of these registers can only be configured while the sensor is not acquiring images (while register 192[0] = 0), while others can be configured while the sensor is acquiring images. for the latter category of registers, it is possible to distinguish the register set that can cause corrupted images (limited number of images containing visible artifacts) from the set of registers that are not causing corrupted images. these three categories are described here. static readout parameters some registers are only modified when the sensor is not acquiring images. reconfiguration of these registers while images are acquired can cause corrupted frames or even interrupt the image acquisition. therefore, it is recommended to modify these static configurations while the sequencer is disabled (register 192[0] = 0). the registers shown in t able 14 should not be reconfigured during image acquisition. a specific configuration sequence applies for these registers. refer to the operation flow and startup description. table 14. static readout parameters group addresses description clock generator 32 configure according to recommendation image core 40 configure according to recommendation afe 48 configure according to recommendation bias 64?71 configure according to recommendation lvds 112 configure according to recommendation sequencer mode selection 192 [5:4] operation modes are: ? triggered_mode ? slave_mode all reserved registers keep reserved registers to their default state, unless otherwise described in the recommendation dynamic configuration potentially causing image artifacts the category of registers as shown in table 15 consists of configurations that do not interrupt the image acquisition process, but may lead to one or more corrupted images during and after the reconfiguration. a corrupted image is an image containing visible artifacts. a typical example of a corrupted image is an image which is not uniformly exposed. the effect is transient in nature and the new configuration is applied after the transient effect. table 15. dynamic configuration potentially causing image artifacts group addresses description black level configuration 128?129 197[12:8] reconfiguration of these registers may have an impact on the black ? level calibration algorithm. the effect is a transient number of images with incorrect black level compensation. sync codes 129[13] 116?126 incorrect sync codes may be generated during the frame in which these registers are modified. datablock test configurations 144 modification of these registers may generate incorrect test patterns during a transient frame.
python 480 www. onsemi.com 23 dynamic readout parameters it is possible to reconfigure the sensor while it is acquiring images. frame related parameters are internally resynchronized to frame boundaries, such that the modified parameter does not affect a frame that has already started. however, there can be restrictions to some registers as shown in table 16. some reconfiguration may lead to one frame being blanked. this happens when the modification requires more than one frame to settle. the image is blanked out and training patterns are transmitted on the data and sync channels. table 16. dynamic readout parameters group addresses description subsampling 192[7] subsampling is synchronized to a new frame start. roi configuration 195 256?265 a roi switch is only detected when a new window is selected as the active window (reconfiguration of register 195). reconfiguration of the roi dimension of the active win- dow does not lead to a frame blank and can cause a corrupted image. exposure reconfiguration 199 ? 203 exposure reconfiguration does not cause artifact. however, a latency of one frame is ob- served unless reg_seq_exposure_sync_mode is set to ?1? in triggered global mode (mas- ter). gain reconfiguration 204 ? 205 gains are synchronized at the start of a new frame. optionally, one frame latency can be incorporated to align the gain updates to the exposure updates (refer to register 204[13] ? gain_lat_comp). freezing active configurations though the readout parameters are synchronized to frame boundaries, an update of multiple registers can still lead to a transient effect in the subsequent images, as some configurations require multiple register uploads. for example, to reconfigure the exposure time in master global mode, both the fr_length and exposure registers need to be updated. internally, the sensor synchronizes these configurations to frame boundaries, but it is still possible that the reconfiguration of multiple registers spans over two or even more frames. to avoid inconsistent combinations, the active configurations can be frozen while altering the spi registers by disabling synchronization for the corresponding functionality before reconfiguration. when all registers are uploaded, re ? enable the synchronization. the sensor?s sequencer then updates its active set of registers and uses them for the coming frames. freezing of the active set of registers can be programmed in the sync_configuration registers, which can be found at the spi address 206. figure 19 shows a reconfiguration that does not use the sync_configuration option. as depicted, new spi configurations are synchronized to frame boundaries. figure 20 shows the usage of the sync_configuration settings. before uploading a set of registers, the corresponding sync_configuration is de ? asserted. after the upload is completed, the sync_configuration is asserted again and the sensor resynchronizes its set of registers to the coming frame boundaries. as seen in the figure, this ensures that the uploads performed at the end of frame n+2 and the start of frame n+3 become active in the same frame (frame n+4). figure 19. frame synchronization of configurations (no freezing) frame nframe n+1?frame n+2?frame n+3 frame n+4 time line spi registers active registers
python 480 www. onsemi.com 24 figure 20. reconfiguration using sync_configuration frame nframe n+1?frame n+2?frame n+3?frame n+4 time line sync_configuration spi registers active registers this configuration is not taken into account as sync_register is inactive. note: spi updates are not taken into account while sync_configuration is inactive. the active configuration is frozen for the sensor. table 17 lists the several sync_configuration possibilities along with the respective registers being frozen. table 17. alternate sync configurations group affected registers description sync_black_lines black_lines update of black line configuration is not synchronized at start of frame when ?0?. the sensor continues with its previous configurations. sync_dummy_lines dummy_lines update of dummy line configuration is not synchronized at start of frame when ?0?. the sensor continues with its previous configurations. sync_exposure mult_timer fr_length exposure update of exposure configurations is not synchronized at start of frame when ?0?. the sensor continues with its previous configurations. sync_gain mux_gainsw afe_gain db_gain update of gain configurations is not synchronized at start of frame when ?0?. the sensor continues with its previous configurations. sync_roi roi_active0[3:0] subsampling update of active roi configurations is not synchronized at start of frame when ?0?. the sensor continues with its previous configurations. note: the window configurations themselves are not frozen. reconfiguration of active windows is not gated by this setting. window configuration up to 4 windows can be defined in global shutter mode (pipelined or triggered). the windows are defined by registers 256 to 265. each window can be activated or deactivated separately using register 195. it is possible to reconfigure the inactive windows while the sensor is acquiring images. switching between predefined windows is achieved by activation of the respective windows. this way a minimum number of registers need to be uploaded when it is necessary to switch between two or more sets of windows. as an example of this, scanning the scene at higher frame rates using multiple windows and switching to full frame capture when the object is tracked. switching between the two modes only requires an upload of one register. black calibration the sensor automatically calibrates the black level for each frame. therefore, the device generates a configurable number of electrical black lines at the start of each frame. the desired black level in the resulting output interface can be configured and is not necessarily targeted to ?0?. configuring the target to a higher level yields some information on the left side of the black level distribution, while the other end of the distribution tail is clipped to ?0? when setting the black level target to ?0?. the black level is calibrated for the 2 columns contained in one kernel. this implies 2 black level of fsets are generated and applied to the corresponding columns. configurable parameters for the black ? level algorithm are listed in table 18.
python 480 www. onsemi.com 25 table 18. configurable parameters for black level algorithm group addresses description black line generation 197[7:0] black_lines this register configures the number of black lines that are generated at the start of a frame. at least one black line must be generated. the maximum number is 255. note: when the automatic black ? level calibration algorithm is enabled, make sure that this register is configured properly to produce sufficient black pixels for the black ? level filtering. the number of black pixels generated per line is dependent on the operation mode and window configurations: each black line contains 404 kernels. 197[12:8] gate_first_line a number of black lines are blanked out when a value different from 0 is configured. these blanked out lines are not used for black calibration. it is recommended to enable this func- tionality, because the first line can have a different behavior caused by boundary effects. black value filtering 129[0] auto_blackcal_enable internal black ? level calibration functionality is enabled when set to ?1?. required black level offset compensation is calculated on the black samples and applied to all image pixels. when set to ?0?, the automatic black ? level calibration functionality is disabled. it is possible to apply an offset compensation to the image pixels, which is defined by the registers 129[10:1]. note: black sample pixels are not compensated; the raw data is sent out to provide external statistics and, optionally, calibrations. 129[9:1] blackcal_offset black calibration offset that is added or subtracted to each regular pixel value when au- to_blackcal_enable is set to ?0?. the sign of the offset is determined by register 129[10] (blackcal_offset_dec). note: all channels use the same offset compensation when automatic black calibration is disabled. the calculated black calibration factors are frozen when this register is set to 0x1ff (all ? ?1?) in auto calibration mode. any value different from 0x1ff re ? enables the black calibration algorithm. this freezing option can be used to prevent eventual frame to frame jitter on the black level as the correction factors are recalculated every frame. it is recommended to enable the black calibration regularly to compensate for temperature changes. 129[10] blackcal_offset_dec sign of blackcal_offset. if set to ?0?, the black calibration offset is added to each pixel. if set to ?1?, the black calibration offset is subtracted from each pixel. this register is not used when auto_blackcal_enable is set to ?1?. 128[10:8] black_samples the black samples are low ? pass filtered before being used for black level calculation. the more samples are taken into account, the more accurate the calibration, but more samples require more black lines, which in turn affects the frame rate. the effective number of samples taken into account for filtering is 2^black_samples. note: an error is reported by the device if more samples than available are requested (refer to register 136). black level filtering monitoring 136 blackcal_error0 an error is reported by the device if there are requests for more samples than are available (each bit corresponding to one data path). the black level is not compensated correctly if one of the channels indicates an error. there are three possible methods to overcome this situation and to perform a correct offset compensation: ? increase the number of black lines such that enough samples are generated at the cost of increasing frame time (refer to register 197). ? relax the black calibration filtering at the cost of less accurate black level determina- tion (refer to register 128). ? disable automatic black level calibration and provide the offset via spi register upload. note that the black level can drift in function of the temperature. it is thus recommended to perform the offset calibration periodically to avoid this drift. note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm.
python 480 www. onsemi.com 26 serial peripheral interface the sensor configuration registers are accessed through an spi. the spi consists of four wires: ? sck: serial clock ? ss_n: active low slave select ? mosi: master out, slave in, or serial data in ? miso: master in, slave out, or serial data out the spi is synchronous to the clock provided by the master (sck) and asynchronous to the sensor?s system clock. when the master wants to write or read a sensor?s register, it selects the chip by pulling down the slave select line (ss_n). when selected, data is sent serially and synchronous to the spi clock (sck). figure 21 shows the communication protocol for read and write accesses of the spi registers. the python 480 image sensors use 9 ? bit addresses and 16 ? bit data words. data driven by the system is colored blue in figure 21, while data driven by the sensor is colored yellow. the data in grey indicates high ? z periods on the miso interface. red markers indicate sampling points for the sensor (mosi sampling); green markers indicate sampling points for the system (miso sampling during read operations). the access sequence is: 3. select the sensor for read or write by pulling down the ss_n line. 4. one spi clock cycle after selecting the sensor, the 9 ? bit data is transferred, most significant bit first. the sck clock is passed through to the sensor as indicated in figure 21. the sensor samples this data on a rising edge of the sck clock (mosi needs to be driven by the system on the falling edge of the sck clock). 5. the tenth bit sent by the master indicates the type of transfer: high for a write command, low for a read command. 6. data transmission: - for write commands, the master continues sending the 16 ? bit data, most significant bit first. - for read commands, the sensor returns the requested address on the miso pin, most significant bit first. the miso pin must be sampled by the system on the falling edge of sck (assuming nominal system clock frequency and maximum 10 mhz spi frequency). 7. when data transmission is complete, the system deselects the sensor one clock period after the last bit transmission by pulling ss_n high. note that the maximum frequency for the spi interface scales with the input clock frequency, bit depth and lvds output multiplexing as described in table 5. consecutive spi commands can be issued by leaving at least two spi clock periods between two register uploads. deselect the chip between the spi uploads by pulling the ss_n pin high. figure 21. spi read and write timing diagram .. a1 a0 `1' a8 d15 d14 .. .. .. .. d1 d0 sck mosi ss_n miso a7 .. .. .. a1 a0 `0' a8 sck mosi ss_n miso a7 .. .. d15 d14 .. .. .. .. d1 d0 ts_mosi th_mosi t_sssck t_sckss ts _miso th_miso t_sckss t_sssck ts _mos i th_mosi tsck tsck spi ? write spi ? read
python 480 www. onsemi.com 27 table 19. spi timing requirements group addresses description units tsck sck clock period 100 (*) ns tsssck ss_n low to sck rising edge tsck ns tsckss sck falling edge to ss_n high tsck ns ts_mosi required setup time for mosi 20 ns th_mosi required hold time for mosi 20 ns ts_miso setup time for miso tsck/2 ? 10 ns th_miso hold time for miso tsck/2 ? 20 ns tspi minimal time between two consecutive spi accesses (not shown in figure) 2 x tsck ns *value indicated is for nominal operation. the maximum spi clock frequency depends on the sensor configuration (operation mode, input clock). tsck is defined as 1/f spi . see text for more information on spi clock frequency restrictions. image sensor timing and readout the following sections describe the configurations for single slope reset mechanism. extra integration time registers are available. pipelined global shutter (master) the integration time is controlled by the registers fr_length[15:0] and exposure[15:0]. the mult_timer configuration defines the granularity of the registers reset_length and exposure. it is read as number of system clock cycles (14.706 ns nominal at 68 mhz). the exposure control for (pipelined) global master mode is depicted in figure 22. the pixel values are transferred to the storage node during fot, after which all photo diodes are reset. the reset state remains active for a certain time, defined by the reset_length and mult_timer registers, as shown in the figure. note that meanwhile the image array is read out line by line. after this reset period, the global photodiode reset condition is abandoned. this indicates the start of the integration or exposure time. the length of the exposure time is defined by the registers exposure and mult_timer. note: the start of the exposure time is synchronized to the start of a new line (during rot) if the exposure period starts during a frame readout. as a consequence, the effective time during which the image core is in a reset state is extended to the start of a new line. ? make sure that the sum of the reset time and exposure time exceeds the time required to readout all lines. if this is not the case, the exposure time is extended until all (active) lines are read out. ? alternatively, it is possible to specify the frame time and exposure time. the sensor automatically calculates the required reset time. this mode is enabled by the fr_mode register. the frame time is specified in the register fr_length. figure 22. integration control for (pipelined) global shutter mode (master) reset integrating reset integrating image array global reset readout fot fot fot fot fot fot reset_length x mult_timer frame n frame n+1 exposure state = rot = readout = readout dummy line (blanked) exposure x mult_timer
python 480 www. onsemi.com 28 triggered global shutter (master) in master triggered global mode, the start of integration time is controlled by a rising edge on the trigger0 pin. the exposure or integration time is defined by the registers exposure and mult_timer, as in the master pipelined global mode. the fr_length configuration is not used. this operation is graphically shown in figure 23. figure 23. exposure time control in triggered shutter mode (master) reset integrating reset integrating image array global reset readout fot fot fot fot fot fot exposure x mult_timer frame n frame n+1 exposure state (no effect on falling edge) trigger0 = rot = readout = readout dummy line (blanked) notes: ? the falling edge on the trigger pin does not have any impact. note however the trigger must be asserted for at least 100 ns. ? the start of the exposure time is synchronized to the start of a new line (during rot) if the exposure period starts during a frame readout. as a consequence, the effective time during which the image core is in a reset state is extended to the start of a new line. ? if the exposure timer expires before the end of readout, the exposure time is extended until the end of the last active line. ? the trigger pin needs to be kept low during the fot. the monitor pins can be used as a feedback to the fpga/controller (eg. use monitor0, indicating the very first line when monitor_select = 0x5 ? a new trigger can be initiated after a rising edge on monitor0). triggered global shutter (slave) exposure or integration time is fully controlled by means of the trigger pin in slave mode. the registers fr_length, exposure and mult_timer are ignored by the sensor. a rising edge on the trigger pin indicates the start of the exposure time, while a falling edge initiates the transfer to the pixel storage node and readout of the image array. in other words, the high time of the trigger pin indicates the integration time, the period of the trigger pin indicates the frame time. the use of the trigger during slave mode is shown in figure 24. notes: ? the registers exposure, fr_length, and mult_timer are not used in this mode. ? the start of exposure time is synchronized to the start of a new line (during rot) if the exposure period starts during a frame readout. as a consequence, the effective time during which the image core is in a reset state is extended to the start of a new line. ? if the trigger is de ? asserted before the end of readout, the exposure time is extended until the end of the last active line. ? the trigger pin needs to be kept low during the fot. the monitor pins can be used as a feedback to the fpga/controller (eg. use monitor0, indicating the very first line when monitor_select = 0x5 ? a new trigger can be initiated after a rising edge on monitor0). figure 24. exposure time control in global ? slave mode reset integrating reset integrating image array global reset readout fot fot fot fot fot fot frame n frame n+1 exposure state trigger0 = rot = readout = readout dummy line (blanked)
python 480 www. onsemi.com 29 additional features multiple window readout the python 480 image sensors support multiple window readout, which means that only the user ? selected regions of interest (roi) are read out. this allows limiting data output for every frame, which in turn allows increasing the frame rate. up to four rois can be configured. window configuration figure 25 shows the four parameters defining a region of interest (roi). figure 25. region of interest configuration y-start y-end x-start?x-end roi 0 ? x ? start[8:0] x ? start defines the x ? starting point of the desired window. the sensor reads out 2 pixels in one single clock cycle. as a consequence, the granularity for configuring the x ? start position is also 2 pixels for no sub sampling. the value configured in the x ? start register is multiplied by 2 to find the corresponding column in the pixel array. ? x ? end[8:0] this register defines the window end point on the x ? axis. similar to x ? start, the granularity for this configuration is one kernel. x ? end needs to be larger than x ? start. ? y ? start[9:0] the starting line of the readout window. the granularity of this setting is one line, except with color sensors where it needs to be an even number. ? y ? end[9:0] the end line of the readout window. y ? end must be configured larger than y ? start. this setting has the same granularity as the y ? start configuration. up to four windows can be defined, possibly (partially) overlapping, as illustrated in figure 26. note: the least significant configuration bits for x and y parameters are located in separate registers (refer to registers 264 ? 265). one may decide not to reconfigure these bits, in which case the configuration granularity becomes 4 pixels for both x ? and y ? configurations. figure 26. overlapping multiple window configuration y0_start y1_start y0_end y1_end x0_start x1_start x0_end x1_end roi 0 roi 1 the sequencer analyses each line that need to be read out for multiple windows. restrictions the following restrictions for each line are assumed for the user configuration: ? windows are ordered from left to right, based on their x ? start address: x_start_roi(i) x_start_roi(j) and x_end_roi(i) x_end_roi(j) where j i > processing multiple windows the sequencer control block houses two sets of counters to construct the image frame. as previously described, the y ? counter indicates the line that needs to be read out and is incremented at the end of each line. for the start of the frame, it is initialized to the y ? start address of the first window and it runs until the y ? end address of the last window to be read out. the last window is configured by the configuration registers and it is not necessarily window #3. the x ? counter starts counting from the x ? start address of the window with the lowest id which is active on the addressed line. only windows for which the current y ? address is enclosed are taken into account for scanning. other windows are skipped.
python 480 www. onsemi.com 30 figure 27 illustrates a practical example of a configuration with four windows. the current position of the read pointer (ys) is indicated by a red line crossing the image array. for this position of the read pointer, three windows need to be read out. the initial start position for the x ? kernel pointer is the x ? start configuration of roi0. kernels are scanned up to the roi2 x ? end position. from there, the x ? pointer jumps to the next window, which is roi3 in this illustration. when reaching roi3?s x ? end position, the read pointer is incremented to the next line and xs is reinitialized to the starting position of roi0. notes: ? the starting point for the readout pointer at the start of a frame is the y ? start position of the first active window. ? the read pointer is not necessarily incremented by one, but depending on the configuration, it can jump in y ? direction. in figure 27, this is the case when reaching the end of roi0 where the read pointer jumps to the y ? start position of roi1 ? the x ? pointer starting position is equal to the x ? start configuration of the first active window on the current line addressed. this window is not necessarily window #0. ? the x ? pointer is not necessarily incremented by one each cycle. at the end of a window it can jump to the start of the next window. ? each window can be activated separately. there is no restriction on which window and how many of the 4 windows are active. figure 27. scanning the image array with four windows roi 0 roi 3 ys roi 2 roi 1 subsampling subsampling is used to reduce the image resolution. this allows increasing the frame rate. two subsampling modes are supported: for monochrome sensors (lvds/cmos) and color sensors (lvds/cmos). monochrome sensors for monochrome sensors, the read ? 1 ? skip ? 1 subsampling scheme is used. subsampling occurs both in x ? and y ? direction. color sensors for color sensors, the read ? 2 ? skip ? 2 subsampling scheme is used. subsampling occurs both in x ? and y ? direction. figure 28 shows which pixels are read and which ones are skipped. figure 28. subsampling scheme for monochrome and color sensors reverse readout reverse readout in y ? direction can be done by toggling reverse_y (reg 194[8]). the reference for y_start and y_end pointers is reversed. reverse readout in x ? direction can be done by toggling reverse_x (reg 194[9]).
python 480 www. onsemi.com 31 black reference the sensor reads out one or more black lines at the start of every new frame. the number of black lines to be generated is programmable and is minimal equal to 1. the length of the black lines depends on the operation mode. the sensor always reads out the entire line (404 kernels), independent of window configurations. the black references are used to perform black calibration and offset compensation in the data channels. the raw black pixel data is transmitted over the usual output interface, while the regular image data is compensated (can be bypassed). on the output interface, black lines can be seen as a separate window, however without frame start and ends (only line start/end). the sync code following the line start and line end indications (?window id?) contains the active window number, which is 0. black reference data is classified by a bl code. reference lines the sensor optionally reads out one or more reference lines after the black lines. the number of reference lines to be generated is programmable. no reference lines shall be generated when set to 0. as for the black lines, the length of the reference lines depends on the operation mode. the reference lines are not used internally in the sensor. the rot for these lines can be configured such that these lines contain particular reference data, such as a grey level, in order to perform prnu correction off ? chip. reference lines are indicated on the output interface by means of a dedicated sync pattern (ref). the black calibration block can be configured to either perform black level correction and compression or not. in the latter case, the lsb is discarded from the adc word. optionally, the black level calibration processor can be configured to transmit the average black level on the reference lines. in this mode, the reference pixel data are replaced by the average black level, as calculated by the black calibration block. channel differences can easily be observed in this mode (see register reg_db_ref_bcal_enable). signal path gain analog gain stages referring to table 20, three gain settings are available in the analog data path to apply gain to the analog signal before it is digitized. the gain amplifier can apply a gain of approximately 1x to 3.5x to the analog signal. the moment a gain reconfiguration is applied and becomes valid can be controlled by the gain_lat_comp configuration. with ?gain_lat_comp? set to ?0?, the new gain configurations are applied from the very next frame. with ?gain_lat_comp? set to ?1?, the new gain settings are postponed by one extra frame. this feature is useful when exposure time and gain are reconfigured together, as an exposure time update always has one frame latency. table 20. signal path gain stages address gain setting gain stage 1 (204[4:0]) gain stage 2 (204[12:5]) overall gain 204[12:0] 0x00e1 1 1 1 204[12:0] 0x00e4 2 1 2 204[12:0] 0x0024 2 1.75 3.5 note: the sensor performance specifications are tested at unity gain. analog gain above 2x affects noise performance. all other gains settings shown in this table are tested for sensor functionality only. digital gain stage the digital gain stage allows fine gain adjustments on the digitized samples. the gain configuration is an absolute 5.7 unsigned number (5 digits before and 7 digits after the decimal point).
python 480 www. onsemi.com 32 automatic exposure control the exposure control mechanism has the shape of a general feedback control system. figure 29 shows the high level block diagram of the exposure control loop. figure 29. automatic exposure control loop aec statistics aec filter aec enforcer requested gain changes total gain integration time analog gain (coarse steps) requested illumination level (target) digital gain (fine steps) image capture three main blocks can be distinguished: ? the statistics block compares the average of the current image?s samples to the configured target value for the average illumination of all pixels ? the relative gain change request from the statistics block is filtered through the aec filter block in the time domain (low pass filter) before being integrated. the output of the filter is the total requested gain in the complete signal path. ? the enforcer block accepts the total requested gain and distributes this gain over the integration time and gain stages (both analog and digital) the automatic exposure control loop is enabled by asserting the aec_enable configuration in register 160. aec statistics block the statistics block calculates the average illumination of the current image. based on the difference between the calculated illumination and the target illumination the statistics block requests a relative gain change. statistics subsampling and windowing for average calculation, the statistics block will sub ? sample the current image or windows by taking every fourth sample into account. note that only the pixels read out through the active windows are visible for the aec. in the case where multiple windows are active, the samples will be selected from the total samples. samples contained in a region covered by multiple (overlapping) window will be taking into account only once. it is possible to define an aec specific sub ? window on which the aec will calculate it?s average. for instance, the sensor can be configured to read out a larger frame, while the illumination is measured on a smaller region of interest, e.g. center weighted as shown in table 21. table 21. aec sample selection register name description 192[10] roi_aec_enable when 0x0, all active windows are selected for statistics calculation. when 0x1, the aec samples are selected from the active pixels contained in the region of interest defined by roi_aec 253 ? 255 roi_aec these registers define a window from which the aec samples will be selected when roi_aec_enable is asserted. configuration is similar to the regular region of interests. the intersection of this window with the active windows define the selected pixels. it is important that this window at least overlaps with one or more active windows.
python 480 www. onsemi.com 33 target illumination the target illumination value is configured by means of register desired_intensity as shown in table 22. table 22. aec target illumination configuration register name description 161[9:0] desired_in- tensity target intensity value, on 10 ? bit scale. color sensor the weight of each color can be configured for color sensors by means of scale factors. note these scale factor are only used to calculate the statistics in order to compensate for (off ? chip) white balancing and/or color matrices. the pixel values itself are not modified. the scale factors are configured as 3.7 unsigned numbers (0x80 = unity). refer to t able 23 for color scale factors. for mono sensors, configure these factors to their default value. table 23. color scale factors register name description 162[9:0] red_scale_factor red scale factor for aec statistics 163[9:0] green1_scale_fa ctor green1 scale factor for aec statistics 164[9:0] green2_scale_fa ctor green2 scale factor for aec statistics 165[9:0] blue_scale_factor blue scale factor for aec statistics aec filter block the filter block low ? pass filters the gain change requests received from the statistics block. the filter can be restarted by asserting the restart_filter configuration of register 160. aec enforcer block the enforcer block calculates the four different gain parameters, based on the required total gain, thereby respecting a specific hierarchy in those configurations. some (digital) hysteresis is added so that the (analog) sensor settings don?t need to change too often. exposure control parameters the several gain parameters are described below, in the order in which these are controlled by the aec for large adjustments. small adjustments are regulated by digital gain only. ? exposure time the exposure is the time between the global image array reset de ? assertion and the pixel charge transfer. the granularity of the integration time steps is configured by the mult_timer register. note: the exposure_time register is ignored when the aec is enabled. the register fr_length defines the frame time and needs to be configured accordingly. ? analog gain the sensor has two analog gain stages, configurable independently from each other. t ypically the aec shall only regulate the first stage. ? digital gain the last gain stage is a gain applied on the digitized samples. the digital gain is represented by a 5.7 unsigned number (i.e. 7 bits after the decimal point). while the analog gain steps are coarse, the digital gain stage makes it possible to achieve very fine adjustments.
python 480 www. onsemi.com 34 aec control range the control range for each of the exposure parameters can be pre ? programmed in the sensor. t able 24 lists the relevant registers. table 24. minimum and maximum exposure control parameters register name description 168[15:0] min_exposure lower bound for the integration time applied by the aec 169[1:0] min_mux_gain lower bound for the first stage analog amplifier. this stage has two configurations with the following approximative gains: 0x1 = 1x 0x4 = 2x 169[3:2] min_afe_gain lower bound for the second stage analog amplifier. this stage has two configurations with the following approximative gain settings: 0x7 = 1x 0x1 = 1.75x 169[15:4] min_digital_gain lower bound for the digital gain stage. this configuration specifies the effective gain in 5.7 unsigned format 170[15:0] max_exposure upper bound for the integration time applied by the aec 171[1:0] max_mux_gain upper bound for the first stage analog amplifier. this stage has two configurations with the following approximative gains: 0x1 = 1x 0x4 = 2x 171[3:2] max_afe_gain upper bound for the second stage analog amplifier this stage has two configurations with the following approximative gain settings: 0x7 = 1x 0x1 = 1.75x 171[15:4] max_digit- al_gain upper bound for the digital gain stage. this configuration specifies the effective gain in 5.7 unsigned format aec update frequency as an integration time update has a latency of one frame, the exposure control parameters are evaluated and updated every other frame. note: the gain update latency must be postpone to match the integration time latency. this is done by asserting the gain_lat_comp register on address 204[13]. exposure control status registers configured integration and gain parameters are reported to the user by means of status registers. the sensor provides two levels of reporting: the status registers reported in the aec address space are updated once the parameters are recalculated and requested to the internal sequencer. the status registers residing in the sequencer?s address space on the other hand are updated once these parameters are taking effect on the image readout. refer to table 25 reflecting the aec and sequencer status registers. table 25. exposure control status registers register name description aec status registers 184[15:0] total_pixels total number of pixels taken into account for the aec statistics. 186[9:0] average calculated average illumination level for the current frame. 187[15:0] exposure aec calculated exposure. note: this parameter is updated at the frame end. 188[1:0] mux_gain aec calculated analog gain (1 st stage) note: this parameter is updated at the frame end. 188[3:2] afe_gain aec calculated analog gain (2 st stage) note: this parameter is updated at the frame end. 188[15:4] digital_gain aec calculated digital gain (5.7 unsigned format) note: this parameter is updated at the frame end.
python 480 www. onsemi.com 35 mode changes and frame blanking dynamically reconfiguring the sensor may lead to corrupted or non-uniformilly exposed frames. for some reconfigurations, the sensor automatically blanks out the image data during one frame. frame blanking is summarized in the following table for the sensor?s image related modes. note: major mode switching (i.e. switching between master, triggered or slave mode) must be performed while the sequencer is disabled (reg_seq_enable = 0x0). table 26. dynamic sensor reconfiguration and frame blanking configuration corrupted frame blanked out frame notes shutter mode and operation triggered_mode do not reconfigure while the sensor is acquiring images. disable image acquisition by setting reg_seq_enable = 0x0. slave_mode do not reconfigure while the sensor is acquiring images. disable image acquisition by setting reg_seq_enable = 0x0. subsampling enabling: no disabling: yes configurable configurable with blank_subsampling_ss register. frame timing black_lines no no exposure control mult_timer no no latency is 1 frame fr_length no no latency is 1 frame exposure no no latency is 1 frame gain mux_gainsw no no latency configurable by means of gain_lat_comp register afe_gain no no latency configurable by means of gain_lat_comp register. db_gain no no latency configurable by means of gain_lat_comp register. window/roi roi_active see note no windows containing lines previously not read out may lead to corrupted frames. roi*_configuration* see note no reconfiguring the windows by means of roi*_configuration* may lead to corrupted frames when configured close to frame boundaries. it is recommended to (re)configure an inactive window and switch the roi_active register. see notes on roi_active. black calibration black_samples no no if configured within range of configured black lines auto_blackal_enable see note no manual correction factors become instantly active when auto_blackcal_enable is deasserted during operation. blackcal_offset see note no manual blackcal_offset updates are instantly active. crc calculation crc_seed no no impacts the transmitted crc sync channel bl_0 no no impacts the sync channel information, not the data channels. img_0 no no impacts the sync channel information, not the data channels. crc_0 no no impacts the sync channel information, not the data channels. tr_0 no no impacts the sync channel information, not the data channels.
python 480 www. onsemi.com 36 monitor pins the internal sequencer has two monitor outputs (pin 44 and pin 45) that can be used to communicate the internal states from the sequencer. a three ? bit register configures the assignment of the pins as shown in table 27. table 27. monitor select monitor select monitor output description 0x0 monitor0: ?0? no information is provided on the output pins. all outputs are driven to logic ?0? monitor1: ?0? monitor2: ?0? 0x1 monitor0: integration time indication high during integration monitor1: rot indication high when rot is active, low outside rot monitor2: dummy line indication high during dummy lines, low during all other lines 0x2 monitor0: integration time indication high during integration monitor1: n/a n/a monitor2: n/a n/a 0x3 monitor0: start of x-readout pulse indicating the start of x-readout monitor1: black line indication high during black lines, low during all other lines monitor2: dummy line indication high during dummy lines, low during all other lines 0x4 monitor0: frame start pulse indicating the start of a new frame monitor1: start of rot pulse indicating the start of rot monitor2: start of x-readout pulse indicating the start of x-readout 0x5 monitor0: first line indication high during the first line of each frame, low for all others monitor1: start of rot indication pulse indicating the start of rot monitor2: rot inactive low when rot is active, high outside rot 0x6 monitor0: rot indication high when rot is active, low outside rot monitor1: start of x-readout pulse indicating the start of x-readout monitor2: x-readout inactive low during x-readout, high outside x-readout 0x7 monitor0: start of x-readout for black lines pulse indicating the start of x-readout for black lines monitor1: start of x-readout for image lines pulse indicating the start of x-readout for image lines monitor2: start of x-readout for dummy lines pulse indicating the start of x-readout for dummy lines
python 480 www. onsemi.com 37 sequences of frame acquisition with different configurations frame dependent configurations require multiple contexts, which are sync?ed upon a start of a new frame. the following configurations are context switchable: ? fot program ? rot programs (only for regular rot in global shutter mode (no muxing for black reference rot programs)) ? integration time ? gain (both digital and analog) ? active roi configuration (not the window configuration themselves) when enabled, the sequencer shall automatically select one set of parameters for the even frames and the other set of parameters for the odd frames. this operation mode is enabled by means of the reg_seq_sequence register and can be used in global shutter modes. the configurations used for even odd frames are summarized in table 28. when the sequenced readout is not enabled, the first set of configurations (?even configurations?) is applicable. the second set (?odd configurations?) is ignored by the sequencer. table 28. odd/even configuration configuration even frames odd frames integration time reg_seq_exposure0 reg_seq_exposure1 fr length reg_seq_fr_length0 reg_seq_fr_length1 mult timer reg_seq_mult_timer0 reg_seq_mult_timer1 gain stage 1 reg_seq_mux_gains w0 reg_seq_mux_gainsw1 gain stage 2 reg_seq_afe_gain0 reg_seq_afe_gain1 digital gain reg_seq_db_gain0 reg_seq_db_gain1 roi active configuration reg_seq_roi_active0 reg_seq_roi_active1
python 480 www. onsemi.com 38 data output format the python 480 image sensor can be configured in lvds output mode, which includes one lvds output channel together with an lvds clock output and an lvds synchronization ou tput channel. the python 480 is also configurable in a cmos output configuration, which includes a 10 ? bit parallel cmos output together with a cmos clock output and ?frame valid? and ?line valid? cmos output signals. lvds interface mode lvds output channels the image data output occurs through one lvds data channel where a synchronization lvds channel and an lvds output clock signal synchronizes the data. the one data channel is used to output the image data only. the sync channel transmits information about the data sent over the data channel (includes codes indicating black pixels, normal pixels, and crc codes). frame format the frame format is explained by example of the readout of two (overlapping) windows as shown in figure 30(a). the readout of a frame occurs on a line ? by ? line basis. the read pointer goes from left to right, bottom to top. figure 30 indicates that, after the fot is completed, the sensor reads out a number of black lines for black calibration purposes. after these black lines, the windows are processed. first a number of lines which only includes information of ?roi 0? are sent out, starting at position y0_start. when the line at position y1_start is reached, a number of lines containing data of ?roi 0? and ?roi 1? are sent out, until the line position of y0_end is reached. from there on, only data of ?roi 1? appears on the data output channels until line position y1_end is reached during read out of the image data over the data channels, the sync channel sends out frame synchronization codes which give information related to the image data that is sent over the four data output channels. each line of a window starts with a line start (ls) indication and ends with a line end (le) indication. the line start of the first line is replaced by a frame start (fs); the line end of the last line is replaced with a frame end indication (fe). each such frame synchronization code is followed by a window id (range 0 to 7). for overlapping windows, the line synchronization codes of the overlapping windows with lower ids are not sent out (as shown in the illustration: no le/fe is transmitted for the overlapping part of window 0). note: in figure 30, only frame start and frame end sync words are indicated in (b). crc codes are also omitted from the figure. for additional information on the synchronization codes, refer to application note and5001.
python 480 www. onsemi.com 39 figure 30. lvds mode: frame sync codes (a) (b) y0_start y1_start y0_end y1_end x0_start x1_start x0_end x1_end roi 0 reset n exposure time n reset n+1 exposure time n+1 roi 0 fot fot integration time handling readout handling fot roi 1 readout frame n-1 readout frame n roi 0 roi 1 fs0 fs1 fe1 fs0 fs1 fe1 figure 31 shows the detail of a black line readout during global or full ? frame readout. figure 31. lvds mode: time line for black line readout data channels sync channel data channels sync channel sequencer internal state line ys line ys+1 line ye black timeslot 0 training tr ls bl le training tr fot rot rot rot rot crc bl bl bl bl bl timeslot 1 timeslot 157 timeslot 158 timeslot 159 crc timeslot
python 480 www. onsemi.com 40 figure 32 shows shows the details of the readout of a number of lines for single window readout, at the beginning of the frame. figure 32. lvds mode: time line for single window readout (at the start of a frame) data channels sync channel data channels sync channel sequencer internal state line ys line ys+1 line ye black timeslot xstart training tr fs id img le training tr fot rot rot rot id rot crc img img img img img timeslot xstart + 1 timeslot xend - 2 timeslot xend - 1 timeslot xend crc timeslot figure 33 shows the detail of the readout of a number of lines for readout of two overlapping windows. figure 33. lvds mode: time line showing the readout of two overlapping windows data channels sync channel data channels sync channel sequencer internal state line ys+1 line ye black timeslot xstartm training tr ls idm img le training tr fot rot rot rot idn rot crc img ls idn img img timeslot xstartn timeslot xendn line ys img frame synchronization table 29 shows the structure of the frame synchronization code. note that the table shows the default data word (configurable). if more than one window is active at the same time, the sync channel transmits the frame synchronization codes of the window with highest index only. table 29. frame synchronization code details sync word bit position register address default value description 9:7 n/a 0x4 frame sequence start (fss). only sent out when reg_seq_fss_enable is asserted. 9:7 n/a 0x7 frame sequence end (fse). only sent out when reg_seq_fse_enable is asserted. 9:7 n/a 0x5 frame start indication 9:7 n/a 0x6 frame end indication 9:7 n/a 0x1 line start indication 9:7 n/a 0x2 line end indication 6:0 117[6:0] 0x2a these bits indicate that the received sync word is a frame synchronization code. the value is programmable by a register setting
python 480 www. onsemi.com 41 ? window identification frame synchronization codes are always followed by a 3 ? bit window identification (bits 2:0). this is an integer number, ranging from 0 to 7, indicating the active window. if more than one window is active for the current cycle, the highest window id is transmitted. ? data classification codes for the remaining cycles, the sync channel indicates the type of data sent through the data links: black pixel data (bl), image data (img), or training pattern (tr). these codes are programmable by a register setting. the default values are listed in table 30. table 30. synchronization channel default identification code values sync word bit position register address default value description 9:0 118 [9:0] 0x015 black pixel data (bl). this data is not part of the image. the black pixel data is used internally to correct channel offsets. 9:0 119 [9:0] 0x035 valid pixel data (img). the data on the data output channels is valid pixel data (part of the image). 9:0 125 [9:0] 0x059 crc value. the data on the data output channels is the crc code of the finished image data line. 9:0 126 [9:0] 0x3a6 training pattern (tr). the sync channel sends out the training pattern which can be programmed by a register setting. training patterns on data channels during idle periods, the data channels transmit training patterns, indicated on the sync channel by a tr code. these training patterns are configurable independent of the training code on the sync channel as shown in table 31. table 31. training code on sync channel in sync word bit position register address default value description [9:0] 116 [9:0] 0x3a6 data channel training pattern. the data output channels send out the training pattern, which can be programmed by a register setting. the default value of the training pattern is 0x3a6, which is identical to the training pattern indication code on the sync channel. cyclic redundancy code at the end of each line, a crc code is calculated to allow error detection at the receiving end. each data channel transmits a crc code to protect the data words sent during the previous cycles. idle and training patterns are not included in the calculation. the sync channel is not protected. a special character (crc indication) is transmitted whenever the data channels send their respective crc code. the polynomial is x 10 +x 9 +x 6 +x 3 +x 2 + x + 1. the crc encoder is seeded at the start of a new line and updated for every (valid) data word received. the crc seed is configurable using the crc_seed register. when ?0?, the crc is seeded by all ? ?0?; when ?1? it is seeded with all ? ?1?. note: the crc is calculated for every line. this implies that the crc code can protect lines from multiple windows. data order: lvds interface version to read out the image data through the output channel, the pixel array is organized in kernels. the kernel size is two pixels in x ? direction by one pixel in y ? direction. figure 34 indicates how the kernels are organized. the first kernel (kernel [0, 0]) is located in the bottom left corner. the pixel data is transmitted in order. the figures in the following paragraphs represent the data order for a non ? mirrored readout (i.e. left ? to ? right readout). figure 34. kernel organization in pixel array (top view) roi kernel (403,607) kernel (x_start,y_start) 0 1 pixel array kernel (0,0)
python 480 www. onsemi.com 42 ? subsampling disabled figure 35 shows how a kernel is read out. the pixels are transferred in order, or in ascending order for normal readout and descending order for mirrored readout. figure 35. p1 ? sn/se/fn: data output order when subsampling is disabled kernel n ? 2 kernel n+1 kernel n kernel n ? 1 0 1 pixel # (even kernel) channel 3 2 pixel # (odd kernel) 10 ? bit 10 ? bit msb lsb msb lsb note: the bit order is always msb first ? subsampling on monochrome sensor during subsampling on a monochrome sensor, every other pixel is read out and the lines are read in a read-1-skip-1 manner. to read out the image data with subsampling enabled on a monochrome sensor, two neighboring kernels are combined to a single kernel of 4 pixels in the x ? direction and one pixel in the y ? direction. only the pixels at the even pixel positions inside that kernel are read out. figure 36. data output order in subsampling mode on a monochrome sensor kernel n ? 2 kernel n+1 kernel n kernel n ? 1 0 2 pixel # channel
python 480 www. onsemi.com 43 ? subsampling on color sensor during subsampling on a color sensor, lines are read in a read-2-skip ? 2 manner. to read out the image data with subsampling enabled on a color sensor, two neighboring kernels are combined to a single kernel of 4 pixels in the x ? direction and one pixel in the y ? direction. only the pixels 0 and 1 are read out. figure 37. data output order for the lvds output channel in subsampling mode on a color sensor kernel n ? 4 kernel n+2 kernel n kernel n ? 2 0 1 pixel # channel cmos interface mode cmos output signals the image data output occurs through a single 10 ? bit parallel cmos data output. a cmos clock output, ?frame valid? and ?line valid? signal synchronizes the output data. no windowing information is sent out by the sensor. frame format frame timing is indicated by means of two signals: frame_valid and line_valid. ? the frame_valid indication is asserted at the start of a new frame and remains asserted until the last line of the frame is completely transmitted. ? the line_valid indication serves the following needs: ? while the line_valid indication is asserted, the data channels contain valid pixel data. ? the line valid communicates frame timing as it is asserted at the start of each line and it is de ? asserted at the end of the line. low periods indicate the idle time between lines (rot). ? the data channels transmit the calculated crc code after each line. this can be detected as the data words right after the falling edge of the line valid. figure 38. cmos mode: frame timing indication data channels sequencer internal state line ys line ys+1 line ye black fot rot rot rot rot fot rot black frame_valid line_valid
python 480 www. onsemi.com 44 the frame format is explained with an example of the readout of two (overlapping) windows as shown in figure 39 (a). the readout of a frame occurs on a line ? by ? line basis. the read pointer goes from left to right, bottom to top. figure 39 (a) and (b) indicate that, after the fot is finished, a number of lines which include information of ?roi 0? are sent out, starting at position y0_start. when the line at position y1_start is reached, a number of lines containing data of ?roi 0? and ?roi 1? are sent out, until the line position of y0_end is reached. then, only data of ?roi 1? appears on the data output until line position y1_end is reached. the line_valid strobe is not shown in figure 39. figure 39. cmos mode: frame format to read out image data (a) (b) 1280 pixels y0_start y1_start y0_end y1_end x0_start x1_start x0_end x1_end roi0 roi 1 reset n exposure time n reset n+1 exposure time n +1 roi0 fot fot integration time handling readout handling fot readout frame n -1 readout frame n roi 0 roi1 frame valid fot fot roi1 pixels 1024 black lines black pixel data is also sent through the data channels. to distinguish these pixels from the regular image data, it is possible to ?mute? the frame and/or line valid indications for the black lines. refer to t able 32 for black line, frame_valid and line_valid settings. table 32. black line frame_valid and line_valid settings bl_frame _valid_enable bl_line _valid_enable description 0x1 0x1 the black lines are handled similar to normal image lines. the frame valid indication is asserted before the first black line and the line valid indication is asserted for every valid (black) pixel. 0x1 0x0 the frame valid indication is asserted before the first black line, but the line valid indication is not asserted for the black lines. the line valid indication indicates the valid image pixels only. this mode is useful when one does not use the black pixels and when the frame valid indication needs to be asserted some time before the first image lines (for example, to precondition isp pipelines). 0x0 0x1 in this mode, the black pixel data is clearly unambiguously indicated by the line valid indication, while the decoding of the real image data is simplified. 0x0 0x0 black lines are not indicated and frame and line valid strobes remain de ? asserted. note however that the data channels contains the black pixel data and crc codes (training patterns are interrupted).
python 480 www. onsemi.com 45 data order: cmos interface mode to read out the image data through the parallel cmos output, the pixel array is divided in kernels. the kernel size is two pixels in x ? direction by one pixel in y ? direction. figure 34 on page 41 indicates how the kernels are organized. the pixel data is transmitted in order. the figures in the following paragraphs represent the data order for a non ? mirrored readout (i.e. left ? to ? right readout). ? no subsampling figure 40 shows the pixel sequence of a kernel which is read out over the single cmos output channel. the pixels are transmitted in order or ascending for a normal readout and descending for a mirrored readout. figure 40. cmos mode: data output order without subsampling kernel n ? 2 kernel n+1 kernel n kernel n ? 1 0 1 pixel # ? subsampling on monochrome sensor to read out the image data with subsampling enabled on a monochrome sensor, two neighboring kernels are combined to a single kernel of 4 pixels in the x ? direction and one pixel in the y ? direction. only the pixels at the even pixel positions inside that kernel are read out. figure 41 shows the data order. figure 41. cmos mode: data output order with subsampling on a monochrome sensor kernel n ? 2 kernel n+1 kernel n kernel n ? 1 0 2 pixel # channel ? subsampling on color sensor to read out the image data with subsampling enabled on a color sensor, two neighboring kernels are combined to a single kernel of 4 pixels in the x ? direction and one pixel in the y ? direction. figure 42 shows the data order. figure 42. cmos mode: data output order with subsampling on a color sensor kernel n ? 4 kernel n+2 kernel n kernel n ? 2 0 1 pixel # channel
python 480 www. onsemi.com 46 register map table 33. register map address offset address bit field register name default (hex) default description type chip id [block offset: 0] 0 0 chip_id 0x5004 20484 chip id status [15:0] id 0x5004 20484 chip id 1 1 reserved 0x0000 0 reserved status [3:0] reserved 0x0 0 reserved [9:8] resolution 0x0 0 chip resolution [11:10] reserved 0x0 0 reserved 2 2 chip_configuration 0x0000 0 chip general configuration rw [0] color 0x0 0 color/monochrome configuration ?0?: monochrome ?1?: color [1] reserved 0x0 0 reserved [15:2] reserved 0x0 0 reserved reset generator [block offset: 8] 0 8 soft_reset_pll 0x0099 153 pll soft reset configuration rw [3:0] pll_soft_reset 0x9 9 pll reset 0x9: soft reset state others: operational [7:4] pll_lock_soft_reset 0x9 9 pll lock detect reset 0x9: soft reset state others: operational 1 9 soft_reset_cgen 0x0009 9 clock generator soft reset rw [3:0] cgen_soft_reset 0x9 9 clock generator reset 0x9: soft reset state others: operational 2 10 soft_reset_analog 0x0999 2457 analog block soft reset rw [3:0] mux_soft_reset 0x9 9 column mux reset 0x9: soft reset state others: operational [7:4] afe_soft_reset 0x9 9 afe reset 0x9: soft reset state others: operational [11:8] ser_soft_reset 0x9 9 serializer reset 0x9: soft reset state others: operational pll [block offset: 16] 0 16 power_down 0x0004 4 pll configuration rw [0] pwd_n 0x0 0 pll power down ?0?: power down, ?1?: operational [1] enable 0x0 0 pll enable ?0?: disabled, ?1?: enabled [2] bypass 0x1 1 pll bypass ?0?: pll active, ?1?: pll bypassed 1 17 reserved 0x2113 8467 reserved rw [7:0] reserved 0x13 19 reserved [12:8] reserved 0x1 1 reserved [14:13] reserved 0x1 1 reserved
python 480 www. onsemi.com 47 table 33. register map (continued) address offset type description default default (hex) register name bit field address i/o [block offset: 20] 0 20 config1 0x0000 0 io configuration rw [0] clock_in_pwd_n 0x0 0 power down clock input [9:8] reserved 0x0 0 reserved [10] reserved 0x0 0 reserved pll lock detector [block offset: 24] 0 24 pll_lock 0x0000 0 pll lock indication status [0] lock 0x0 0 pll lock indication 2 26 reserved 0x2280 8832 reserved rw [7:0] reserved 0x80 128 reserved [10:8] reserved 0x2 2 reserved [14:12] reserved 0x2 2 reserved 3 27 reserved 0x3d2d 15661 reserved rw [7:0] reserved 0x2d 45 reserved [15:8] reserved 0x3d 61 reserved clock generator [block offset: 32] 0 32 config0 0x2014 8212 clock generator configuration rw [0] enable_analog 0x0 0 enable analogue clocks ?0?: disabled, ?1?: enabled [1] enable_log 0x0 0 enable logic clock ?0?: disabled, ?1?: enabled [2] select_pll 0x1 1 input clock selection ?0?: select lvds clock input, ?1?: select pll clock input [3] adc_mode 0x0 0 set operation mode of cgen block ?0?: divide by 5 mode (10-bit mode) [4] enable_clkgate 0x1 1 clock gate on master distribution ?0?: clock active ?1?: clock inactive (gated) [11:8] reserved 0x0 0 reserved [14:12] reserved 0x2 2 reserved general logic [block offset: 34] 0 34 config0 0x0000 0 clock generator configuration rw [0] enable 0x0 0 logic general enable configuration ?0?: disable ?1?: enable 0 38 reserved 0x0000 0 reserved rw [15:0] reserved 0x0000 0 reserved image core [block offset: 40] 0 40 image_core_config0 0x0000 0 image core configuration rw [0] imc_pwd_n 0x0 0 image core power down ?0?: powered down, ?1?: powered up [1] mux_pwd_n 0x0 0 column multiplexer power down ?0?: powered down, ?1?: powered up [2] colbias_enable 0x0 0 bias enable ?0?: disabled ?1?: enabled 1 41 image_core_config1 0x085a 2138 image core configuration rw
python 480 www. onsemi.com 48 table 33. register map (continued) address offset type description default default (hex) register name bit field address [3:0] reserved 0xa 10 reserved [7:4] reserved 0x5 5 reserved [10:8] reserved 0x0 0 reserved [12:11] reserved 0x1 1 reserved [13] reserved 0x0 0 reserved [14] reserved 0x0 0 reserved [15] reserved 0x0 0 reserved 2 42 reserved 0x0003 3 reserved rw [0] reserved 0x1 1 reserved [1] reserved 0x1 1 reserved [6:4] reserved 0x0 0 reserved [10:8] reserved 0x0 0 reserved [15:12] reserved 0x0 0 reserved 3 43 reserved 0x0508 1288 reserved rw [0] reserved 0x0 0 reserved [1] reserved 0x0 0 reserved [2] reserved 0x0 0 reserved [3] reserved 0x1 1 reserved [6:4] reserved 0x0 0 reserved [7] reserved 0x0 0 reserved [11:8] reserved 0x5 5 reserved [15:12] reserved 0x0 0 reserved afe [block offset: 48] 0 48 power_down 0x0000 0 afe configuration rw [0] pwd_n 0x0 0 power down for afe?s ?0?: powered down, ?1?: powered up bias [block offset: 64] 0 64 power_down 0x0000 0 bias power down configuration rw [0] pwd_n 0x0 0 power down bandgap ?0?: powered down, ?1?: powered up 1 65 configuration 0xf8cb 63691 bias configuration rw [0] extres 0x1 1 external resistor selection ?0?: internal resistor, ?1?: external resistor [3:1] reserved 0x5 5 reserved [7:4] reserved 0xc 12 reserved [11:8] reserved 0x8 8 reserved [15:12] reserved 0xf 15 reserved 2 66 reserved 0x53c8 21448 reserved rw [3:0] reserved 0x8 8 reserved [7:4] reserved 0xc 12 reserved [14:8] reserved 0x53 83 reserved 3 67 reserved 0x8788 34696 reserved rw [3:0] reserved 0x8 8 reserved [7:4] reserved 0x8 8 reserved
python 480 www. onsemi.com 49 table 33. register map (continued) address offset type description default default (hex) register name bit field address [11:8] reserved 0x7 7 reserved [15:12] reserved 0x8 8 reserved 4 68 lvds_bias 0x0085 133 lvds bias configuration rw [3:0] lvds_ibias 0x5 5 lvds ibias [7:4] lvds_iref 0x8 8 lvds iref 5 69 reserved 0x0088 2184 reserved rw [3:0] reserved 0x8 8 reserved [7:4] reserved 0x8 8 reserved [11:8] reserved 0x8 8 reserved 6 70 reserved 0x4111 16657 reserved rw [3:0] reserved 0x1 1 reserved [7:4] reserved 0x1 1 reserved [11:8] reserved 0x1 1 reserved [15:12] reserved 0x4 4 reserved 7 71 reserved 0x9788 38792 reserved rw [15:0] reserved 0x9788 38792 reserved charge pump [block offset: 72] 0 72 configuration 0x3330 13104 charge pump configuration rw [0] reserved 0x0 0 reserved [1] reserved 0x0 0 reserved [2] reserved 0x0 0 reserved [6:4] reserved 0x3 3 reserved [10:8] reserved 0x3 3 reserved [14:12] reserved 0x3 3 reserved 0 80 reserved 0x0000 0 reserved rw [1:0] reserved 0x0 0 reserved [3:2] reserved 0x0 0 reserved [5:4] reserved 0x0 0 reserved [7:6] reserved 0x0 0 reserved [9:8] reserved 0x0 0 reserved 1 81 reserved 0x8881 34945 reserved rw [15:0] reserved 0x8881 34945 reserved temperature sensor [block offset: 96] 0 96 enable 0x0000 0 temperature sensor configuration rw [0] reserved 0x0 0 reserved [1] reserved 0x0 0 reserved [2] reserved 0x0 0 reserved [3] reserved 0x0 0 reserved [4] reserved 0x0 0 reserved [5] reserved 0x0 0 reserved [13:8] offset 0x0 0 temperature offset (signed) 1 97 temp 0x0000 0 temperature sensor status status [7:0] temp 0x00 0 temperature readout 0 104 reserved 0x0000 0 reserved rw
python 480 www. onsemi.com 50 table 33. register map (continued) address offset type description default default (hex) register name bit field address [15:0] reserved 0x0 0 reserved 1 105 reserved 0x0000 0 reserved rw [1:0] reserved 0x0 0 reserved [5:2] reserved 0x0 0 reserved [7] reserved 0x0 0 reserved [9:8] reserved 0x0 0 reserved [13:10] reserved 0x0 0 reserved [15] reserved 0x0 0 reserved 2 106 reserved 0x0000 0 reserved rw [15:0] reserved 0x0000 0 reserved 3 107 reserved 0x0000 0 reserved rw [10:0] reserved 0x0000 0 reserved serializers/lvds/io [block offset: 112] 0 112 power_down 0x0000 0 lvds power down configuration rw [0] clock_out_pwd_n 0x0 0 power down for clock output. ?0 ?: powered down, ?1?: powered up [1] sync_pwd_n 0x0 0 power down for sync channel ?0?: powered down, ?1?: powered up [2] data_pwd_n 0x0 0 power down for data channels (4 channels) ?0?: powered down, ?1?: powered up sync words [block offset: 116] 4 116 trainingpattern 0x03a6 934 data formating - training pattern rw [9:0] trainingpattern 0x3a6 934 training pattern sent on data channels during idle mode. this data is used to perform word alignment on the lvds data channels. 5 117 sync_code0 0x002a 42 lvds power down configuration rw [6:0] frame_sync_0 0x02a 42 frame sync code lsbs - even kernels 6 118 sync_code1 0x0015 21 data formating - bl indication rw [9:0] bl_0 0x015 21 black pixel identification sync code - even kernels 7 119 sync_code2 0x0035 53 data formating - img indication rw [9:0] img_0 0x035 53 valid pixel identification sync code - even kernels 8 120 sync_code3 0x0025 37 data formating - img indication rw [9:0] ref_0 0x025 37 reference pixel identification sync code - even kernels 9 121 sync_code4 0x002a 42 lvds power down configuration rw [6:0] frame_sync_1 0x02a 42 frame sync code lsbs - odd kernels 10 122 sync_code5 0x0015 21 data formating - bl indication rw [9:0] bl_1 0x015 21 black pixel identification sync code - odd kernels 11 123 sync_code6 0x0035 53 data formating - img indication rw [9:0] img_1 0x035 53 valid pixel identification sync code - odd kernels 12 124 sync_code7 0x0025 37 data formating - img indication rw [9:0] ref_1 0x025 37 reference pixel identification sync code - odd kernels
python 480 www. onsemi.com 51 table 33. register map (continued) address offset type description default default (hex) register name bit field address 13 125 sync_code8 0x0059 89 data formating - crc indication rw [9:0] crc 0x059 89 crc value identification sync code 14 126 sync_code9 0x03a6 934 data formating - tr indication rw [9:0] tr 0x3a6 934 training value identification sync code 15 127 reserved 0x02aa 682 reserved rw [9:0] reserved 0x2aa 682 reserved data block [block offset: 128] 0 128 blackcal 0x4714 18196 black calibration configuration rw [7:0] black_offset 0x014 20 desired black level at output [10:8] black_samples 0x7 7 black pixels taken into account for black calibration. total samples = 2**black_samples [14:11] reserved 0x8 8 reserved [15] crc_seed 0x0 0 crc seed ?0?: all-0 ?1?: all-1 1 129 general_configuration 0x0001 1 black calibration and data formating configuration rw [0] auto_blackcal_enable 0x1 1 automatic blackcalibration is enabled when 1, bypassed when 0 [9:1] blackcal_offset 0x00 0 black calibration offset used when au- to_black_cal_en = ?0?. [10] blackcal_offset_dec 0x0 0 blackcal_offset is added when 0, subtracted when 1 [11] reserved 0x0 0 reserved [12] reserved 0x0 0 reserved [13] reserved 0x0 0 reserved [14] ref_mode 0x0 0 data contained on reference lines: ?0?: reference pixels ?1?: black average for the corresponding data channel [15] ref_bcal_enable 0x0 0 enable black calibration on reference lines ?0?: disabled ?1?: enabled 2 130 general_configuration1 0x000f 15 data formating - training pattern rw [0] bl_frame_valid_en- able 0x1 1 assert frame_valid for black lines when ?1?, gate frame_valid for black lines when ?0?. parallel output mode only. [1] bl_line_valid_enable 0x1 1 assert line_valid for black lines when ?1?, gate line_valid for black lines when ?0?. parallel output mode only. [2] ref_frame_valid_en- able 0x1 1 assert frame_valid for ref lines when ?1?, gate frame_valid for black lines when ?0?. parallel output mode only. [3] ref_line_valid_enable 0x1 1 assert line_valid for ref lines when ?1?, gate line_valid for black lines when ?0?. parallel output mode only. [4] frame_valid_mode 0x0 0 behaviour of frame_valid strobe between overhead lines when [0] and/or [1] is deasserted: ?0?: retain frame_valid deasserted between lines ?1?: assert frame_valid between lines [5] invert_bitstream 0x0 0 negative image ?0?: normal ?1?: negative
python 480 www. onsemi.com 52 table 33. register map (continued) address offset type description default default (hex) register name bit field address [8] data_negedge 0x0 0 clock ? data relation ?0?: data is clocked out on the rising edge of the related clock ?1?: data is clocked out on the falling edge of the related clock [9] reserved 0x0 0 reserved 8 136 blackcal_error0 0x0000 0 black calibration status status [1:0] blackcal_error[1:0] 0x0000 0 black calibration error. this flag is set when not enough black samples are availlable. black calibration shall not be valid. 12 140 reserved 0x0000 0 reserved rw [15:0] reserved 0x0000 0 reserved 16 144 test_configuration 0x0010 16 data formating test configuration rw [0] testpattern_en 0x0 0 insert synthesized testpattern when ?1? [1] inc_testpattern 0x0 0 incrementing testpattern when ?1?, constant testpattern when ?0? [2] prbs_en 0x0 0 insert prbs when ?1? [3] frame_testpattern 0x0 0 frame test patterns when ?1?, unframed testpatterns when ?0? [13:4] testpattern 0x1 1 testpattern used when testpatterns_en = ?1? aec [block offset: 160] 0 160 configuration 0x0010 16 aec configuration rw [0] enable 0x0 0 aec enable [1] restart_filter 0x0 0 restart aec filter [2] freeze 0x0 0 freeze aec filter and enforcer gains [3] pixel_valid 0x0 0 use every pixel from channel when 0, every 4th pixel when 1 [4] amp_pri 0x1 1 column amplifier gets higher priority than afe pga in gain distribution if 1. vice versa if 0 1 161 intensity 0x60b8 24760 aec configuration rw [9:0] desired_intensity 0xb8 184 target average intensity [15:10] reserved 0x018 24 reserved 2 162 red_scale_factor 0x0080 128 red scale factor rw [9:0] red_scale_factor 0x80 128 red scale factor 3.7 unsigned 3 163 green1_scale_factor 0x0080 128 green1 scale factor rw [9:0] green1_scale_factor 0x80 128 green1 scale factor 3.7 unsigned 4 164 green2_scale_factor 0x0080 128 green2 scale factor rw [9:0] green2_scale_factor 0x80 128 green2 scale factor 3.7 unsigned 5 165 blue_scale_factor 0x0080 128 blue scale factor rw [9:0] blue_scale_factor 0x80 128 blue scale factor 3.7 unsigned 6 166 reserved 0x03ff 1023 reserved rw [15:0] reserved 0x03ff 1023 reserved 7 167 reserved 0x0800 2048 reserved rw [1:0] reserved 0x0 0 reserved [3:2] reserved 0x0 0 reserved [15:4] reserved 0x080 128 reserved
python 480 www. onsemi.com 53 table 33. register map (continued) address offset type description default default (hex) register name bit field address 8 168 min_exposure 0x0001 1 minimum exposure time rw [15:0] min_exposure 0x0001 1 minimum exposure time 9 169 min_gain 0x0800 2048 minimum gain rw [1:0] min_mux_gain 0x0 0 minimum column amplifier gain [3:2] min_afe_gain 0x0 0 minimum afe pga gain [15:4] min_digital_gain 0x080 128 minimum digital gain 5.7 unsigned 10 170 max_exposure 0x03ff 1023 maximum exposure time rw [15:0] max_exposure 0x03ff 1023 maximum exposure time 11 171 max_gain 0x1001 4097 maximum gain rw [1:0] max_mux_gain 0x1 1 maximum column amplifier gain [3:2] max_afe_gain 0x0 0 maximum afe pga gain [15:4] max_digital_gain 0x100 256 maximum digital gain 5.7 unsigned 12 172 reserved 0x0083 131 reserved rw [7:0] reserved 0x083 131 reserved [13:8] reserved 0x00 0 reserved [15:14] reserved 0x0 0 reserved 13 173 reserved 0x2824 10276 reserved rw [7:0] reserved 0x024 36 reserved [15:8] reserved 0x028 40 reserved 14 174 reserved 0x2a96 10902 reserved rw [3:0] reserved 0x6 6 reserved [7:4] reserved 0x9 9 reserved [11:8] reserved 0xa 10 reserved [15:12] reserved 0x2 2 reserved 15 175 reserved 0x0080 128 reserved rw [9:0] reserved 0x080 128 reserved 16 176 reserved 0x00f1 241 reserved rw [9:0] reserved 0xf1 241 reserved 17 177 reserved 0x0100 256 reserved rw [9:0] reserved 0x100 256 reserved 18 178 reserved 0x0080 128 reserved rw [9:0] reserved 0x080 128 reserved 19 179 reserved 0x00aa 170 reserved rw [9:0] reserved 0x0aa 170 reserved 20 180 reserved 0x0100 256 reserved rw [9:0] reserved 0x100 256 reserved 21 181 reserved 0x0155 341 reserved rw [9:0] reserved 0x155 341 reserved 24 184 total_pixels0 0x0000 0 aec status status [15:0] total_pixels[15:0] 0x0000 0 total number of pix els sampled for average, lsb 25 185 total_pixels1 0x0000 0 aec status status [7:0] total_pixels[23:16] 0x0 0 total number of pix els sampled for average, msb
python 480 www. onsemi.com 54 table 33. register map (continued) address offset type description default default (hex) register name bit field address 26 186 average_status 0x0000 0 ase status status [9:0] average 0x000 0 aec average status [12] avg_locked 0x0 0 aec average lock status 27 187 exposure_status 0x0000 0 ase status status [15:0] exposure 0x0000 0 aec exposure status 28 188 gain_status 0x0000 0 ase status status [1:0] mux_gain 0x0 0 aec mux gain status [3:2] afe_gain 0x0 0 aec afe gain status [15:4] digital_gain 0x000 0 aec digital gain status 5.7 unsigned 29 189 reserved 0x0000 0 reserved status [12:0] reserved 0x000 0 reserved [13] reserved 0x0 0 reserved sequencer [block offset: 192] 0 192 general_configuration 0x0002 2 sequencer general configuration rw [0] enable 0x0 0 enable sequencer ?0?: idle, ?1?: enabled [1] fast_startup 0x1 1 fast startup ?0?: first frame is full frame (blanked out) ?1?: reduced startup time [2] reserved 0x0 0 reserved [3] reserved 0x0 0 reserved [4] triggered_mode 0x0 0 triggered mode selection ?0?: normal mode, ?1?: triggered mode [5] slave_mode 0x0 0 master/slave selection ?0?: master, ?1?: slave [6] reserved 0x0 0 reserved [7] subsampling 0x0 0 subsampling mode selection ?0?: no subsampling, ?1?: subsampling [8] reserved 0x0 0 reserved [10] roi_aec_enable 0x0 0 enable windowing for aec statistics. ?0?: subsample all windows ?1?: subsample configured window [13:11] monitor_select 0x0 0 control of the monitor pins [14] reserved 0x0 0 reserved [15] sequence 0x0 0 enable a sequenced readout with different parameters for even and odd frames 2 194 integration_control 0x00e4 228 integration control rw [0] reserved 0x0 0 reserved [1] reserved 0x0 0 reserved [2] fr_mode 0x1 1 representation of fr_length. ?0?: reset length ?1?: frame length [3] reserved 0x0 0 reserved [4] int_priority 0x0 0 integration priority ?0?: frame readout has priority over integration ?1?: integration end has priority over frame readout
python 480 www. onsemi.com 55 table 33. register map (continued) address offset type description default default (hex) register name bit field address [5] halt_mode 0x1 1 the current frame will be completed when the sequencer is disabled and halt_mode = ?1?. when ?0?, the sensor stops immediately when disabled, without finishing the current frame. [6] fss_enable 0x1 1 generation of frame sequence start sync code (fss) ?0?: no generation of fss ?1?: generation of fss [7] fse_enable 0x1 1 generation of frame sequence end sync code (fse) ?0?: no generation of fse ?1?: generation of fse [8] reverse_y 0x0 0 reverse readout ?0?: bottom to top readout ?1?: top to bottom readout [9] reverse_x 0x0 0 reverse readout (x ? direction) ?0?: left to right ?1?: right to left [11:10] subsampling_mode 0x0 0 subsampling mode ?00?: subsampling in x and y (vita compatible) ?01?: subsampling in x, not y ?10?: subsampling in y, not x ?11?: subsampling in x an y [13:12] reserved 0x0 0 reserved [14] reserved 0x0 0 reserved [15] reserved 0x0 0 reserved 3 195 roi_active0_0 0x0001 1 active roi selection rw [3:0] roi_active0 0x01 1 active roi selection [0] roi0 active [1] roi1 active ... [3] roi3 active 5 197 black_lines 0x0104 260 black line configuration rw [7:0] black_lines 0x04 4 number of black lines. minimum is 1. range 1-255 [12:8] gate_first_line 0x1 1 blank out first lines 0: no blank 1-31: blank 1-31 lines 6 198 init_reset_length 0x0040 64 initial reset length rw [15:0] init_reset_length 0x0040 64 initial reset length in fast startup mode (reg_sec_fast_startup = 0x1) 7 199 mult_timer0 0x0001 1 exposure/frame rate configuration rw [15:0] mult_timer0 0x0001 1 mult timer (global shutter only) defines granularity (unit = 1/pll clock) of exposure and reset_length 8 200 fr_length0 0x0000 0 exposure/frame rate configuration rw [15:0] fr_length0 0x0000 0 frame/reset length (global shutter only) reset length when fr_mode = ?0?, frame length when fr_mode = ?1? granularity defined by mult_timer 9 201 exposure0 0x0000 0 exposure/frame rate configuration rw [15:0] exposure0 0x0000 0 exposure time granularity defined by mult_timer 10 202 reserved 0x0000 0 reserved rw [15:0] reserved 0x0000 0 reserved 11 203 reserved 0x0000 0 reserved rw [15:0] reserved 0x0000 0 reserved
python 480 www. onsemi.com 56 table 33. register map (continued) address offset type description default default (hex) register name bit field address 12 204 gain_configuration0 0x01e1 481 gain configuration rw [4:0] mux_gainsw0 0x01 1 column gain setting [12:5] afe_gain0 0xf 15 afe programmable gain setting [13] gain_lat_comp 0x0 0 postpone gain update by 1 frame when ?1? to compensate for exposure time updates latency. gain is applied at start of next frame if ?0? 13 205 digital_gain _configuration0 0x0080 128 gain configuration rw [11:0] db_gain0 0x080 128 digital gain 14 206 sync_configuration 0x037a 890 synchronization configuration rw [1] sync_black_lines 0x1 1 update of black_lines will not be sync?ed at start of frame when ?0? [3] sync_exposure 0x1 1 update of exposure will not be sync?ed at start of frame when ?0? [4] sync_gain 0x1 1 update of gain settings (gain_sw, afe_gain) will not be sync?ed at start of frame when ?0? [5] sync_roi 0x1 1 update of roi updates (active_roi) will not be sync?ed at start of frame when ?0? [6] sync_ref_lines 0x1 1 update of ref_lines will not be sync?ed at start of frame when ?0? [8] blank_roi_switch 0x1 1 blank first frame after roi switching [9] blank _subsampling_ss 0x1 1 blank first frame after subsampling mode ?0?: no blanking ?1?: blanking [10] exposure_sync_mode 0x0 0 when ?0?, exposure configurations are sync?ed at the start of fot. when ?1?, exposure configurations sync is disabled (continuously syncing). this mode is only relevant for trig- gered global - master mode, where the ex- posure configurations are sync?ed at the start of exposure rather than the start of fot. for all other modes it should be set to ?0?. note: sync is still postponed if sync_exposure=?0?. 15 207 ref_lines 0x0000 0 reference line configuration rw [7:0] ref_lines 0x00 0 number of reference lines 0-255 16 208 reserved 0xc900 51456 reserved rw [7:0] reserved 0x00 0 reserved [15:8] reserved 0xc9 201 reserved 17 209 reserved 0x0004 4 reserved rw [0] reserved 0x0 0 reserved [2] reserved 0x1 1 reserved [15:8] xsm_delay 0x00 0 delay between rot end and x ? readout 19 211 reserved 0x0049 73 reserved rw [0] reserved 0x1 1 reserved [1] reserved 0x0 0 reserved [2] reserved 0x0 0 reserved [3] reserved 0x1 1 reserved [6:4] reserved 0x4 4 reserved [15:8] reserved 0x0 0 reserved 20 212 reserved 0x0000 0 reserved rw [9:0] reserved 0x0000 0 reserved
python 480 www. onsemi.com 57 table 33. register map (continued) address offset type description default default (hex) register name bit field address [15] reserved 0x00 0 reserved 21 213 reserved 0x025f 607 reserved rw [9:0] reserved 0x025f 607 reserved 22 214 reserved 0x0100 256 reserved rw [7:0] reserved 0x00 0 reserved 23 215 reserved 0x191f 6431 reserved rw [0] reserved 0x1 1 reserved [1] reserved 0x1 1 reserved [2] reserved 0x1 1 reserved [3] reserved 0x1 1 reserved [4] reserved 0x1 1 reserved [5] reserved 0x0 0 reserved [6] reserved 0x0 0 reserved [8] reserved 0x1 1 reserved [9] reserved 0x0 0 reserved [10] reserved 0x0 0 reserved [11] reserved 0x1 1 reserved [12] reserved 0x1 1 reserved [13] reserved 0x0 0 reserved [14] reserved 0x0 0 reserved 24 216 reserved 0x0000 0 reserved rw [6:0] reserved 0x00 0 reserved 25 217 reserved 0x4848 18504 reserved rw [6:0] reserved 0x48 72 reserved [14:8] reserved 0x48 72 reserved 26 218 reserved 0x4848 18504 reserved rw [6:0] reserved 0x48 72 reserved [14:8] reserved 0x48 72 reserved 27 219 reserved 0x005c 92 reserved rw [6:0] reserved 0x05c 92 reserved [14:8] reserved 0x00 0 reserved 28 220 reserved 0x3624 13860 reserved rw [6:0] reserved 0x24 36 reserved [14:8] reserved 0x36 54 reserved 29 221 reserved 0x0036 54 reserved rw [6:0] reserved 0x36 54 reserved [14:8] reserved 0x0 0 reserved 30 reserved 0x0 reserved rw [14:8] reserved 0x0 0 reserved 32 224 reserved 0x3e07 15879 reserved rw [3:0] reserved 0x7 7 reserved [7:4] reserved 0x00 0 reserved [8] reserved 0x0 0 reserved
python 480 www. onsemi.com 58 table 33. register map (continued) address offset type description default default (hex) register name bit field address [9] reserved 0x1 1 reserved [10] reserved 0x1 1 reserved [11] reserved 0x1 1 reserved [12] reserved 0x1 1 reserved [13] reserved 0x1 1 reserved 33 225 reserved 0x5ef1 24305 reserved rw [4:0] reserved 0x11 17 reserved [9:5] reserved 0x17 23 reserved [14:10] reserved 0x17 23 reserved [15] reserved 0x0 0 reserved 34 226 reserved 0x6000 24576 reserved rw [4:0] reserved 0x00 0 reserved [9:5] reserved 0x00 0 reserved [14:10] reserved 0x18 24 reserved [15] reserved 0x0 0 reserved 35 227 reserved 0x0000 0 reserved rw [0] reserved 0x0 0 reserved [1] reserved 0x0 0 reserved [2] reserved 0x0 0 reserved [3] reserved 0x0 0 reserved [4] reserved 0x0 0 reserved 36 228 roi_active0_1 0x0001 1 active roi selection rw [3:0] roi_active1 0x01 1 active roi selection [0] roi0 active [1] roi1 active [2] roi2 active [3] roi3 active 38 230 reserved 0x0001 1 reserved rw [15:0] reserved 0x0001 1 reserved 39 231 reserved 0x0000 0 reserved rw [15:0] reserved 0x0000 0 reserved 40 232 reserved 0x0000 0 reserved rw [15:0] reserved 0x0000 0 reserved 41 233 reserved 0x0000 0 reserved rw [15:0] reserved 0x0000 0 reserved 42 234 reserved 0x0000 0 reserved rw [15:0] reserved 0x0000 0 reserved 43 235 reserved 0x01e3 483 reserved rw [4:0] reserved 0x03 3 reserved [12:5] reserved 0xf 15 reserved 44 236 reserved 0x0080 128 reserved rw [11:0] reserved 0x080 128 reserved 47 239 reserved 0x0000 0 reserved rw [1:0] reserved 0x0 0 reserved 58 250 reserved 0x1081 4225 reserved rw [4:0] reserved 0x01 1 reserved
python 480 www. onsemi.com 59 table 33. register map (continued) address offset type description default default (hex) register name bit field address [9:5] reserved 0x04 4 reserved [14:10] reserved 0x04 4 reserved 59 251 reserved 0x030f 783 reserved rw [7:0] reserved 0xf 15 reserved [15:8] reserved 0x3 3 reserved 60 252 reserved 0x0601 1537 reserved rw [7:0] reserved 0x1 1 reserved [15:8] reserved 0x6 6 reserved 61 253 roi_aec_configura- tion0 0xc900 51456 aec roi configuration rw [7:0] x_start 0x00 0 aec roi x start configuration (used for aec statistics when roi_aec_enable=?1?) (bits 8..1) [15:8] x_end 0x0c9 201 aec roi x end configuration (used for aec statistics when roi_aec_enable=?1?) (bits 8..1) 62 254 roi_aec_configura- tion1 0x9700 0 aec roi configuration rw [7:0] y_start 0x00 0 aec roi y start configuration (used for aec statistics when roi_aec_enable=?1?) (bits 9..2) [15:8] x_end 0x97 151 aec roi end configuration (used for aec statistics when roi_aec_enable=?1?) (bits 9..2) 63 255 roi_aec_configura- tion2 0x00c4 0 aec roi configuration rw [0] x_start(0) 0x0 0 aec roi y end configuration (used for aec statistics when roi_aec_enable=?1?) (bit 0) [2] x_end(0) 0x1 1 aec roi end configuration (used for aec statistics when roi_aec_enable=?1?) (bit 0) [5:4] y_start(1:0) 0x0 0 aec roi end configuration (used for aec statistics when roi_aec_enable=?1?) (bits 1..0) [7:6] y_end(1:0) 0x3 3 aec roi end configuration (used for aec statistics when roi_aec_enable=?1?) (bits 1..0) sequencer roi [block offset: 256] 0 256 roi0_configuration0 0xc900 51456 roi configuration rw [7:0] x_start 0x00 0 roi 0 ? x start configuration (bits 8..1) [15:8] x_end 0xc9 201 roi 0 ? x end configuration (bits 8..1) 1 257 roi0_configuration1 0x9700 38656 roi configuration rw [7:0] y_start 0x00 0 roi 0 ? y start configuration (bits 9..2) [15:8] y_end 0x97 151 roi 0 ? y end configuration (bits 9..2) 2 258 roi1_configuration0 0xc900 51456 roi configuration rw [7:0] x_start 0x00 0 roi 1 ? x start configuration (bits 8..1) [15:8] x_end 0xc9 201 roi 1 ? x end configuration (bits 8..1) 3 259 roi1_configuration1 0x9700 38656 roi configuration rw [7:0] x_start 0x00 0 roi 1 ? y start configuration (bits 9..2) [15:8] x_end 0x97 151 roi 1 ? y end configuration (bits 9..2) 4 260 roi2_configuration0 0xc900 51456 roi configuration rw [7:0] x_start 0x00 0 roi 2 ? x start configuration (bits 8..1) [15:8] x_end 0xc9 201 roi 2 ? x end configuration (bits 8..1) 5 261 roi2_configuration1 0x9700 38656 roi configuration rw [7:0] y_start 0x00 0 roi 2 ? y start configuration (bits 9..2) [15:8] y_end 0x97 151 roi 2 ? y end configuration (bits 9..2)
python 480 www. onsemi.com 60 table 33. register map (continued) address offset type description default default (hex) register name bit field address 6 262 roi3_configuration0 0xc900 51456 roi configuration rw [7:0] x_start 0x00 0 roi 3 ? x start configuration (bits 8..1) [15:8] x_end 0xc9 201 roi 3 ? x end configuration (bits 8..1) 7 263 roi3_configuration1 0x9700 38656 roi configuration rw [7:0] y_start 0x00 0 roi 3 ? y start configuration (bits 9..2) [15:8] y_end 0x97 151 roi 3 ? y end configuration (bits 9..2) 8 264 roi_configuration_lsb0 0xc4c4 50372 roi configuration rw [0] x_start0(0) 0x0 0 roi 0 ? x start configuration (bit 0) [2] x_end0(0) 0x1 1 roi 0 ? x end configuration (bit 0) [5:4] y_start0(1:0) 0x0 0 roi 0 ? y start configuration (bits 1..0) [7:6] y_end0(1 :0) 0x3 3 roi 0 ? y end configuration (bits 1..0) [8] x_start1(0) 0x0 0 roi 1 ? x start configuration (bit 0) [10] x_end1(0) 0x1 1 roi 1 ? x end configuration (bit 0) [13:12] y_start1(1:0) 0x0 0 roi 1 ? y start configuration (bits 1..0) [15:14] y_end1(1 :0) 0x3 3 roi 1 ? y end configuration (bits 1..0) 9 265 roi_configuration_lsb1 0xc4c4 50372 roi configuration rw [0] x_start0(0) 0x0 0 roi 2 ? x start configuration (bit 0) [2] x_end0(0) 0x1 1 roi 2 ? x end configuration (bit 0) [5:4] y_start0(1:0) 0x0 0 roi 2 ? y start configuration (bits 1..0) [7:6] y_end0(1 :0) 0x3 3 roi 2 ? y end configuration (bits 1..0) [8] x_start1(0) 0x0 0 roi 3 ? x start configuration (bit 0) [10] x_end1(0) 0x1 1 roi 3 ? x end configuration (bit 0) [13:12] y_start1(1:0) 0x0 0 roi 3 ? y start configuration (bits 1..0) [15:14] y_end1(1 :0) 0x3 3 roi 3 ? y end configuration (bits 1..0) sequencer roi [block offset: 384] 0 384 reserved reserved rw [15:0] reserved reserved ? ? ? rw ? ? ? 95 479 reserved reserved rw [15:0] reserved reserved
python 480 www. onsemi.com 61 package information pin list the lvds i/os comply to the tia/eia ? 644 ? a standard and the cmos i/os have a 1.8 v signal level. table 34. pin list pin map pin name i/o type direction description a1 vdd_pix supply pixel array supply b1 vdd_33 supply 3.3 v supply c1 monitor0 cmos output monitor output #0 d1 monitor1 cmos output monitor output #1 e1 ibias_master analog i/o master bias reference. connect with 47kohm to vss_33 f1 cp_respd analog output for test only ? do not connect g1 cp_calib analog output for test only ? do not connect h1 mbsinout_1 analog i/o for test only ? do not connect a2 vdd_18 supply 1.8 v supply b2 vss_colpc supply pixel array ground c2 scan_en cmos input for test only ? connect to vss_18 d2 vss_18 supply 1.8 v ground e2 vss_33 supply 3.3 v ground f2 monitor2 cmos output monitor output #2 g2 vss_33 supply 3.3 v ground h2 mbsinout_1 analog i/o for test only ? do not connect a3 tr2 cmos input connect to vss_18 b3 tr1 cmos input connect to vss_18 c3 trigger0 cmos input trigger input #0 g3 vdd_33 supply 3.3 v supply h3 mbsinout_2 analog i/o for test only ? do not connect a4 ss_n cmos input spi slave select (active low) b4 sck cmos input spi clock c4 reset_n cmos input sensor reset (active low) g4 miso cmos output spi master in ? slave out h4 cp_sel_sample analog output for test only ? do not connect a5 frame_valid cmos output frame valid output b5 line_valid cmos output line valid output c5 dout9 cmos output data output #9 g5 mosi cmos input spi master out ? slave in h5 test_enable cmos input for test only ? connect to vss_18 a6 vss_colpc supply pixel array ground b6 vdd_pix supply pixel array supply c6 dout8 cmos output data output #8 g6 vss_18 supply 1.8 v ground h6 vref_botplate supply input 1.8 v supply for sample and hold a7 dout7 cmos output data output #7 b7 dout6 cmos output data output #6
python 480 www. onsemi.com 62 table 34. pin list (continued) pin map description direction i/o type pin name c7 dout5 cmos output data output #5 g7 vss_18 supply 1.8 v ground h7 vss_33 supply 3.3 v ground a8 clk_out cmos output clock output b8 dout4 cmos output data output #4 c8 dout3 cmos output data output #3 g8 vss_18 supply 1.8 v ground h8 vss_33 supply 3.3 v ground a9 dout2 cmos output data output #2 b9 dout0 cmos output data output #0 c9 dout1 cmos output data output #1 g9 clk_pll cmos input reference clock input for pll h9 vdd_18 supply 1.8 v supply a10 vdd_18 supply 1.8 v supply b10 vdd_pix supply pixel array supply c10 clock_outn lvds output lvds clock output (negative) d10 doutn lvds output lvds data output (negative) e10 syncn lvds output lvds sync channel output (negative) f10 lvds_clock_inn lvds input lvds clock input (negative) g10 lock_detect cmos output lock detect output h10 vdd_33 supply 3.3 v supply a11 vss_colpc supply pixel array ground b11 clock_outp lvds output lvds clock output (positive) c11 doutp lvds output lvds data output (positive) d11 syncp lvds output lvds sync channel output (positive) e11 lvds_clock_inp lvds input lvds clock input (positive) f11 vdd_33 supply 3.3 v supply g11 vss_18 supply 1.8 v ground h11 vdd_33 supply 3.3 v supply
python 480 www. onsemi.com 63 mechanical specifications mechanical specifications symbol min typ max units package body dimensions (top view, bumps down, with pin a1 top left corner) package body dimension x a 6105 6130 6155 m package body dimension y b 4905 4930 4955 m package height c 631.2 691.2 751.2 m ball height c1 100 130 160 m package body thickness c2 516.2 561.2 606.2 m thickness fo glass surface to wafer c3 425 445 465 m ball diameter d 220 250 280 m total pin count n 67 m pin count x ? axis n1 11 m pin count y ? axis n2 8 m pins pitch x ? axis j1 500 m pins pitch y ? axis j2 500 m edge to pin center distance along x s1 535 565 595 m edge to pin center distance along y s2 685 715 745 m optical center referenced from package center (x ? dir) 0 m optical center referenced from package center (y ? dir) ? 175 m glass lid glass thickness 400 m mechanical shock jesd22 ? b104c; condition g 2000 g vibration jesd22 ? b103b; condition 1 2000 hz note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm.
python 480 www. onsemi.com 64 figure 43. mechanical diagram pixel (0,0)
python 480 www. onsemi.com 65 package drawing figure 44. package drawing for the odcsp67 package
python 480 www. onsemi.com 66 packing and tray specification the PYTHON480 packing specification with on semiconductor packing labels is packed as follows: figure 45. tray drawing
python 480 www. onsemi.com 67 figure 46. pin 1 location
python 480 www. onsemi.com 68 glass lid the python 480 image sensors use a glass lid without any coatings. figure 44 shows the transmission characteristics of the glass lid. as shown in figure 42 , no infrared attenuating color filter glass is used. use of an ir cut filter is recommended in the optical path when color devices are used. (source: http://www.pgo ? online.com ). figure 47. transmission characteristics of the glass lid protective foil the sensor is delivered with protective foil that is intended to be removed after assembly. the dimensions of the foil are as illustrated in figure 48 with tab aligned left center with pin a1 to the bottom left. figure 48. dimensions of the protective foil (units in mm)
python 480 www. onsemi.com 69 specifications and useful references the following references are available to customers under nda at the on semiconductor image sensor portal: https://www.onsemi.com/powersolutions/myon/ercispfol der.do ? product acceptance criteria ? product qualification report ? python developer?s guide and9362/d useful references for information on esd and cover glass care and cleanliness, please download the image sensor handling and best practices application note (an52561/d) from www.onsemi.com . for quality and reliability information, please download the quality & reliability handbook (hbd851/d) from www.onsemi.com . for information on standard terms and conditions of sale, please download terms and conditions from www.onsemi.com . for information on acronyms and a glossary of terms used, please download image sensor terminology (tnd6116/d) from www.onsemi.com . return material authorization (rma) refer to the on semiconductor rma policy procedure at http://www.onsemi.com/site/pdf/cat_returns_failurean alysis.pdf on semiconductor and are trademarks of semiconductor components industries, llc dba on semiconductor or its subsidiaries i n the united states and/or other countries. on semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property . a listing of on semiconductor?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent ? marking.pdf . on semiconductor reserves the right to make changes without further notice to any products herein. on semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does o n semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. buyer is responsible for its products and applications using on semiconductor products, including compliance with all laws, reg ulations and safety requirements or standards, regardless of any support or applications information provided by on semiconductor. ?typical? parameters which may be provided in on semiconductor data sheets and/or specifications can and do vary in dif ferent applications and actual performance may vary over time. all operating parameters, including ?typic als? must be validated for each customer application by customer?s technical experts. on semiconductor does not convey any license under its patent rights nor the right s of others. on semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any fda class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. should buyer purchase or use on semicondu ctor products for any such unintended or unauthorized application, buyer shall indemnify and hold on semiconductor and its officers, employees, subsidiaries, affiliates, and distrib utors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that on semiconductor was negligent regarding the design or manufacture of the part. on semiconductor is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 noip1sn0480a/d literature fulfillment : literature distribution center for on semiconductor 19521 e. 32nd pkwy, aurora, colorado 80011 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative ?

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