HS7541A 12-bit cmos multiplying dac ? copyright 2000 sipex corporation 1 description the HS7541A is a lowCcost, high stability monolithic 12Cbit cmos 4Cquadrant multiplying dac. it is constructed using a proprietary lowCtcr thinCfilm process that requires no laserCtrimming to achieve 12Cbit performance. the HS7541A is a superior pinCcompatible replacement for the industry standard 7541 and ad7541a. it is available in both commercial and industrial temperature ranges. it operates with +5v to +15v power supply voltages. it is available in 18C pin plastic dip and soic, and 20Cpin plcc packages. n 0.5 lsb dnl and inl n high stability, segmented architecture (3 msbs) n proprietary, low tcr thinCfilm resistor technology n low sensitivity to output amplifier offset n 2kv esd protection on all digital inputs n operates with +5v to +15v power supplies n ad7541/7541a replacement n low cost d 11 (msb) [4] d 10 [5] d 9 [6] d 8 [7] d 7 [8] d 6 [9] d 5 [10] d 4 [11] d 3 [12] d 2 [13] d 1 [14] d 0 (lsb) [15] r fb [18] v dd [16] gnd [3] v ref [17] 20k w 10k w 20k w 10k w 20k w 10k w 20k w 10k w 20k w 10k w 20k w 10k w 20k w 10k w 20k w 10k w 20k w 10k w 20k w 10k w 20k w 10k w 20k w 20k w i o2 [2] i o1 [1] 10k w ? HS7541A 12Cbit cmos multiplying dac
HS7541A 12-bit cmos multiplying dac ? copyright 2000 sipex corporation 2 specifications (t a =25 c; v dd =+15v, v ref = +10v; i o1 = i o2 = gnd = 0v; unipolar unless otherwise noted.) parameter min. typ. max. unit conditions static performance resolution 12 bits integral non-linearity note 6 -aj, -aa 1.0 lsb note 5; 11-bit relative accuracy -ak, -ab 0.5 lsb note 5; 12-bit relative accuracy differential non-linearity note 7 -aj, -aa 1.0 lsb note 5; monotonic to 12-bits -ak, -ab 0.5 lsb note 5; monotonic to 12-bits gain error note 17 -aj, -aa 6 lsb 8 lsb note 5 -ak, -ab 3 lsb 5 lsb note 5 output leakage current 5 na at i o1 (pin 1); note 18 10 na note 5 ac performance characteristics output amplifier hos-050; note 8 propagation delay 100 ns note 9 current settling time 0.6 m s full scale transition; note 10 output capacitance ci o1 (pin 16) 200 pf note 5; data inputs v ih ci o2 (pin 15) 70 pf note 5; data inputs v ih ci o1 (pin 16) 70 pf note 5; data inputs v il ci o2 (pin 15) 200 pf note 5; data inputs v il glitch energy 1,000 nvs note 11 multiplying feedthrough error 1.0 mv p-p measured at output i o1 ; note 12 0.1 mv p-p measured at output i o1 ; note 13 stability gain error tc 1.0 ppm/ c inl tc 0.1 ppm/ c dnl tc 0.1 ppm/ c power supply rejection ratio 0.02 %/% v dd = 14 to 16v reference input input resistance 7 10 15 k w pin 19 to gnd input resistance tc 150 ppm/ c voltage range 25 volts note 5 and 14 caution: esd (electrostatic discharge) sensitive device. permanent damage may occur on unconnected devices subject to high energy electrostatic fields. unused devices must be stored in conductive foam or shunts. personnel should be properly grounded prior to handling this device. the protective foam should be discharged to the destination socket before devices are removed. absolute maximum ratings (t a = 25 c unless otherwise noted.) these are stress ratings only and functional operation of the device at these or any other above those indicated in the operation sections of the specifications below is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. v dd to gnd .................................................................. C0.3v, +17v digital input voltage to gnd ................................. C0.3v, v dd +0.3v v ref or v rfb to gnd ................................................................ 25v output voltage (pin 1, pin 2) ................................ C0.3v, v dd +0.3v power dissipation (any package to +75 c) ........................ 450mw derates above 75 c by ...................................................... 6mw/ c dice junction temperature ................................................. +150 c storage temperature ............................................ C65 c to +150 c lead temperature (soldering, 60 seconds) ........................ +300 c
HS7541A 12-bit cmos multiplying dac ? copyright 2000 sipex corporation 3 specifications (continued) (t a =25 c; v dd =+15v, v ref = +10v; i o1 = i o2 = gnd = 0v; unipolar unless otherwise noted.) parameter min. typ. max. unit conditions digital inputs logic levels v ih 2.4 v dd volts 2.4 volts note 5 v il -0.3 0.8 volts 0.8 volts note 5 input current 1.0 m av in = 0v or v dd 10 m a note 5 and 15 input capacitance v in = 0; note 5 and 14 bits 112 8 pf note 5 coding unipolar binary bipolar offset binary power requirements voltage range +5 +15 volts note 16 +16 volts note 5 supply current 2.0 2.5 ma all digital inputs v il or v ih 2.5 ma note 5; all digital inputs v il or v ih 0.2 0.5 ma all digital inputs 0v or 5v to v dd 1.0 ma note 5; all digital inputs 0v or 5v to v dd environmental and mechanical operating temperature -ak, -aj 0 +70 c -ab, -aa -40 +85 c storage temperature -65 +150 c package -ak, -aj 18-pin plastic dip, 20-pin plcc, 18Cpin soic notes and cautions: 1. do not apply voltages higher than vdd or less than gnd potential on any terminal other than v ref or v rfb . 2. the digital inputs are diode-clamp protected against esd damage. however, permanent damage may occur on unprotected units from high-energy electrostatic fields. keep units in conductive foam at all times until ready to use. 3. use proper anti-static handling procedures. 4. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation at or above these specifications is not implied. exposure to the above maximum rated conditions for extended periods may affect device reliability. 5. from t min to t max . 6. integral non-linearity is measured as the arithmetic mean value of the magnitudes of the greatest positive deviation and the greatest negative deviation from the theoretical value of any given input combination. 7. differential non-linearity is the deviation of an output step from the theoretical value of 1 lsb for any two adjacent digital input codes. 8. ac performance characteristics are included for design guidance only and are subject to sample testing only. 9. r l = 100 w , c ext = 13pf; all data inputs 0v to v dd or v dd to 0v; from 50% digital input change to 90% of final analog output. 10. settling to 0.01% fsr (strobed); all data inputs 0v to v dd or v dd to 0v. 11. v ref = 0v, dac register alternatively loaded with all 0s and all 1s. 12. v ref = 20v p-p ; f = 10khz sinewave. 13. v ref = 20v p-p ; f = 1khz sinewave. 14. guaranteed by design, but not production tested. 15. logic inputs are mos gates. i in typically is less than 1na @ 25 c. 16. accuracy is guaranteed at v dd = +15v only. 17. measured using internal feedback resistor with dac loaded with all 1s. 18. all digital inputs = 0v.
HS7541A 12-bit cmos multiplying dac ? copyright 2000 sipex corporation 4 pin assignments 18Cpin plastic dip and soic pin 1 i o1 inverted current output. pin 2 i o2 current output. pin 3 gnd analog ground. pin 4 d 11 (msb) data bit 11 (most significant bit). pin 5 d 10 data bit 10. pin 6 d 9 data bit 9. pin 7 d 8 data bit 8. pin 8 d 7 data bit 7. pin 9 d 6 data bit 6. pin 10 d 5 data bit 5. pin 11 d 4 data bit 4. pin 12 d 3 data bit 3. pin 13 d 2 data bit 2. pin 14 d 1 data bit 1. pin 15 d 0 (lsb) data bit 0 (least significant bit). pin 16 v dd +5v to +15v power supply. pin 17 v ref voltage reference input. pin 18 r fb feedback resistor. 20Cpin plastic lcc pin 1 i o1 inverted current output. pin 2 i o2 current output. pin 3 gnd analog ground. pin 4 n.c. no connection. pin 5 d 11 (msb) data bit 11 (most significant bit). pin 6 d 10 data bit 10. pin 7 d 9 data bit 9. pin 8 d 8 data bit 8. pin 9 d 7 data bit 7. pin 10 d 6 data bit 6. pin 11 d 5 data bit 5. pin 12 d 4 data bit 4. pin 13 d 3 data bit 3. pin 14 d 2 data bit 2. pin 15 d 1 data bit 1. pin 16 d 0 (lsb) data bit 0 (least signifi- cant bit). pin 17 n.c. no connection. pin 18 v dd +5v to +15v power supply. pin 19 v ref voltage reference input. pin 20 r fb feedback resistor. features the HS7541A is a lowCcost, high stability mono- lithic 12Cbit cmos 4Cquadrant multiplying dac. it is constructed using a proprietary lowC tcr thinCfilm process that requires no laserC trimming to achieve 12Cbit performance. with its inherent high stability and a segmented (de- coded) dac architecture, the HS7541A retains its performance over time and temperature. to further improve reliability, all digital inputs are protected against 2kv esd. each dac is fully characterized by allCcodes testing to eliminate any hidden errors. the HS7541A consists of a highly stable thinC film rC2r ladder network and twelve nmos current switches (please refer to the block dia- gram on the first page of this data sheet). the switches are temperature compensated, and their on resistances are binarily scaled so that the voltage drop across each switch is identical, which contributes to the stability of the dac. the internal feedback resistor used in the output currentCtoCvoltage conversion by an external op amp is matched to the rC2r ladder. circuit description general the HS7541A is a 12-bit multiplying d/a con- verter consisting of a highly stable, sichrome thin-film r-2r resistor ladder network, and twelve pairs of nmos current-steering switches on a monolithic chip. a simplified circuit of the HS7541A is shown in figure 1 . the r-2r inverted ladder binarily divides the input currents that are switched between the i out1 and i out2 bus lines. this switch- ing allows a constant current to be maintained in each ladder leg independent of the input code.
HS7541A 12-bit cmos multiplying dac ? copyright 2000 sipex corporation 5 v ref 10k w 20k w d 11 (msb) d 1 d 2 d 0 (lsb) i out2 i out1 r fb 10k w 10k w 20k w 20k w 20k w 20k w s 1 s 2 s 11 s 0 switches shown for digital inputs "high" r = 10k w i leakage 30pf r feedback i out1 i leakage 85pf i out2 1/4096 i ref v ref r = 10k w the twelve output current-steering switches are in series with the r-2r ladder, and therefore, can introduce bit errors. it is essential then, that the switch on resistance be binarily scaled so that the voltage drop across each switch remains constant. if, for example, switch s 0 of figure 1 was designed with an on resistance of 10 ohms, switch s 1 for 20 ohms, etc., then with a 10v reference input, the current through s 0 is 0.5ma, s 1 is 0.25ma, etc.; a constant 5mv drop will then be maintained across each switch. to further insure accuracy across the full tem- perature range, permanently on mos switches are included in series with the feedback resistor and the r-2r ladders terminating resistor. these series switches are equivalently scaled to two times switch s 11 (msb) and to switch s 0 (lsb) respectively to maintain constant relative volt- age drops with varying temperature. during any testing of the resistor ladder or r fb (such as incoming inspection), v dd must be present to turn on these series switches. figure 3. equivalent circuit C all inputs high figure 1. simplified dac circuit 2001v esd protection in the design of the HS7541A s data inputs, 2001v esd resistance has been incorporated through careful layout and the inclusion of input protection circuitry. equivalent circuit analysis figures 2 and 3 show the equivalent circuits for all digital inputs low and high respectively. the reference current is switched to i out2 when all inputs are low, and to i out1 when all inputs are high. the i leakage current source is the combination of surface and junction leakages to the substrate; the 1/4096 current source represents the constant 1-bit current drain through the ladder terminating resis- tor. the output capacitance is dependent upon the digital input code, and therefore varies between the low and high values. output impedance the output resistance, as in the case of the output capacitance, varies with the digital input code. the resistance, looking back into the i out1 ter- r = 10k w i leakage 30pf r feedback i out1 i leakage 85pf i out2 1/4096 i ref v ref r = 10k w figure 2. equivalent circuit C all inputs low v ref (?0v) d 11 (msb) d 0 (lsb) input data 2k w gain trim 1k w gain trim 15pf +15v ?5v v out + r fb i o1 i o2 gnd v ref v dd +15v 4 15 3 2 1 18 16 17 HS7541A figure 4. unipolar operation
HS7541A 12-bit cmos multiplying dac ? copyright 2000 sipex corporation 6 minal, may be anywhere between 10k w (the feedback resistor alone when all digital inputs are low) and 7.5k w (the feedback resistor in parallel with approximately 30k w of the r-2r ladder network resistance when any single bit is high). static accuracy and dynamic perfor- mance will be affected by these variations. unipolar operation figure 4 shows the connections to implement digital unipolar operation of the HS7541A . the reference voltage applied to v ref (pin17) may be positive or negative. the 2k w potentiometer tied to v ref , and the 1k w resistor in the feed- back loop are both optional; they are needed only when gain error must be trimmed to less than 0.3% fsr. they should track each other to better than 0.1%. it is not necessary that they track the resistors internal to the HS7541A . figure 5. bipolar operation v ref (?0v) d 11 (msb) d 0 (lsb) input data 2k w gain trim 1k w v out + r fb i o1 i o2 gnd v ref v dd +15v 4 15 3 2 1 18 16 17 HS7541A + 10k w 10k w 10k w 390 w 500 w as shown in the figure, the output current of the HS7541A is typically connected to an external op amp, with its non-inverting input tied to ground. the amplifier should be selected for low input bias current and low drift over tem- perature. to maintain the specified linearity, the amplifiers input offset voltage should be mulled to less than 200 m v (0.1 lsb). bipolar operation figure 5 shows the connections for bipolar operation of the HS7541A . the digital input coding is offset binary as shown in table 2. as is the case for unipolar operation, the gain trim resistors can be omitted if minimum gain error is not required. the op amp selection criteria and offset nulling are the same as for unipolar operation. digital input i 0ut 1111 1111 1111 -0.99975 x v ref 1000 0000 0000 -0.50000 x v ref 0111 1111 1111 -0.49975 x v ref 0000 0000 0000 0v table 1. unipolar input coding digital input i 0ut 1111 1111 1111 -0.99951 x v ref 1000 0000 0001 -0.00049 x v ref 1000 0000 0000 0v 0100 0000 0000 +0.50000 x v ref 0000 0000 0000 +1.00000 x v ref table 2. bipolar input coding
HS7541A 12-bit cmos multiplying dac ? copyright 2000 sipex corporation 7 ordering information model .............................................................................................. relative accuracy .......................................................................... package 0 c to +70 c operating temperature: HS7541Akn ........................................................................................... 0.5 lsb ............................................................... 18-pin, 0.3" plastic dip HS7541Ajn ............................................................................................ 1.0 lsb ............................................................... 18-pin, 0.3" plastic dip HS7541Akp ............................................................................................ 0.5 lsb ................................................................................ 20-pin plcc HS7541Ajp ............................................................................................ 1.0 lsb ................................................................................ 20-pin plcc HS7541Aks ............................................................................................ 0.5 lsb ........................................................................ 18-pin, 0.3" soic HS7541Ajs ............................................................................................ 1.0 lsb ........................................................................ 18-pin, 0.3" soic C40 c to +85 c operating temperature: HS7541Abn ........................................................................................... 0.5 lsb ............................................................... 18-pin, 0.3" plastic dip HS7541Aan ........................................................................................... 1.0 lsb ............................................................... 18-pin, 0.3" plastic dip HS7541Abp ............................................................................................ 0.5 lsb ................................................................................ 20-pin plcc HS7541Aap ............................................................................................ 1.0 lsb ................................................................................ 20-pin plcc HS7541Abs ............................................................................................ 0.5 lsb ........................................................................ 18-pin, 0.3" soic HS7541Aas ............................................................................................ 1.0 lsb ........................................................................ 18-pin, 0.3" soic
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