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general description the max1215n evaluation kit (ev kit) is a fully assembledand tested printed-circuit board (pcb) that contains all the components necessary to evaluate the performance of the max1215n analog-to-digital converter (adc). the ev kit features a singled-ended-to-differential conversion circuit to drive the max1215n inputs. the digital outputs produced by the adc can be captured with a user- provided high-speed logic analyzer or data-acquisition system. additionally, the ev kit includes circuitry that gen- erates a differential clock signal from a user-provided single-ended ac signal. features ? up to 250msps sampling rate ? low-voltage and low-power operation ? fully differential signal input configuration ? on-board differential output drivers ? fully assembled and tested evaluates: max1215n max1215n evaluation kit ___________________________________________________ _____________ maxim integrated products 1 19-0955; rev 0; 8/07 component list for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. ordering information designation qty description c1?9, c13, c15, c16, c18, c19, c20, c35?39, c49, c52 22 0.1? ?0%, 10v x5r ceramiccapacitors (0402) murata grm155r61a104k tdk c1005x5r1a104k c10, c27, c28, c40 4 220? ?0%, 6.3v tantalumcapacitors (c case) avx tpsc227m006r0250 c11, c30 2 22? ?0%, 6.3v x5r ceramiccapacitors (0805) tdk c2012x5r0j226k c12 1 1pf 0.25pf, 50v c0g ceramic capacitor (0402)murata grm1555c1h1r0c tdk c1005c0g1h010c c14, c33 2 2.2? ?0%, 6.3v x5rceramic capacitors (0603) taiyo yuden jmk107bj225ka tdk c1608x5r0j225k c21?24 4 0.22? ?0%, 6.3v x5rceramic capacitors (0402) taiyo yuden jmk105bj224kv tdk c1005x5r0j224k c25, c26, c51, c53, c54, c55 6 0.1? ?0%, 50v x7r ceramic capacitors (0603) murata grm188r71h104k tdk c1608x7r1h104k designation qty description c29, c41 2 10? ?0%, 6.3v x5r ceramiccapacitors (0805) murata grm21br60j106k tdk c2012x5r0j106m c31, c43 0 not installed, ceramiccapacitors (0805) c32, c42 2 1.0? ?0%, 10v x5r ceramiccapacitors (0603) murata grm188r61a105k tdk c1608x5r1a105k c34, c44 0 not installed, ceramiccapacitors (0603) c45?48 0 not installed, tantalumcapacitors (c case) c50, c56 2 0.01? ?0%, 50v x7rceramic capacitors (0603) murata grm188r71h103k tdk c1608x7r1h103k c58?71 0 not installed, ceramiccapacitors (0402) clk, in 2 sma pcb vertical-mountconnectors j1 1 2 x 4-pin male header,2.54mm j2?5 4 2 x 20-pin male headers,2.54mm part temp range ic package MAX1215NEVKIT# 0? to +70?* 68 qfn-ep** # denotes an rohs-compliant ev kit. * this limited temperature range applies to the ev kit pcb only. the max1215n ic temperature range is -40? to +85?. ** ep = exposed paddle. downloaded from: http:///
evaluates: max1215n max1215n evaluation kit 2 __________________________________________________ _____________________________________ quick start recommended equipment before beginning, the following equipment is needed: dc power supplies: analog (vcc) 1.8v, 1a digital (ovcc) 1.8v, 200ma clock (vclk) 3.3v, 200ma buffers (vpecl) 3.3v, 400ma one signal generator with low-phase noise and low jitter for clock input (e.g., hp/agilent 8644b); band-pass filtering is strongly recommended (e.g., allen avionics, k&l microwave) one signal generator for analog signal input (e.g., hp/agilent 8644b); bandpass filtering is strongly rec-ommended (e.g., allen avionics, k&l microwave) logic analyzer or data-acquisition system (e.g., hp/agilent 16500c with high-speed state cardhp/agilent 16517a) digital voltmeter component suppliers supplier phone website avx corp. 843-946-0238 www.avxcorp.com irc 361-992-7900 www.irctt.com tdk corp. 847-803-6100 www.component.tdk.com note : indicate that you are using the max1215n when con- tacting these component suppliers. component list (continued) designation qty description ju1, ju2, ju3, ju5 4 3-pin headers ju4 0 not installed, 2-pin header ju6 0 not installed, 3-pin header r1, r11, r13 0 not installed, resistors (0603) r2, r4?7, r10, r12, r14, r15, r38, r39, r41, r43?79 49 49.9 ?% resistors (0402) r3, r82 2 0 resistors (0603) r8, r9 2 24.9 ?0.1% resistors (0603) irc pfc-w0603rlf-02-24r9-b r16, r17 2 10 ?% resistors (0603) r18?24, r28?32, r34, r35 14 100 ?% resistors (0603) r25, r37 2 510 ?% resistors (0603) r26 1 10k ?% resistor (0603) r27 1 5k p otenti om eter , 19-tur n, 3/8i n vishay t93yb-5k-10-d06 ormouser 72-t93yb-5k r33 1 3.16k ?% resistor (0603) r36 1 1.82k ?% resistor (0603) r40 1 100k potentiometer, 12-turn, 1/4in bourns 3266w-1-104 or mouser 652-3266w-1-104 r42 1 13k ?% resistor (0603) designation qty description r80 0 not installed, resistor?hortedby pc trace (0603) r81 1 0 resistor (0402) t1 1 1:1 800mhz rf transformermini-circuits adt1-1wt+ t2 1 1:1 250mhz rf transformercoilcraft ttwb2010-1lb tp1 1 red test point u1 1 max1215negk+d (68-pinqfn-ep, 10mm x 10mm) u2 1 max9388eup+ differential 4:1multiplexer (20-pin tssop) u3?6 4 3.3v ecl quad differentialreceivers (20-pin so) on semiconductor mc100lvel17dwg digi-key mc100lvel17dwgos-ng y1 0 not installed, clock oscillator(9mm x 14mm) 5 shunts ? pcb: max1215n evaluationkit# downloaded from: http:///
procedure the max1215n ev kit is a fully assembled and testedsurface-mount board. follow the steps below for board operation. caution: do not turn on power supplies or enable signal generators until all connections are completed. 1) verify that shunts are installed in the following loca- tions: ju1 (2-3) u2 selects clk ju2 (1-2) divide-by-two disabled ju3 (2-3) two?-complement output selected j1 (3-4) internal reference enabled ju5 (2-3) clock signal (clk) duty cycle set to 50% 2) connect the filtered clock signal generator to the sma connector labeled clk. 3) connect the filtered analog input signal generator to the sma connector labeled in. 4) connect the logic analyzer with a high-speed probe to either headers j2/j3 (lvds-compatiblesignals) or j4/j5 (lvpecl-compatible signals). see table 4 for header connections. 5) connect a 1.8v, 1a power supply to vcc. connect the ground terminal of this supply to gnd closestto the vcc pad. 6) connect a 1.8v, 200ma power supply to ovcc. connect the ground terminal of this supply to gndclosest to the ovcc pad. 7) connect a 3.3v, 200ma power supply to vclk. connect the ground terminal of this supply to gndclosest to the vclk pad. 8) connect a 3.3v, 400ma power supply to vpecl. connect the ground terminal of this supply to gndclosest to the vpecl pad. 9) turn on all power supplies. 10) enable the signal generators. set the clock signal generator to output a 250mhz signal with anamplitude of 2.4v p-p . set the analog input signal generator to output the desired frequency with an amplitude 2v p-p . for coherent sampling, the signal generators should be synchronized. 11) enable the logic analyzer. 12) capture data using the logic analyzer. detailed description the max1215n ev kit is a fully assembled and testedpcb that contains all the components necessary to evaluate the performance of the max1215n, 12-bit lvds output adc. the max1215n can be evaluated with a maximum clock frequency (f clk ) of 250mhz. the max1215n converter accepts differential inputs.applications that only have a single-ended signal source available can use the on-board transformers (t1 and t2) to convert the singled-ended signal to a differential signal. differential receivers (u3?6) buffer and convert the lvds output signals of the max1215n to higher volt- age lvpecl signals that can be captured by a wide variety of logic analyzers. the lvds outputs are accessed at headers j2 and j3. the lvpecl outputs are accessed at headers j4 and j5. the ev kit is designed as a four-layer pcb to optimize the pcb layout. separate analog, digital, clock, and buffer power planes minimize noise coupling between analog and digital signals; 50 microstrip transmission lines are used for analog and clock inputs and 100 differential microstrip transmission lines are used for all digital lvdsoutputs. all lvds differential outputs are terminated with 100 termination resistors between true and complemen- tary digital outputs. the trace lengths of the 100 differential lvds lines are matched to within a fewthousandths of an inch to minimize layout-dependent delays. all lvpecl differential outputs are y- terminated with 49.9 resistors on each branch. power supplies the max1215n ev kit requires separate analog, digitaloutput, clock, and buffer power supplies for best per- formance. two 1.8v power supplies are used to power the analog and digital portions of the max1215n. the on-board clock circuitry is powered by a 3.3v power supply. a separate 3.3v power supply is used to power the output buffers (u3?6) on the ev kit. clock the max1215n requires a differential clock signal.however, only a single-ended clock signal source is required. the ev kit? on-board circuitry converts a singled-ended clock signal to the required differential sig- nal. the frequency of the sinusoidal input clock signal determines the sampling frequency (f clk ) of the adc. a differential multiplexer (u2) processes the input signal togenerate the required clock signal. the input signal should not exceed an amplitude of 2.6v p-p . the fre- quency of the clock signal should not exceed 250mhz. evaluates: max1215n max1215n evaluation kit ___________________________________________________ ____________________________________ 3 downloaded from: http:///
evaluates: max1215n the output clock duty cycle at u2 can be set to a fixed50% duty cycle or can be adjusted whenever a single- ended signal is applied to the clk sma connector. configure jumper ju5 to set the signal? duty cycle to 50% or to adjust the duty cycle with potentiometer r27. see table 1 for configuring jumper ju5. the max1215n ev kit also provides circuitry so the user can install a crystal oscillator (y1, valpey fisher vf561e series recommended) to generate an on-board differen- tial clock source. the differential line receiver and multi- plexer ic (u2) can be configured to select between the sma clk signal and the crystal oscillator y1 output sig- nal by using jumper ju1. see table 2 for configuring jumper ju1. note: the crystal oscillator? duty cycle can- not be adjusted with jumper ju5. clock divider the max1215n features an internal divide-by-two clockdivider. use jumper ju2 to enable/disable this feature. see table 3 for shunt positions. input signal the max1215n accepts differential analog inputsignals. however, the ev kit only requires a 50 terminated single-ended analog input signal with anamplitude of less than 2v p-p provided by the user. the on-board transformers (t1 and t2) convert the single-ended analog input into a differential analog signal, which is applied to the adc? differential input pins. optional input transformer the max1215n ev kit uses two transformers toenhance the thd and the sfdr performance at high input frequencies (> 100mhz). these two transformers help reduce the increase of even-order harmonics at high frequencies. to use only one transformer, follow the directions below: 1) remove transformer t1. 2) install 0 resistors (0603) on r11 and r13. reference voltage there are two methods to set the full-scale range (fsr)of the max1215n. the max1215n ev kit can be config- ured to use the adc? internal reference, or a stable, low-noise, external reference can be applied to the refio pad. jumper j1 controls which reference source is used. see table 4 for shunt settings. output signal the max1215n features a single 12-bit, parallel, lvds-compatible, digital output bus. the digital outputs also feature a clock bit (dclkp/n) for data synchronization, and a data overrange bit (orp/n). see table 6 for header connections. max1215n evaluation kit 4 __________________________________________________ _____________________________________ shunt position description 1-2 internal reference disabled. apply an externalreference voltage to the refio pad 3-4* internal reference enabled 5-6 increases fsr through potentiometer r40 7-8 decreases fsr through potentiometer r40 table 4. reference shunt settings (j1) shunt position max1215n clkdiv pin description 1-2* connected to vcc clock signal divided by 1 2-3 connected to gnd clock signal divided by 2 table 3. clock-divider shunt settings (ju2) shunt position u2 sel0 pin clock source selection 1-2 connected to vclk selects crystal oscillatory1 2-3* connected to gnd selects sma clk input table 2. selecting clock source (ju1) * default position. shunt position u2 d0 pin function 1-2 connected to potentiometer r27 clock duty cycle isadjustable with r27 2-3* connected to vbb2 clock duty cycle is setto 50% table 1. clock duty cycle (ju5) * default position. * default position. * default position. downloaded from: http:///
output format the digital output coding can be chosen to be either intwo?-complement or straight offset binary format by configuring jumper ju3. see table 5 for shunt settings. output bit locations the digital outputs of the adc are connected to two40-pin headers (j2 and j3). pcb trace lengths are matched to minimize output skew and improve perfor- mance of the device. in addition, four differential receivers (u3?6) buffer and level translate the adc? digital outputs to lvpecl-compatible signals. the differential receivers increase the differential voltage swing and are able to drive large capacitive loads, which may be present at the logic analyzer connection. the outputs of the buffers are connected to two 40-pin headers (j4 and j5). see table 6 for headers j4 and j5 bit locations. evaluates: max1215n max1215n evaluation kit ___________________________________________________ ____________________________________ 5 shunt position max1215n t /b pin description 1-2 connected to vcc digital output instraight offset binary 2-3* connected to gnd digital output in two?complement bit unbuffered (lvds) buffered (lvpecl) bit description p j2-10 j4-10 p d11 n j2-9 j4-9 n ld11 msb p j2-16 j4-16 p d10 n j2-15 j4-15 n ld10 p j2-22 j4-22 p d9 n j2-21 j4-21 n ld9 p j2-28 j4-28 p d8 n j2-27 j4-27 n ld8 p j2-34 j4-34 p d7 n j2-33 j4-33 n ld7 p j2-40 j4-40 p d6 n j2-39 j4-39 n ld6 p j3-8 j5-8 p d5 n j3-7 j5-7 n ld5 p j3-14 j5-14 p d4 n j3-13 j5-13 n ld4 p j3-20 j5-20 p d3 n j3-19 j5-19 n ld3 p j3-26 j5-26 p d2 n j3-25 j5-25 n ld2 p j3-32 j5-32 p d1 n j3-31 j5-31 n ld1 data bits p j3-38 j5-38 p d0 n j3-37 j5-37 n ld0 lsb p j2-4 j4-4 p or n j2-3 j4-3 n lor overrange bit p j3-2 j5-2 p dclk n j3-1 j5-1 n ldc0 clock output signal table 6. output bit locations table 5. output-format shunt settings (ju3) * default position. downloaded from: http:///
evaluates: max1215n max1215n evaluation kit 6 __________________________________________________ _____________________________________ figure 1a. max1215n ev kit schematic (sheet 1 of 3) refi0 j2-4 j2-2 j2 j2-5 j2-6 j2-3j2-1 orp orn j2-10 j2-8 j2-7 j2-12 j2-9j2-11 d11p d11n j2-16 j2-14 j2-13 j2-18 j2-15j2-17 d10p d10n j2-22 j2-20 j2-19 j2-24 j2-21j2-23 d9p d9n j2-28 j2-26 j2-25 j2-30 j2-27j2-29 d8p d8n j2-34 j2-32 j2-31 j2-36 j2-33j2-35 d7p d7n j2-40 j2-38 j2-37 j2-39 d6p d6n j3-2 j3-3 j3 j3-4 j3-6 j3-1j3-5 dcop dcon j3-8 j3-9 j3-10 j3-12 j3-7j3-11 d5p d5n j3-14 j3-15 j3-16 j3-18 j3-13j3-17 d4p d4n j3-20 j3-21 j3-22 j3-24 j3-19j3-23 d3p d3n j3-26 j3-27 j3-28 j3-30 j3-25j3-29 d2p d2n j3-32 j3-33 j3-34 j3-36 j3-31j3-35 d1p d1n j3-38 j3-39 j3-40 j3-37 d0p d0n ovcc c210.22 f c30.1 f c40.1 f c50.1 f vclk vcc c10.1 f c27220 f 6.3v c20.1 f c220.22 f c230.22 f c60.1 f c70.1 f c240.22 f c80.1 f 1 av cc av cc av cc av cc av cc av cc av cc av cc av cc av cc av cc 6111213142025626365 vcc ovcc ov cc ov cc ov cc ov cc ov cc 27 28 41 44 60 16 agndagnd agnd agnd agnd agnd agnd agnd agnd agnd agnd 25710151819212464 agndagnd ognd ognd ognd 66 67 26 45 61 u1 max1215n t2 c9 0.1 f 32 1 65 4 8 inp c12 1pf r8 24.9 0.1% r16 10 1% r9 24.9 0.1% c25 0.1 f r82 0 9 inn c20 0.1 f r17 10 1% c26 0.1 f clkp 22 23 refadj tp1 4 refi0 3 r18100 1%r19 100 1% orp orporn 5958 orn d11p d11pd11n 5756 d11n r20100 1% d10p d10pd10n 5554 d10n r21100 1% d9p d9pd9n 5352 d9n r22100 1% d8p d8pd8n 5150 d8n r23100 1% d7p d7pd7n 4948 d7n r24100 1% d6p d6pd6n 4746 d6n dclkp dcopdcon 4342 dclkn r29100 1% r28100 1% d5p d5pd5n 4039 d5n r30100 1% d4p d4pd4n 3837 d4n r31100 1% d3p d3pd3n 3635 d3n r32100 1% d2p d2pd2n 3433 d2n r34100 1% d1p d1pd1n 3231 d1n r35100 1% d0p d0pd0n 3029 d0n clkp clkn clkn refadj 31 2 vcc j1 clkdiv 17 t/b 68 1 2 3 ju3 vcc j1-3 j1-5 j1-7 rj refadj rj j1-1 j1-2 j1-4j1-6 j1-8 refadj r40100k r42 13k 1% t1 t1 - 1 15 3 42 6 r3 0 r13 open r1open r80 short (pc trace) in t1 - 3 t1 - 1 r11 open t1 - 3 c45open vclk c2910 f c321.0 f gnd c28220 f 6.3v c48open vcc c3022 f c34open c332.2 f vcc c31open gnd c10220 f 6.3v c47open ovcc c1122 f c44open c142.2 f ovcc c43open gnd 1 2 3 ju2 vcc r81 0 downloaded from: http:///
evaluates: max1215n max1215n evaluation kit ___________________________________________________ ____________________________________ 7 j4-4 j4-2 j4-5 j4-6 j4-3j4-1 borp born j4-10 j4-8 j4-7 j4-12 j4-9j4-11 bd11p bd11n j4-16 j4-14 j4-13 j4-18 j4-15j4-17 bd10p bd10n j4-22 j4-20 j4-19 j4-24 j4-21j4-23 bd9p bd9n j4-28 j4-26 j4-25 j4-30 j4-27j4-29 bd8p bd8n j4-34 j4-32 j4-31 j4-36 j4-33j4-35 bd7p bd7n j4-40 j4-38 j4-37 j4-39 bd6p bd6n j5-2 j5-3 j5 j4 j5-4 j5-6 j5-1j5-5 bdc0p bdc0n j5-8 j5-9 j5-10 j5-12 j5-7j5-11 bd5p bd5n j5-14 j5-15 j5-16 j5-18 j5-13j5-17 bd4p bd4n j5-20 j5-21 j5-22 j5-24 j5-19j5-23 bd3p bd3n j5-26 j5-27 j5-28 j5-30 j5-25j5-29 bd2p bd2n j5-32 j5-33 j5-34 j5-36 j5-31j5-35 bd1p bd1n j5-38 j5-39 j5-40 j5-37 bd0p bd0n vpecl vpecl gnd c40220 f 6.3v c4110 f c421.0 f r4149.9 1%r44 49.9 1% q0 borp r7 49.9 1% c58 open orp 19 d0 2 orn d0 3 d11p d1 4 d11n d1 5 d10p d2 6 d10n d2 7 d9p d3 8 d9n d3 9 born q0 18 r4549.9 1%r46 49.9 1% q1 bd11p 17 bd11n q1 16 r4749.9 1%r48 49.9 1% q2 bd10p 15 bd10n q2 14 r4949.9 1%r50 49.9 1% q3 bd9p 13 bd9n q3 vbb n.c. n.c. n.c.n.c. n.c.n.c. n.c. n.c. n.c. n.c. vee 12 11 10 vpecl vcc 20 c36 0.1 f vcc 1 u3 mc100lvel17 r3849.9 1%r39 49.9 1% q0 bd8p d8p 19 d0 2 d8n d0 3 d7p d1 4 d7n d1 5 d6p d2 6 d6n d2 7 d3 8 d3 9 bd8n q0 18 r5149.9 1%r52 49.9 1% q1 bd7p 17 bd7n q1 16 r5349.9 1%r54 49.9 1% q2 bd6p 15 bd6n q2 14 q3 13 q3 12 vbb vee 11 10 vpecl vcc 20 c38 0.1 f vcc 1 u4 mc100lvel17 r5749.9 1%r58 49.9 1% q0 bdcop dcop 19 d0 2 dcon d0 3 d5p d1 4 d5n d1 5 d4p d2 6 d4n d2 7 d3p d3 8 d3n n.c.n.c. d3 9 bdcon q0 18 r5949.9 1%r60 49.9 1% q1 bd5p 17 bd5n q1 16 r6149.9 1% r6249.9 1% q2 bd4p 15 bd4n q2 14 r6349.9 1% r6449.9 1% q3 bd3p 13 bd3n q3 vbb vee 12 11 10 vpecl vcc 20 c37 0.1 f vcc 1 u5 mc100lvel17 r5549.9 1%r56 49.9 1% q0 bd2p d2p 19 d0 2 d2n d0 3 d1p d1 4 d1n d1 5 d0p d2 6 d0n d2 7 d3 8 d3 9 bd2n q0 18 r6549.9 1%r66 49.9 1% q1 bd1p 17 bd1n q1 16 r6749.9 1%r68 49.9 1% q2 bd0p 15 bd0n q2 14 q3 13 q3 12 vbb vee 11 10 vpecl vcc 20 c39 0.1 f vcc 1 u6 mc100lvel17 r10 49.9 1% c59 open r43 49.9 1% c60 open r69 49.9 1% c61 open r72 49.9 1% c64 open r71 49.9 1% c63 open r70 49.9 1% c62 open r73 49.9 1% c65 open r74 49.9 1% c66 open r75 49.9 1% c67 open r76 49.9 1% c68 open r79 49.9 1% c69 open r78 49.9 1% c70 open r77 49.9 1% c71 open c48open figure 1b. max1215n ev kit schematic (sheet 2 of 3) downloaded from: http:///
evaluates: max1215n max1215n evaluation kit 8 __________________________________________________ _____________________________________ figure 1c. max1215n ev kit schematic (sheet 3 of 3) r249.9 1% ju4 r449.9 1% clkp r5 49.9 1% c19 0.1 f c16 0.1 f c18 0.1 f q d0 2 d0 3 d1 4 d1 5 vbb1 d1 d1 vee 11 13 vbb2 12 vclk vbb2 vbb2 vclk clk vclk vcc vcc 114 u2 max9388 c15 0.1 f c13 0.1 f vclk vcc vcc 17 16 15 1 3 2 20 c35 0.1 f clkn c49 0.1 f q 18 sel0 ju1 ju5 19 sel1 c53 0.1 f r2610k 1% r25510 r37 510 c540.1 f c52 0.1 f r14 49.9 1% r6 49.9 1% r12 49.9 1% r15 49.9 1% 1 3 2 vclk r36 1.82k 1% r33 3.16k 1% d2 6 d2 7 d3 8 d3 9 vee 10 c51 0.1 f c50 0.01 f vbb2 vclk y1 (open) gnd vcc out n.c. 1 6 d1 4 out d1 5 oe vclk 1 3 2 3 2 ju6 vclk c56 0.01 f c55 0.1 f r27 5k downloaded from: http:///
evaluates: max1215n max1215n evaluation kit ___________________________________________________ ____________________________________ 9 figure 2. max1215n ev kit component placement guide?omponent side downloaded from: http:///
evaluates: max1215n max1215n evaluation kit 10 _________________________________________________ _____________________________________ figure 3. max1215n ev kit pcb?omponent side downloaded from: http:///
evaluates: max1215n max1215n evaluation kit ___________________________________________________ ___________________________________ 11 figure 4. max1215n ev kit pcb layout?round plane (layer 2) downloaded from: http:///
evaluates: max1215n max1215n evaluation kit 12 _________________________________________________ _____________________________________ figure 5. max1215n ev kit pcb layout?ower plane (layer 3) downloaded from: http:///
maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 13 2007 maxim integrated products is a registered trademark of maxim integrated products, inc. evaluates: max1215n max1215n evaluation kits figure 6. max1215n ev kit pcb layout?older side downloaded from: http:///

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