VBUS54FD-SD1 www.vishay.com vishay semiconductors rev. 1.1, 20-sep-16 1 document number: 82665 for technical questions, contact: esdprotection@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 4-line bus-port esd protection array - flow through design marking 5f4 = type code ? mm = date code month ? yy = date code year features ? compact chip level page clp1007-5l ? length = 1 mm; width = 0.7 mm; ? height = 0.27 mm ? 4-lines, unidirectional esd-protection array ? low leakage current i r < 0.1 a ? low capacitance at v r = 0 v = 0.9 pf (typ.) ? ideal for high sp eed data line like ? - hdmi, displayport, esata ? - usb, 1394/firewire ? - thunderbolt ? esd-protection acc. iec 61000-4-2 ? 15 kv contact discharge ? 15 kv air discharge ? e4 - precious metal (e.g. ag, au, nipd, nipdau) (no sn) ? material categorization: fo r definitions of compliance please see www.vishay.com/doc?99912 ? ? ? ? mm yy type 1 22736 13 2 5 4 pin 1 22738 mm yy 5f4 ordering information device name ordering code taped units per reel (8 mm tape on 7" reel) minimum order quantity VBUS54FD-SD1 VBUS54FD-SD1-g4-08 10 000 10 000 package data device name package name type code weight moisture sensitivity level soldering conditions VBUS54FD-SD1 clp1007-5l 5f4 0.1 mg msl level 1 (according j-std-020) 260 c/10 s at terminals absolute maximum ratings (t amb = 25 c, unless otherwise specified) parameter test conditions symbol value unit peak pulse current acc. iec 61000-4-5; t p = 8/20 s; single shot i ppm 3a peak pulse power acc. iec 61000-4-5; t p = 8/20 s; single shot p pp 45 w esd immunity contact discharge acc. iec 61000-4-2; 10 pulses v esd 15 kv air discharge acc. iec 61000-4-2; 10 pulses 15 operating temperature junction temperature t j -40 to +125 c storage temperature t stg -55 to +150 c
VBUS54FD-SD1 www.vishay.com vishay semiconductors rev. 1.1, 20-sep-16 2 document number: 82665 for technical questions, contact: esdprotection@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 application note the VBUS54FD-SD1 is a four-line esd-protection device with the characteristic of a z-diode with a high esd-immunity and a very low capacitance which makes it usable for high fr equency applications like usb 2.0, usb 3.0 or hdmi. ? with the VBUS54FD-SD1 four high speed data lines can be protected agains t transient voltage signals like esd (electro static discharge). connected to the data line (pin 1, 3 and pin 4, 5) and to ground (p in 2) negative transients will be clamped close below the ground level while positive transients will be clam ped close above the 5.5 v working range. the clamping behavior of the VBUS54FD-SD1 is bidirectional but asymmetrical ( bias ) and so it offers the best prote ction for applications running up to 5.5 v. pin configuration: ? pin 2 is the central ground pin and has to be connected to ground ? pin 1, 3 and 4, 5 are the inputs for the data lines d 1+ and d 1- and d 2+ and d 2- flow through design modern digital transmission lines ca n be clocked up to 480 mbit/s (u sb 2.0) or 1.65 gbit/s (hdmi). ? at such high data rates the tran smission lines like cables or the line traces on the pcbs have to be very homogeneous regarding their surge impedance. this requ ires well defined trace dimensions as trace wi dth and distance which have to be calculated depending on the requested surge impedance (e.g. 50 ? ) and the pcb material and layer dimensions. any device connected to the data lines - like esd-protection devi ces - have to be connected with minimal changes in these trace dimensions and distances. ? with the package in the so called flow through design this is possible. the lines are running straight along the pcb while th e VBUS54FD-SD1 is placed on top without any vias or loops. electrical characteristics (pin 1, 3, 4 or 5 to pin 2) ? (t amb = 25 c, unless otherwise specified) parameter test conditions/remarks symbol min. typ. max. unit protection paths number of li nes which can be protected n channel --4lines reverse stand-off voltage max. reverse working voltage v rwm --5.5v reverse voltage at i r = 0.1 a v r 5.5 - - v reverse current at v rwm = 5.5 v i r - < 1 na 0.1 a reverse breakdown voltage at i r = 1 ma v br 6.9 7.5 8.7 v reverse clamping voltage at i pp = 1 a v c -9.511v at i pp = i ppm = 3 a v c - 12.9 15 v forward clamping voltage at i pp = 1 a v f -1.82.2v at i pp = 3 a v f -34v capacitance at v r = 0 v; f = 1 mhz c d -0.91pf at v r = 3.3 v; f = 1 mhz - 0.9 1 pf clamping voltage transmiss ion line pulse (tlp); t p = 100 ns, i tlp = 8 a v c-tlp -18- v clamping voltage transmissi on line pulse (tlp); t p = 100 ns, i tlp = 16 a v c-tlp -24- v dynamic resistance transmissi on line pulse (tlp); t p = 100 ns v c-tlp -0.93- ? 22736 13 2 5 4 receiver tran s mitter d1+ d1- g nd d2+ d2- d1+ d1- g nd d2+ d2- 1 2 3 5 4 22737
VBUS54FD-SD1 www.vishay.com vishay semiconductors rev. 1.1, 20-sep-16 3 document number: 82665 for technical questions, contact: esdprotection@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 typical characteristics (t amb = 25 c, unless otherwise specified) fig. 1 - esd discharge current wave form acc. iec 61000-4-2 (330 ? /150 pf) fig. 2 - 8/20 s peak pulse current wave form acc. iec 61000-4-5 fig. 3 - typical capacitance c d vs. reverse voltage v r fig. 4 - typical forward current i f vs. forward voltage v f fig. 5 - typical reverse voltage v r vs. reverse current i r fig. 6 - typical peak clamping voltage v c vs. peak pulse current i pp 0 % 20 % 40 % 60 % 80 % 100 % 120 % -10 0 102030405060708090100 time (ns) discharge current i esd rise time = 0.7 ns to 1 ns 53 % 27 % 20557 0 % 20 % 40 % 60 % 80 % 100 % 010203040 time (s) i ppm 20 s to 50 % 8 s to 100 % 20548 c d in pf v r in v 22779 0.0 0.2 0.4 0.6 0.8 1.0 1.2 0123456 f = 1mhz pin 1, 3, 4 or 5 to pin 2 0.001 0.01 22780 0.1 1 10 100 1000 0 0.5 1 1.5 2 v f in v i f in ma i r in a v r in v 0 22781 1 2 3 4 5 6 7 8 9 0.01 0.1 1 10 100 1000 10 000 i pp in a v c in v 22782 0 2 4 6 8 10 12 14 0123 pin 1, 3, 4 or 5 to pin 2 pin 2 to pin 1, 3, 4 or 5 mea s ured acc. iec 61000-4-5 (8/20 s - wave form)
VBUS54FD-SD1 www.vishay.com vishay semiconductors rev. 1.1, 20-sep-16 4 document number: 82665 for technical questions, contact: esdprotection@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 fig. 7 - typical clamping performance at 100 ns transmission li ne pulse (tlp) package dimensions in millimeters: clp1007-5l ? footprint and solder ing recommendation: ? please see application note: www.vishay.com/doc?85917 i tlp in a v c-tlp in v 22783 0 5 10 15 20 25 30 35 40 45 0 5 10 15 20 25 30 tlp: t p = 100 n s foot print recommendation: document no.:s8-v-3906.04-041 (4) package = chip dimensions in mm created - date: 11. august 2015 be 12 3 4 5 e e d l d a a1 ty p e mm yy millimeter s a a1 b d e radiu s l min. max. 0.25 0.68 0.98 0.23 0.29 0.15 0.73 1.03 0.075 e 0.03 0.35 0.35 0.155 0.855 0.7 0.25 0.27 - 0.02 0.13 e 0.35 22857
VBUS54FD-SD1 www.vishay.com vishay semiconductors rev. 1.1, 20-sep-16 5 document number: 82665 for technical questions, contact: esdprotection@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 carrier tape in millimeters: clp1007 orientation in carrier tape: clp1007 s ee note 1 s ee note 2 2 0.05 1.5 +0.1 0 8 +0.3 -0.1 1.75 0.1 3.5 0.05 ? 0.3 0.1 0.2 0.05 a0 a0 = 0.82 0.05 b0 = 1.12 0.05 k0 = 0.40 0.05 b0 k0 r 0.1 max. s ee note 2 r 0.1 typ. 2 4 (5) a - a a a notes: 1. 10 s procket hole pitch cumulative tolerance 0.2 2. pocket po s ition relative to s procket hole mea s ured a s true po s ition of pocket, not pocket hole 3. a0 and b0 are calculated on a plane at a di s tance r above the bottom of the pocket document no.: s8-v-3906.04-042 (3) created - date: 23. november 2015 22858 unreeling direction top view pad layout - view from top s een at bottom s ide clp1007 document no.: s8-v-3906.04-043 (4) created - date: 17. august 2015 22859 mm yy type mm yy type mm yy type mm yy type 123 4 5
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