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datasheet 2:1 differential-to-hcsl multiplexer with low input level alarm ics851s201i ics851s201cki may 27, 2017 1 ?2017 integrated device technology, inc. general description the ics851s201i is a high performance 2:1 differential-to-hcsl multiplexer with a 2 output fanout buffer. the ics851s201i operates up to 250mhz and accepts hcsl and other low level differential inputs levels. input level detection circuitry is available to flag input levels that drops below a specified value and on the selected input. this signal is latched until the status is reset via the alarm reset input. the ics851s201i is packaged in a small 3mm x 3mm 16 lead vfqfn package, making it ideal for use on space constrained boards. block diagram features ? two differential hcsl output pairs ? two selectable differential clock input pairs ? clkx, nclkx pairs can accept hcsl level inputs ? low level input detection on selected input (latched) ? maximum input frequency: 250mhz ? output skew: 5ps (typical) ? propagation delay: 1.4ns (typical) ? additive rms phase jitter at 133.33mhz (12khz - 20mhz): 0.151ps (typical) ? full 3.3v operating supply ? -40c to 85c ambient operating temperature ? lead-free (rohs 6) packaging pin assignment ics851s201i 16-lead vfqfn top view q0 nq 0 ll a c lk_sel clk0 nclk0 0 1 pulldown pullup/pulldown pulldown pulldown iref llar q1 nq 1 clk1 nclk1 pulldown pullup/pulldown 5 6 7 8 16 15 14 13 1 2 3 4 12 11 10 9 clk0 n clk0 clk1 n clk1 nq 0 q0 nq 1 q1 v dd l lar lla gnd clk_se l iref v dd gnd
ics851s201cki may 27, 2017 2 ?2017 integrated device technology, inc. ics851s201i data sheet 2:1 differential-to-hcsl multiplexer pin descriptions and characteristics table 1. pin descriptions note: pullup and pulldown refer to internal input resistors. see table 2, pin characteristics, for typical values. table 2. pin characteristics number name type description 1 clk0 input pulldown non-inverting differential hcsl clock input. 2 nclk0 input pullup/ pulldown inverting differential hcsl clock input. v dd /2 default when left floating. 3 clk1 input pulldown non-inverting differential hcsl clock input. 4 nclk1 input pullup/ pulldown inverting differential hcsl clock input. v dd /2 default when left floating. 5, 13 v dd power positive supply pins. 6 llar input pulldown low level alarm reset. when high, resets lla latch. must be low to allow lla to set. lvcmos/lvttl interface levels. 7 lla output low level alarm. when high, low level input has been detected on selected differential input (latched). 8, 16 gnd power power supply ground. 9, 10 q1, nq1 output differential output pair. hcsl interface levels. 11, 12 q0, nq0 output differential output pair. hcsl interface levels. 14 iref input external fixed precision resistor (475 ??? from this pin to ground provides a reference current used for differential current-mode qx, nqx clock outputs. 15 clk_sel input pulldown clock select input. when high, selects clk1, nclk1 inputs. when low, selects clk0, nclk0 inputs. lvcmos/lvttl interface levels. symbol parameter test conditions minimum typical maximum units c in input capacitance 2 pf r pulldown input pulldown resistor 50 k ? r pullup input pullup resistor 50 k ?
ics851s201cki may 27, 2017 3 ?2017 integrated device technology, inc. ics851s201i data sheet 2:1 differential-to-hcsl multiplexer function tables table 3a. low level alarm function table note: input amplitude that is <550mv and >325mv will not reliably cause the lla output to go high. input amplitude that is <325 mv will always flag the lla output high. note: logic high, logic low, and a differential short on the inputs will cause the lla output to go high. this feature is only available when both differential inputs are being used, and their respective frequencies are within 50% of one another (i.e.: clk0 is 100mhz, clk1 must be within 50mhz to 150mhz). table 3b. control input function table valid input level on selected input llar lla v ih ? 550mv 0 low (default) v ih ? 325mv 0 high n/a 1 forced low clk_sel input selected 0 clk0, nclk0 (default) 1 clk1, nclk1
ics851s201cki may 27, 2017 4 ?2017 integrated device technology, inc. ics851s201i data sheet 2:1 differential-to-hcsl multiplexer absolute maximum ratings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional operation of product at these conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. dc electrical characteristics table 4a. power supply dc characteristics, v dd = 3.3v5%; t a = -40c to 85c table 4b. lvcmos/lvttl dc characteristics, v dd = 3.3v5%; t a = -40c to 85c note 1: see parameter measurement information section, 3.3v output load test circuit diagram . table 4c. dc characteristics, v dd = 3.3v5%; t a = -40c to 85c note 1: common mode input voltage is defined at the cross point. item rating supply voltage, v dd 4.6v inputs, v i -0.5v to v dd + 0.5v outputs, v o -0.5v to v dd + 0.5v package thermal impedance, ? ja 74.7 ? c/w (0 mps) storage temperature, t stg -65 ? c to 150 ? c symbol parameter test conditions minimum typical maximum units v dd positive supply voltage 3.135 3.3 3.465 v i dd power supply current unloaded outputs 44 ma symbol parameter test conditions minimum typical maximum units v ih input high voltage 2.2 v dd + 0.3 v v il input low voltage -0.3 0.8 v i ih input high current llar, clk_sel v dd = v in = 3.465v 150 a i il input low current llar, clk_sel v dd = 3.465v, v in = 0v -10 a v oh output high voltage lla; note 1 2.6 v v ol output low voltage lla; note 1 0.5 v symbol parameter test conditions minimum typical maximum units i ih input high current clk0, clk1, nclk0, nclk1 v dd = v in = 3.465v 150 a i il input low current clk0, clk1 v dd = 3.465v, v in = 0v -10 a nclk0, nclk1 v dd = 3.465v, v in = 0v -150 a v pp peak-to-peak voltage 150 1300 mv v cmr common mode input voltage; note 1 gnd ? 0.5 v dd ? 0.85 v
ics851s201cki may 27, 2017 5 ?2017 integrated device technology, inc. ics851s201i data sheet 2:1 differential-to-hcsl multiplexer ac electrical characteristics table 5. ac characteristics, v dd = 3.3v5%; t a = -40c to 85c note: electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when th e device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. the device will meet specifications after thermal equilibrium has been reached under these conditions. note: all parameters measured at ? ? 250mhz unless otherwise noted. note 1: measured from the differential input crossing point to the differential output crossing point. note 2: this parameter is defined in accordance with jedec standard 65. note 3: defined as skew between outputs on different devices operating at the same supply voltage, same temperature, same frequ ency and with equal load conditions. using the same type of inputs on each device, the outputs are measured at the differential cros s points. note 4: defined as skew between outputs at the same supply voltages and with equal load conditions. measured at the output diff erential cross points. note 5: measurement taken from differential waveform. note 6: measured from -150mv to +150mv on the differential waveform (derived from qx minus nqx). the signal must be monotonic through the measurement region for rise and fall time. the 300mv measurement window is centered on the differential zero crossi ng. see parameter measurement information section. note 7: measurement taken from single ended waveform. note 8: defined as the maximum instantaneous voltage including overshoot. see parameter measurement information section. note 9: defined as the minimum instantaneous voltage including undershoot. see parameter measurement information section. note 10: measured at crossing point where the instantaneous voltage value of the rising edge of qx equals the falling edge of n qx. see parameter measurement information section note 11: refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. ref ers to all crossing points for this measurement. see parameter measurement information section. note 12: defined as the total variation of all crossing voltage of rising qx and falling nqx. this is the maximum allowed varia nce in the v cross for any particular system. see parameter measurement information section. note 13: qx, nqx output measured differentially. see parameter measurement information for mux isolation diagram. symbol parameter test conditions minimum typical maximum units f out output frequency 250 mhz t pd propagation delay; note 1 1.24 1.4 1.70 ns t sk(pp) part-to-part skew; note 2, 3 150 ps tsk(o) output skew, note 2, 4 534ps tjit buffer additive phase jitter, rms 133.33mhz, integration range: 12khz - 20mhz 0.151 0.166 ps rise/fall edge rate; note 5, 6 1.60 2.56 3.74 v/ns v max absolute max output voltage; note 7, 8 1150 mv v min absolute min output voltage note 7, 9 -300 mv v cross absolute crossing voltage; note 7, 10, 11 250 550 mv ? v cross total variation of v cross over all edges; note 7, 10, 12 140 mv odc output duty cycle 47 50 53 % mux isol mux isolation; note 13 ? out ? 100mhz -65 -63 -62 db
ics851s201cki may 27, 2017 6 ?2017 integrated device technology, inc. ics851s201i data sheet 2:1 differential-to-hcsl multiplexer parameter measurement information output load ac test circuit differential input level part-to-part skew output load ac test circuit output skew mux isolation hcsl gnd 0v 0v scop e iref 3.3v5% this load condition is used for i dd, tjit, tsk(pp), tsk(o) and t pd measurements. v dd gnd nclkx clkx t sk(pp) p art 1 p art 2 nqx qx nqx qx 475 33 50 50 33 49.9 49.9 hcsl gnd 2pf 2pf qx nqx 0v iref 3.3v5% nqx qx nqx qx amplitude (db) a0 spectrum of output signal q mux _isol = a0 ? a1 (fundamental) frequency ? mux selects static inp ut mux selects active input clock signal a1
ics851s201cki may 27, 2017 7 ?2017 integrated device technology, inc. ics851s201i data sheet 2:1 differential-to-hcsl multiplexer parameter measurement information, continued propagation delay differential measurement points for duty cycle/period single-ended measurement points for absolute cross point and swing single-ended measurement points for delta cross point output rise/fall edge rate t pd nqx qx nclkx clkx
ics851s201cki may 27, 2017 8 ?2017 integrated device technology, inc. ics851s201i data sheet 2:1 differential-to-hcsl multiplexer applications information recommendations for unused input and output pins inputs: clk/nclk inputs for applications not requiring the use of a differential input, both the clk and nclk pins can be left floating. though not required, but for additional protection, a 1k ? resistor can be tied from clk to ground. lvcmos control pins all control pins have internal pulldowns; additional resistance is not required but can be added for additional protection. a 1k ? resistor can be used. outputs: differential outputs all unused differential outputs can be left floating. we recommend that there is no trace attached. both sides of the differential output pair should either be left floating or terminated. differential clock input interface the clk /nclk accepts hcsl and other differential signals. both differential signals must meet the v pp and v cmr input requirements. figure 2 shows interface examples for the clk/nclk input driven by the most common driver types. the input interfaces suggested here are examples only. please consult with the vendor of the driver component to confirm the driver termination requirements. figure 2. clk/nclk input driven by a 3.3v hcsl driver hcsl *r3 *r4 clk nclk 3.3v 3.3v differential input
ics851s201cki may 27, 2017 9 ?2017 integrated device technology, inc. ics851s201i data sheet 2:1 differential-to-hcsl multiplexer vfqfn epad thermal release path in order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the printed circuit board (pcb) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in figure 3. the solderable area on the pcb, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. sufficient clearance should be designed on the pcb between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. while the land pattern on the pcb provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are necessary to effectively conduct from the surface of the pcb to the ground plane(s). the land pattern must be connected to ground through these vias. the vias act as ?heat pipes?. the number of vias (i.e. ?heat pipes?) are application specific and dependent upon the package power dissipation as well as electrical conductivity requirements. thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. it is recommended to use as many vias connected to ground as possible. it is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. this is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal land. precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. note: these recommendations are to be used as a guideline only. for further information, please refer to the application note on the surface mount assembly of amkor?s thermally/ electrically enhance leadframe base package, amkor technology. figure 3. p.c. assembly for exposed pad thermal release path ? side view (drawing not to scale) solder solder pin pin exposed heat slug pin pad pin pad ground plane land pattern (ground pad) thermal via
ics851s201cki may 27, 2017 10 ?2017 integrated device technology, inc. ics851s201i data sheet 2:1 differential-to-hcsl multiplexer recommended termination figure 4a is the recommended source termination for applications where the driver and receiver will be on a separate pcbs. this termination is the standard for pci express? and hcsl output types. all traces should be 50 impedance single-ended or 100 differential. figure 4a. recommended source termination (where the driver and receiver will be on separate pcbs) figure 4b is the recommended termination for applications where a point-to-point connection can be used. a point-to-point connection contains both the driver and the receiver on the same pcb. with a matched termination at the receiver, transmission-line reflections will be minimized. in addition, a series resistor (rs) at the driver offers flexibility and can help dampen unwanted reflections. the optional resistor can range from 0 to 33 . all traces should be 50 impedance single-ended or 100 differential. figure 4b. recommended termination (where a point-to-point connection can be used)
ics851s201cki may 27, 2017 11 ?2017 integrated device technology, inc. ics851s201i data sheet 2:1 differential-to-hcsl multiplexer power considerations this section provides information on power dissipation and junction temperature for the ics851s201i. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ics851s201i is the sum of the core power plus the power dissipated in the load(s). the following is the power dissipation for v dd = 3.3v + 5% = 3.465v, which gives worst case results. note: please refer to section 3 for details on calculating power dissipated in the load. the maximum current at 85c is as follows: i dd_max = 37ma ? power (core) max = v dd_max * i dd = 3.465v * 44ma = 152.46mw ? power (hcsl) max = 2 * 44.5mw = 89mw total power_ max = 152.46mw + 89mw = 241.46mw 2. junction temperature. junction temperature, tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. the maximum recommended junction temperature is 125c. limiting the internal transistor junction temperature, tj, to 125c ensures that the bond wire and bond pad temperature remains below 125c. the equation for tj is as follows: tj = ? ja * pd_total + t a tj = junction temperature ? ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ? ja must be used. assuming no air flow and a multi-layer board, the appropriate value is 74.7c/w per table 7 below. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 0.242w * 74.7c/w = 103c. this is below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). table 6. thermal resistance ? ja for 16 lead vfqfn, forced convection ? ja vs. air flow meters per second 0 1 2.5 multi-layer pcb, jedec standard test boards 74.7c/w 65.3c/w 58.5c/w
ics851s201cki may 27, 2017 12 ?2017 integrated device technology, inc. ics851s201i data sheet 2:1 differential-to-hcsl multiplexer 3. calculations and equations. the purpose of this section is to calculate power dissipation on the ic per hcsl output pair. hcsl output driver circuit and termination are shown in figure 6. figure 6. hcsl driver circuit and termination hcsl is a current steering output which sources a maximum of 17ma of current per output. to calculate worst case on-chip power dissipation, use the following equations which assume a 50 ? load to ground. the highest power dissipation occurs when v dd _ max . power = (v dd_max ? v out ) * i out since v out = i out * r l power = (v dd_max ? i out * r l ) * i out = (3.465v ? 17ma * 50 ? ) * 17ma total power dissipation per output pair = 44.5mw v dd v out r l 50 ? ic i out = 17ma r ref = 4 75 ? 1%
ics851s201cki may 27, 2017 13 ?2017 integrated device technology, inc. ics851s201i data sheet 2:1 differential-to-hcsl multiplexer reliability information table 7. ? ja vs. air flow table for a 16 lead vfqfn transistor count the transistor count for ics851s201i is: 713 ? ja by velocity meters per second 0 1 2.5 multi-layer pcb, jedec standard test boards 74.7c/w 65.3c/w 58.5c/w
ics851s201cki may 27, 2017 14 ?2017 integrated device technology, inc. ics851s201i data sheet 2:1 differential-to-hcsl multiplexer package outline drawings (sheet 1)
ics851s201cki may 27, 2017 15 ?2017 integrated device technology, inc. ics851s201i data sheet 2:1 differential-to-hcsl multiplexer package outline drawings (sheet 2)
ics851s201cki may 27, 2017 16 ?2017 integrated device technology, inc. ics851s201i data sheet 2:1 differential-to-hcsl multiplexer ordering information table 9. ordering information part/order number marking package shipping packaging temperature 851S201CKILF 1cil ?lead-free? 16 lead vfqfn tube -40 ? c to 85 ? c 851S201CKILFt 1cil ?lead-free? 16 lead vfqfn tape & reel -40 ? c to 85 ? c
ics851s201i data sheet 2:1 differential-to-hcsl multiplexer 17 ?2017 integrated device technology, inc. disclaimer integrated device technology, inc. (idt) and its affiliated companies (herein referred to as ?idt?) reserve the righ t to modify the products and/or specifications described herein at any time, without notice, at idt?s sole discretion. performance specifications and operating parameters of the described products are det ermined in an independent state and are not guaranteed to perform the same way when installed in customer products. the information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of idt's products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual p roperty rights of others. this document is presented only as a guide and does not convey any license under intellectual property rights of idt or any third parties. idt's products are not intended for use in applications involving extreme environmental conditions or in life support systems o r similar devices where the failure or malfunction of an idt product can be rea- sonably expected to significantly affect the health or safety of users. anyone using an idt product in such a manner does so at their own risk, absent an express, written agreement by idt. integrated device technology, idt and the idt logo are trademarks or registered trademarks of idt and its subsidiaries in the u nited states and other countries. other trademarks used herein are the property of idt or their respective third party owners. for datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary . integrated device technology, inc.. all rights reserved. tech support www.idt.com/go/support sales 1-800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com/go/sales corporate headquarters 6024 silver creek valley road san jose, ca 95138 usa www.idt.com revision history sheet rev table page description of change date a amr t4b t5 t5 4 4 5 5 supply voltage, v dd = 4.6v. note 1: deleted ?outputs terminated with 50 ?? to vdd/2.?. output duty cycle: 47%(min), 53%(max). mux isol : -65db (min) 9/62013 b - 14 updated the package outline drawings. 5/27/2017

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