ds108-1 (v1.7) april 3, 2007 www.xilinx.com 1 product specification ? 2002-2007 xilinx, inc. all rights reserved. all xilinx trademarks, registered trademarks, patents, and disclaimers are as lis ted at http://www.xilinx.com/legal.htm . all other trademarks and registered trademarks are the property of their respective owners. all specifications are subject to c hange without notice. k features ? aec-q100 device qualification and full ppap support available in both extended temperature q-grade and i-grade. ? guaranteed to meet full electrical specifications over t a = -40 c to +105 c with t j maximum = +125 c (q-grade) ? system frequency up to 64.5 mhz (15.5 ns) ? available in small footprint packages ? optimized for high-performance 3.3v systems - 5v tolerant i/o pins accept 5v, 3.3v, and 2.5v signals ? ideal for multi-voltage system interfacing and level shifting - technology: 0.35 m cmos process ? advanced system features - in-system programmable enabling higher system reliability through reduced handling and reducing production programming times - superior pin-locking and routability with fastconnect? ii switch matrix allowing for multiple design iterations without board re-spins - input hysteresis on all user and boundary-scan pin inputs to reduce noise on input signals - bus-hold circuitry on all user pin inputs which reduces cost associated with pull-up resistors and reduces bus loading - full ieee standard 1149.1 boundary-scan (jtag) for in-system device testing fast concurrent programming ? slew rate control on individual outputs for reducing emi generation ? refer to xc9500xl family data sheet (ds054) for architecture description ? refer to xa9536xl data sheet (ds598), the xa9572xl data sheet (ds599), and the xa95144xl data sheet (ds600) for pin tables ? xilinx received iso/ts 16949 certification in march 2005. warning: programming temperature range of t a = 0 c to +70 c description the xa9500xl 3.3v cpld automotive xa product family is targeted for leading-edge, high-performance automotive applications that require either automotive industrial (?40c to +85c ambient) or extended (?40c to +105c ambient) temperature reconfigurable devices. power estimation power dissipation in cplds can vary substantially depend- ing on the system frequency, design application and output loading. each macrocell in an xa9500xl automotive device must be configured for low-power mode (default mode for xa9500xl devices). in addition, unused product-terms and macrocells are automatically deactivated by the software to further conserve power. for a general estimate of i cc , the following equation may be used: i cc (ma) = mc(0.052*pt + 0.272) + 0.04 * mc tog *mc* f where: mc = # macrocells pt = average number of product terms per macrocell f = maximum clock frequency mc tog = average % of flip-flops toggling per clock (~12%) this calculation is based on typical operating conditions using a pattern of 16-bit up/down counters in each function block with no output loading. the actual i cc value varies with the design application and should be verified during 0 xa9500xl automotive cpld product family ds108-1 (v1.7) april 3, 2007 00 product specification r table 1: xa9500xl device family device temperature grade macrocells usable gates registers f system (mhz) xa9536xl i, q 36 800 36 64.5 xa9572xl i, q 72 1,600 72 64.5 xa95144xl i 144 3,200 144 64.5
xa9500xl automotive cpld product family 2 www.xilinx.com ds108-1 (v1.7) april 3, 2007 product specification r absolute maximum ratings (1,2) recommended operating conditions quality and reliability characteristics table 2: xa9500xl packages and user i/o pins (not including four dedicated jtag pins) device vqg44 vqg64 TQG100 csg144 xa9536xl 34 -- -- -- xa9572xl 34 52 72 -- xa95144xl -- -- -- 117 symbol description min. max. units v cc supply voltage relative to gnd ?0.5 4.0 v v in input voltage relative to gnd (3) ?0.5 5.5 v v ts voltage applied to 3-state output (3) ?0.5 5.5 v t stg storage temperature (ambient) (4) ?65 +150 o c t j junction temperature - +125 o c notes: 1. all automotive customers are required to set the macrocell power setting to low, and set logic optimization to density. 2. stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under operating condi tions is not implied. exposure to absolute maximum ratings conditions for extended periods of time may affect device reliability. 3. maximum dc undershoot below gnd must be limited to either 0.5v or 10 ma, whichever is easier to achieve. during transitions, the device pins may undershoot to ?2.0 v or overshoot to +7.0v, provided this over- or undershoot lasts less than 10 ns and with th e forcing current being limited to 200 ma. 4. for soldering guidelines, see the package information on the xilinx website. symbol parameter min max units t a ambient temperature i-grade ?40 +85 c q-grade ?40 +105 c v ccint supply voltage for internal logic and input buffers 3.0 3.6 v v ccio supply voltage for output drivers for 3.3v operation 3.0 3.6 v supply voltage for output drivers for 2.5v operation 2.3 2.7 v v il low-level input voltage 0 0.80 v v ih high-level input voltage 2.0 5.5 v v o output voltage 0 v ccio v symbol parameter min max units t dr data retention 20 - years n pe program/erase cycles (endurance) @ t a = 70c 10,000 - cycles
xa9500xl automotive cpld product family ds108-1 (v1.7) april 3, 2007 www.xilinx.com 3 product specification r component availability ordering information xa9500xl automotive requirements and recommendations requirements the following requirements are for all automotive applica- tions: 1. all automotive customers are required to keep the macrocell power selection set to low, and the logic optimization set to density when designing with ise software. these are the default settings when xa9500xl devices are selected for design. these settings are found on the process properties page for implement design. see the ise online help for details on these properties. 2. use a monotonic, fast ramp power supply to power up xa9500xl . a v cc ramp time of less than 1 ms is required. 3. do not float i/o pins during device operation. floating i/o pins can increase i cc as input buffers will draw 1-2 ma per floating input. in addition, when i/o pins are floated, noise can propagate to the center of the cpld. i/o pins should be appropriately terminated with keeper/bus-hold. unused i/os can also be configured as c gnd (programmable gnd). 4. do not drive i/o pins without v cc /v ccio powered. 5. sink current when driving leds. because all xilinx cplds have n-channel pull-down transistors on outputs, it is required that an led anode is sourced through a resistor externally to v cc . consequently, this will give the brightest solution. 6. avoid external pull-down resistors. always use external pull-up resistors if external termination is required. this is because the xa9500xl automotive cpld, which includes some i/o driving circuits beyond the input and output buffers, may have contention with external pull-down resistors, and, consequently, the i/o will not switch as expected. pins 44 64 100 144 type quad flat pack quad flat pack thin quad flat pack chip scale package code vqg44 vqg64 TQG100 csg144 xa9536xl -15 i,q -- -- -- xa9572xl -15 i,q i,q i,q -- xa95144xl -15 -- -- -- i notes: 1. q = automotive extended temperature (t a = ?40c to +105c). 2. i = automotive industrial temperature (t a = ?40c to +85c). 3. all packages pb-free. xa9572xl -1 5 v q g 44q example: temperature range number of pins pb-free package type device type speed grade device ordering options device speed package temperature xa9536xl -15 15.5 ns pin-to-pin delay vqg44 44-pin quad flat pack (vqfp) i-grade t a = ?40c to +85c xa9572xl vqg64 64-pin quad flat pack (vqfp) q-grade t a = ?40c to +105c with t j maximum = 125c xa95144xl TQG100 100-pin thin quad flat pack (tqfp) csg144 144-pin chip scale package (csp)
xa9500xl automotive cpld product family 4 www.xilinx.com ds108-1 (v1.7) april 3, 2007 product specification r 7. do not drive i/os pins above the v ccio assigned to its i/o bank. a. the current flow can go into v ccio and affect a user voltage regulator. b. it can also increase undesired leakage current associated with the device. c. if done for too long, it can reduce the life of the device. 8. do not rely on the i/o states before the cpld configures. 9. use a voltage regulator which can provide sufficient current during device power up. as a rule of thumb, the regulator needs to provide at least three times the peak current while powering up a cpld in order to guarantee the cpld can configure successfully. 10. ensure external jtag terminations for tms, tck, tdi, tdo comply with ieee 1149.1. all xilinx cplds have internal weak pull-ups of ~50 k on tdi, tms, and tck. 11. attach all cpld v cc and gnd pins in order to have necessary power and ground supplies around the cpld. 12. decouple all v cc and v ccio pins with capacitors of 0.01 f and 0.1 f closest to the pins for each v cc /v ccio -gnd pair. recommendations the following recommendations are for all automotive appli- cations. 1. use strict synchronous design (only one clocking event) if possible. a synchronous system is more robust than an asynchronous one. 2. include jtag stakes on the pcb. jtag stakes can be used to test the part on the pcb. they add benefit in reprogramming part on the pcb, inspecting chip internals with intest, identifying stuck pins, and inspecting programming patterns (if not secured). 3. xa9500xl automotive cplds work with any power sequence, but it is preferable to power the v cci (internal v cc ) before the v ccio for the applications in which any glitches from device i/os are unwanted. 4. do not disregard report file warnings. software identifies potential problems when compiling, so the report file is worth inspecting to see exactly how your design is mapped onto the logic. 5. understand the timing report. this report file provides a speed summary along with warnings. read the timing file (*.tim) carefully. analyze key signal chains to determine limits to given clock(s) based on logic analysis. 6. review fitter report equations. equations can be shown in abel-like format, or can also be displayed in verilog or vhdl formats. the fitter report also includes switch settings that are very informative of other device behaviors. 7. let design software define pinouts if possible. xilinx cpld software works best when it selects the i/o pins and manages resources for users. it can spread signals around and improve pin-locking. if users must define pins, plan resources in advance. 8. perform a post-fit simulation for all speeds to identify any possible problems (such as race conditions) that might occur when fast-speed silicon is used instead of slow-speed silicon. 9. distribute ssos (simultaneously switching outputs) evenly around the cpld to reduce switching noise. 10. terminate high speed outputs to eliminate noise caused by very fast rising/falling edges.
xa9500xl automotive cpld product family ds108-1 (v1.7) april 3, 2007 www.xilinx.com 5 product specification r warranty disclaimer this warranty does not extend to any implementation in an application or environment that is not contained within xilinx specifications. pro ducts are not designed to be fail-safe and are not warranted for use in the deployment of ai rbags. further, products are not warranted for use in applications that affect control of the vehicle unless there is a fail-safe or redundancy feature and also a warning signal to the operator of the vehicle upon failure. use of products in such applications is fully at the risk of customer subject to applicable laws and regulations governing limitations on product liability. revision history the following table shows the revision history for this document. date version revision 05/17/02 1.0 initial xilinx release. 07/17/02 1.1 updated n pe quality and reliability specification. 02/03/03 1.2 added reference to xc9500xl, xc9536xl, and xc9572xl data sheets. 05/21/04 1.3 updated the vq44 column of ta b l e 2 and the component availability table on page 2. 10/18/04 1.4 extensive edits to update family from iq to xa. 09/29/05 1.5 changes to packaging information. 01/12/07 1.6 updated for introduction of individual device data sheets. f system changed to 64.5 mhz. 04/03/07 1.7 add programming temperature range warning on page 1.
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