supertex inc. supertex inc. www.supertex.com hv9408 doc.# dsfp-hv9408 b072213 features ? processed with hvcmos ? technology ? low power level shifting ? shift register speed 8.0mhz ? latched data outputs ? 5.0v cmos compatible inputs ? diode to v pp allows eficient power recovery general descriptionthe hv9408 is a low voltage serial to high voltage parallel converter with push-pull outputs. this device has been designed for use as a driver for ac-electroluminescent displays. it can also be used in any application requiring multiple output, high voltage current sourcing and sinking capabilities such as driving plasma panels, vacuum luorescent, or large matrix lcd displays. this device consists of a 32-bit shift register, 32 latches, and control logic to enable outputs. hv out 1 is connected to the irst stage of the shift register through the output enable logic. data is shifted through the shift register on the low to high transition of the clock. the hv9408 shifts in the counter-clockwise direction when viewed from the top of the package. a data output buffer is provided for cascading devices. this output relects the current status of the last bit of the shift register (32). operation of the shift register is not affected by the le (latch enable) or the oe (output enable) inputs. transfer of data from the shift register to the latch occurs when the le input is high. the data in the latch is retained when le is low. block diagram 32-channel serial to parallel converter with high voltage push-pull outputs output enable latch enable clock 32 bit static shift register 32 latches v pp hv out 1 hv out 2 ?? ? 32 outputs total ?? ? hv out 31 hv out 32 data out data input downloaded from: http:///
2 hv9408 supertex inc. www.supertex.com doc.# dsfp-hv9408 b072213 absolute maximum ratings supply voltage, v dd -0.5v to +7.0v supply voltage, v pp -0.5v to +90v logic input levels -0.5v to v dd +0.5v ground current 1 1.5a continuous total power dissipation 2 1200w operating temperature range -40 to +85 o c storage temperature range -65 to +150 o c parameter value sym parameter min max units recommended operating conditions v dd logic voltage supply 4.5 5.5 v v pp high voltage supply 8.0 80 v v ih input high voltage v dd - 0.5 v dd v v il input low voltage 0 0.5 v f clk clock frequency 0 8.0 mhz t a operating free-air temperature -40 +85 o c notes: 1. duty cycle is limited by the total power dissipated in the package. 2. for operation above 25c ambient derate linearly to maximum operatin temperature at 20mw/c. product marking absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these conditions is not implied. continuous operation of the device at the absolute rating level may affect device reliability. all voltages are referenced to device ground. yy = year sealed ww = week sealed l = lot number a = assembler id c = country of origin* = ?green? packaging *may be part of top marking top marking bottom marking yyww aaa hv9408pj llllllllll ccccccccccc 44-lead plastic leaded chip carrier package may or may not include the following marks: si or part number package options packing HV9408PJ-G 44-lead plcc 27/tube HV9408PJ-G m903 44-lead plcc 500/reel ordering informationmounted on fr-4 board, 25mm x 25mm x 1.57mm typical thermal resistance package ja 44-lead plcc 37 o c/w -g denotes a lead (pb)-free / rohs compliant package pin coniguration 1 44 6 40 44-lead plastic leaded chip carrier (top view) downloaded from: http:///
3 hv9408 supertex inc. www.supertex.com doc.# dsfp-hv9408 b072213 sym parameter min max units conditions electrical characteristics (v pp = 60v, v dd = 5.0v, t a = 25c) dc characteristics ac characteristics sym parameter min max units conditions f clk clock frequency - 8.0 mhz --- t wl or t wh clock width, high or low 62 - ns --- t su setup time before clk rises 25 - ns --- t h hold time after clk rises 10 - ns --- t dlh (data) data output delay after l to h clk - 110 ns cl = 15pf t dhl (data) data output delay after h to l clk - 110 ns cl = 15pf t dle le delay after l to h clk 50 - ns --- t wle width of le pulse 50 - ns --- t sle le setup time before l to h clk 50 - ns --- t on delay from le to hv out , l to h - 500 ns --- t off delay from le to hv out , h to l - 500 ns --- i pp v pp supply current - 100 a hv outputs high to low i ddq i dd supply current (quiescent) - 100 a all inputs = v dd or gnd i dd i dd supply current (operating) - 15 ma v dd = v dd max, f clk = 8.0 mhz v oh (data) shift register output voltage v dd -0.5 - v i o = -100a v ol (data) shift register output voltage - 0.5 v i o = 100a i ih current leakage, any input - 1.0 a input = v dd i il current leakage, any input - -1.0 a input = gnd v oc hv output clamp diode voltage - -1.5 v i oc = -5.0ma v oh hv output when sourcing 52 - v i oh = -20ma, 0 to 70c v ol hv output when sinking - 4.0 v i ol = 5.0ma, 0 to 70c power-up sequence 1. connect ground 2. apply v dd 3. set all inputs (data, clk, enable, etc.) to a known state 4. apply v pp power-down sequence should be the reverse of the above. the v pp should not drop below v dd during operations. downloaded from: http:///
4 hv9408 supertex inc. www.supertex.com doc.# dsfp-hv9408 b072213 input and output equivalent circuits switching waveforms vdd input gnd vpp gnd logic inputs gnd data out logic data output high voltage outputs vdd hv out latch enable hv out w/ s/r low data valid 50% data inpu t c loc k data ou t t su t h t wl t wh 50% 50% t dlh t dhl 50% t wle t dle t sle 50% 50% t on 10% 90% 90% 10% t off v ih v il v ih v il v oh v ol v oh v ol v oh v ol v oh v ol v oh v ol hv out w/ s/r high 50% 50% 50% 50% downloaded from: http:///
5 hv9408 supertex inc. www.supertex.com doc.# dsfp-hv9408 b072213 pin description data input le oe hv output x x l all hv out = low x l h previous latched data h h h h l h h l function tables data input clk data output h h l l x no no change = low to high level transition. pin function description 1 hv out 16 high voltage outputs.high voltage push-pull outputs, which, depending on controlling low voltage data, can drive loads either to a gnd, or to v pp rail levels. 2 hv out 17 3 hv out 18 4 hv out 19 5 hv out 20 6 hv out 21 7 hv out 22 8 hv out 23 9 hv out 24 10 hv out 25 11 hv out 26 12 hv out 27 13 hv out 28 14 hv out 29 15 hv out 30 16 hv out 31 17 hv out 32 18 data out serial data outputdata output for cascading to the data input of the next device. 19 n/c no connect. 20 n/c 21 n/c 22 clk data shift register clock.input are shifted into the shift register on the positive edge of the clock. 23 gnd logic and high voltage ground. 24 vpp high voltage power rail. 25 vdd low voltage logic power rail. downloaded from: http:///
6 hv9408 supertex inc. www.supertex.com doc.# dsfp-hv9408 b072213 pin function description 26 latch enable latch enable input. when le is high, shift register data is transferred into a data latch. when le is low, data is latched, and new data can be clocked into the shift register. 27 data in serial data input.data needs to be present before each rising edge of the clock. 28 output enable output enable input.when oe is low, all hv outputs are forced into a low state, regardless of data in each channel. when oe is high, all hv outputs relect data latched. 29 n/c no connect. 30 hv out 1 high voltage outputs.high voltage push-pull outputs, which, depending on controlling low voltage data, can drive loads either to a gnd, or to v pp rail levels. 31 hv out 2 32 hv out 3 33 hv out 4 34 hv out 5 35 hv out 6 36 hv out 7 37 hv out 8 38 hv out 9 39 hv out 10 40 hv out 11 41 hv out 12 42 hv out 13 43 hv out 14 44 hv out 15 downloaded from: http:///
supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives an adequate ?product liability indemnification insurance agreement.? supertex inc . does not assume responsibility for use of devices described, and limits its liabilit y to the replacement of the devices determined defective due to workmanship. no responsibility is assumed for possible omissions and inaccuracies. circuitry and specifications are subject to change without notice. for the latest product specifications refer to the supertex inc . (website: http//www .supertex.com) ?2013 supertex inc. all rights reserved. unauthorized use or reproduction is prohibited. supertex inc. 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www.supertex.co m 7 hv9408 (the package drawing(s) in this data sheet may not relect the most current speciications. for the latest package outline information go to http://www.supertex.com/packaging.html .) doc.# dsfp-hv9408 b072213 44-lead plcc package outline (pj) .653x.653in body, .180in height (max), .050in pitch symbol a a1 a2 b b1 d d1 e e1 e r dimension (inches) min .165 .090 .062 .013 .026 .685 .650 .685 .650 .050 bsc .025 nom .172 .105 - - - .690 .653 .690 .653 .035 max .180 .120 .083 .021 .036 ? .695 .656 .695 .656 .045 jedec registration ms-018, variation ac, issue a, june, 1993. ? this dimension differs from the jedec drawing. drawings not to scale. supertex doc. #: dspd-44plccpj, version f031111. 1 64 0 44 .150max .048/.042 x 45 o d d1 e1 e top vi ew view b a a2 a1 seating plane .056/.042 x 45 o base plane .020min b vi ew b b1 horizontal side view vertical side vi ew .020max(3 places) r e note 1 (index area) note 2 .075max notes: 1. a pin 1 identiier must be located in the index area indicated. the pin 1 identiier can be: a molded mark/identiier; an embedded metal marker; or a printed indicator. 2. actual shape of this feature may vary. downloaded from: http:///
|
