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[ ak7735 ] 016014707 - e - 00 201 6 / 12 - 1 - 1. g eneral d escription the ak773 5 is a highly integrated digital signal processor, including a 24 - bit stereo adc with mic gain amplifiers, a 24 - bit stereo adc with input selector, two 32 - bit stereo dacs, 2 stereo sampling rate convertors supporting the sampling frequency up to 192khz and dual dsps for aud io/hf process. each dsp has 3072 step/fs (when fs=48khz) parallel processing power. as the ak773 5 is a ram based dsp, it is freely programmable for user requirements, such as acoustic effects and proprietary high performance hands - free func tion. the ak773 5 is available in a 48 - pin lqfp package. 2. f eatures dual dsp: ( dsp1 and dsp2 have the same specification. memory a reas are shared by them ) - word length : 28 - bit ( simple floating point supported ) - instruction cycle : max . 6.8 ns ( 3072 fs at fs=48khz) - multiplier : 24 x 24 48 - bit ( double precision arithmetic available ) - divider : 24 / 24 24 - bit ( floating point normalization function ) - alu: 52 - bit arithmetic operation (with 4bits overflow margin ) - program ram : 4096 - word x 36 - bit - coefficient ram : 6144 - word x 24 - bit - data ram : 4096 - word x 28 - bit - delay ram : 12288 - word x 28 - bit - jx pins (interrupt) - independent power management function for dsp1, dsp2 adc1: 24 - bit stereo adc with mic gain amplifiers - sampling frequency : fs = 8khz ~ 192khz - channel independent analog gain amplifiers (0~18db(2db step), 18~36db(3db s tep)) - differential input or single - ended input - adc characteristics s/n: 10 6 db (fs=48khz , differential input, mic gain=0db ) - channel independent digital volume control (24db adc2: 24 - bit stereo adc with input selector - sampling frequency : fs = 8khz ~ 192khz - analog input selector : differential input x1 or single - ended input x2, - adc characteristics s/n: 10 6 db (fs=48khz , differential input ) - channel independent digital volume (24db ~ - 103db, 0.5db step, mute) - digital hpf for dc offset cancelling - 4 types of digital filter for sound color selection ak 7735 dual dsp with 4chadc + 4chdac + 4chsrc
[ ak7735 ] 016014707 - e - 00 201 6 / 12 - 2 - dac: advanced 32bit dac - 2ch x 2 - sampling frequency : fs = 8khz ~ 192khz - single - ended output - dac characteristics s/n: 108db (fs=48khz) - channel independent digital volume control (12db ~ - 115db, 0.5db step, mute) - 4 types of digital filter for sound color selection src: - 2ch x 2 - fsi = 8khz ~ 192khz, fso = 8khz ~ 192khz (fso/fsi = 0.167 ~ 6.0) digital interfaces - digital input port x 4 ( m ax 32ch , in tdm mode ) - digital output port x 4 ( m ax 32ch , in tdm mode ) - independent lrck/bick port x 3 - data format : msb 32, 24bit / lsb 2 4, 20, 16bit / i 2 s - pcm short / long frame supported - tdm format supported (max : 8ch / 256fs, fs=96khz) pll circuit p interface : spi( max 6 mh z ) / i 2 c( 400khz fast mode, 1mhz fast mode p lus) power supply : analog: avdd: 3.0v ~ 3.6v ( typ . 3.3v) digital: lvdd: 3.0v ~ 3.6v ( typ . 3.3v) (3.3v 1.2v regulator integrated ) i/f vdd33: 3.0v ~ 3.6v ( typ . 3.3v) tvdd: 1.7v ~ 3.6 v ( typ . 3.3v) operating temperature range : ak7735vq: ta = - 40 ~ 85 ? ? package : 48 - pin lqfp (7mm x 7mm, 0.5mm pitch)
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 3 - 3. table of contents 1. general description ................................ ................................ ................................ .......................... 1 2. features ................................ ................................ ................................ ................................ ............ 1 3. table of conten ts ................................ ................................ ................................ .............................. 3 4. block diagrams ................................ ................................ ................................ ................................ . 5 block diag ram ................................ ................................ ................................ ................................ ... 5 dsp block diagram ................................ ................................ ................................ ........................... 6 5. pin configurations and functions ................................ ................................ ................................ ..... 7 pin configurations ................................ ................................ ................................ ............................. 7 pin functions ................................ ................................ ................................ ................................ ..... 8 handling of unused pins ................................ ................................ ................................ .................. 11 internal pulled - down pins status ................................ ................................ ................................ ..... 11 power - down status of output pins ................................ ................................ ................................ . 12 6. absolute maximum ratings ................................ ................................ ................................ ............ 13 7. recommended operating conditions ................................ ................................ ............................ 13 8. electrical characteristics ................................ ................................ ................................ ................. 14 analog characteristics ................................ ................................ ................................ .................... 14 po wer consumption ................................ ................................ ................................ ........................ 19 9. d igital filter characteristics ................................ ................................ ................................ ............ 20 adc block ................................ ................................ ................................ ................................ ....... 20 dac block ................................ ................................ ................................ ................................ ....... 24 src block ................................ ................................ ................................ ................................ ....... 28 10. dc characteristics ................................ ................................ ................................ .......................... 30 11. sw itching characateristics ................................ ................................ ................................ .............. 31 system clock ................................ ................................ ................................ ................................ .. 31 power down ................................ ................................ ................................ ................................ .... 31 serial data interface (sdin1 ~ sdin4, sdout1 ~ sdout4) ................................ ....................... 32 spi interface ................................ ................................ ................................ ................................ .... 35 i 2 c interface ................................ ................................ ................................ ................................ ..... 37 12. functional descriptions ................................ ................................ ................................ ................... 38 system clock ................................ ................................ ................................ ................................ .. 38 audio hub ................................ ................................ ................................ ................................ ....... 40 audio data path setting ................................ ................................ ................................ .................. 46 power - up sequence ................................ ................................ ................................ ........................ 64 vreg ( internal circuit drive regulator ) ................................ ................................ ......................... 65 power - down and reset ................................ ................................ ................................ ................... 66 ram clear ................................ ................................ ................................ ................................ ....... 68 sto pin output status ................................ ................................ ................................ .................... 69 p interface setting and pin statuses ................................ ................................ ............................ 70 spi interface ................................ ................................ ................................ ................................ .... 71 i 2 c interface ................................ ................................ ................................ ................................ ..... 85 simple write error check ................................ ................................ ................................ ................ 90 dsp block ................................ ................................ ................................ ................................ ....... 91 analog input block ................................ ................................ ................................ .......................... 94 adc block ................................ ................................ ................................ ................................ ....... 97 dac block ................................ ................................ ................................ ................................ ..... 102 src block ................................ ................................ ................................ ................................ ..... 107 register map ................................ ................................ ................................ ................................ .. 113 register definitions ................................ ................................ ................................ ........................ 116 13. recommended external circuits ................................ ................................ ................................ .. 135 connection diagram ................................ ................................ ................................ ..................... 135
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 4 - peripheral circuit ................................ ................................ ................................ ........................... 137 14. pa ckage ................................ ................................ ................................ ................................ ........ 139 outline dimensions ................................ ................................ ................................ ....................... 139 material and lead finish ................................ ................................ ................................ ............... 139 marking ................................ ................................ ................................ ................................ .......... 140 15. ordering guide ................................ ................................ ................................ .............................. 141 16. revision history ................................ ................................ ................................ ............................ 141 impo rtant notice ................................ ................................ ................................ ........................ 142
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 5 - 4. block diagram s block diagram figure 1 . block diagram
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 6 - dsp block diagram figure 2 . dsp block diagram note * 1 . coefficient ram, data ram, delay ram, program ram areas are shared by dsp1 and dsp2 and the sizes are configurable by control registers. tmp 8 28bit sdout3 cp0, cp1 dp0, dp1 d ata ram 4096 w x 2 8 bit max mpx 2 4 mpx2 4 x y multiply 2 4 2 4 48 bit micon i/f control program ram 4096 w 36 bit max dec pc s tack : 8 l evel (max) mul dbus shift a b alu 52 bit o verflow margin: 4 bit dr0 ? 3 over flow data generator division 24 ? 24 2 4 peak detector se rial i/f cbus ( 2 4 bit) dbus(2 8 bit) 4 8 bit 28 bit 48 bit 52 bit 52 bit 12288 w x 2 8 bit max p tmp (lifo) 6 2 8 bit d l p0, d l p1 52 - bit tmp 12 28 bit ofr eg 64 w x 1 4 bit d e lay ram coefficient ram 6144 2 4 bit max pointer 2048w unit 2048w unit 4096w unit 2048w unit 2 8bit x fifo16 dtmp ( connection between dsp 1/2 ) 2 x 24 bit din4 2 x 24 bit din3 2 x 24 bit din2 2 x 24 bit din1 2 x 32bit dout4 2 x 32bit dout3 2 x 32bit dout2 2 x 32bit dout1 2 x 24 bit din 6 2 x 24 bit din 5 2 x 32bit dout 6 2 x 32bit dout 5
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 7 - 5. pin configurations and functions pin configurations inn2 ain2lp/ain3l ain2ln/ain4l ain2rp/ain3r ain2rn/ain4r lvdd dvss3 avdrv pdn si/i2cfil sclk/scl so/sda - - 36 35 34 33 32 31 30 29 28 27 26 25 ain1r/inp2 37 24 csn inn1 38 lvdd 23 sto/rdy/sdout2 ain1l/inp1 39 22 - dvss2 mpref 40 tvdd 21 - tvdd mpwr 41 20 sdout1/rdy avdd - 42 avdd 19 bick1 avss - 43 18 lrck1 vcom 44 17 sdin1 vrefh 45 16 bick2/jx2 vrefl 46 15 lrck2/jx1 aout1r 47 vdd33 14 sdin2/jx0 aout1l 48 13 xto 1 2 3 4 5 6 7 8 9 10 11 12 - - aout2r aout2l testi lrck3 sdout4/gpo2 bick3 sdout3/clko/gpo1 sdin3/jx3 sdin4 dvss1 vdd33 xti ak7735 top view input output in/out - power
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 8 - pin functions no. pin name i/o function supply power 1 aout2r o dac2 rch analog output pin this pin outputs hi z during hi z during
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 9 - no. pin name i/o function supply power 23 sto o status output pin this pin outputs pin 2 c mode i 2 c i/f chip address pin this pin must be pulled up or pulled down. 25 so o serial data output pin for spi i/f this pin outputs 2 c i/f this pin outputs 2 c i/f 27 si i serial data input pin for spi i/f tvdd i2cfil i i 2 c i/f mode select input pin i2cfil = l: fast mode (400khz) = h: fast mode plus (1mhz) ( pdn pin should be held l when power is supplied.
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 10 - no. pin name i/o function supply power 32 ain2rn i adc2 rch inverted differential input 2 pin avdd ain4r i adc2 rch single - ended input 4 pin 33 ain2rp i adc2 rch non - inverted differential input 2 pin avdd ain3r i adc2 rch single - ended input 3 pin 34 ain2ln i adc2 lch inverted differential input 2 pin avdd ain4l i adc2 lch single - ended input 4 pin 35 ain2lp i adc2 lch non - inverted differential input 2 pin avdd ain3l i adc2 lch single - ended input 3 pin 36 inn2 i adc1 rch inverted differential input 2 pin avdd 37 ain1r i adc1 rch single - ended input 1 pin avdd inp2 i adc1 rch non - inverted differential input 2 pin 38 inn1 i adc1 lch inverted differential input 1 pin avdd 39 ain1l i adc1 lch single - ended input 1 pin avdd inp1 i adc1 lch non - inverted differential input 1 pin 40 mpref o ripple filter pin for microphone power supply connect a 1 uf ceramic capacitor between this pin and avss. do not connect this pin to an external circuit. avdd 41 mpwr o power supply output pin for microphone this pin outputs hi z durin durin hi z durin hi z durin
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 11 - handling of unused pins unused i/o pins must be connected appropriately. classification pin name setting analog mpref, mpwr, ain1l/inp1, inn1, ain1r/inp2, inn2, ain2lp/ain3l, ain2ln/ain4l, ain2rp/ain3r, ain2rn/ain4r, aout1l, aout1r, aout2l, aout2r open digital xti, xto, sdout1/rdy, sto/rdy/sdout2, sdout3/clko/gpo1, sdout4/gpo2 open sdin4, sdin3/jx3, sdin2/jx0, sdin1, lrck1, bick1, lrck2/jx1, bick2/jx2, lrck3, bick3 , testi connect to dvss1 / dvss2 table 1 . handling of unused pins i nternal pulled - down pin s status no. pin name power down status pdn pin = l pdn pin = h pdn pin = h k k k k (46 k) k (46 k) k (46 k) k (46 k) k (46 k) k (46 k) k k k k
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 12 - power - down status of output pins no pin name i/o power - down s tatus no pin name i/o power - down status 44 vcom o l l hi z hi z hi z l hi z l hi z l hi z l hi z l
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 13 - 6. absolute maximum ratings (avss=dvss1=dvss2=dvss3=0v * 3 ) parameter symbol min. max. unit power supplies analog digital1(core) digital2(i/f) digital3(i/f) difference (avss, dvss1, dvss2, dvss3) * 3 avdd lvdd tvdd vdd33 gnd ? ? ? 7. recommended operating conditions (avss=dvss1=dvss2=dvss3=0v * 3 ) parameter symbol min. typ. max. unit power supplies analog digital1(core) digital2(i/f) digital3(i/f) difference1 difference2 difference3 difference4 avdd lvdd tvdd vdd33 avdd C C C C be held l when power is supplied. the pdn pin is allowed to be h after all power supplies are applied and settled. * 8 . do not turn off the power supply of the ak773 5 with the power supply of the peripheral device turned on. when using the i 2 c interface, pull - up resistors of sda and scl pins should be connected to tvdd or less voltage. warning: akm assumes no responsibility for the usage beyond the conditions in the datasheet.
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 14 - 8. electrical characteristics analog characteristics 1. mic amp (ta= 2 5 ? c ; avdd=lvdd=tvdd=vdd33=3.3v; avss=dvss1=dvss2=dvss3=0v ; adc1vl/r bit s =0) mic amp parameter min. typ. max. unit input impedance 14 20 26 k 2. mic bias output (ta= 2 5 ? c ; avdd=lvdd=tvdd=vdd33=3.3v; avss=dvss1=dvss2=dvss3=0v ; measurement frequency =20hz~20khz) mic bias parameter min. typ. max. unit output voltage * 9 2.3 2.5 2.7 v load resistance 2 k
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 15 - 3. mic amp + adc1 (ta= 2 5 ? c ; avdd=lvdd=tvdd=vdd33=3.3v; avss=dvss1=dvss2=dvss3=0v; signal frequency =1khz; 24bit data; bick=64fs; @ fs=48khz , measuremen t frequency bw=20hz ~ 20khz; @ fs=96khz ,192khz , bw=20hz ~ 40khz; adc1vl/r bit s =0; mgnl/r[3:0] bits=0h (0db) ; differential input, unless otherwise specified. ) notes * 10 . inp1, inn1, inp2 and inn2 pins * 11 . ain1l and ain1r pins * 12 . inter - channel isolation with - 1dbfs signal input. * 13 . adc1vl/r bit s = 0, mgnl/r[3:0] bits = 0h (0db). input full - scale voltage is proportional to avdd (0.7 x avdd). * 14 . adc1vl/r bit s = 0, mgnl/r[3:0] bits = 9h (+18db). input full - scale voltage is proportional to avdd (0.088 x avdd). * 15 . adc1vl/r bit s = 1, mgnl/r[3:0] bits = 0h (0db). input full - scale voltage is proportional to avdd (0. 86 x avdd). * 16 . common mode rejection ratio when inputting 1khz, 100mvpp sine wave to both differential inputs. the value refers to the case when input a 1khz , 100mvpp sine wave as differential input. mic amp + adc1 parameter min. typ. max. unit resolution 24 b it input full scale voltage * 10 differential input * 13 2.1 2.3 2.5 vpp differential input * 14 0.264 0.290 0.315 differential input * 15 2.55 2.83 3.11 input full scale voltage * 11 single - ended input * 13 2.1 2.3 2.5 vpp single - ended input * 14 0.264 0.290 0.315 single - ended input * 15 2.55 2.83 3.11 s/(n+d) ( - 1dbfs) fs=48khz * 13 85 95 db fs=48khz * 14 87 fs=96khz * 13 92 fs=96khz * 14 84 fs=192khz * 13 92 fs=192khz * 14 84 dynamic range ( - 60dbfs) fs=48khz (a - weighted) * 13 98 106 db fs=48khz (a - weighted) * 14 95 fs=96khz * 13 99 fs=96khz * 14 89 fs=192khz * 13 99 fs=192khz * 14 89 s/n fs=48khz (a - weighted) * 13 98 106 db fs=48khz (a - weighted) * 14 95 fs=96khz * 13 99 fs=96khz * 14 89 fs=192khz * 13 99 fs=192khz * 14 89 inter - channel isolation * 12 90 105 db channel gain mismatch 0.0 0.3 db cmrr * 16 60 80 db
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 16 - 4. adc2 (ta=25 ? c ; avdd=lvdd=tvdd=vdd33=3.3v; avss=dvss1=dvss2=dvss3=0v; signal frequency =1khz; 24bit data; bick=64fs; @ fs=48khz, measurement frequency bw=20hz ~ 20khz; @ fs=96khz,192khz, bw=20hz ~ 40khz; adc2vl/r bits=0; differential input , unless otherwise specified. ) notes * 17 . ain2lp, ain2ln, ain2rp and ain2rn pins * 18 . ain3l, ain3r, ain4l and ain4r pins * 19 . adc2vl/r bit s = 0 . input full - scale voltage is propotional to avdd (0.7 x avdd). * 20 . adc2vl/r bit s = 1 . input full - scale voltage is propotional to avdd (0. 86 x avdd). adc2 parameter min. typ. max. unit resolution 24 bit input impedance 14 20 26 k input full scale voltage * 17 differential input * 19 2.1 2.3 2.5 vpp differential input * 20 2.55 2.83 3.11 input full scale voltage * 18 single - ended input * 19 2.1 2.3 2.5 vpp single - ended input * 20 2.55 2.83 3.11 s/(n+d) ( - 1dbfs) fs=48khz 85 95 db fs=96khz 92 fs=192khz 92 dynamic range ( - 60dbfs) fs=48khz (a - weighted) 98 106 db fs=96khz 99 fs=192khz 99 s/n fs=48khz (a - weighted) 98 106 db fs=96khz 99 fs=192khz 99 inter - channel isolation * 12 90 105 db channel gain mismatch 0.0 0.3 db cmrr * 16 60 80 db
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 1 7 - 5. dac (ta= 2 5 ? c ; avdd=lvdd=tvdd=vdd33=3.3v; avss=dvss1=dvss2=dvss3=0v; signal frequency =1khz; 32bit data; bick=64fs; @ fs=48khz , measurement frequency bw=20hz ~ 20khz; @ fs=96khz,192khz , measurement frequency bw=20hz ~ 40khz) dac1 dac2 parameter min. typ. max. unit resolution 32 bit output voltage * 21 2.55 2.83 3.11 vpp s/(n+d) (0dbfs) fs=48khz 80 91 db fs=96khz 89 fs=192khz 89 dynamic range ( - 60dbfs) fs=48khz (a - weighted) 100 108 db fs=96khz 101 fs=192khz 101 s/n fs=48khz (a - weighted) 100 108 db fs=96khz 101 fs=192khz 101 inter - channel isolation (fin=1khz) * 22 90 110 db channel gain mismatch 0.0 0.7 db load resistance * 23 10 k
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 18 - 6. src (ta= 2 5 ? c ; avdd=lvdd=tvdd=vdd33=3.3v; avss=dvss1=dvss2=dvss3=0v; signal frequency =1khz; 24bit data; measurement frequency bw=20hz ~ fso/2) src parameter symbol min. typ. max. unit resolution 24 bit input sample rate fsi 8 192 khz output sample rate fso 8 192 khz thd+n (input=1khz, 0dbfs) audio mode (srcfaud bit = 1 0) 0, srcfec bit 0) 1, srcfec bit 0) 0, srcfec bit 0)
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 19 - power consumption (t a =25 ? c ; avdd=lvdd=vdd33=3.0~3.6v( typ =3.3v, max =3.6v); tvdd=1.7~3.6v( typ =3.3v, max =3.6v); avss=dvss1=dvss2=dvss3=0v; fs=192khz; bick=64fs; master mode; sdout1~4/lrck1~3/bick1~3=output; c l =20pf) parameter symbol min. typ. max. unit power - up * 24 (pdn pin = h) = l
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 20 - 9. d igital filter characteristics adc block (ta= - 40 ~ 85 ? c ; avdd=3.0~3.6v; lvdd=3.0~3.6v; tvdd=1.7~3.6v; vdd33=3.0~3.6v; avss=dvss1=dvss2 =dvss3 =0v) 1. sharp roll - off filter (adsd bit = 0, adsl bit = 0) fs=48khz parameter symbol min. typ. max. unit sharp roll - off passband * 25 0db ~ - 0.06db pb 0 22.1 khz - 3.0db pb 23.7 khz stopband * 25 sb 27.8 khz stopband attenuation sa 85 .0 db group delay distortion : 0hz~20khz ? ? ?
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 21 - 2. slow roll - off filter (adsd bit = 0, adsl bit = 1) fs=48khz parameter symbol min. typ. max. unit slow roll - off passband * 25 0db ~ - 0.074db pb 0 12.5 khz - 3.0db pb 19.2 khz stopband * 25 sb 36.5 khz stopband attenuation sa 85 .0 db group delay distortion : 0hz~20khz ? ? ?
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 22 - 3. short delay sharp roll - off filter (adsd bit = 1, adsl bit = 0) fs=48khz parameter symbol min. typ. max. unit short delay sharp roll - off passband * 25 0db ~ - 0.06db pb 0 22.1 khz - 3.0db pb 23.7 khz stopband * 25 sb 27.8 khz stopband attenuation sa 85 .0 db group delay distortion : 0hz~20khz ? ? ?
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 23 - 4. short delay slow roll - off filter (adsd bit = 1, adsl bit = 1) fs=48khz parameter symbol min. typ. max. unit short delay slow roll - off passband * 25 0db ~ - 0.074db pb 0 12.5 khz - 3.0db pb 19.2 khz stopband * 25 sb 36.5 khz stopband attenuation sa 85 .0 db group delay distortion : 0hz~20khz ? ? ? a reference value of each gain amplitude is the maximum value of frequency response. * 26 . d elay time caused by the digital filter calculation. this time is measured from an analog signal input until 24 - bit data of both channels are set into the output register. it includes group delay by hpf .
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 24 - dac block ( ta= - 40 ~ 85 ? c ; avdd=3.0~3.6v; lvdd=3.0~3.6v; tvdd=1.7~3.6v; vdd33=3.0~3.6v; avss=dvss1=dvss2=dvss3=0v) 1. sharp roll - off filter (dasd bit = 0, dasl bit = 0) fs= 48 khz parameter symbol min. typ. max. unit sharp roll - off passband * 27 ? ? ? ? ? ? ? ? ? pb = 0.4535 ? fs , sb = 0.546 ? fs * 28 . pas s - band gain amplitude of double over sampling filter at the first step of interpolator . * 29 . d elay time caused by the digital filter calculation. this time is measured from setting of the 16/20/24/32 - bit impulse data to the input registers to output of the analog peak signal. * 30 . the output level with a 1khz, 0db sine wave input is defined as 0db. * 31 . band width of sto pband attenuation ranges from 0 hz to fs.
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 25 - 2. slow roll - off filter (dasd bit = 0, dasl bit = 1) fs= 48 khz parameter symbol min. typ. max. unit slow roll - off passband * 32 ? ? ? ? ? ? ? ? ? pb = 0.185 ? fs , sb = 0.888 ? fs
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 26 - 3. short delay sharp roll - off filter (dasd bit = 1, dasl bit = 0) fs= 48 khz parameter symbol min. typ. max. unit short delay sharp roll - off passband * 27 ? ? ? ? ? ? ? ? ?
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 27 - 4. short delay slow roll - off filter (dasd bit = 1, dasl bit = 1) fs= 48 khz parameter symbol min. typ. max. unit short delay slow roll - off passband * 33 ? ? ? ? ? ? ? ? ? pb = 0.252 ? fs , sb = 0.864 ? fs
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 28 - src block ( ta= - 40 ~ 85 ? c ; avdd=3.0~3.6v; lvdd=3.0~3.6v; tvdd=1.7~3.6v; vdd33=3.0~3.6v; avss=dvss1=dvss2=dvss3=0v ) 1. audio mode (srcfaud bit = 1, srcfec bit = 0) note * 34 . this val u e is src block only. it is the time from a rising edge of input lrck after data is input to a rising edge of output lrck just before the data is output when there is no phase difference between input and output lrck . parameter symbol min. typ. max. unit passband - 0.01db 0.980 fso/fsi 6.000 pb 0 0.4583fsi khz - 0.01db 0.900 fso/fsi < 0.990 pb 0 0.4167fsi khz - 0.01db 0.533 fso/fsi < 0.909 pb 0 0.2182fsi khz - 0.01db 0.490 fso/fsi < 0.539 pb 0 0.2177fsi khz - 0.01db 0.450 fso/fsi < 0.495 pb 0 0.1948fsi khz - 0.01db 0.225 fso/fsi < 0.455 pb 0 0.1312fsi khz - 0.50db 0.167 fso/fsi < 0.227 pb 0 0.0658fsi khz stopband 0.980 fso/fsi 6.000 sb 0.5417fsi khz 0.900 fso/fsi < 0.990 sb 0.5021fsi khz 0.533 fso/fsi < 0.909 sb 0.2974fsi khz 0.490 fso/fsi < 0.539 sb 0.2812fsi khz 0.450 fso/fsi < 0.495 sb 0.2604fsi khz 0.225 fso/fsi < 0.455 sb 0.1802fsi khz 0.167 fso/fsi < 0.227 sb 0.0970fsi khz passband ripple 0.225 fso/fsi 6.000 pr 0.01 db 0.167 fso/fsi < 0.227 pr 0.50 db stopband attenuation 0.450 fso/fsi 6.000 sa 95.2 db 0.167 fso/fsi < 0.455 sa 85.0 db group delay * 34 (ts=1/fs) gd 6 7 ( 55 /fsi+ 12 /fso) ts
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 29 - 2. voice mode (srcfaud bit = 0, srcfec bit = 0) 3. echo canceller mode (srcfec bit = 1) parameter symb ol min. typ. max. unit passband - 0.01db 0.980 passband - 0.01db 0.167
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 30 - 10. dc characteristics ( ta= - 40 ~ 85 ? c ; avdd=3.0~3.6v; lvdd=3.0~3.6v; tvdd=1.7~3.6v; vdd33=3.0~3.6v; avss=dvss1=dvss2=dvss3=0v) parameter symbol min. typ. max. unit high - level input voltage 1 * 35 vih1 75 %tvdd v low - level input voltage 1 * 35 vil1 2 5 %tvdd v high - level input voltage 2 * 36 vih2 75 %vdd33 v low - level input voltage 2 * 36 vil2 2 5 %vdd33 v scl, sda high - level input voltage vih3 70%tvdd v scl, sda low - level input voltage vil3 30%tvdd v high - level output voltage iout= - 100 ? ? ? ? 2.0v (iout=3ma) vol3 0.4 v tvdd < 2.0v (iout=3ma) vol3 20%tvdd v fast mode plus tvdd 2.0v (iout=20ma) vol3 0.4 v tvdd < 2.0v (iout=3ma) vol3 20%tvdd v input leak current * 39 iin 10 ? ? ? ? ? l ) , the pull down resistors of lrck1, bick1, lrck2/jx1, bick2/jx2, lrck3 and bick3 pins is 50 k (typ. @3.3v) . * 41 . w hen the ak 7735 is powered up (pdn pin = h ) , the pull down resistors of lrck1, bick1, lrck2/jx1, bick2/jx2, lrck3 and bick3 pin s is 4 6 k (typ. @3.3v) . * 42 . leak current in case of inputting 3.3v when lvdd=tvdd=vdd33=3.3v .
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 31 - 11. switching characateristics system clock ( ta= - 40 ~ 85 ? c ; avdd=3.0~3.6v; lvdd=3.0~3.6v; tvdd=1.7~3.6v; vdd33 =3.0~3.6v; avss=dvss1=dvss2 =dvss3 =0v; c l =20pf) parameter symbol min. typ. max. unit xti input timing a) xtal oscillator clko output timing output frequency fclko 2.048 24.576 mhz duty cycle dclko 50 % lrck/bick input timing (slave mode) lrck input timing frequency fs 8 192 khz bick input timing frequency * 43 fbclk 0.256 24.576 mhz pulse width low tbclkl 0.4 / fbclk ns pulse width high tbclkh 0.4 / fbclk ns lrck/bick output timing (pll master mode) lrck output timing frequency fs 8 192 khz pulse width high pcm mode except pcm mode tlrckh tlrckh 1/fbclk 50 ns % bick output timing frequency * 43 fbclk 0.256 24.576 mhz duty dbclk 50 % note * 43 . required to meet the following expression: fbc l k 2 x fs x ( input/output data length ) . power down ( ta= - 40 ~ 85 ? c ; avdd=3.0~3.6v; lvdd=3.0~3.6v; tvdd=1.7~3.6v; vdd33 =3.0~3.6v; avss=dvss1=dvss2 =dvss3 =0v) parameter symbol min. typ. max. unit pdn pulse width * 44 trst 600 ns note * 44 . the pdn pin must be l when power up the ak7735. figure 3 . reset timing vil 1 trst pdn
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 32 - serial data interface (sdin1 ~ sdin4, sdout1 ~ sdout4) ( ta= - 40 ~ 85 ? c ; avdd=3.0~3.6v; lvdd=3.0~3.6v; tvdd=1.7~3.6v; vdd33 =3.0~3.6v; avss=dvss1=dvss2 =dvss3 =0v; c l =20pf) parameter symbol min. typ. max. unit slave mode delay time from bick bick delay time from bick to serial data output master mode bick frequency fbclk 32, 48, 64, 128, 256 fs bick duty cycle 50 % delay time from bick when the bick polarity is inverted by setting bckpx bit = 1 . * 46 . it is measured from bick when the bick polarity is inverted by setting bckpx bit = 1 . * 47 . set sdophx bit to 1 and the data from sdoutx pin is output based on bick when bick speed is more than 12.288mhz such as when using tdm256 mode with 96khz sampling frequency or tdm128 mode with 192khz sampling frequency in slave mode. sdophx bit must be set to 0 in mas ter mode.
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 33 - 1. slave mode figure 4 . serial interface input timing in slave mode figure 5 . serial interface output timing in slave mode (sdophx bit = 0 ) figure 6 . serial interface output timing in slave mode (sdophx bit = 1 ) tbsids tblrd tlrbd d vih d vil d tbsidh sdin 1 ~ 4 lrck(i) bick(i) vih d vil d vih d vil d vih lrck (i) bick (i) vil sdout 1~ 4 50% t vdd tbsod 1 d vih vil 50% vdd33 tblrd tlrbd d tbsod1 d vih lrck (i) bick (i) vil sdout 1~ 4 50% t vdd tbsod 2 d vih vil 50% vdd33 tblrd tlrbd d tbsod 2 d
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 34 - 2. master mode figure 7 . serial interface input timing in master mode figure 8 . serial interface output timing in master mode (sdophx bit = 0) tbsids tmbl tmbl d lrck (o) bick(o) vih d vil tbsidh sdin1~ 4 50%tvdd 50% vdd33 50%tvdd 50% vdd33 tbsod d lrck (o) bi ck (o) sdout 1~4 50%tvdd 50% vdd33 50%tvdd 50% vdd33 5 0%tvdd 50% vdd33 tbsod d
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 35 - spi interface ( ta= - 40 ~ 85 ? c ; avdd=3.0~3.6v; lvdd=3.0~3.6v; tvdd=1.7~3.6v; vdd33 =3.0~3.6v; avss=dvss1=dvss2 =dvss3 =0v; c l =20pf) 1. spi low speed mode parameter symbol min. typ. max. unit p interface signal sclk frequency * 49 fsclk 3.0 mhz sclk low - level width tsclkl 160 ns sclk high - level width tsclkh 160 ns microcontroller ak7735 csn high - level width twrqh 300 ns from csn to pdn trst 360 ns from pdn to csn tirrq 1 ms from csn to sclk twsc 300 ns from sclk to csn tscw 480 ns si latch setup time tsis 120 ns si latch hold time tsih 120 ns ak7735 microcontroller delay time from sclk to so output tsos 120 ns so output hold time from sclk * 48 tsoh 120 ns 2. spi high speed mode parameter symbol min. typ. max. unit p interface signal sclk frequency * 49 fsclk 6 mhz sclk low - level width tsclkl 72 ns sclk high - level width tsclkh 72 ns microcontroller ak7735 csn high - level width twrqh 150 ns from csn to pdn trst 180 ns from pdn to csn tirrq 1 ms from csn to sclk twsc 150 ns from sclk to csn tscw 240 ns si latch setup time tsis 60 ns si latch hold time tsih 60 ns ak7735 microcontroller delay time from sclk to so output tsos 60 ns so output hold time from sclk * 48 tsoh 60 ns notes * 48 . except when writ ing the 24 th bit (8 bits command + 16 bits address) of the command code . this will be the 8th bit (8 bits command) with write preparation data read command (24h, 25h, 26h and 27h) . * 49 . dummy command writing for switch ing to spi interface from i 2 c interface and control register access can always be made in spi high speed mode (max. 6mhz) . d sp ram area can be accessed in spi low speed mode (max. 3mhz) in clock reset state (ckresetn bit = 0 ) and can also be accessed in spi high speed mode (max. 6mhz) when pll is locked (ckresetn bit = 1 and pll is locked). i t is necessary to set dlrdy bit to 1 when accessing to the dsp ram area while pll is unlocked ( figure 47 ).
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 36 - figure 9 . spi interface timing 1 figure 10 . spi interface timing 2 (microcontroller ak773 5) figure 11 . spi interface timing 3 ( ak773 5 microcontroller) tsclkh tsclkl 1/fsclk 1/fsclk sclk vih 1 vil 1 vih 1 vil 1 vih 1 vil 1 trst pd n csn tirrq twrqh tsis tsih tscw tscw twsc tscw cs n si vih 1 vil 1 vih 1 twsc sclk vil 1 vih 1 vil 1 tsos tsoh sclk vil 1 vih 1 so 50%tvdd
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 37 - i 2 c interface ( ta= - 40 ~ 85 ? c ; avdd=3.0~3.6v; lvdd=3.0~3.6v; tvdd=1.7~3.6v; vdd33 =3.0~3.6v; avss=dvss1=dvss2 =dvss3 =0v) 1. i 2 c: fast mode parameter symbol min. typ. max. unit i 2 c timing scl clock frequency fscl - - 400 khz bus free time between transmissions tbuf 1.3 - - ? s start condition hold time (prior to first clock pulse) thd:sta 0.6 - - ? s clock low time tlow 1.3 - - ? s clock high time thigh 0.6 - - ? s setup time for repeated start condition tsu:sta 0.6 - - ? s sda hold time from scl falling thd:dat 0 - - ? s sda setup time from scl rising tsu:dat 0.1 - - ? s rise time of both sda and scl lines tr - - 0.3 ? s fall time of both sda and scl lines tf - - 0.3 ? s setup time for stop condition tsu:sto 0.6 - - ? s pulse width of spike noise suppressed by input filter tsp 0 - 50 ns capacitive load on bus cb - - 400 pf 2. i 2 c: fast mode plus parameter symbol min. typ. max. unit i 2 c timing scl clock frequency fscl - - 1 mhz bus free time between transmissions tbuf 0.5 - - ? s start condition hold time (prior to first clock pulse) thd:sta 0.26 - - ? s clock low time tlow 0.5 - - ? s clock high time thigh 0.26 - - ? s setup time for repeated start condition tsu:sta 0.26 - - ? s sda hold time from scl falling thd:dat 0 - - ? s sda setup time from scl rising tsu:dat 0.05 - - ? s rise time of both sda and scl lines tr - - 0.12 ? s fall time of both sda and scl lines tf - - 0.12 ? s setup time for stop condition tsu:sto 0.26 - - ? s pulse width of spike noise suppressed by input filter tsp 0 - 50 ns capacitive load on bus cb - - 550 pf figure 12 . i 2 c interface timing thigh scl sda vih 3 tlow tbuf thd:sta t r tf thd:dat tsu:dat tsu:sta stop start start stop tsu:sto vil 3 vih 3 vil 3 tsp
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 38 - 12. functional descriptions system clock 1. pll mode the ak773 5 has a pll circuit to generate an internal operation clock. an input pin for the pll referen ce clock is selected by refsel[1 :0] bits. refmode[4:0] bits set the frequency of the reference clock. a reference clock input pin and the reference clock frequency must be changed during clock reset (ckreset n bit = 0 ) . mode refsel[1:0] bits reference clock input pin use of crystal oscillator 0 00 xti available (default) 1 01 bick1 n/a 2 10 bick2 n/a 3 11 bick3 n/a table 4 . pll reference clock input pin select mode refmode[4:0] bits input frequency 48khz base 44.1khz base 0 00000 256khz 235.2khz (default) 1 00001 384khz 352.8khz 2 00010 512khz 470.4khz 3 00011 768khz 705.6khz 4 00100 1.024mhz 940.8khz 5 00101 1.152mhz 1.0584mhz 6 00110 1.536mhz 1.4112mhz 7 00111 2.048mhz 1.8816mhz 8 01000 2.304mhz 2.1168mhz 9 01001 3.072mhz 2.8224mhz 10 01010 4.096mhz 3.7632mhz 11 01011 4.608mhz 4.2336mhz 12 01100 6.144mhz 5.6448mhz 13 01101 8.192mhz 7.5264mhz 14 01110 9.216mhz 8.4672mhz 15 01111 12.288mhz 11.2896mhz ( xtal available xtal available
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 39 - 1 - 1. xti input when using a crystal oscillator, connect it between xti pin and xto pin. only 11.2896mhz, 12.288mhz, 16.9344mhz and 18.432mhz c rystal oscillator s are available . when using an external clock, t he external clock must be input to the xti pin and the xto pin must be open. the xti pin should also be open when not using xti input . figure 13 . using crystal oscillator figure 14 . using external system clock 1 - 2. bick input a stable bick of single frequency is required when using clock input from bickx (x=1~ 3 ) pin as reference clock. ak773 5 ak77 3 5 external clock xto xti xto xti external clock
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 40 - audio hub 1. audio hub audio hub provides simultaneous data trans mitting and flexible path configuration for various audio sources by s etting sample rate converters, i nput/ o utput port s that support tdm mode and registers. therefore the ak7735 is able to support various use cases of audio systems. 2. definition of clock sync domain the ak 7735 has four c lock s ync d omain s ( figure 15 ). reference clock s ( lrcksdx, bicksdx, x=1~ 4 ) are output according to each register settings . the internal audio data and input/output data of the ak 7735 mus t be synchronized with one of thes e four cloc k sync domains. when msnx bit =0, clocks from input pins (lrckx pin/bickx pin) are selected as reference clock of clock sync domain 1~3 . when msnx bit = 1, internal dividing clocks (mlrck x /mbick x ) are selected as reference clock of clock sync domain 1~3. for clock sync domain 4, internal dividing clocks (mbick4/mlrck4) are selected as reference clock ( bicksd 4 /lrcksd 4) ( table 7 ). clock sync domain msnx bit reference c l ock sync domain x (x=1 ~ 3) msnx = 0 clocks from input pin s (bickx pin/lrckx pin) msnx = 1 internal dividing clock s (mbickx/mlrckx) reference clock is generated internally by cksx [2:0], bdvx[9:0] and sdvx[2:0] bits settings. sync domain 4 - internal dividing clock s (mbick 4 /mlrck 4 ) reference clock is generated internally by cks4[2:0], bdv4[9:0] and sdv4[2:0] bits settings. table 7 . reference clock of clock sync domain figure 15 . definition of clock sync domain pllmclk div bdv 1 [ 9 :0] s dv 1 [2 :0] mlrck 1 mbick 1 lrcksd 1 b icksd 1 lrck 1 (pin input ) bick 1 (pin input ) div cks 1 [2:0] cks 4 [2:0] / bdv 4 [ 9 :0] / s dv 4 [ 2 :0] bicksd 4 lrcksd4 xt i pin bick1~ 3 pin p msn 1 bicks d2 lrcksd2 cks 2 [2:0] / bdv 2 [ 9 :0] / s dv 2 [ 2 :0] lrck2(pin input) bick2(pin input) msn2 bicksd3 lrcksd3 cks 3 [2:0] / bdv 3 [ 9 :0] / s dv 3 [ 2 :0] lrck3(pin input) bick3(pin input) msn3
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 41 - the clock source of i nternal dividing clock mbickx is sel ected by cksx[2:0] bits ( table 8 ) . mbickx is generated by dividing the selected clock source according to the bdvx[ 9 :0] bits setting ( table 9 ) . additionally, mlrckx is generated by dividing this mbickx according to the sdvx[2:0] bits setting ( table 10 ) . cksx[2:0] bits clock source 000 tielow (default) 001 pllmclk 010 xti pin 011 bick1 pin 100 bick2 pin 101 bick3 pin others n/a table 8 . clock source of internal dividing clock (n/a: not available) bdvx[9:0] bits divide by 0x000 1 (default) 0x001 C 000( divide by 64) , mbickx = 147.456 mhz / 48 = 3.072mh z, mlrckx = 3.072mhz/64 = 48khz .
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 42 - bdvx[9:0] bits mbickx dividing mbickx(mhz) sdvx[2:0] bits mlrckx dividing mlrckx(khz) 48khz base 44.1khz base 48khz base 44.1khz base 0x23f 576 0.256 0.2352 010 32 8 n/a 0x17f 384 0.384 0.3528 001 48 8 n/a 0x11f 288 0.512 0.4704 000 64 8 n/a 0x08f 144 1.024 0.9408 011 128 8 n/a 0x047 72 2.048 1.8816 100 256 8 n/a 0x17f 384 0.384 0.3528 010 32 12 11.025 0x0ff 256 0.576 0.5292 001 48 12 11.025 0x0bf 192 0.768 0.7056 000 64 12 11.025 0x05f 96 1.536 1.4112 011 128 12 11.025 0x02f 48 3.072 2.8224 100 256 12 11.025 0x11f 288 0.512 0.4704 010 32 16 14.7 0x0bf 192 0.768 0.7056 001 48 16 14.7 0x08f 144 1.024 0.9408 000 64 16 14.7 0x047 72 2.048 1.8816 011 128 16 14.7 0x023 36 4.096 3.7632 100 256 16 14.7 0x0bf 192 0.768 0.7056 010 32 24 22.05 0x07f 128 1.152 1.0584 001 48 24 22.05 0x05f 96 1.536 1.4112 000 64 24 22.05 0x02f 48 3.072 2.8224 011 128 24 22.05 0x017 24 6.144 5.6448 100 256 24 22.05 0x08f 144 1.024 0.9408 010 32 32 29.4 0x05f 96 1.536 1.4112 001 48 32 29.4 0x047 72 2.048 1.8816 000 64 32 29.4 0x023 36 4.096 3.7632 011 128 32 29.4 0x011 18 8.192 7.5264 100 256 32 29.4 0x05f 96 1.536 1.4112 010 32 48 44.1 0x03f 64 2.304 2.1168 001 48 48 44.1 0x02f 48 3.072 2.8224 000 64 48 44.1 0x017 24 6.144 5.6448 011 128 48 44.1 0x00b 12 12.288 11.2896 100 256 48 44.1 0x02f 48 3.072 2.8224 010 32 96 88.2 0x01f 32 4.608 4.2336 001 48 96 88.2 0x017 24 6.144 5.6448 000 64 96 88.2 0x00b 12 12.288 11.2896 011 128 96 88.2 0x005 6 24.576 22.5792 100 256 96 88.2 0x017 24 6.144 5.6448 010 32 192 176.4 0x00f 16 9.216 8.4672 001 48 192 176.4 0x00b 12 12.288 11.2896 000 64 192 176.4 0x005 6 24.576 22.5792 011 128 192 176.4 table 11 . clock sync domain setting when pllmclk is clock source (n/a: not available) for clock sync domain, set bdvx[ 9 :0] bits and sdvx[2:0] bits according to the input clock frequency when the xti or bick pin input is selected as the c lock source, as well as the pll mclk. mbickx = xti pin or bickx pin frequency divided by bdvx[9:0] bits setting mlrckx = mbickx divided by sdvx[2:0] bits setting
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 43 - 3. sa mpling frequency setting of adc and dac blocks available sampling modes for analog block of the ak7735 are shown below. sampling frequency mode is set by fsmode[4:0] bits. adc1 can be operated by a different sampling frequency from adc2, dac1 and dac2. mode fsmode[4:0] bits adc2, dac1, dac2 adc1 0 00000 8khz 8khz (default) 1 00001 12khz 12khz 2 00010 16khz 16khz 3 00011 24khz 24khz 4 00100 32khz 32khz 5 00101 32khz 16khz 6 00110 32khz 8khz 7 00111 48khz 48khz 8 01000 48khz 24khz 9 01001 48khz 16khz 10 01010 48khz 8khz 11 01011 96khz 96khz 12 01100 96khz 48khz 13 01101 96khz 32khz 14 01110 96khz 24khz 15 01111 96khz 16khz 16 10000 96khz 8khz 17 10001 192khz 192khz 18 10010 192khz 96khz 19 10011 192khz 48khz 20 10100 192khz 32khz 21 10101 192khz 16khz others n/a n/a n/a table 12 . sampling frequency settings of adc and dac blocks (fs=48khz base, n/a: not available ) clock sync domain of the adc1 (sdadc1) is selected by sdadc1[2:0] bits and clock sync domain of the adc2, dac1 and dac2 (sdcodec) is selected by sdcodec[2:0] bits ( table 18 ) . the sampling frequency of lrcksdx for sdadc1 and the sampling frequency of the adc1 should be the same. the sampling frequency of lrcksdx for sdcodec and the sampling frequency of the adc2, dac1 and dac2 should also be the same. sdadc1 and sdcodec must be synchronized with pll mclk. set sda dc1[2:0] bits to 000 (reference clock is fixed to l ) when not using the adc1 . in the same manner, sdcodec[2:0] bits should be set to 00 0 when not using the adc2, dac1 and dac2 .
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 44 - 4. master clock output setting the master clock output frequency setting of the clko pin is controlled by clkosel[2:0] bits. mode clkosel[2:0] bits output frequency (fs=48khz base ) output frequency (fs=44.1khz base ) 0 000 12.288mhz 11.2896mhz (default) 1 001 24.576mhz 22.5792mhz 2 010 8.192mhz 7.5264mhz 3 011 6.144mhz 5.6448mhz 4 100 4.096mhz 3.7632mhz 5 101 2.048mhz 1.8816mhz others n/a n/a n/a table 13 . clko output frequency setting (n/a: not available) 5. sdinx/bickx/lrckx pin setting the ak7735 has three bick / lrck pin s and they are independent each other. msnx bit selects master/slave mode setting of the bick x pin and the lrckx pin (x=1~3) . ( table 14 ) msnx bit (x=1~3) bickx pin, lrckx pin 0 slave mode (input) (default) 1 master mode (output) table 14 . bickx/lrckx p in mode selection note * 50 . set msn x bit to 0 when using the bickx pin as pll reference clock input pin. when bickx/lrckx (x=1~ 3 ) pin s are set to slave mode, the reference clock s of clock sync domain x are the clocks from bickx/lrckx pin s ( table 7 ). when bickx/lrckx pin s are set to m aster mode, the output clock s of the bickx/lrckx pin s can be selected from four sync domains by sdbckx[2:0] bits (x= 1~ 3 ) . ( table 15 ) msnx bit sdbckx[2:0] bits bickx pin/lrckx pin 1 000 tielow (default) 1 001 bicksd1, lrcksd1 1 010 bicksd2, lrcksd2 1 011 bicksd3, lrcksd3 1 100 bicksd4, lrcksd4 1 others n/a table 15 . clock sync domain setting of bickx /lrckx p in s in master mode (n/a: not available ) note * 51 . sdbckx[2:0] bits can be in the default setting 000 (tielow) when bickx pin /lrckx pin (x=1~3) are in slave mode. the ak7735 has four serial data input ports (sdinx pin). synchronizing clock of sdinx pin can be selected from three bickx/lrckx pins by exbckx[1:0] bits. exbckx[1:0] bits bick/lrck synchronizing with sdinx pin 00 tielow (default) 01 bick1 pin, lrck1 pin 10 bick2 pin, lrck2 pin 11 bick3 pin, lrck3 pin table 16 . bick/lrck setting synchroniz ing with sdinx p in
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 45 - 6. clock sync domain setting of dsp clock sync domain of dsp1 is selected by sddsp1[2:0] bits. the dsp1 input port inherits the sync domain of the input data. clock sync domain of the output ports are set by sddsp1o1[2:0] ~ sddsp1o6[2:0] bits. clock sync domain of dsp 2 is selected by sddsp2[2:0] bits. the dsp2 in put port inherits the sync domain of the input data. clock sync domain of the output ports are set by sddsp 2 o1[2:0] ~ sddsp 2 o6[2:0] bits. dsp
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 46 - audio data path setting 1. data bus, in /output port t he ak 7735 has a 32 - bit serial audio stereo data bus ( figure 17 ) . inputs and outputs of each internal block and all input/output pins of the ak 7735 are connected to this serial audio data bus. the port that data is input to this serial audio data bus is defined as input port and the port that data is output from the audio data bus is defined as output port . each port selects clock sync domain and inputs (outputs) audio data that synchronized to the reference clock of the clock sync domain to the data bus ( figure 17 ) . a stereo data on each port is defined as data source . all data sources are connected to the serial audio bus and a data source on any input port can be output to any output port. data co nnection of the input port and the output port with the same sampling frequency via data bus is defined as data path . input and output ports on the same data path should have the same clock sync domain. if these ports have different clock sync domains, r eference clocks (bicksdx, lrck sdx) must be synchronized and the sampling frequency of lrcksdx must be the same. however , p hase synchronization of reference clocks is not necessary and frequencie s of bick sdx can be different. an src is necessary for data transmission between two ports that have clock sync domain with different sampling frequencies or a synchron ous reference clocks. e .g. ) data path example ( figure 16 ) it is an example of outputting data from the dac1 after converting fs=8khz input data from the sdin1 pin to fs=48khz by src. path 1 is defined from the sdin1 pin to src1. path2 is defined from src1 to dac1. set the same clock sync domain for data ports of the path1 (sdin1 input and src1 output ports), and for the data ports of the path2 (src1 input port and dac1), independently. figure 16 . data path example data bus dac1 sdout1 5 dac i 1 sdin1pin sdin1 sdout1 5 : input port : output port sdin1 sdin1 src1 sdin1 s rco1 sdout1 5 s rci1 path1 (fs=8khz) path 2 (fs=48khz)
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 47 - figure 17 . ak7735 audio data path 2. data bus group delay when the input and output ports with the same sampling frequency are connected via data bus, group delay of 2/fs occurs in total as audio data will have 1/fs group delay at each input and output port of the data bus (fs is the sampling frequency of the sync domain of the input and output ports). therefore, this group delay will increase as the number of times that th e data go es through the data path increases . in the example of figure 16 , 2 /fs (fs=8khz) group delay occurs when inputting the sdin1 data to src via d ata bus and another 2/fs (fs= 4 8khz) group delay occurs when inputting the src1 output data to dac1 via data bus. sdin1 all0 serial data bus (stereo 32bit) sdin2pin sdin1 sdin2 sdin3pin sdin1 sdin3 sdin4pin sdin1 sdin4 sdin1pin sdin1 sdin1 sdout1 5 sdout4 pin sdout4 sdout1 5 sdout2 pin sdout2 sdout1 5 sdout3 pin sdout3 sdout1 5 sdout1 pin sdout1 src1 sdin1 s rco1 sdout1 5 s rci1 src2 sdin1 s rco 2 sdout1 5 s rci 2 dac1 sdout1 5 dac1 dac2 sdout1 5 dac2 sdin1 adc1 sdin1 adc2 adc1 adc2 sdin1 sdout1 5 : input port : output port sdin1 dout1 sdout1 5 din1 sdin1 dout2 sdout1 5 din2 sdin1 dout3 sdout1 5 din3 sdin1 dout4 sdout1 5 din4 sdin1 dout5 sdout1 5 din5 sdin1 dout6 sdout1 5 din6 dsp1 sdin1 dout1 sdout1 5 din1 sdin1 dout2 sdout1 5 din2 sdin1 dout3 sdout1 5 din3 sdin1 dout4 sdout1 5 din4 sdin1 dout5 sdout1 5 din5 sdin1 dout6 sdout1 5 din6 dsp2
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 48 - 3. clock sync domain setting of input/output port domain numbers are assigned to each clock sync domain ( table 18 ). each input/output port has setting registers for clock sync domain ( figure 20 ). set a domain number to clock sync domain setting registers for each input/output port. ( table 19 , table 20 ) domain number clock sync domain 0x0 tielow 0x1 lrcksd1, bicksd1 (sd1) 0x2 lrcksd2, bicksd2 (sd2) 0x3 lrcksd3, bicksd3 (sd3) 0x4 lrcksd4, bicksd4 (sd4) table 18 . clock sync domain number if the output port sync d omain setting is in auto mode, the output port inherits the sync domain of the input data. e.g. ) data path example it is an example of outputting data from the dac1 after converting fs=8khz input data from the sdin1 pin to fs=48khz by src ( figure 16 ) . the output port of src1 is in auto mode. therefore the output port inherits the clock sync domain of sdin1 input port. clock sync domain of the sdinx pin is automatically selected by setting exbckx[1 :0] bits, msn bit and sdbckx[2:0] bits ( table 15 , table 16 ) . e.g.) clock sync domain 3 is selected for the sdin2 pin when exbck2[ 1 :0] bits = 01 1 and msn 3 bit = 0 ( figure 18 ). figure 18 . clock sync domain setting example 1 of sdinx pin e.g.) clock sync domain 3 is selected for the sdin1 pin when exbck1[ 1 :0] bits = 001 , msn 2 bit = 1 and sdbck 2 [2:0] bits = 01 1 ( figure 19 ). figure 19 . s clock sync domain setting example2 of sdinx pin
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 49 - figure 20 . clock sync domain setting
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 50 - 4. source address, source selecting registers a source address is assigned to each input port source ( table 19 ) . the output port can select any input port source by setting a source address to the source select register. source address source name source contents input port clock sync domain setting register 0x00 all0 0x0000 0000 fixed all0 * 53 0x01 sdin1 sdin1a sdin1 (pin) input tdmi1 slot1, 2 input sdin1 * 54 0x02 sdin1b tdmi1 slot3, 4 input 0x03 sdin1c tdmi1 slot5, 6 input 0x04 sdin1d tdmi1 slot7, 8 input 0x05 sdin2 sdin2a sdin2 (pin) input tdmi2 slot1, 2 input sdin2 * 54 0x06 sdin2b tdmi2 slot3, 4 input 0x07 sdin2c tdmi2 slot5, 6 input 0x08 sdin2d tdmi2 slot7, 8 input 0x09 sdin3 sdin3a sdin3 (pin) input tdmi3 slot1, 2 input sdin3 * 54 0x0a sdin3b tdmi3 slot3, 4 input 0x0b sdin3c tdmi3 slot5, 6 input 0x0c sdin3d tdmi3 slot7, 8 input 0x0d sdin4 sdin4a sdin4 (pin) input tdmi4 slot1, 2 input sdin4 * 54 0x0e sdin4b tdmi4 slot3, 4 input 0x0f sdin4c tdmi4 slot5, 6 input 0x10 sdin4d tdmi4 slot7, 8 input 0x11 dout101 dsp1 output 1 dout101 sddsp1o1[2:0] 0x12 dout102 dsp1 output 2 dout102 sddsp1o2[2:0] 0x13 dout103 dsp1 output 3 dout103 sddsp1o3[2:0] 0x14 dout104 dsp1 output 4 dout104 sddsp1o4[2:0] 0x15 dout105 dsp1 output 5 dout105 sddsp1o5[2:0] 0x16 dout106 dsp1 output 6 dout106 sddsp1o6[2:0] 0x17 dout201 dsp2 output 1 dout201 sddsp2o1[2:0] 0x18 dout202 dsp2 output 2 dout202 sddsp2o2[2:0] 0x19 dout203 dsp2 output 3 dout203 sddsp2o3[2:0] 0x1a dout204 dsp2 output 4 dout204 sddsp2o4[2:0] 0x1b dout205 dsp2 output 5 dout205 sddsp2o5[2:0] 0x1c dout206 dsp2 output 6 dout206 sddsp2o6[2:0] 0x1d adc1 adc1 output adc1 sdadc1[2:0] 0x1e adc2 adc2 output adc2 sdcodec[2:0] 0x1f srco1 src1 output srco1 sdsrco1[2:0] 0x20 srco2 src2 output srco2 sdsrco2[2:0] others n/a n/a n/a n/a table 19 . source address es of input port s (n/a: not available)
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 51 - source select registers contents output port clock sync domain setting register seldo1a[5:0] sdout1(pin) output tdmo1 slot1, slot2 sdout1 sddo1[2:0] seldo1b[5:0] tdmo1 slot3, slot4 seldo1c[5:0] tdmo1 slot5, slot6 seldo1d[5:0] tdmo1 slot7, slot8 seldo2a[5:0] sdout2(pin) output tdmo2 slot1, slot2 sdout2 sddo2[2:0] seldo2b[5:0] tdmo2 slot3, slot4 seldo2c[5:0] tdmo2 slot5, slot6 seldo2d[5:0] tdmo2 slot7, slot8 seldo3a[5:0] sdout3(pin) output tdmo3 slot1, slot2 sdout3 sddo3[2:0] seldo3b[5:0] tdmo3 slot3, slot4 seldo3c[5:0] tdmo3 slot5, slot6 seldo3d[5:0] tdmo3 slot7, slot8 seldo4a[5:0] sdout4(pin) output tdmo4 slot1, slot2 sdout4 sddo4[2:0] seldo4b[5:0] tdmo4 slot3, slot4 seldo4c[5:0] tdmo4 slot5, slot6 seldo4d[5:0] tdmo4 slot7, slot8 selda1[5:0] dac1 input dac1 sdcodec[2:0] selda2[5:0] dac2 input dac2 d1seldi1[5:0] dsp1 input 1 din101 (auto) d1seldi2[5:0] dsp1 input 2 din102 (auto) d1seldi3[5:0] dsp1 input 3 din103 (auto) d1seldi4[5:0] dsp1 input 4 din104 (auto) d1seldi5[5:0] dsp1 input 5 din105 (auto) d1seldi6[5:0] dsp1 input 6 din106 (auto) d2seldi1[5:0] dsp2 input 1 din201 (auto) d2seldi2[5:0] dsp2 input 2 din202 (auto) d2seldi3[5:0] dsp2 input 3 din203 (auto) d2seldi4[5:0] dsp2 input 4 din204 (auto) d2seldi5[5:0] dsp2 input 5 din205 (auto) d2seldi6[5:0] dsp2 input 6 din206 (auto) selsrci1[5:0] src1 input srci1 (auto) selsrci2[5:0] src2 input srci2 (auto) table 20 . source select registers of output port s notes * 53 . if the output port source is changed to all0 when the c lock s ync d omain setting is auto , the clock sync domain before changing the data source will be kept. this clock sync domain should not be stopped immediately after changing the data source otherwise the output data will not become all0 correctly. * 54 . clock sync do main of the sdinx pin is automatically selected by setting exbckx [ 1 :0] bits, msnx bit and sdbckx[2:0] bits ( table 14 , table 15 , table 16 ) . * 55 . sdinxb~d are only valid in tdm mode. these ports are fixed to 0 if it is not in tdm mode. * 56 . input data to the input port 1~ 6 of the dsp must be selected from a data based on a clock sync domain which is synchronized with pllmclk.
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 52 - 5. input/output serial interface format 5 - 1. data clocks the ak773 5 has three lrck/bick pins that are input/output switchable to interface with external equipment. msnx bit controls master and slave modes of lrck x /bick x pins ( table 14 ) . dcf x [ 2 :0] bits control each clock format of these pins independently. if lrckx/bickx pins are configured as slave mode, set dcfx[2:0] bits according to the input clock. if lrckx/bickx pins are configured as master mode, the output clock format is selected by dcfx[2:0] bits. mode dcfx[2] dcfx[1] dcfx[0] clock format 0 0 0 0 i 2 s mode (default) 1 1 0 1 dsp mode 2 1 1 0 pcm short frame 3 1 1 1 pcm long frame table 21 . ak773 5 data clock format bckpx bit controls the relationship of bickx and lrckx edges. bckpx bit bickx edge referenced to lrckx start edge 0 falling ed ge (default) 1 rising edge table 22 . relationship of bickx and lrckx edges
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 53 - figure 21 . i 2 s mode figure 22 . dsp mode figure 23 . pcm short frame / pcm long frame (bckpx bit = 0) figure 24 . pcm short frame / pcm long frame (bckpx bit = 1) lch rch lrckx bickx lch rch lrckx bickx l ch + rch lrckx bickx l ch + rch lrckx bickx
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 54 - 5 - 2. data definitions a serial bit stream that is sent or received by the ak773 5 is a long sequence composed of 1 and 0 . this data sequence has hierarchical levels of slot, word and bit. bit: it is a smallest component in a serial data stream. the bit duration is one serial clock cycle. word: it is a group of multiple bits that composes transmitting data between external devices and the ak 7735 . figure 25 shows an example of a word consists of eight bits. slot: it is composed of a word and adequate additional bits for interfacing to an external device. in figure 25 , the audio data is an 8 - bit valid data and a 12 - bit slot needs additional four zero e s to satisfy an interface protocol of the external device. if the word length is shorter than the slot length, the data alignment of the word will be the beginning of the slot ( msb justified) o r end of the slot ( lsb justified) . figure 25 shows an example of msb justified form at. figure 25 . bit, word and slot definitions bit word slot
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 55 - 5 - 3. input/ output interface format the ak 7735 has four digital input ports and four digital output ports. the data format can be set independently . the input data format is determined by a combination of dislx[1:0], diedg enx, dilsbex and didlx[1:0] bits settings (x=1~4 ). the output data format is determined by a combination of doslx[1:0], doedgenx, dolsbex and dodlx[1:0] bits settings (x=1~ 4 ). dislx[1:0] bits / doslx[1:0] bits (x=1~ 4 ) control input/output data slot length. mode dislx[1] bit doslx[1] bit dislx[0] bit doslx[0] bit slot length 0 0 0 24bit (default) 1 0 1 20bit 2 1 0 16bit 3 1 1 32bit table 23 . slot length setting of input/output data didlx[1:0] bits / dodlx[1:0] bits (x=1~ 4 ) control input/output audio data word length. mode didlx[1] bit dodlx[1] bit didlx[0] bit dodlx[0] bit word length 0 0 0 24bit (default) 1 0 1 20bit 2 1 0 16bit 3 1 1 32bit table 24 . word length setting of input/output audio data dilsbex bit / d o lsbex bit (x=1~ 4 ) select the audio data format of a slot. dilsbex bit dolsbex bit slot data format 0 msb first (default) 1 lsb first table 25 . slot data format setting diedgenx bi t / d o edgenx bit (x=1~ 4 ) select data transmission start timing of the data after second channel diedgenx bit doedgenx bit start timing 0 lrck edge basis (default) 1 slot length basis table 26 . d ata t ransmission s tart t iming selection of t he d ata a fter s econd c hannel if the data transmitting timing is set to slot l ength basis, the next channel s data is transmitted immediately without waiting a lrck edge after transmitted one slot data ( figure 29 ~ figure 33 ). if the data transmitting timing is set to lrck edge basis, th e next channel s data will not be transmitted until a lrck edge even finished transmitting one slot data ( figure 26 ~ figure 28 ) .
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 56 - 5 - 3 - 1. stereo mode ak7735 supports stereo mode. the bick x pin should be set to arbitrary frequency more than word length x 2fs when diedgenx bit = 0 . the bick x pin should be set to arbitrary frequency more than slot length x 2fs when diedgenx bit = 1 . bick clock is supported up to 256fs (max. 24.576mhz ) . the sdinx input pins of the ak7735 suppor t stereo input mode. two slots data input is available for each pin. a source address is assigned to each sdinx input pin when using stereo input mode ( table 19 ) . disl x [1:0] bits control input data slot length of the sdinx pin. didl x [1:0] bits control the input data word length of the sdinx pin. the slot data format is set by dilsbe x bit . in stereo mode, diedgenx bit should be set to 0 if the data transmission timing of second channel is lrck edge basis . in this case, d i sl x [1:0] bits setting are ignored. the sdoutx output pins of the ak7735 support stereo output mode. two slots data output is available for each pin. each slot d ata can be assig ned by setting seldoxa[5:0] bits . d o sl x [1:0] bits control output data slot length of the sdoutx pin. d o dl x [1:0] bits control the output data word length of the sdoutx pin. the slot da ta format is set by d o lsbe x bit . in stereo mode, doedgenx bit must be set to 0 if the data transmission timing of second channel is lrck edge basis . in this case, d o sl x [1:0] bits setting are ignored . setting example of stereo mode is shown in table 27 . mode data format dcfx[2:0] dilsbex dolsbex diedgenx doedgenx dislx[1:0] doslx[1:0] didlx[1:0] dodlx[1:0] 0 i 2 s compatible 000 0 0 - word length 1 msb justified 101 0 0 - word length 2 lsb justified 101 1 0 - word length 3 pcm short frame 110 0 1 slot length word length 4 pcm long frame 111 0 1 slot length word length 5 irregular i 2 s 000 0 1 slot length word length table 27 . stereo mode setting example ( - : do no t care)
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 57 - mode 0 : i2s compatible format figure 26 . i2s compatible format mode 1 : msb justified format figure 27 . msb justified format m ode 2 : lsb justified format figure 28 . lsb justified format lch data (msb first) s din x lch rch s dout x l rck x b ick x rch data (msb first) dont care dont care lch data (msb first) rch data (msb first) lch data (msb first) s din x lch rch s dout x l rck x b ick x rch data (msb first) dont care dont care lch data (msb first) rch data (msb first) lch data (msb first) s din x lch rch s dout x l rck x bick x rch data (msb first) dont care dont care lch data (msb first) rch data (msb first)
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 58 - mode 3 : pcm short frame format figure 29 . pcm short frame format (bckpx bit = 0) figure 30 . pcm short frame format (bckpx bit = 1) lch data (msb f irst) s din x s dout x l rck x b ick x rch data (msb first) dont care lch data (msb first) rch data (msb first) tbclk tbclk x slotlength tbclk x 2 x slotlength lch da ta (msb first) s din x s dout x l rck x b ick x rch data (msb first) dont care lch data (msb first) rch data (msb first) tbclk tbclk x slotlength tbclk x 2 x slotlength
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 59 - mode 4 : pcm long frame format figure 31 . pcm long frame format (bckpx bit = 0) figure 32 . pcm long frame format (bckpx bit = 1) mode 5 : irregular i 2 s format figure 33 . irregular i 2 s format lch data (msb fir st) s din x s dout x l rck x (slave) b ick x rch data (msb first) dont care lch data (msb first) rch data (msb first) tbclk tbclk x slotlength tbclk x 2 x slotlength dont care lrck x (master) lch data (msb first) s din x s dout x l rck x (slave) b ick x rch data (msb first) dont care lch data (msb first) rch data (msb first) tbclk tbclk x slotlength tbclk x 2 x slotlength dont care lrck x (master) lch data (msb first) s din x lch rch s dout x l rck x b ick x rch data (msb first) dont care lch data (msb first) rch data (msb first)
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 60 - 5 - 3 - 2. tdm mode ak7735 supports tdm mode. bick clock for data input/output should be set to 128fs, 192fs or 256fs when using tdm mode. s ampling frequency up to 192khz in 128fs mode (max. fs=128khz in 192 mode, max. fs=96khz in 256 mode ) is supported. the sd in x input pin s of the ak7735 support tdm mode. eight s lots data input is available at a maximum. a source address is assigned to each 2 slot of sd in x input pin s when using tdm mode. ( table 19 ) . disl x [1:0] bits control input data slot length of the sdin x pin. didl x [1:0] bits control the input data word length of the sdin x pin. the slot data format is set by dilsbe x bit . in tdm mode, diedgen x bit must be s et to 1 since the data transmission timing after second channel is slot length basis. slot length , word length and slot data format of each input data slot should be the same setting. the sdout x output pins of th e ak7735 sup port tdm mode. eight slots data output is available for each pin at a maximum. each slot d ata can be assig ned independently by setting seldo xa - d [5:0] bits in every two slots. d o sl x [1:0] bits control output data slot length of the sdout x pin. d o dl x [1:0] bits control the output data word length of the sdout x pin. the slot data format is set by d o lsbe x bit . in tdm mode, doedgen x bit must be set to 1 since the data transmission timing after second channel is slot length basis. slot length , word length and slot data format of each input data slot should be the same setting. setting example of tdm mode is shown in table 28 . mode data format dcfx[2:0] dilsbex dolsbex diedgenx doedgenx dislx[1:0] doslx[1:0] didlx[1:0] dodlx[1:0] 0 i 2 s compatible 000 0 1 11 (32bit) word length 1 msb justified 101 0 1 11 (32bit) word length 2 lsb justified 101 1 1 11 (32bit) word length 3 pcm short frame 110 0 1 slot length word length 4 pcm long frame 111 0 1 slot length word length 5 irregular i 2 s 000 0 1 slot length word length table 28 . tdm mode setting example
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 61 - mode 0: i2s compatible format figure 34 . tdm mode i 2 s compatibl e (bick=256fs) figure 35 . tdm mode i 2 s compatibl e (bick=128fs) mode 1: msb justified format figure 36 . tdm m ode msb justified for mat (bick=256fs) figure 37 . tdm m ode msb justified for mat (bick=128fs) 256bick sdin x /sdoutx bick x 32 bick 32 bick 32 bick 32 bick 32 bick 32 bick 3 2 bick 32 bick s lot1 s lot 2 s lot 3 s lot 4 s lot 5 s lot 6 s lot 7 s lot 8 l rck x 128 bick sdin x /sdoutx bick x l rck x 32 bick 32 bick 32 bick 32 bick s lot1 s lot2 s lot3 s lot4 256bick sdinx / sdoutx bick x l rck x 32 bick 32 bick 32 bick 32 bick 32 bick 32 bick 32 bick 32 bick s lot1 s lot 2 s lot 3 s lot 4 s lot 5 s lot 6 s lot 7 s lot 8 128 bick sdinx/sdoutx bick x l rck x 32 bick 32 bick 32 bick 32 bick s lot1 s lot2 s lot3 s lot4
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 62 - mode 2: lsb justified format figure 38 . tdm mode lsb justified format (bick=256fs) figure 39 . tdm mode lsb justified format (bick=128fs) mode 3: pcm short frame format figure 40 . tdm m ode pcm short frame (bick=256fs, bckp bit = 0) * 57 figure 41 . tdm m ode pcm short frame (bick=128fs, bckp bit = 0) * 57 note * 57 . when bckp bit = 1 , a bick rising edge corresponds to a lrck rising edge . 256bick sdinx/ sdoutx bick x l rck x 32 bick 32 bick 32 bick 32 bick 32 bick 32 bick 32 bick 32 bick s lot1 s lot 2 s lot 3 s lot 4 s lot 5 s lot 6 s lot 7 s lot 8 128 bick sdinx/sdoutx bick x l rck x 32 bick 32 bick 32 bick 32 bick s lot1 s lot2 s lot3 s lot4 256bick sdinx bick x l rck x s lot 2 s lot 3 s lot 4 s lot 5 s lot 6 s lot 7 s lot 8 sdoutx don t care s lot1 128 bick sdinx bick x l rck x s lot2 s lot3 s lot4 don t care sdoutx s lot1
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 63 - mode 4: pcm long frame format figure 42 . tdm m ode pcm long frame (bick=256fs, bckp bit = 0) * 58 figure 43 . tdm m ode pcm long frame (bick=128fs, bckp bit = 0) * 58 note * 58 . when bckp bit = 1 , a bick rising edge corresponds to a lrck rising edge . mode 5: irregular i 2 s format figure 44 . tdm mode ir regular i 2 s for mat (bick=256fs) figure 45 . tdm mode ir regular i 2 s for mat (bick=128fs) 256bick bick x lrck x ( slave ) l rck x (master) s lot 2 s lot 3 s lot 4 s lot 5 s lot 6 s lot 7 s lot 8 s lot1 don t care sdinx sdoutx don t care 128 bick bick x lrck x ( slave ) l rck x (master) s lot1 s lot2 s lot3 s lot4 dont care sdinx don t care sdoutx 256bick bick x s lot 2 s lot 3 s lot 4 s lot 5 s lot 6 s lot 7 s lot 8 sdinx sdoutx don t care s lot1 l rck x 128 bick bick x s lot2 s lot3 s lot4 sdinx don t care sdoutx s lot1 l rck x (master)
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 64 - power - up sequence the ak 7735 should be powered up when the pdn pin = l. set the pdn pin to h to start the power supply circuits for ref (reference voltage source) generator and digital circuits after all power supplies are fed. by setting the pdn pin to h , control registers are initialized. control register settings should be made with an interval of 1ms or more after the pdn pin = h. the pll starts operation by a clock reset release (ckresetn bit = 0 1) and generates the internal master clock after setting control regi sters. therefore, necessary system clock must be input before a clock reset release. interfacing with the ak 7735 except control register settings should be made when pll oscillation is stabilized after clock reset release (take a 10ms interval or confirm h output of plllock signal from the sto bit ( figure 46 ) ) . however, dsp program and coefficient data can be written even when the system clock is stoppe d or during clock reset ( ckresetn bit= 0 ) . dsp program and coefficient data can be written in 1ms by setting dlrdy bit 0 1. dl rdy bit must be set to 0 after download ing programs or data ( 112h figure 47 ). when using a crystal oscillator, release clock reset after crystal oscillation is stabilized. the stabilizing time of crystal oscillation is dependent on the crystal and external circuits. the system clock must not be stopped except during clock reset and power - down mode (pdn pin = l ) . figure 46 . power - up sequence
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 65 - figure 47 . power - up sequence 2 (dlrdy bit setting ) vreg ( internal circuit drive regulator ) the ak 7735 has a regulator for driving internal digital circuits ( vreg ). connect a 2.2 f (30%) capacitor between the avdrv pin and the d vss 3 pin. the regulator starts operation by releasing power - down mode, and control register settings can be made 1ms after the power - down release (pdn pin= h ) . the ak7735 has an overcurrent protection circuit to avoid abnormal heat of the device that is caused by a short of the avdrv pin to vss and etc., and an overvoltage protection circuit to protect from exceeded voltage when the voltage to the avdrv pin gets too high. when these protection circuits perform, internal circuits are powered down. the internal circuit will not return to a normal operation until being reset by the pdn pin after removing the problems.
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 66 - power - down and reset 1. ak7735 power - down and reset statuses and power management power - down and power - down release of the ak773 5 is controlled by the pdn pin. after power - down is released, the power mana gement and reset of the ak7735 are controlled by registers such as ckresetn bit (clock reset), hresetn bit (hub reset), d1resetn and d2resetn bits (dsp reset) , c resetn bit s (codec reset) and power management bits for each block. there are three states for the ak773 5 other than normal operation: power - down, clock reset and system reset. 1) the power - down state means the status that the pdn pin is l . in this state, all blocks of the ak773 5 stop the operation. 2) the clock reset state means the status that the pdn pin is h and ckresetn bi t is 0 . in this state, the dsp, adc, dac and src blocks are not in operation because the pll circuit and internal clocks are stopped. 3) the system reset state means the status that the pdn pin is h , ckresetn bit is 1 , hresetn bit is 0 , cresetn bit is 0 and dxresetn bit (x= 1, 2 ) is 0 . in th is state, the dsp, adc, dac and src blocks are not in operation although the pll circuit and internal clocks are started. the system reset is released by setting either hresetn bit or cresetn bit or dxresetn bit (x=1, 2) to 1 . state setting pdn pin ckresetn bit dxresetn bit (x=1, 2) hresetn bit cresetn bit power - down l x x x x clock reset h 0 0 0 0 system reset * 59 h 1 0 0 0 system reset release * 60 h 1 1 1 1 table 29 . reset state definitions of the ak7 735 (x: dont care) notes * 59 . a stable clock should be supplied before releasing clock reset (ckresetn bit = 1 ). * 60 . the system reset is released by setting either hresetn bit or cresetn bit or dxresetn bit (x=1, 2) to 1 . 2. power - down the ak 773 5 can be powered down by bringing the pdn pin = l. p ower - down status of output pins is shown in table 3 . 3. power - down release the ref generation circuit (reference voltage source) and a power supply circuit for internal digital circuit are powered - up by bringing the pdn pin to h from l after an interval of 600ns or more when a vdd , lvdd, tvdd and vdd 33 are powered up. control register settings should be made with an interval of 1ms or more after setting the pdn pin = h .
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 67 - 4. clock reset when ckresetn bit = 0 after power - down mode is released (pdn pin = h), the ak 773 5 is in clock reset state. all blocks except the power supply circuits for ref generation and digital circuits are in power - save mode. even the internal pll for master clock generation is powered down. control register settings should be made with an interval of 1ms (min) after releasing the power - down mode. dsp program and coefficient data can be written in 1ms by setting dlrdy bit 0 1 during clock reset . dlrdy bit must be set to 0 after download ing ( 112h figure 47 ). necessary system clock s ( table 4 , table 5 ) should be i nput before the clock reset is released. th e internal pll starts operation and the master clock is generated when clock reset is released (ckresetn bit = 1). dsp program and coefficient data should be sent 10ms after clock reset release or after confirm ing h output of plllock signal from the sto pin ( figure 46 ) . system clocks must be changed during clock reset or in power - down mode (pdn pin = l). the pll and the internal clock s are stopped by this clock reset and the clock change can be done safely. change register settings and system clock frequencies during the clock reset. after system c l ock is stabilized, the pll starts operation by setting ckresetn bit to 1. clock operated blocks (adc, dac and src ) must be powered down before executing clock reset. these blocks can be powered down simultaneously by setting hresetn bit to 0 from 1 . set hresetn bit to 1 from 0 with an interval of 10ms for stabilization o f pll after clock reset is released. figure 48 . clock mode switching sequence cs n sclk (simplified) si xti b ick 1 refsel mode 0 refsel mode 1 h reset n dxresetn command code & dsp program transition ckr e s e t n pll stop input clock and clock mode can be changed pll stabilize blocks except pll are stopped c0 00 6e 00 c0 00 01 00 00 00 xx 8x c0 c0 00 6e 0f resume operation 10ms
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 68 - ram clear the ak773 5 has a ram clear function. after a dsp reset release , dram and dlram are cleared by 0. the internal pll must have st able oscillation before a dsp reset release. a period of 8/fs (fs: dsp operating sampling rate) is required from a dsp reset release to the ram clear start. the required time to clear ram is about 112 s . during the ram clear period , it is possible to send a command to the dsp. (the dsp is stopped during ram clear sequence. the sent command is accepted automatically after this sequence is completed.) figure 49 . ram clear sequence register and ram settings of the ak7735 are not held if the pd n pin goes to l . the dram and dlram are not held by a clock reset or a dsp reset . state register pram cram dram dlram ofreg power down (pdn pin = p dn(p in) d x reset n bit (x=1,2) ram clear period ( 112 us) dsp program start ram clear ds p1, dsp2 operation start ds p1, dsp2 period before ram clear start ( 8 /fs)
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 69 - sto pin output status the no. 2 3 pin has the function of the sto (status output) pin , the rdy pin and the sdout2 pin . do2 sel[1:0] bits control the function of this pin. the sto pin function is selected in the default setting. when sdout2 en bit = 0 (default), the sto pin output is enab led. w h en sdout 2 en bit = 1 , the sto pin outputs l . the sto pin outputs l when the ak7735 is powered up and the pdn pin is l . the sto pin outputs h when the internal digital power - supply circuit (vreg) is powered up after releasing the power - down (pdn pin = h ). after the power - down state is released, vreg shut down signal , pll lock signal, wdt1 and wdt2 (watchdog timer) error s of the dsp , crc err or and src 1~2 lock signal can be output from th e sto pin by control register settings. the ak7735 is distinguished as error state when the pdn pin = h , do2sel[1:0] bits = 0 0 , sdout2en bit = 0 and the sto pin = l . vreg shut down status and wdt1 - 2 s tatus es , which are set by dsp instruction, are output from the sto pin when the control register settings are in the default value. pdn pin vreg d1 wdten bit d2 wdten bit crce bit plllocke bit srclocke1 bit srclocke2 bit sto pin note l power down - - - - l h error - - - - l normal operation 0 0 0 0 wdtnerr (default) * 61 , * 62 1 1 0 0 crcerr 1 0 1 0 plllockerr 1 0 0 1 srcnlockerr * 61 0 1 1 1 wdtnerr & crcerr & plllockerr & srclockerrn * 61 , * 62 table 31 . sto pin output setting ( - : not care ) notes * 61 . the sto pin outputs l if the one of status signal becomes l when setting multiple statuses to the sto pin. * 62 . a dsp instruction setting is necessary when using wdt1 and wdt 2 ( watchdog timer).
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 70 - p interface setting and pin statuses the ak773 5 supports both spi and i 2 c inter faces. when using spi interface, release the power - down state of the ak7735 while the csn pin is h . when using i 2 c interface, the csn pin must be pulled up or down since it bec omes a chip address pin. after a power - down release, the ak7735 is set to i 2 c interface mode. spi interface mode become enabled by sending the dummy command mentioned below. input 0xde 0xadda 0x7a to the si/i2cfil pin while the csn pin is l after a falling edge of the csn pin for the dummy command. the data is in msb first format. statuses of the csn, so/sda , sclk/scl and si/i2cfil pin s are changed depending on the pdn pin . pdn pin csn pin so/sda pin sclk/scl pin si/i2cfil pin spi interface l input ( 2 c interface l pull - up / pull - down hi z pull 2 c fast mode 2 c fast mode plus table 32 . p interface setting note * 63 . the csn pin and the si/i2cfil pin should be fixed to l or h when using i 2 c interface mode. the so/sda pin should be pulled - up/down when using spi interface mode. cs n sclk si 0xde (8bit) 0xadda (16bit ) 0x7a ( 8bit ) dont care (l/h) dont care (l/h)
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 71 - spi interface 1. configuration the access format consists of command code (8bits) + address (16bits) + data (msb first). bit length description command code 8 msb bit is an r/w flag. the following 7 bits indicate access area such as pram/ cram/registers. address 16 address is fixed to 16bits. data mentioned in later section read/write data table 33 . p interface format write figure 50 . spi interface timing ( write ) read (except read operation during run figure 51 . spi interface timing ( read ) (except command 24h , 25h, 26h and 2 7 h) read (during run ) figure 52 . spi interface timing ( read ) (command 24h, 25h , 26h and 27h ) cs n sclk si command code (8bit) address (16bit ) data (write) so dont care (l/h) hi - z hi - z echo back dont care (l/h) cs n sclk si command code (8bit) address (16bit ) data ( read ) so dont care (l/h) hi - z hi - z echo back dont care (l/h) cs n sclk si command code (8bit) data ( read ) so dont care (l/h) hi - z hi - z address (16bit) dont care (l/h)
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 72 - 1 - 1. write command address data length description 80h ~ 8fh 16bit 24bit x n write preparation to cram of dsp1/dsp2 during run ( 80 h: write 1data , 81 h: write 2 data , ---- , 8f h: write 16 data ) if the actual amount of write operations exceeds the defined amount, th e data will be ignored. 90h ~ 9fh 16bit 24bit x n write preparation to ofreg of dsp1/dsp2 during run ( 9 0 h: write 1data , 9 1 h: write 2 data , ---- , 9 f h: write 16 data ) if the actual amount of write operations exceeds the defined amount, th e data will be ignored. a2h 16bit - write execution to ofreg of dsp1 during run. 0 address should be written. a3h 16bit - write execution to ofreg of dsp2 during run. 0 address should be written. a4h 16bit - write execution to cram of dsp1 during run. 0 address should be written. a5h 16bit - write execution to cram of dsp2 during run. 0 address should be written. b2h 16bit 24bit x n write operation to ofreg of dsp1 (during dsp reset) b3h 16bit 24bit x n write operation to ofreg of dsp 2 (during dsp reset) b4h 16bit 24bit x n write operation to cram of dsp1 (during dsp reset) b5h 16bit 24bit x n write operation to cram of dsp2 (during dsp reset) b8h 16bit 40bit x n write operation to pram of dsp1 (during dsp reset) b9h 16bit 40bit x n write operation to pram of dsp2 (during dsp reset) c0h 16bit 8bit x n sequential control register write f2h 16bit 16bit crc result write 0 address should be written. f4h 16bit 8bit write operation of dsp1 jx code 0 address should be written. f5h 16bit 8bit write operation of dsp 2 jx code 0 address should be written. the d ata length is defined by the command code which specifies the area to be accessed. writing other than the above - mentioned command code is prohibited.
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 73 - 1 - 2. read command address data length description 24h 0bit 16bit + 24bit x n read cram write preparation data of dsp1 25h 0bit 16bit + 24bit x n read ofreg write preparation data of dsp1 26h 0bit 16bit + 24bit x n read cram write preparation data of dsp 2 27h 0bit 16bit + 24bit x n read ofreg write preparation data of dsp 2 32h 16bit 24bit x n read operation from ofreg of dsp1 (during dsp reset) 33h 16bit 24bit x n read operation from ofreg of dsp2 (during dsp reset) 34h 16bit 24bit x n read operation from cram of dsp1 (during dsp reset) 35h 16bit 24bit x n read operation from cram of dsp2 (during dsp reset) 38h 16bit 40bit x n read operation from pram of dsp1 (during dsp reset) 39h 16bit 40bit x n read operation from pram of dsp2 (during dsp reset)) 40h 16bit 8bit x n sequential control register read 40h 16bit 8bit device identification no. ( recognized as register: address = 0100h) 40h 16bit 8bit device revision no. ( recognized as register: address = 0101h) 72h 16bit 16bit crc result read 0 address should be written. 76h 16bit 32bit x n sequential read operation from mir of dsp1. (max. 8) 0 address should be written. 28bit s are upper - bit justified. lower 4 bits are for validity flags. valid at 0000 . * 64 77h 16bit 32bit x n sequential read operation from mir of dsp2. (max. 8) 0 address should be written. 28bit s are upper - bit justified. lower 4 bits are for validity flags. valid at 0000 . * 64 note * 64 . lower 4 bits for validity flags are common in eight mir data. if the mir data is updated by a dsp program , all eight data flags become 0000 . if an mir read command by a microcontroller is executed, all eight data flags become 1111 . when accessing ram or control registers, data may be read from sequential address loca tions by reading data continuously. reading other than the above - mentioned command code is prohibited.
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 74 - 2. echo - back mod e the ak773 5 has echo - back mode that outputs the writing data sequentially from the so pin. 2 - 1. write figure 53 . echo - back mode writing (spi) the input data of the si pin is echoed back on the so pin by shifting 8 - bits to the right. the last 1 byte written data is not echoed - back. the data will not echoed - back when writing dummy command . 2 - 2. read figure 54 . echo - back mode reading (spi) data of the address 1/2 field s are not echoed back in read operation. the read data on the so pin is output after writing to the address2 field. cs n si command address1 address2 data1 data2 command address1 so command address1 address2 data1 command dontcare (l/h) hi - z cs n si command address1 address2 command address1 so command dummydata read data read data command dontcare (l/h) h i - z
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 75 - 3. command format 3 - 1 . dsp ram write and read 3 - 1 - 1. write operation during dsp reset (1) program ram (pram) write (during dsp reset) field write data (1) command code 0xb8 (dsp1) / 0xb9 (dsp2) (2) address1 0 0 0 0 a11 a10 a9 a8 (3) address2 a7 a6 a5 a4 a3 a2 a1 a0 (4) data1 0 0 0 0 d35 d34 d33 d32 (5) data2 d31~d24 (6) data3 d23~d16 (7) data4 d15~d8 (8) data5 d7~d0 five bytes of data may be written continuously for each address. (2) coefficient ram (cram) write (during dsp reset) field write data (1) command code 0xb4 (dsp1) / 0xb5 (dsp2) (2) address1 0 0 0 a12 a11 a10 a9 a8 (3) address2 a7 a6 a5 a4 a3 a2 a1 a0 (4) data1 d23~d16 (5) data2 d15~d8 (6) data3 d7~d0 three bytes of data may be written continuously for each address. (3) offset reg (ofreg) write (during system reset) field write data (1) command code 0xb2 (dsp1) / 0xb3 (dsp2) (2) address1 0 0 0 0 0 0 0 0 (3) address2 0 0 a5 a4 a3 a2 a1 a0 (4) data1 0 0 0 0 0 0 0 0 (5) data2 0 0 d13 d12 d11 d10 d9 d8 (6) data3 d7~d0 three bytes of data may be written continuously for each address.
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 76 - 3 - 1 - 2. write operation during run (1) coefficient ram (cram) write preparation (during run) preparation write data (1) command code 0x80~0x8f (one data at 0x80 , sixteen data at 0x8f ) (2) address1 0 0 0 a12 a11 a10 a9 a8 (3) address2 a7 a6 a5 a4 a3 a2 a1 a0 (4) data1 d23~d16 (5) data2 d15~d8 (6) data3 d7~d0 three bytes of data may be written continuously for each address. (2) coefficient ram (cram) write operation ( during run) execute write data (1) command code 0xa4 (dsp1) / 0xa5 (dsp2) (2) address1 0 0 0 0 0 0 0 0 (3) address2 0 0 0 0 0 0 0 0 (3). offset reg (ofreg) write preparation (during run) preparation write data (1) command code 0x90~0x9f (one data at 0x90, sixteen data at 0x9f) (2) address1 0 0 0 0 0 0 0 0 (3) address2 0 0 a5 a4 a3 a2 a1 a0 (4) data1 0 0 0 0 0 0 0 0 (5) data2 0 0 d13 d12 d11 d10 d9 d8 (6) data3 d7~d0 three bytes of data may be written continuously for each address. (4). offset reg (ofreg) write operation (during run) execute write data (1) command code 0xa2 (dsp1) / 0xa3 (dsp2) (2) address1 0 0 0 0 0 0 0 0 (3) address2 0 0 0 0 0 0 0 0
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 77 - 3 - 1 - 3. read operation during dsp reset (1) program ram (pram) read ( during dsp reset) field write data readout data (1) command code 0x38 (dsp1) / 0x39 (dsp2) (2) address1 0 0 0 0 a11 a10 a9 a8 (3) address2 a7 a6 a5 a4 a3 a2 a1 a0 (4) data1 0 0 0 0 d35 d34 d33 d32 (5) data2 d31~d24 (6) data3 d23~d16 (7) data4 d15~d8 (8) data5 d7~d0 five bytes of data may be read continuously for each address. (2) coefficient ram (cram) read (during dsp reset) field write data readout data (1) command code 0x34 (dsp1) / 0x35 (dsp2) (2) address1 0 0 0 a12 a11 a10 a9 a8 (3) address2 a7 a6 a5 a4 a3 a2 a1 a0 (4) data1 d23~d16 (5) data2 d15~d8 (6) data3 d7~d0 three bytes of data may b e read c ontinuously for each address. (3) offset reg (ofreg) read (during dsp reset) field write data readout data (1) command code 0x32 (dsp1) / 0x33 (dsp2) (2) address1 0 0 0 0 0 0 0 0 (3) address2 0 0 a5 a4 a3 a2 a1 a0 (4) data1 0 0 0 0 0 0 0 0 (5) data2 0 0 d13 d12 d11 d10 d9 d8 (6) data3 d7~d0 three bytes of data may b e read c ontinuously for each address.
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 78 - 3 - 1 - 4. read operation during run (1) cram write preparation read (during run) field write data readout data (1) command code 0x24 (dsp1) / 0x26 (dsp2) (2) address1 0 0 0 a12 a11 a10 a9 a8 (3) address2 a7 a6 a5 a4 a3 a2 a1 a0 (4) data1 d23~d16 (5) data2 d15~d8 (6) data3 d7~d0 (2) ofreg write preparation read (during run) field write data readout data (1) command code 0x25 (dsp1) / 0x27 (dsp2) (2) address1 0 0 0 0 0 0 0 0 (3) address2 0 0 a5 a4 a3 a2 a1 a0 (4) data1 0 0 0 0 0 0 0 0 (5) data2 0 0 d13 d12 d11 d10 d9 d8 (6) data3 d7~d0 (3) mir register read (during run) field write data readout data (1) command code 0x76 (dsp1) / 0x77 (dsp2) (2) address1 0 0 0 0 0 0 0 0 (3) address2 0 0 0 0 0 0 0 0 (4) data1 d27~d20 (5) data2 d19~d12 (6) data3 d11~d4 (7) data4 d3 d2 d1 d0 (flag3) (flag2) (flag1) (flag0) mir register sequential read for dsp1/dsp2 . max 8 data (32 bytes) may b e read c ontinuously . the data is 28 - bit msb justified. lower 4 bits are validity flags ; the data is valid only when all flags are zero.
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 79 - 3 - 2 . register write and read 3 - 2 - 1. register write (1) control register write field write data (1) command code 0xc0 (2) address1 a15~a8 (3) address2 a7~a0 (4) data d7~d0 one byte of data may be written continuously for each address. (2) external conditional jump code (jx register) write field write data (1) command code 0xf4 (dsp1) / 0xf5 (dsp2) (2) address1 0 0 0 0 0 0 0 0 (3) address2 0 0 0 0 0 0 0 0 (4) data d7~d0 (3) crc code write field write data (1) command code 0xf2 (2) address1 0 0 0 0 0 0 0 0 (3) address2 0 0 0 0 0 0 0 0 (4) data1 d15~d8 (5) data2 d7~d0
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 80 - 3 - 2 - 2. register read (1) control register read field write data readout data (1) command code 0x40 (2) address1 a15~a8 (3) address2 a7~a0 (4) data d7~d0 one byte of data may be written continuously for each address. ( 2 ) crc code read field write data readout data (1) command code 0x72 (2) address1 0 0 0 0 0 0 0 0 (3) address2 0 0 0 0 0 0 0 0 (4) data1 d15~d8 (5) data2 d7~d0
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 81 - 4. ram and register write/read timing 4 - 1. ram writ e timing during dsp reset write to program ram (pram), coeffici ent ram (cram) and offset reg (ofreg) duri ng dsp reset in the order of command code (8 bits) , address (16 bits) and data. when writing the data to consecutive address locations, continue to input data only. a ddress is incremented by 1 automatically. figure 55 . writing to ram at consecutive address locations (spi) figure 56 . writing to ram at random address locations (spi) cs n si sclk d x reset n bit rdy = h command address data data data data data dont care (l/h) dont care (l/h) (x=1,2) cs n si sclk rdy = h command address data command address data dont care (l/h) dont care (l/h) dont care (l/h) dxreset n bit (x=1,2 )
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 82 - 4 - 2. ram write timing during run these operations described below are to rewrite the coefficient ram (cram) and offset reg (ofreg) during run. data writing is executed in two steps; write preparation and write execution. the written data can be confirmed by reading the write preparation data. (1) write preparation afte r inputting the assigned command code (8 bits) to select the number of data from 1 to 16, input the starting address of writ e (16 bits) and the number of data assigned by command code in this order. (2) write preparation data confirmation after write preparation, prepared data for writing can be confirmed. address and d ata are read in this order by write preparation data confirmation command 24 h /26h (cram) or 25h /27h (ofreg) . the data will be 0x000001 when reading more than write prep aration data. execute write preparation again w hen the address and data are disturbed by external noise. (3) write execution upon completion of the above operation, execute a ram write during run by inputting the corresponding command code and address (16 bits, all 0) in this order. note * 65 . execute write p reparation and write preparation data confirmation before w rite e xecution. a write preparation data confirmation sequence can be skipped , but a malfunction occurs w hen executing write execution to ram without a w rite p reparation sequence . access operation by a microcontroller is prohibited until rdy changes to h. write modification of the ram content is executed whenever the ram address for modification is accessed . for exampl e, when 5 d ata are written, from ram address 10, it is executed as shown below. ram execution address 7 8 9 10 11 13 16 11 12 13 14 15 address 13 is not executed until rewriting address 12. figure 57 . cram/ofreg write preparation (spi) csn si sclk command c ode address rdy = h data 0 ( ex. ) when # of data is 4 cram 0x80( # of data: 1 ) ~ 0x8f ( # of data: 16 ) ofreg 0x90( # of data: 1 ) ~ 0x9f( # of data: 16 ) cram command code 0x83 of reg command code 0x93 dont care (l/h) data 1 data n - 1 data n dont care (l/h) dx reset n bit= 1 ( x= 1, 2 )
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 83 - figure 58 . cram/ofreg write preparation data read (spi) figure 59 . cram/ofreg write (spi) notes * 67 . the rdy pin rises to h in two lrck cycles at maximum if the dsp program is designed to access the modification address in every sampling cycle . the rdy signal keeps l level even if a write command is completed internally w hile csn is l level . * 68 . writing to a cram or ofreg address that is not used in the dsp program is prohibited during run. if it is executed, the rdy pin keeps l output until the pdn pin becomes l . in the case of i 2 c interface mode, communication will not be made correctly after that. * 67 si sclk rdy= h command address data data data data dat a so dont care (l/h) dont care (l/h) cs n hi - z hi - z dxresetn bit= 1 (x=1,2) cram : 2 4 h /26h , o freg : 25h /27h rdylg cs n si sclk command max 400ns rdy cram : a4 h /a 5 h , ofreg : a2 h /a3 h 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 dontcare (l/h) dxresetn bit= 1 (x=1,2)
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 84 - 4 - 3. external conditional jump external conditional jump code writing (1) command 0x f4 (dsp1) / 0xf5 (dsp2) (2) address0 0 0 0 0 0 0 0 0 (3) address1 0 0 0 0 0 0 0 0 (4) data d7~d0 an external conditional jump code can be input during both dsp reset and run. input data is set to the designated register on the rising edge of lrc k assigned to the dsp . the rdy pin changes to l when the command code is transferred, and it changes to h when write operations are completed. this jump code is reset to 0 by setting th e pdn pin to l, but it is not reset by dsp reset or clock reset . a dsp instruction setting is necessary when using external conditional jump code. figure 60 . external conditional jump timing (spi) f4h / f5h cs n sclk si rdy dontcare (l/h) dontcare (l/h) 00h 00h d7 d0
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 85 - i 2 c interface access to the ak 773 5 registers and ram can be controlled by an i2c bus. the ak 773 5 supports fast - mode i 2 c - bus (max: 400khz) and fast - mode plus (max: 1mhz) . si/i2cfil pin bus mode l fast mode h fast mode plus table 34 . i 2 c bus mode setting note * 69 . the csn pin and the si/i2cfil pin must be fixed to l or h when using i 2 c interface. the ak773 5 does not support hs mode (max: 3.4mhz) . 1. data transfer in order to access any ic devices on the i 2 c bus, input a start condition first, followed by one byte of slave address which includes the device address. ic devices on the bus compare this device address with their own address es and the ic device which has an identical address with the device address generates an acknowledgement. an ic device with the identical address then executes either a read or a write operation. after the command execution, input a stop condition. 1 - 1. data change change the data on the sda line while the scl line is l. the sda line condition must be stable and fixed while the clock is h. change the data line condition between h and l only when the clock signal on the scl line is l. change the sda line condition while the scl line is h only when the start condit ion or stop condition is input. figure 61 . data change i 2 c ) 1 - 2. start condition and stop condition a start condition is generated by the transition of h to l on the sda line while the scl line is h. all instructions are initiated by a start condition. a stop condition is generated by the transition of l to h on the sda line while the scl line is h. all instructions end by a stop condition. figure 62 . start condition and stop condition ( i 2 c ) scl sda data line stable : data valid change of data allowed scl sda stop condition start condition
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 86 - 1 - 3. repeated start condition when a start condition is received again instead of a stop condition, the bus changes to a repeated start condition. a repeated start condition is functionally the same as a start condition. figure 63 . repeated start condition ( i 2 c ) 1 - 4. acknowledge the ic device that sends data releases the sda line (h) after sending one byte of data. the ic device that receives data then sets the sda line to l at the next clock. this operation is called acknowledgement, and it enables verification that the data transfer has been properly executed. the ak 773 5 generates an acknowledgement upon receipt of a start condition and a slave address. for a write instruction, an acknowledgement is generated whenever receipt of each byte is completed. for a r ead instruction, succeeded by generation of an acknowledgement, the ak 773 5 releases the sda line after outputting data at the designated address, and it monitors the sda line condition. when the master side generates an acknowledgement without sending a st op condition, the ak 773 5 outputs data at the next address location. when no acknowledgement is generated, the ak 773 5 ends data output (not acknowledged). figure 64 . generation of acknowledgement ( i 2 c ) scl sda repeated start condition start condition scl fro m master acknowledge data output by transmitter data output by receiver 1 9 8 start condition clock pulse for acknowledge not acknowledge
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 87 - 1 - 5. the first byte the first byte, which includes the slave - address, is input after the start condition is set, and a target ic device that will be accessed on the bus is selected by the slave - address. when the slave - address is inputted, an external device that has the iden tical device address generates an acknowledgement and instructions are then executed. the 8 th bit of the first byte (lowest bit) is allocated as the r/w bit. when the r/w bit is 1, the read instruction is executed, and when it is 0, the write instructi on is executed. the slave - address of the ak773 5 is set by the csn pin. csn pin = h csn pin = l figure 65 . first byte configuration ( i 2 c ) note * 70 . in this document, there is a case that describes a write slave - address assignment when both address bits match and a slave - address at r/w bit = 0 is received. there is a case that describes read slave - address assignment when both address bit s matches and a s lave - address at r/w bit = 1 is received. 1 - 6. the second and succeeding bytes the data format of the second and succeeding bytes of the ak 773 5 transfer / receive serial data (command code, address and data in microcontroller interface format) on the i 2 c bus are all configured with a multiple of 8 - bits. when transferring or receiving those data on the i 2 c bus, they are divided into an 8 - bit data stream segment and they are transferred / received with the msb side data first with an acknowledgement in - be tween. example ) when transferring / receiving a1b2c3 (hex) 24 - bit serial data in microprocessor interface format: figure 66 . division of data ( i 2 c ) note * 71 . in this document, there is a case that describes a write instruction command code which is received at the second byte as write command. there is a case that describes a read instruction command code which is received at the second byte as read command. 0 0 1 1 0 0 0 r/w 0 0 1 1 1 0 0 r/w a1 b2 c3 a1 b2 c3 a a 24bit 8bit 8bit 8bit a acknowledge (1) microcomputer format (1) i 2 c format
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 88 - 2. write sequence in the ak 773 5 , when a write - slave - address assignment is received at the first byte, the write command at the second byte, the address at the third and fourth bytes, and data at the fifth and succeeding bytes are received. the number of write data bytes is fixed by the received command code. figure 67 . write sequence ( i 2 c ) 3. read sequence in the ak 773 5 , when a write - slave - address assignment is received at the first byte, the rea d command at the second byte and the address at the third and fourth bytes are receive d. when the fourth byte is received and an acknowledgement is transferred, the read command waits for the next restart condition. when a read slave - address assignment is received at the first byte, data is transferred at the second and succeeding bytes. the number of readable data bytes is fixed by the received read command. after reading the last byte, assure that a not acknowledged signal is received. if this not acknowledged signal is not received, the ak 773 5 continues to send data regardless whether data is present or not, and since it did not release the bus, the stop condition cannot be properly received. f igure 68 . read sequence ( i 2 c ) sda command code s slave address address(0) address(1) data( 0 ) data( 1 ) data( n ) p r/w= 0 t r s a t a c k a c k a c k a c k a c k a c k a c k a c k s t o p sda command code address(0) address(1) p r/w= 0 t r s a t a c k a c k a c k a c k s t o p s slave address r/w= 1 e a s t r t r da ta( 0 ) data( 1 ) a c k a c k s slave address data( n ) a c k a c k m t a s e r m t a s e r m t a s e r m t a s e r n a c k
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 89 - 4. not acknowledg e the ak 773 5 cannot receive instructions while the rdy pin (data write ready pin) is at a low level. the maximum transition time of the rdy pin from low level to high lev el is 2 lrck . it is possible to confirm in a faster cycle than 2 x lrck that the rdy pin become s high by checking the ak773 5 internal condition, which is made by verifying the acknowledgement. 4 - 1. generation of not acknowledge the ak 773 5 does not accept command codes until the rdy pin become s high, when a command is received to set the rdy pin to a low level. in order to confirm the rdy pin condition, a write slave - address assignment should be sent after the start condition. if the rdy pin is then at a low level, acknowledgement is not generated at the succeeding clock (generation of not acknowledged). after sending not acknowledged, the bus is released and all receiving data are ignored until the next start condition (behaves as if it received slave address of other device). 4 - 2. when read slave - address assignment is received without receiving read command code data read in the ak 773 5 can be made only in the previously documented read sequence. data cannot be read out without receiving a read command code. in the ak 773 5 , a not acknowledged is generated when a read slave - address assignment without proper receipt of read command is r eceived. 5. limitation in use of i2c interface the ak7735 does not operate in hs mode (max: 3.4mhz). the ak773 5 s upports f ast mode (max: 400 k hz) and fast plus mode (max: 1mhz) . note * 72 . do not turn off the power of the ak 773 5 whenever the power supplies of other devices of the same system are turned on. p u ll - up resistors of sda and scl pins should be connected to tvdd or less voltage . (the diode s against tvdd exist in the sda and scl pins.)
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 90 - s i mple write error check the ak 773 5 have a cyclic redundancy check (crc) function for a simple checking of writing data for ram and registers. 1. checked data 1 - 1. spi interface s i data during csn = l is checked. ? serial data d(x): si data which is input during a period from a falling edge to a rising edge of csn ? generator polynomial g(x)=x 16 +x 12 +x 5 +1 ( divisor=0x1021, d efault=0 , msb - first, not inverted) ? the remainder of d(x) divided by g(x) is r(x). 1 - 2. i 2 c interface command code, address and data from the second byte are checked. (acknowledge is not included. therefore, the checked result will be the same as the spi interface if the same command code, address and data are written.) the first byte which includes a slave address is not checked. it can be checked by acknowle dge. ? serial data d(x): command code, address and data (slave address is not included) ? generator polynomial g(x) =x 16 +x 12 +x 5 +1 ( divisor=0x1021, d efault=0 , msb - first, not inverted) ? the remainder of d(x) divided by g(x) is r(x). 2. simple write error check sequence there are two ways to check write error. 2 - 1. crc result (1) write serial data d(x) to be checked. (2) read out a crc result (remainder r(x)) by the command code 72 h . (3) check the result by a microprocessor. (4) when checking other serial data, repeat the sequence from (1) to (3). note * 73 . the internal crc result is not updated by command code 72 h . 2 - 2. sto pin state (1) set control register crce bit to 1. (2) write serial data d(x) to be checked. (3) write the r(x) value to registers by the command code f2 h . (4) if the remainder of d(x) divided by g(x) is equal to r(x), the sto pin outputs h. if not, it outputs l. (5) when checking other serial data, repeat the sequence from (2) to (4). note * 74 . the sto pin keeps outputting l until a correct value of r(x) is written in sequence (3).
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 91 - dsp block 1. settings of dsp memory the ak773 5 integrates two dsps (dsp1 and dsp2) which have the same architecture . the dsp1 and the dsp2 share program ram (pram), coefficient ram (cram) data ram (dram) and delay ram (dlram). assigned memory area for each dsp is set by register settings. both dsps must be in reset state when setting memory assignment . pramdiv bit control s pram assignment for dsp1 and dsp2. cramdiv[1:0] bits control cram assignment, dramdiv bit control s dram assignment and dlramdiv[ 1 :0] bits control d l ram assignment. mode pramdiv bit dsp1 dsp2 0 0 2048 word 2048 word (default) 1 1 4096 word reset table 35 . pram assignment for dsp1 and dsp2 note * 75 . the dsp2 must be reset when setting to mode 1 ( pramdiv bit = 1 ) . mode cramdiv[1:0] bits dsp1 dsp2 0 00 4096 word 2048 word (default) 1 01 2048 word 4096 word 2 10 6144 word reset 3 11 n/a n/a table 36 . cram assignment for dsp1 and dsp2 (n/a: not available) note * 76 . the dsp2 must be reset when setting to mode 2 ( cramdiv[1:0] bits = 10 ) . mode dramdiv bit dsp1 dsp2 0 0 2048 word 2048 word (default) 1 1 4096 word reset table 37 . dram assignment for dsp1 and dsp2 note * 77 . the dsp2 must be reset when setting to mode 1 ( dramdiv bit = 1 ) . mode dlramdiv[1:0] bits dsp1 dsp2 0 00 12288 word not connected (default) 1 01 8192 word 4096 word 2 10 4096 word 8192 word 3 11 not connected 12288 word table 38 . dlram assignment for dsp1 and dsp2 note * 78 . the dsp1 and dsp2 can be operated without connecting to dlram . however, program access to dlram is not permitted.
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 92 - bank size and bank addressing mode of dram, that is assigned, can be set independently for the dsp1 and the dsp2. dram bank size s for d sp1 and dsp2 are controlled by d1drmbk[1:0] bits and d2drmbk[1:0] bits, respectively. mode d1drmbk[1:0] bits d2drmbk[1:0] bits bank 1 size bank 0 size 0 00 1024 rest of area (default) 1 01 2048 rest of area 2 10 3072 rest of area 3 11 n/a n/a table 39 . dram bank size setting for dsp1 and dsp2 (n/a: not available) dram bank addressing mode s for dsp1 and dsp2 are controlled by d1drma[1:0] bits and d2drma[ 1:0] bits, respectively. mode d1drma[1:0] bits d2drma[1:0] bits bank 1 (dp1) bank 0 (dp0) 0 00 ring ring (default) 1 01 ring linear 2 10 linear ring 3 11 linear linear table 40 . dram bank addressing mode setting for dsp1 and dsp2 bank size and bank addressing mode of dlram, that is assigned, can be set independently for the dsp1 and dsp2. dlram bank size s for dsp1 and dsp2 are controlled by d1dlrmbk[ 2 :0] bits and d2dlrmbk[ 2 :0] bits, respectively. mode d1dlrmbk [2:0] bits d2dlrmbk [2:0] bits bank 1 size bank 0 size 0 000 0 rest of area (default) 1 001 2048 word rest of area 2 010 4096 word rest of area 3 011 6144 word rest of area 4 100 8192 word rest of area 5 101 10240 word rest of area 6 110 12288 word 0 7 111 n/a n/a table 41 . dlram bank size setting for dsp1 and dsp2 (n/a: not available) dlram bank addressing mode s for dsp1 and dsp2 are controlled by d1dlrma bit and d2dlrma bit, respectively. mode d1dlrma bit d2dlrma bit bank 1 bank 0 0 0 ring ring (default) 1 1 linear ring table 42 . dlram bank addressing mode setting for dsp1 and dsp2
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 93 - sampling mode of dlram bank 0 for the dsp1 and dsp2 are controlled by d1ss[1:0] bits and d2ss[1:0] bits, respectively. mode d1ss[1:0] bits d2ss[1:0] bits sampling mode of dlram bank 0 0 00 update address in every sampling (default) 1 01 update address in every 2 samplings 2 10 update address in every 4 samplings 3 11 update address in every 8 samplings table 43 . dlram bank0 sampling mode setting of dsp1/dsp2 the dsp1 and dsp2 are able to generate a trigonometric cos table for trigonometric processing. input 1/4 cycle data of the cos table to cram and the dsp generates rest of 3/4 cycle data automatically. cos tab le length for cram input is variable according to the cycle resolution setting. the cycle resolution of dsp1 and dsp2 is controlled by d1wavp[2:0] bits and d2wavp[2:0] bits, respectively. mode d1wavp[2:0] bits d2wavp[2:0] bits cycle resolution cos table length 0 000 128 points 33 word (default) 1 001 256 points 65 word 2 010 512 points 129 word 3 011 1024 points 257 word 4 100 2048 points 513 word 5 101 4096 points 1025 word 6 110 n/a n/a 7 111 n/a n/a table 44 . cycle resolution setting of trigonometric table for dsp1/dsp2 (n/a: not available) 2. soft src function dout 1 port of dsp1 has a built - in fifo to realize synchronous src program for sampling rate conversion . the out put data of d out1 port of dsp1 can be up s ampled by the fifo . a dsp filtering process is necessary when using the s oft src function. the s oft src is capable of integral multiple conversion of a sampling rate between two synchronized clock sync d omains , supporting 6 times up sampling at maximum . figure 69 . dsp1 soft src function dsp1 up sampling ( 6 word fifo x2 ) dout1 dout2 dout3 dout4 dout5 dout6 din1 din2 din3 din4 din5 din6
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 94 - analog input block 1. microphone input gain the ak 7735 has gain amplifiers for microphone input. the gain of l and r channels can be independently selected by mgnl[3:0] and mgnr[3:0] bits ( table 45 ) . the i nput impedance is typ. 20k ? when adc1vl/r bits is 0 and it is typ.25 k ? when adc1vl/r bits are 1 . this gain amplifier executes zero crossing detection when changing the gain by setting miclzce bit = 1 / micrzce bit = 1 . zero crossing detection is executed independently for l and r channels. zero crossing timeout period is 16ms ( @fs=48k hz base) . when miclzce bit = 0 / micrzce bit = 0 , the volume is changed immediately by register settings. when writing to mgnl/r[3:0] bits continu ously , take an interval of zero cross ing timeout period or more. if the mgnl/r[3:0] bits are changed before zero crossing, the volume of lch and rch may differ. when the volume level that is same as the present volume is set, the ze ro crossing counter is not reset and time out s according to the previous writing timing. therefore , in this case, writing to mgnl/r [3:0] bits continuously is possible with a shorter interval of the zero crossing timeout period. 1 - 1. microphone gain mode mgnl[3] mgnr[3] mgnl[2] mgnr[2] mgnl[1] mgnr[1] mgnl[0] mgnr[0] input gain 0 0 0 0 0 0db (default) 1 0 0 0 1 2db 2 0 0 1 0 4db 3 0 0 1 1 6db 4 0 1 0 0 8db 5 0 1 0 1 10db 6 0 1 1 0 12db 7 0 1 1 1 14db 8 1 0 0 0 16db 9 1 0 0 1 18db a 1 0 1 0 21db b 1 0 1 1 24db c 1 1 0 0 27db d 1 1 0 1 30db e 1 1 1 0 33db f 1 1 1 1 36db table 45 . microphone input gain 1 - 2. zero crossing timeout the microphone gain is changed independently on the timing of zero crossing detection or zero crossing timeout. 48khz base 44.1khz base zero crossing timeout period 16ms 17.4ms table 46 . zero crossing timeout period
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 95 - 1 - 3. start - up time of mic input pin the ak7735 sta rts to charge a dc cut capacitor when the pdn pin is set to h from l . since the input impedanc e is 25k , the time constant will be 25ms if the dc cut capacitor is 1 f. a wait time of about 100ms should be taken before power up the adc to charge the dc cut capacitor sufficiently. a click noise may occur just after the adc is powered up if this wait time is n ot enough . 2. microphone input selector t h e ak773 5 has microphone input selectors. each microphone amplifier input is selectable between single - ended input and differential input by ad1lsel bi t or ad1rsel bit . figure 70 . microphone input selector ad1lsel bit adc lch ad1rsel bit adc rch 0 inp1/inn1 (default) 0 inp2/inn2 (default) 1 ain1l 1 ain1r table 47 . microphone input selector note * 79 . when using differential input mode, it is prohibited to input signal to only one side like pseudo differential input. ain 1l / inp1 pin ak773 5 mic - amp rch inn1 pin adc lch ad1lsel bit mic - amp lch adc rch ain 1r / inp2 pin inn2 pin ad1rsel bit
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 96 - 3. microphone bias output the ak773 5 has a line of microphone bias output. the power supply of microphone is supplied from the mpwr pin by setting pmmb bit = 1 . the output voltage is 2.5v (avdd=3.3v) and the load resistance is min. 2k . pmmb bit mpwr pin 0 hi - z (default) 1 output table 48 . microphone bias output figure 71 . mic block circuit (differential input) figure 72 . mic block circuit (single - end input) inp1 ak773 5 microphone 100 n f 4.7k mpwr pin pmmb bit mic - amp lch inn1 microphone 4.7k 4.7 k 4.7k inp2 inn2 mic - amp rch 100nf ain 1l ak773 5 microphone 100 n f mpwr pin pmmb bit mic - amp lch microphone 4.7 k 4.7 k ain 1r mic - amp rch 100nf
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 97 - adc block 1. adc block high pass filter the ak773 5 has a digital high pass filter (hpf) for dc offset cancelling of each adc. the cut - off fr equency of the hpf is about 0.9 hz (fs=48khz) , depending on operation frequency. 2. adc digital volume the ak773 5 has independent digital volume controls for lch and rch (256 levels, 0.5db steps) of each adc. adc1 volad1l[7:0] adc1 volad1r[7:0] adc2 volad2l[7:0] adc2 volad2r[7:0] attenuation level 00h 00h 00h 00h +24.0db 01h 01h 01h 01h +23.5db 02h 02h 02h 02h +23.0db : : : : : 2fh 2fh 2fh 2fh +0.5db 30h 30h 30h 30h 0.0db (default) 31h 31h 31h 31h - 0.5db : : : : : fdh fdh fdh fdh - 102.5db feh feh feh feh - 103.0db ffh ffh ffh ffh mute ( - n pin goes to l , the volume of each adc channel is initialized to 30h . atspad bit 00h ?
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 98 - code db code db code db code db code db code db code db code db 00h 24.0 20h 8.0 40h - 8.0 60h - 24.0 80h - 40.0 a0h - 56.0 c0h - 72.0 e0h - 88.0 01h 23.5 21h 7.5 41h - 8.5 61h - 24.5 81h - 40.5 a1h - 56.5 c1h - 72.5 e1h - 88.5 02h 23.0 22h 7.0 42h - 9.0 62h - 25.0 82h - 41.0 a2h - 57.0 c2h - 73.0 e2h - 89.0 03h 22.5 23h 6.5 43h - 9.5 63h - 25.5 83h - 41.5 a3h - 57.5 c3h - 73.5 e3h - 89.5 04h 22.0 24h 6.0 44h - 10.0 64h - 26.0 84h - 42.0 a4h - 58.0 c4h - 74.0 e4h - 90.0 05h 21.5 25h 5.5 45h - 10.5 65h - 26.5 85h - 42.5 a5h - 58.5 c5h - 74.5 e5h - 90.5 06h 21.0 26h 5.0 46h - 11.0 66h - 27.0 86h - 43.0 a6h - 59.0 c6h - 75.0 e6h - 91.0 07h 20.5 27h 4.5 47h - 11.5 67h - 27.5 87h - 43.5 a7h - 59.5 c7h - 75.5 e7h - 91.5 08h 20.0 28h 4.0 48h - 12.0 68h - 28.0 88h - 44.0 a8h - 60.0 c8h - 76.0 e8h - 92.0 09h 19.5 29h 3.5 49h - 12.5 69h - 28.5 89h - 44.5 a9h - 60.5 c9h - 76.5 e9h - 92.5 0ah 19.0 2ah 3.0 4ah - 13.0 6ah - 29.0 8ah - 45.0 aah - 61.0 cah - 77.0 eah - 93.0 0bh 18.5 2bh 2.5 4bh - 13.5 6bh - 29.5 8bh - 45.5 abh - 61.5 cbh - 77.5 ebh - 93.5 0ch 18.0 2ch 2.0 4ch - 14.0 6ch - 30.0 8ch - 46.0 ach - 62.0 cch - 78.0 ech - 94.0 0dh 17.5 2dh 1.5 4dh - 14.5 6dh - 30.5 8dh - 46.5 adh - 62.5 cdh - 78.5 edh - 94.5 0eh 17.0 2eh 1.0 4eh - 15.0 6eh - 31.0 8eh - 47.0 aeh - 63.0 ceh - 79.0 eeh - 95.0 0fh 16.5 2fh 0.5 4fh - 15.5 6fh - 31.5 8fh - 47.5 afh - 63.5 cfh - 79.5 efh - 95.5 10h 16.0 30h 0.0 50h - 16.0 70h - 32.0 90h - 48.0 b0h - 64.0 d0h - 80.0 f0h - 96.0 11h 15.5 31h - 0.5 51h - 16.5 71h - 32.5 91h - 48.5 b1h - 64.5 d1h - 80.5 f1h - 96.5 12h 15.0 32h - 1.0 52h - 17.0 72h - 33.0 92h - 49.0 b2h - 65.0 d2h - 81.0 f2h - 97.0 13h 14.5 33h - 1.5 53h - 17.5 73h - 33.5 93h - 49.5 b3h - 65.5 d3h - 81.5 f3h - 97.5 14h 14.0 34h - 2.0 54h - 18.0 74h - 34.0 94h - 50.0 b4h - 66.0 d4h - 82.0 f4h - 98.0 15h 13.5 35h - 2.5 55h - 18.5 75h - 34.5 95h - 50.5 b5h - 66.5 d5h - 82.5 f5h - 98.5 16h 13.0 36h - 3.0 56h - 19.0 76h - 35.0 96h - 51.0 b6h - 67.0 d6h - 83.0 f6h - 99.0 17h 12.5 37h - 3.5 57h - 19.5 77h - 35.5 97h - 51.5 b7h - 67.5 d7h - 83.5 f7h - 99.5 18h 12.0 38h - 4.0 58h - 20.0 78h - 36.0 98h - 52.0 b8h - 68.0 d8h - 84.0 f8h - 100.0 19h 11.5 39h - 4.5 59h - 20.5 79h - 36.5 99h - 52.5 b9h - 68.5 d9h - 84.5 f9h - 100.5 1ah 11.0 3ah - 5.0 5ah - 21.0 7ah - 37.0 9ah - 53.0 bah - 69.0 dah - 85.0 fah - 101.0 1bh 10.5 3bh - 5.5 5bh - 21.5 7bh - 37.5 9bh - 53.5 bbh - 69.5 dbh - 85.5 fbh - 101.5 1ch 10.0 3ch - .6.0 5ch - 22.0 7ch - 38.0 9ch - 54.0 bch - 70.0 dch - 86.0 fch - 102.0 1dh 9.5 3dh - 6.5 5dh - 22.5 7dh - 38.5 9dh - 54.5 bdh - 70.5 ddh - 86.5 fdh - 102.5 1eh 9.0 3eh - 7.0 5eh - 23.0 7eh - 39.0 9eh - 55.0 beh - 71.0 deh - 87.0 feh - 103.0 1fh 8.5 3fh - 7.5 5fh - 23.5 7fh - 39.5 9fh - 55.5 bfh - 71.5 dfh - 87.5 ffh mute table 52 . adc digital volume settings
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 99 - 3. adc soft mute the adc block has a di gital soft mute circuit. the soft mute operation is performed at digital domain. the output signal is attenuated to - in att setting level x att transition time from the current adc digital volume setting level by setting ad 1 mute bit or ad2mute bit to 1. when the ad1mute bit or ad2mute bit return s to 0, the mute is cancelled and the output attenuati on level gradually changes to att setting level in att setting level x att transition time. if the soft mute is cancelled before attenuating to - after starting the operation, the attenuation is discontinued and the volume level return s to original volu me setting l evel by the same cycle. the soft mute is effectiv e for changing the signal source without stopping the signal transmission. the attenuation level transition takes 828/fs from 0db to - and from - to 0db. soft mute function is available when e ach adc is in operation . the attenuation value is initialized by setting the pdn pin = l . figure 73 . adc soft mute 4. adc2 input selector adc 2 of the ak77 35 has an input selector for 1 stereo differential input and 2 stereo single - ended input s . these inputs are selected by ad2sel[1:0] bits . in the case that these registers are changed during operation, mute output signal to reduce switching noise as needed. mode ad2sel[1:0] bits selected pin 0 00 ain2lp , ain2ln , ain2rp , ain2rn (default) 1 01 ain3l , ain3r 2 10 ain4l , ain4r 3 11 n/a table 53 . adc2 input select (n/a: not available) note * 80 . when using differential input mode, it is prohibited to input signal to only one side like pseudo differential input. ad1mute , ad 2mut e , - db 0db attenuation level output image group delay ( gd ) gd 828/fs 828/fs
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 100 - 4 - 1 . input s elector s witching s equence the input selector should be changed after enabling soft mute function to avoid the switching noise of the input selector. adc2 in put selector switching sequence : 1) enable s oft m ute function before c hanging c hannel 2) change channel 3) disable soft mute function figure 74 . adc2 input channel switching sequence example the period of (1) vari es according to the setting value of the datt level . transition time of attenuation level from 0db to - ? is shown below. atspad bit (1) period ( max ) lrck cycle fs=48khz fs=44.1khz fs=8khz 0 828/fs 17.25ms 18.78ms 103.5ms (default) 1 828/fs x 4 69ms 75.10ms 414ms t he input channel should be changed during the period (2). an interval around 2 00ms is needed before releasing the soft mute after changing the channel (period (3)). 5. adc digital filter select the ak773 5 has four kinds of digital filters in adc block. adsd and adsl bits select a digital filter. adc1 and adc2 have a common setting for digital filter. mode adsd bit adsl bit digital filter 0 0 0 sharp roll - off filter (default) 1 0 1 slow roll - off filter 2 1 0 short delay sharp roll - off filter 3 1 1 short delay slow roll - off filter table 54 . adc digital filter select attenuation channel datt level - (1) (2) in 3 l/in 3 r in 4 l/in 4 r (1) (3) ad 2 mute bit
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 101 - 6. adc input volume selection single - ended input amplitude (differential input amplitude) of adc1 l/rch and adc2 l/rch can be switched between 2.3vpp ( 2.3vpp) and 2.83vpp ( 2.83vpp) by adc1vl/r bit and adc2v l /r bit , respectively. mode adc1vl bit / adc1vr bit adc2vl bit / adc2vr bit input full scale voltage single - end input differential input 0 0 2.3vpp 2.3vpp (default) 1 1 2.83vpp 2.83vpp table 55 . adc input full scale voltage selection
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 102 - dac block 1. dac digital volume the ak773 5 has channel - independent digital volume controls in dac block . (256 levels, 0.5 steps) dac1 lch volda1l[7:0] dac1 rch volda1r[7:0] dac2 lch volda2l[7:0] dac2 rch volda2r[7:0] attenuation level 00h 00h 00h 00h +12.0db 01h 01h 01h 01h +11.5db 02h 02h 02h 02h +11.0db : : : : : 17h 17h 17h 17h +0.5db 18h 18h 18h 18h 0.0db (default) 19h 19h 19h 19h - 0.5db : : : : : fdh fdh fdh fdh - 114.5db feh feh feh feh - 115.0db ffh ffh ffh ffh mute ( - ) pin is set to l, the vold a1 l[7:0], vold a1 r[7:0], vold a2 l[7:0] and vold a2 r[7:0] bits are initialized to 18h. atspda bit 00h ? ? ffh )
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 103 - table 59 . dac digital volume level setting code db code db code db code db code db code db code db code db 00h 12.0 20h - 4.0 40h - 20.0 60h - 36.0 80h - 52.0 a0h - 68.0 c0h - 84.0 e0h - 100.0 01h 11. 5 21h - 4.5 41h - 20.5 61h - 36.5 81h - 52.5 a1h - 68.5 c1h - 84.5 e1h - 100.5 02h 11.0 22h - 5.0 42h - 21.0 62h - 37.0 82h - 53.0 a2h - 69.0 c2h - 85.0 e2h - 101.0 03h 10.5 23h - 5.5 43h - 21.5 63h - 37.5 83h - 53.5 a3h - 69.5 c3h - 85.5 e3h - 101.5 04h 10.0 24h - .6.0 44h - 22.0 64h - 38.0 84h - 54.0 a4h - 70.0 c4h - 86.0 e4h - 102.0 05h 9.5 25h - 6.5 45h - 22.5 65h - 38.5 85h - 54.5 a5h - 70.5 c5h - 86.5 e5h - 102.5 06h 9.0 26h - 7.0 46h - 23.0 66h - 39.0 86h - 55.0 a6h - 71.0 c6h - 87.0 e6h - 103.0 07h 8.5 27h - 7.5 47h - 23.5 67h - 39.5 87h - 55.5 a7h - 71.5 c7h - 87.5 e7h - 103.5 08h 8.0 28h - 8.0 48h - 24.0 68h - 40.0 88h - 56.0 a8h - 72.0 c8h - 88.0 e8h - 104.0 09h 7.5 29h - 8.5 49h - 24.5 69h - 40.5 89h - 56.5 a9h - 72.5 c9h - 88.5 e9h - 104.5 0ah 7.0 2ah - 9.0 4ah - 25.0 6ah - 41.0 8ah - 57.0 aah - 73.0 cah - 89.0 eah - 105.0 0bh 6.5 2bh - 9.5 4bh - 25.5 6bh - 41.5 8bh - 57.5 abh - 73.5 cbh - 89.5 ebh - 105.5 0ch 6.0 2ch - 10.0 4ch - 26.0 6ch - 42.0 8ch - 58.0 ach - 74.0 cch - 90.0 ech - 106.0 0dh 5.5 2dh - 10.5 4dh - 26.5 6dh - 42.5 8dh - 58.5 adh - 74.5 cdh - 90.5 edh - 106.5 0eh 5.0 2eh - 11.0 4eh - 27.0 6eh - 43.0 8eh - 59.0 aeh - 75.0 ceh - 91.0 eeh - 107.0 0fh 4.5 2fh - 11.5 4fh - 27.5 6fh - 43.5 8fh - 59.5 afh - 75.5 cfh - 91.5 efh - 107.5 10h 4.0 30h - 12.0 50h - 28.0 70h - 44.0 90h - 60.0 b0h - 76.0 d0h - 92.0 f0h - 108.0 11h 3.5 31h - 12.5 51h - 28.5 71h - 44.5 91h - 60.5 b1h - 76.5 d1h - 92.5 f1h - 108.5 12h 3.0 32h - 13.0 52h - 29.0 72h - 45.0 92h - 61.0 b2h - 77.0 d2h - 93.0 f2h - 109.0 13h 2.5 33h - 13.5 53h - 29.5 73h - 45.5 93h - 61.5 b3h - 77.5 d3h - 93.5 f3h - 109.5 14h 2.0 34h - 14.0 54h - 30.0 74h - 46.0 94h - 62.0 b4h - 78.0 d4h - 94.0 f4h - 110.0 15h 1.5 35h - 14.5 55h - 30.5 75h - 46.5 95h - 62.5 b5h - 78.5 d5h - 94.5 f5h - 110.5 16h 1.0 36h - 15.0 56h - 31.0 76h - 47.0 96h - 63.0 b6h - 79.0 d6h - 95.0 f6h - 111.0 17h 0.5 37h - 15.5 57h - 31.5 77h - 47.5 97h - 63.5 b7h - 79.5 d7h - 95.5 f7h - 111.5 18h 0.0 38h - 16.0 58h - 32.0 78h - 48.0 98h - 64.0 b8h - 80.0 d8h - 96.0 f8h - 112.0 19h - 0.5 39h - 16.5 59h - 32.5 79h - 48.5 99h - 64.5 b9h - 80.5 d9h - 96.5 f9h - 112.5 1ah - 1.0 3ah - 17.0 5ah - 33.0 7ah - 49.0 9ah - 65.0 bah - 81.0 dah - 97.0 fah - 113.0 1bh - 1.5 3bh - 17.5 5bh - 33.5 7bh - 49.5 9bh - 65.5 bbh - 81.5 dbh - 97.5 fbh - 113.5 1ch - 2.0 3ch - 18.0 5ch - 34.0 7ch - 50.0 9ch - 66.0 bch - 82.0 dch - 98.0 fch - 114.0 1dh - 2.5 3dh - 18.5 5dh - 34.5 7dh - 50.5 9dh - 66.5 bdh - 82.5 ddh - 98.5 fdh - 114.5 1eh - 3.0 3eh - 19.0 5eh - 35.0 7eh - 51.0 9eh - 67.0 beh - 83.0 deh - 99.0 feh - 115.0 1fh - 3.5 3fh - 19.5 5fh - 35.5 7fh - 51.5 9fh - 67.5 bfh - 83.5 dfh - 99.5 ffh mute
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 104 - 2. dac soft mute the dac block has a digital soft mute circuit. the soft mute operation is performed at digital domain. the output signal is attenuated to - in att setting level x att transition time from the current dac digital volume setting level by setting da1 mute bit or da2mute bit to 1. when the da 1mute bit or da 2mute bit return s to 0, the mute is cancelled and the output attenuation level gradually changes to att sett ing level in att setting level x att transition time. if the soft mute is cancelled before attenuating to - after starting the operation, the attenuation is discontinued and the volume level return s to original volume setting level by the same cycle. th e soft mute is effective for changing the signal source without stopping the signal transmission. the attenuation level transition takes 924/fs from 0db to - and from - to 0db. soft mute function is available when each dac is in operation . the attenuation value is initialized by setting the pdn pin = l . the dac 1 (dac2) is reset by setting pmda1 bit ( pmda2 bit ) to 0 . a click noise may occur when reset the dac block and releasing the reset. the output signal should be muted externally i f the click noise adversely affects the system performance. figure 75 . dac soft mute operation da 1 mute or da2mute bit - db 0db attenuation level output image 924/fs 924/fs group delay ( gd ) gd soft mute operation
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 105 - analog ouptut pins will output vcom voltage by setting hresetn bit = 1 0 while pmdax bit is 1 . use this mode when changing system clock during dac ope ration to prevent a click noise caused by resuming dac operation after changing the system clock ( figure 76 , case1 ) . analog outputs goes to hi - z state by setting hresetn bi = 1 0 while pmdax bit is 0 . therefore a click noise may occur when resuming dac operation after changing the system clock ( figure 76 , case2 ) . the output signal should be muted externally if the click noise adversely affects the system performance. pmdax bit hresetn bit analog output 0 0 hi - z output 0 1 hi - z output 1 0 vcom voltage output 1 1 normal operation table 60 . analog ou tp ut status durin g hub reset figure 76 . analog output status during hub reset 3. dac digital f i lter select the ak773 5 has four kinds of digital filters in dac block. dasd and dasl bits select a digital filter. d ac1 and dac2 have a c ommon digital filter setting . mode dasd bit dasl bit digital filter 0 0 0 sharp roll - off filter (default) 1 0 1 slow roll - off filter 2 1 0 short delay sharp roll - off filter 3 1 1 short delay slow roll - off filter table 61 . dac digital filter select hresetn bit pmdax bit = 1 pmdax bit analog output vcom output operation start analog output hi - z output operation start case 1 case 2 click noise
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 106 - 4. dac de - emphasis filter control the ak7735 h as a digital de - emphasis filter (tc=50/15s) that correspond s to three sampling frequencies (32khz, 44.1khz and 48khz) by iir filter. the de - emphasis filter frequency is selected by demx[1:0] bits (x=1, 2) ( table 62 ). the de - emphasis filer only corresponds to the frequencies shown in table 62 . demx[1:0] bits must be set to the default setting 01 when the ak7735 is operated with other sampling frequencies. demx[1] bit demx[0] bit mode 0 0 44.1khz 0 1 off (default) 1 0 48khz 1 1 32khz table 62 . dac de - emphasis filter cont rol
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 107 - src block 1. sampling rate the ak 773 5 includes two stereo digital sampling rate converter s (src). the input sampling r ate (fsi) and the output sampling rate (fso) are supported from 8khz to 192 khz. available sampling rate ratio is fso/fsi = 0.167~6. 0. 1 - 1. up sampling ( 1.00 ? ? supported sampling rates are shown below. (passband and stopband are proportional to fsi when the fso/fsi ratios are same. ) fso fsi fso/fsi passband stopband 192khz 48khz 4.00 22.00khz 26.00khz 48khz 48khz 1.00 22.00khz 26.00khz 48khz 44.1khz 1.09 20.21khz 23.89khz 48khz 32khz 1.50 14.67khz 17.33khz 48khz 24khz 2.00 11.00khz 13.00khz 48khz 16khz 3.00 7.33khz 8.67khz 48khz 12khz 4.00 5.50khz 6.50khz 48khz 8khz 6.00 3.67khz 4.33khz 192khz 44.1khz 4.35 20.21khz 23.89khz 44.1khz 44.1khz 1.00 20.21khz 23.89khz 44.1khz 32khz 1.38 14.67khz 17.33khz 44.1khz 24khz 1.84 11.00khz 13.00khz 44.1khz 16khz 2.76 7.33khz 8.67khz 44.1khz 12khz 3.68 5.50khz 6.50khz 44.1khz 8khz 5.51 3.67khz 4.33khz 16khz 16khz 1.00 7.33khz 8.67khz 16khz 8khz 2.00 3.67khz 4.33khz 8khz 8khz 1.00 3.67khz 4.33khz table 63 . up sampling example
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 108 - 1 - 2. down sampling (0.167 ? three kinds of filter mode can be selected by srcfaud bit and srcfec bit when down sampling . supported sampling rates are shown below. (passband and stopband are proportional to fsi when the fso/fsi ratios are same. ) 1) audio mode (srcfaud bit = 1, srcfec bit = 0) fso fsi fso/fsi passband stopband 44.1khz 48khz 0.919 20.00khz 24.10khz 48khz 88.2khz 0.544 19.25khz 26.23khz 48khz 96khz 0.5 20.90khz 27.00khz 44.1khz 88.2khz 0.5 19.20khz 24.81khz 44.1khz 96khz 0.459 18.70khz 25.00khz 16khz 44.1khz 0.363 5.79khz 7.95khz 48khz 192khz 0.25 25.19khz 34.60khz 44.1khz 192khz 0.229 25.19khz 34.60khz 8khz 48khz 0.167 3.16khz 4.66khz 8khz 44.1khz 0.181 2.90khz 4.28khz table 64 . down sampling example (audio mode ) 2) voice mode ( srcfaud bit = 0, srcfec bit = 0) fso fsi fso/fsi passband stopband 24khz 32khz 0.75 10.94khz 11.95khz 16khz 24khz 0.667 7.22khz 7.97khz 16khz 32khz 0.5 7.14khz 7.97khz 8khz 16khz 0.5 3.57khz 3.98khz 16khz 48khz 0.333 6.80khz 7.97khz 8khz 32khz 0.25 3.26khz 3.99khz table 65 . down sampling example (voice mode ) 3) echo canceller mode (srcfec bit = 1) in e cho c anceller mode, t he input signal should be attenuated sufficiently for more than fso/2 frequency . fso fsi fso/fsi passband stopband 32khz 44.1khz 0.726 20.21 khz 23. 89 khz 32khz 48khz 0.667 22.00 khz 26.00k hz 24khz 44.1khz 0.544 20.21 khz 23. 89 khz 24khz 48khz 0.5 22.00 khz 26.00k hz 16khz 44.1khz 0.363 20.21 khz 23. 89 khz 16khz 48khz 0.333 22.00 khz 26.00k hz table 66 . down sampling example (echo canceller mode )
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 109 - 2. src input/output input sources of src1~ 2 are selected by selsrci1[5:0] and selsrci2 [5:0] bits ( table 19 , table 20 ) . the input clock sync domains are inherited from the input data. the outpu t clock sync d omains are set by sdsrco1[2:0] and sdsrco2 [2:0] bits ( table 19 , table 20 ) . then the output data is sent to the data bus. 3. src soft mute the src1 and src 2 have soft mute function independently. 3 - 1. manual mode when s mute x bit (x=1, 2) is set to 1, the src output data a re attenuated to ? ? in 1024 fso cycles. when the smute x bit is set to 0 , the mute is cancelled and the output attenuation level gradually changes to 0db in 1024 fso cycles. if the soft mute is cancelled before mute state, the attenuati on is discontinued and the attenuation level returns to 0db by the same cycles. the soft mute is effective for changing the signal source without stopping the signal . figure 77 . soft mute manual mode (1) smutex bit (x=1, 2) = 0 1 : the output data is attenuated to ? ? during 1024 fso cycles . (2) smutex bit (x=1, 2) = 1 0 : the output attenuation level gradually changes to 0db from ? ? in 1024 fso cycles. (3) if the soft mute is cancelled within 1024 fso cycles , the attenuation is discontinued and the attenuation level return s to 0db by the same number of clock cycles. s mute x bit 0db attenuation level at srco x - ? db (1) ( 3 ) ( 2 )
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 110 - 3 - 2. semi - auto mode semi - automatic soft mute mode is set by s auto x bit (x=1, 2) = 1. in this mode, soft mute is released within 21 .25 ms after continuing the mute when pm sr cx bit (x=1, 2) i s set to 1. if s mute x bit is 1 when pm sr cx bit is released (0 1), the soft mute is not cancelled. figure 78 . soft mute semi - auto mode (1) the attenuation level of the output data is changed to 0db by 1024 fso cycles. 4. src reset bringing pm sr cx bit (x= 1, 2) to 0 resets the src of the ak 773 5 and initializes the digital filters. when pm sr cx bit = 0, the src output is l. the src outputs data within 21 ms by releasing the src reset ( pm sr cx bit = 1) after inputting a clock . until then, the src outputs l. before releasing the pm sr cx bit to 1, the src settings should be completed. figure 79 . src reset example 1 pmsrcx bit db 0db attenuation 0 smutex bit don t care srco 0 (1) <21.25ms case 1 input clock src i x don t care srco x (internal state) power - down normal operation clock stable normal data input clocks 1 output clock don t care don t care pmsrc x bit power - down don t care don t care don t care 0 data normal operation clock stable < 2 1 ms normal data pd input data 1 ou tput clocks 1 input clocks 2 input data 2 output clocks 2 0 data 0 data src xlock < 2 1 ms
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 111 - figure 80 . src reset example 2 5. src clock chan ge 5 - 1. internal reset function for clock change the src block executes internal reset automatically when an input or output clock is stopped. normal data will be output within 21 ms after the clock is restarted. 5 - 2. clock change sequence a clock change sequence of src is shown in figure 81 . figure 81 . src clock change sequence notes * 81 . the data on src output may cause a clicking noise. to prevent this, input 0 dat a to src input (s rcix ) before pm src x bit (x= 1, 2) is set to 0 , that will keep the data on src output as 0. * 82 . this click noise ( * 81 ) can also be removed by setting s mute x bit (x= 1, 2) . * 81 * 82 case 2 i nput clock srci x srco x (internal state) power - down no rmal operation clock stable normal data (no clock) output clock pmsrc x bit power - down don t care don t care don t care 0 data clock unstable input clocks input data output clocks 0 data (don t care) (don t care) srcxlock < 2 1 ms clock stable power down clock (input or output) state 1 srco x (interlal state) normal operation normal operation state 2 (unknown) smute x bit ( r ecommended ) 1024/fso att.level 0db - ? db normal data normal data 1024/fso pmsrc x bit < 2 1 ms
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 112 - 6. src lock the sto pin outputs the src status by setting srclocke x bit (x= 1 , 2 ) to 1. the sto pin output s h if the src is locked, and outputs l when the src is un locked or w hen the src is in reset state ( pm sr cx bit = 0) . 7. group delay when using src s in the same rate when src1 and src2 use the same sync domain for input clock (fsi) and the same sync domain for output clock (fso), a maximum 2xfso mismatch of group delay may occur between them . this group delay mismatch can be avoided by setting pmsrc1 and pmsrc2 bits to 1 simultaneous ly after setting srcphgr bit to 1 . a click noise m ay occur if pmsrc 1/2 bits are not set to 1 at the same time when srcphgr bit is 1 .
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 113 - register map control registers can be initialized by a power - down release (pdn pin = l h ). addr [hex] register name d7 d6 d5 d4 d3 d2 d1 d0 default 0000 system clock setting 1 0 refsel[1:0] refmode[4:0] 00 0001 system clock setting 2 ckresetn 0 0 fsmode[4:0] 00 0002 mic bias power management 0 0 0 0 0 0 0 pmmb 00 0003 sync domain 1 setting 1 bdv1[9] bdv1[8] cks1[2:0] sdv1[2:0] 00 0004 sync domain 1 setting 2 bdv1[7:0] 00 0005 sync domain 2 setting 1 bdv2[9] bdv2[8] cks2[2:0] sdv2[2:0] 00 0006 sync domain 2 setting 2 bdv2[7:0] 00 0007 sync domain 3 setting 1 bdv3[9] bdv3[8] cks3[2:0] sdv3[2:0] 00 0008 sync domain 3 setting 2 bdv3[7:0] 00 0009 sync domain 4 setting 1 bdv4[9] bdv4[8] cks4[2:0] sdv4[2:0] 00 000a sync domain 4 setting 2 bdv4[7:0] 00 000b sync domain m/s setting 0 0 0 0 0 msn3 msn2 msn1 00 000c reserved 0 0 0 0 0 0 0 0 00 000d clko output setting 0 0 0 0 clkoe clkosel[2:0] 00 000e reserved 0 0 0 0 0 0 0 0 00 000f sync domain select 1 0 sdbck1[2:0] 0 sdbck2[2:0] 00 0010 sync domain select 2 0 sdbck3[2:0] 0 0 0 0 00 0011 sync domain select 3 0 sddsp1[2:0] 0 sddsp2[2:0] 00 0012 sync domain select 4 0 sddsp1o1[2:0] 0 sddsp1o2[2:0] 00 0013 sync domain select 5 0 sddsp1o3[2:0] 0 sddsp1o4[2:0] 00 0014 sync domain select 6 0 sddsp1o5[2:0] 0 sddsp1o6[2:0] 00 0015 sync domain select 7 0 sddsp2o1[2:0] 0 sddsp2o2[2:0] 00 0016 sync domain select 8 0 sddsp2o3[2:0] 0 sddsp2o4[2:0] 00 0017 sync domain select 9 0 sddsp2o5[2:0] 0 sddsp2o6[2:0] 00 0018 sync domain select 10 0 sdsrco1[2:0] 0 sdsrco2[2:0] 00 0019 sync domain select 11 0 sdadc1[2:0] 0 sdcodec[2:0] 00 001a sync domain select 12 0 sddo1[2:0] 0 sddo2[2:0] 00 001b sync domain select 13 0 sddo3[2:0] 0 sddo4[2:0] 00 001c external clock domain select exbck4[1:0] exbck3[1:0] exbck2[1:0] exbck1[1:0] 00 001d reserved 0 0 0 0 0 0 0 0 00 001e reserved 0 0 0 0 0 0 0 0 00 001f sdout1a output data select 0 0 seldo1a[5:0] 00 0020 sdout1b output data select 0 0 seldo1b[5:0] 00 0021 sdout1c output data select 0 0 seldo1c[5:0] 00 0022 sdout1d output data select 0 0 seldo1d[5:0] 00 0023 sdout2a output data select 0 0 seldo2a[5:0] 00 0024 sdout2b output data select 0 0 seldo2b[5:0] 00 0025 sdout2c output data select 0 0 seldo2c[5:0] 00 0026 sdout2d output data select 0 0 seldo2d[5:0] 00 0027 sdout3a output data select 0 0 seldo3a[5:0] 00 0028 sdout3b output data select 0 0 seldo3b[5:0] 00 0029 sdout3c output data select 0 0 seldo3c[5:0] 00 002a sdout3d output data select 0 0 seldo3d[5:0] 00 002b sdout4a output data select 0 0 seldo4a[5:0] 00 002c sdout4b output data select 0 0 seldo4b[5:0] 00 002d sdout4c output data select 0 0 seldo4c[5:0] 00 002e sdout4d output data select 0 0 seldo4d[5:0] 00 002f dac1 input data select 0 0 selda1[5:0] 00
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 114 - addr [hex] register name d7 d6 d5 d4 d3 d2 d1 d0 default 0030 dac2 input data select 0 0 selda2[5:0] 00 0031 dsp1 din1 input data select 0 0 d1seldi1[5:0] 00 0032 dsp1 din2 input data select 0 0 d1seldi2[5:0] 00 0033 dsp1 din3 input data select 0 0 d1seldi3[5:0] 00 0034 dsp1 din4 input data select 0 0 d1seldi4[5:0] 00 0035 dsp1 din5 input data select 0 0 d1seldi5[5:0] 00 0036 dsp1 din6 input data select 0 0 d1seldi6[5:0] 00 0037 dsp2 din1 input data select 0 0 d2seldi1[5:0] 00 0038 dsp2 din2 input data select 0 0 d2seldi2[5:0] 00 0039 dsp2 din3 input data select 0 0 d2seldi3[5:0] 00 003a dsp2 din4 input data select 0 0 d2seldi4[5:0] 00 003b dsp2 din5 input data select 0 0 d2seldi5[5:0] 00 003c dsp2 din6 input data select 0 0 d2seldi6[5:0] 00 003d src1 input data select 0 0 selsrci1[5:0] 00 003e src2 input data select 0 0 selsrci2[5:0] 00 003f reserved 0 0 0 0 0 0 0 0 00 0040 reserved 0 0 0 0 0 0 0 0 00 0041 clock format setting 1 bckp1 dcf1[2:0] bckp2 dcf2[2:0] 00 0042 clock format setting 2 bckp3 dcf3[2:0] 0 0 0 0 00 0043 sdin1 digital input format diedgen1 0 disl1[1:0] dilsbe1 0 didl1[1:0] 00 0044 sdin2 digital input format diedgen2 0 disl2[1:0] dilsbe2 0 didl2[1:0] 00 0045 sdin3 digital input format diedgen3 0 disl3[1:0] dilsbe3 0 didl3[1:0] 00 0046 sdin4 digital input format diedgen4 0 disl4[1:0] dilsbe4 0 didl4[1:0] 00 0047 sdout1 digital output format doedgen1 0 dosl1[1:0] dolsbe1 0 dodl1[1:0] 00 0048 sdout2 digital output format doedgen2 0 dosl2[1:0] dolsbe2 0 dodl2[1:0] 00 0049 sdout3 digital output format doedgen3 0 dosl3[1:0] dolsbe3 0 dodl3[1:0] 00 004a sdout4 digital output format doedgen4 0 dosl4[1:0] dolsbe4 0 dodl4[1:0] 00 004b sdout phase setting 0 0 0 0 sdoph4 sdoph3 sdoph2 sdoph1 00 004c output port enable setting 0 0 0 0 sdout4e sdout3e sdout2en sdout1e 00 004d shared input port select 0 0 0 0 di3sel di2sel lck2sel bck2sel 00 004e shared output port select 0 0 do4sel do3sel [1:0] do2sel [1:0] do1sel 00 004f reserved 0 0 0 0 0 0 0 0 00 0050 mic amp gain mgnl[3:0] mgnr[3:0] 00 0051 mic amp gain control 0 0 0 0 0 0 miclzce micrzce 00 0052 adc1 lch digital volume volad1l[7:0] 30 0053 adc1 rch digital volume volad1r[7:0] 30 0054 adc2 lch digital volume volad2l[7:0] 30 0055 adc2 rch digital volume volad2r[7:0] 30 0056 analog input select setting adsd adsl 0 0 ad1lsel ad1rsel ad2sel[1:0] 00 0057 adc mute & hpf control atspad ad1mute ad2mute 0 0 0 ad1hpfn ad2hpfn 00 0058 adc fullscale control 0 0 0 0 adc1vl adc1vr adc2vl adc2vr 00 0059 dac1 lch digital volume volda1l[7:0] 18 005a dac1 rch digital volume volda1r[7:0] 18 005b dac2 lch digital volume volda2l[7:0] 18 005c dac2 rch digital volume volda2r[7:0] 18 005d dac mute & filter setting atspda da1mute da2mute 0 0 0 dasd dasl 00 005e dac de - emphasis setting 0 0 0 0 dem2[1:0] dem1[1:0] 05 005f reserved 0 0 0 0 0 0 0 0 00
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 115 - addr [hex] register name d7 d6 d5 d4 d3 d2 d1 d0 default 0060 src fi l ter setting srcfec srcfaud 0 srcphgr 0 0 0 0 00 0061 src mute setting 0 0 0 0 smute1 smute2 sauto1 sauto2 00 0062 reserved 0 0 0 0 0 0 0 0 00 0063 reserved 0 0 0 0 0 0 0 0 00 0064 dsp memory assignment dlramdiv[1:0] 0 0 cramdiv[1:0] dramdiv pramdiv 00 0065 dsp1/2 dram setting d1drma[1:0] d1drmbk[1:0] d2drma[1:0] d2drmbk[1:0] 00 0066 dsp1 dlram setting d1ss[1:0] d1dlrma 0 0 d1dlrmbk[2:0] 00 0067 dsp2 dlram setting d2ss[1:0] d2dlrma 0 0 d2dlrmbk[2:0] 00 0068 wavp & dlp0 setting d1dlp0 d1wavp[2:0] d2dlp0 d2wavp[2:0] 00 0069 jx setting d1jx0e d1jx1e d1jx2e d1jx3e d2jx0e d2jx1e d2jx2e d2jx3e 00 006a reserved 0 0 0 0 0 0 0 0 00 006b reserved 0 0 0 0 0 0 0 0 00 006c sto flag setting crce 0 0 plllocke srclocke1 srclocke2 d1wdten d2wdten 00 006d power management 0 0 pmsrc1 pmsrc2 pmad1 pmad2 pmda1 pmda2 00 006e reset control dlrdy 0 0 0 d1resetn d2resetn cresetn hresetn 0 0 006f reserved 0 0 0 0 0 0 0 0 00 0070 reserved 0 0 0 0 0 0 0 0 00 addr [hex] register name d7 d6 d5 d4 d3 d2 d1 d0 default 0100 device id devid[7:0] 35 0101 revision num revnum[7:0] 00 0102 dsp error status crcerrn wdt1errn wdt2errn plllock 0 0 gpo1 gpo0 e0 0103 src status 0 0 src2lock src1lock 0 0 0 0 00 0104 sto read out sto 0 0 0 0 0 0 0 80 note * 83 . the bits defined as 0 must contain a 0 value . do not write to the address other than 0000h ~ 0070h.
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 116 - register definitions addr register name d7 d6 d5 d4 d3 d2 d1 d0 0000 system clock setting 1 0 refsel[1:0] refmode[4:0] r/w r/w r/w r/w d efault 0 00 00h refsel[1:0]: pll reference clock input pin setting ( table 4 ) d efault: 00 (xti) refmode[4:0]: pll reference clock frequency setting ( table 5 ) d efault: 00h (256khz) addr register name d7 d6 d5 d4 d3 d2 d1 d0 0001 system clock setting 2 ckresetn 0 0 fsmode[4:0] r/w r/w r/w r/w r/w d efault 0 0 0 00h ckresetn: clock reset 0: clock reset (default) 1: clock reset release fsmode[4:0]: operation sampling frequency mode setting for analog block ( table 12 ) d efault: 00h (adc2, dac1, dac2=8khz, adc1=8khz) addr register name d7 d6 d5 d4 d3 d2 d1 d0 0002 mic bias power management 0 0 0 0 0 0 0 pmmb r/w r/w r/w r/w r/w r/w r/w r/w r/w d efault 0 0 0 0 0 0 0 0 pmmb: power management setting for mic bias output 0: power - off (default) 1: normal operation addr register name d7 d6 d5 d4 d3 d2 d1 d0 0003 sync domain 1 setting 1 bdv1[9] bdv1[8] cks1[2:0] sdv1[2:0] 0004 sync domain 1 setting 2 bdv1[7:0] 0005 sync domain 2 setting 1 bdv2[9] bdv2[8] cks2[2:0] sdv2[2:0] 0006 sync domain 2 setting 2 bdv2[7:0] 0007 sync domain 3 setting 1 bdv3[9] bdv3[8] cks3[2:0] sdv3[2:0] 0008 sync domain 3 setting 2 bdv3[7:0] 0009 sync domain 4 setting 1 bdv4[9] bdv4[8] cks4[2:0] sdv4[2:0] 000a sync domain 4 setting 2 bdv4[7:0] r/w r/w r/w r/w r/w r/w r/w r/w r/w d efault 0 0 0 0 0 0 0 0 cksx[2:0]: internal divider clock source setting of sync domain x ( table 8 ) d efault: 000 (tielow) sdvx[2:0]: mlrck divider setting of sync domain x ( table 10 ) d efault: 000 ( divided by 64) bdvx[9:0]: mbick d i vider setting of syn c domain x ( table 9 ) d efault: 000h ( divided by 1)
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 117 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 000b sync domain m/s setting 0 0 0 0 0 msn3 msn2 msn1 r/w r/w r/w r/w r/w r/w r/w r/w r/w d efault 0 0 0 0 0 0 0 0 msn3: slave/master mode setting of lrcksd3/bicksd3 ( table 7 , table 14 ) 0: slave mode (default) 1: master mode msn2: slave/master mode setting of lrcksd2/bicksd2 ( table 7 , table 14 ) 0: slave mode (default) 1: master mode msn1: slave/master mode setting of lrcksd1/bicksd1 ( table 7 , table 14 ) 0: slave mode (default) 1: master mode addr register name d7 d6 d5 d4 d3 d2 d1 d0 000d clko output setting 0 0 0 0 clkoe clkosel[2:0] r/w r/w r/w r/w r/w r/w r/w d efault 0 0 0 0 0 000 clkoe: output enable of the clko pin 0: clko pin = l (default) 1: clko pin output enable clkosel[2:0]: clko p in output clock freque ncy setting ( table 13 ) d efault: 000 (12.288mhz / 11.2896mhz)
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 118 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 000f sync domain select 1 0 sdbck1[2:0] 0 sdbck2[2:0] 0010 sync domain select 2 0 sdbck3[2:0] 0 0 0 0 0011 sync domain select 3 0 sddsp1[2:0] 0 sddsp2[2:0] 0012 sync domain select 4 0 sddsp1o1[2:0] sddsp1o2[2:0] 0013 sync domain select 5 0 sddsp1o3[2:0] 0 sddsp1o4[2:0] 0014 sync domain select 6 0 sddsp1o5[2:0] 0 sddsp1o6[2:0] 0015 sync domain select 7 0 sddsp2o1[2:0] 0 sddsp2o2[2:0] 0016 sync domain select 8 0 sddsp2o3[2:0] 0 sddsp2o4[2:0] 0017 sync domain select 9 0 sddsp2o5[2:0] 0 sddsp2o6[2:0] 0018 sync domain select 10 0 sdsrco1[2:0 0 sdsrco2[2:0 0019 sync domain select 11 sdadc1[2:0] 0 sdcodec[2:0] 001a sync domain select 12 0 sddo1[2:0] 0 sddo1[2:0] 001b sync domain select 13 0 sddo3[2:0] 0 sddo4[2:0] r/w r/w r/w r/w r/w d efault 0 000 0 000 sdxxxx[2:0]: sync domain setting of input/output port for data and clocks ( table 19 , table 20 ) d efault: 000 (tielow) addr register name d7 d6 d5 d4 d3 d2 d1 d0 001c external clock domain select exbck4[1:0] exbck3[1:0] exbck2[1:0] exbck1[1:0] r/w r/w r/w r/w r/w d efault 00 00 00 00 exbck4[1:0]: synchronizing bick/lrck pin setting with sdin 4 p in ( table 16 ) d efault: 00 (tielow) exbck3[1:0]: synchronizing bick/lrck pin setting with sdin 3 p in ( table 16 ) d efault: 00 (tielow) exbck2[1:0]: synchronizing bick/lrck pin setting with sdin 2 p in ( table 16 ) d efault: 00 (tielow) exbck1[1:0]: synchronizing bick/lrck pin setting with sdin 1 p in ( table 16 ) d efault: 00 (tielow)
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 119 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 001f sdout1a output data select 0 0 seldo1a[5:0] 0020 sdout1b output data select 0 0 seldo1b[5:0] 0021 sdout1c output data select 0 0 seldo1c[5:0] 0022 sdout1d output data select 0 0 seldo1d[5:0] 0023 sdout2a output data select 0 0 seldo2a[5:0] 0024 sdout2b output data select 0 0 seldo2b[5:0] 0025 sdout2c output data select 0 0 seldo2c[5:0] 0026 sdout2d output data select 0 0 seldo2d[5:0] 0027 sdout3a output data select 0 0 seldo3a[5:0] 0028 sdout3b output data select 0 0 seldo3b[5:0] 0029 sdout3c output data select 0 0 seldo3c[5:0] 002a sdout3d output data select 0 0 seldo3d[5:0] 002b sdout4a output data select 0 0 seldo4a[5:0] 002c sdout4b output data select 0 0 seldo4b[5:0] 002d sdout4c output data select 0 0 seldo4c[5:0] 002e sdout4d output data select 0 0 seldo4d[5:0] 002f dac1 input data select 0 0 selda1[5:0] 0030 dac2 input data select 0 0 selda2[5:0] 0031 dsp1 din1 input data select 0 0 d1seldi1[5:0] 0032 dsp1 din2 input data select 0 0 d1seldi2[5:0] 0033 dsp1 din3 input data select 0 0 d1seldi3[5:0] 0034 dsp1 din4 input data select 0 0 d1seldi4[5:0] 0035 dsp1 din5 input data select 0 0 d1seldi5[5:0] 0036 dsp1 din6 input data select 0 0 d1seldi6[5:0] 0037 dsp2 din1 input data select 0 0 d2seldi1[5:0] 0038 dsp2 din2 input data select 0 0 d2seldi2[5:0] 0039 dsp2 din3 input data select 0 0 d2seldi3[5:0] 003a dsp2 din4 input data select 0 0 d2seldi4[5:0] 003b dsp2 din5 input data select 0 0 d2seldi5[5:0] 003c dsp2 din6 input data select 0 0 d2seldi6[5:0] 003d src1 input data select 0 0 selsrci1[5:0] 003e src2 input data select 0 0 selsrci2[5:0] r/w r/w r/w r/w d efault 0 0 00h selxxxx[5:0]/d1selxxxx[5:0]/d2sel[5:0]: source data select of each port ( table 19 , table 20 ) d efault: 00h (all0) addr register name d7 d6 d5 d4 d3 d2 d1 d0 0041 clock format setting 1 bckp1 dcf1[2:0] bckp2 dcf2[2:0] r/w r/w r/w r/w r/w d efault 0 000 0 000 bckp1: relationship of lrck1 and bick1 edges ( table 22 ) 0: lrck1 starts on a bick1 falling e dge (default) 1: lrck1 starts on a bick1 rising e dge dcf1[2:0]: lrck1/bick1 clock format setting ( table 21 ) d efault: 000 (i 2 s mode) bckp2: relationship of lrck2 and bick 2 edges ( table 22 ) 0: lrck 2 starts on a bick 2 falling e dge (default) 1: lrck 2 starts on a bick 2 rising e dge dcf2[2:0]: lrck2/bick2 clock format setting ( table 21 ) d efault: 000 (i 2 s mode)
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 120 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 0042 clock format setting 2 bckp3 dcf3[2:0] 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w d efault 0 000 0 0 0 0 bckp3: relationship of lrck3 and bick 3 edges ( table 22 ) 0: lrck 3 starts on a bick 3 falling e dge (default) 1: lrck 3 starts on a bick 3 rising e dge dcf3[2:0]: lrck 3 /bick 3 clock format setting ( table 21 ) d efault: 000 (i 2 s mode) addr register name d7 d6 d5 d4 d3 d2 d1 d0 0043 sdin1 digital input format diedgen1 0 disl1[1:0] dilsbe1 0 didl1[1:0] 0044 sdin2 digital input format diedgen2 0 disl2[1:0] dilsbe2 0 didl2[1:0] 0045 sdin3 digital input format diedgen3 0 disl3[1:0] dilsbe3 0 didl3[1:0] 0046 sdin4 digital input format diedgen4 0 disl4[1:0] dilsbe4 0 didl4[1:0] r/w r/w r/w r/w r/w r/w r/w default 0 0 00 0 0 00 diedgenx: start timing setting of data transferring for second and succeeding channels of sdin x ( table 26 ) 0: lrck edge basis (default) 1: slot length basis dislx[ 1 :0]: sdinx data slot length setting ( table 23 ) d efault: 00 (24bit) dilsbex: msb/lsb setting of audio data in sdinx data slot ( table 25 ) 0: msb (default) 1: lsb didlx[ 1 :0]: audio data word length setting of sdinx ( table 24 ) d efault: 00 (24bit) addr register name d7 d6 d5 d4 d3 d2 d1 d0 0047 sdout1 digital output f ormat doedgen1 0 dosl1[1:0] dolsbe1 0 dodl1[1:0] 0048 sdout2 digital output format doedgen2 0 dosl2[1:0] dolsbe2 0 dodl2[1:0] 0049 sdout3 digital output format doedgen3 0 dosl3[1:0] dolsbe3 0 dodl3[1:0] 004a sdout4 digital output format doedgen4 0 dosl4[1:0] dolsbe4 0 dodl4[1:0] r/w r/w r/w r/w r/w r/w r/w d efault 0 0 00 0 0 00 doedgenx: start timing setting of data transferring for second and succeeding channels of sd outx ( table 26 ) 0: lrck edge basis (default) 1: slot length basis doslx[ 1 :0]: sdoutx data slot length setting ( table 23 ) d efault: 0 0 (24bit) dolsbex: msb/lsb setting of audio data in sdoutx data slot ( table 25 ) 0: msb (default) 1: lsb dodlx[ 1 :0]: audio data word length setting of sd outx ( table 24 ) d efault: 00 (24bit)
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 121 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 004b sdout phase setting 0 0 0 0 sdoph4 sdoph3 sdoph2 sdoph1 r/w r/w r/w r/w r/w r/w r/w r/w r/w d efault 0 0 0 0 0 0 0 0 sdoph4: sdout 4 fast mode setting for data output in slave m ode ( * 47 ) 0: slow mode (default) 1: fast mode sdoph3: sdout 3 fast mode setting for data output in slave m ode ( * 47 ) 0: slow mode (default) 1: fast mode sdoph2: sdout 2 fast mode setting for data output in slave m ode ( * 47 ) 0: slow mode (default) 1: fast mode sdoph1: sdout 1 fast mode setting for data output in slave m ode ( * 47 ) 0: slow mode (default) 1: fast mode addr register name d7 d6 d5 d4 d3 d2 d1 d0 004c output port enable setting 0 0 0 0 sdout4e sdout3e sdout2en sdout1e r/w r/w r/w r/w r/w r/w r/w r/w r/w d efault 0 0 0 0 0 0 0 0 sdout4e: sdout4 /gpo 2 p in output setting 0: sdout4/gpo2 pin = l (default) 1: sdout4/gpo2 pin output enable sdout3e: sdout3/clko/gpo1 p in output setting 0: sdout3/clko/gpo1 pin = l (default) 1: sdout3/clko/gpo1 pin output enable sdout2en: sto/rdy/sdout2 p in output setting 0: sto/rdy/sdout2 pin output enable (default) 1: sto/rdy/sdout2 pin = l sdout1e: sdout1/rdy p in output setting 0: sdout1/rdy pin = l (default) 1: sdout1/rdy pin output enable
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 122 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 004d shared input port select 0 0 0 0 di3sel di2sel lck2sel bck2sel r/w r/w r/w r/w r/w r/w r/w r/w r/w d efault 0 0 0 0 0 0 0 0 di3sel: sdin3/jx3 p in input function setting 0: sdin3 input (default) 1: jx3 input di2sel: sdin2/jx0 p in input function setting 0: sdin2 input (default) 1: jx0 input lck2sel: lrck2/jx1 p in input function setting 0: lrck2 input (default) 1: jx1 input ( set msn2 bit to 0 ) bck2sel: bick2/jx2 p in input function setting 0: bick2 input (default) 1: jx2 input ( set msn2 bit to 0 ) addr register name d7 d6 d5 d4 d3 d2 d1 d0 004e shared output port select 0 0 do4sel do3sel [1:0] do2sel [1:0] do1sel r/w r/w r/w r/w r/w r/w r/w d efault 0 0 0 00 00 0 do4sel: sdout4/gpo2 p in output function setting 0: sdout4 output (default) 1: gpo2 output ( gpo output of dsp2) do3sel: sdout3/clko/gpo1 p in output function setting 00: sdout3 output (default) 01: clko output 10: gpo1 output ( gpo output of dsp1) do2sel: sto/rdy/sdout2 p in output function setting 00: sto output (default) 01: rdy output 10: sdout2 output do1sel: sdout1/rdy p in output function setting 0: sdout1 output (default) 1: rdy output
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 123 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 0050 mic amp gain mgnl[3:0] mgnr[3:0] r/w r/w r/w d efault 0000 0000 mgnl[3:0]: lch gain setting of microphone input ( table 45 ) d efault: 0000 (0db) mgnr[3:0]: rch gain setting of microphone input ( table 45 ) d efault: 0000 (0db) addr register name d7 d6 d5 d4 d3 d2 d1 d0 0051 mic amp gain control 0 0 0 0 0 0 miclzce micrzce r/w r/w r/w r/w r/w r/w r/w r/w r/w d efault 0 0 0 0 0 0 0 0 miclzce: zero cross enable of lch microphone gain 0: lch zero crossing detection is off (default) 1: lch zero crossing detection is on micrzce: zero cross enable of rch microphone gain 0: r ch zero crossing detection is off (default) 1: r ch zero crossing detection is on addr register name d7 d6 d5 d4 d3 d2 d1 d0 0052 adc1 lch digital volume volad1l[7:0] 0053 adc1 rch digital volume volad1r[7:0] 0054 adc2 lch digital volume volad2l[7:0] 0055 adc2 rch digital volume volad2r[7:0] r/w r/w d efault 30h volad1l[7:0]: lch digital volume setting of adc1 ( table 49 ) d efault: 30h (0db) volad1r[7:0]: r ch digital volume setting of adc1 ( table 49 ) d efault: 30h (0db) volad2l[7:0]: lch digital volume setting of adc2 ( table 49 ) d efault: 30h (0db) volad2r[7:0]: r ch digital volume setting of adc2 ( table 49 ) d efault: 30h (0db)
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 124 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 0056 analog input select setting adsd adsl 0 0 ad1lsel ad1rsel ad2sel[1:0] r/w r/w r/w r/w r/w r/w r/w r/w d efault 0 0 0 0 0 0 00 adsd, adsl: adc digital filter select ( table 54 ) 00: sharp roll - off fi l ter (default) 01: slow roll - off filter 10: short delay sharp roll - off filter 11: short delay slow roll - off filter ad1lsel: adc1 lch input pin select ( table 47 ) 0: inp1/inn1 (default) 1: ain1l ad1rsel: adc1 r ch input pin select ( table 47 ) 0: inp2/inn2 (default) 1: ain1r ad2sel[1:0]: adc2 input pin select ( table 53 ) 00: ain2lp, ain2ln, ain2rp, ain2rn (default) 01: ain3l, ain3r 10: ain4l, ain4r addr register name d7 d6 d5 d4 d3 d2 d1 d0 0057 adc mute & hpf control atspad ad1mute ad2mute 0 0 0 ad1hpfn ad2hpfn r/w r/w r/w r/w r/w r/w r/w r/w r/w d efault 0 0 0 0 0 0 0 0 atspad: adc digital volume transition time setting ( table 50 ) 0: 4/fs (default) 1: 16/fs ad1mute: adc1 soft mute enable 0: soft mute disable (default) 1: soft mute enable ad2mute: adc 2 soft mute enable 0: soft mute disable (default) 1: soft mute enable ad1hpfn: adc1 hpf enable for dc offset cancelling 0: hpf enable (default) 1: hpf disable ad2hpfn: adc 2 hpf enable for dc offset cancelling 0: hpf enable (default) 1: hpf disable
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 125 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 0058 adc fullscale control 0 0 0 0 adc1vl adc1vr adc2vl adc2vr r/w r/w r/w r/w r/w r/w r/w r/w r/w d efault 0 0 0 0 0 0 0 0 adc1vl: lch input voltage full scale setting of adc1 0: 2.3vpp (2.3vpp) (default) 1: 2.83vpp (2.83vpp) adc1vr: rch input voltage full scale setting of adc1 0: 2.3vpp (2.3vpp) (default) 1: 2.83vpp (2.83vpp) adc2vl: lch input voltage full scale setting of adc 2 0: 2.3vpp (2.3vpp) (default) 1: 2.83vpp (2.83vpp) adc2vr: rch input voltage full scale setting of adc 2 0: 2.3vpp (2.3vpp) (default) 1: 2.83vpp (2.83vpp) addr register name d7 d6 d5 d4 d3 d2 d1 d0 0059 dac1 lch digital volume volda1l[7:0] 005a dac1 rch digital volume volda1r[7:0] 005b dac2 lch digital volume volda2l[7:0] 005c dac2 rch digital volume volda2r[7:0] r/w r/w d efault 18h volda1l[7:0]: lch digital volume setting of dac1 ( table 56 ) d efault: 18h (0db) volda1r[7:0]: rch digital volume setting of dac1 ( table 56 ) d efault: 18h (0db) volda2l[7:0]: lch digital volume setting of dac2 ( table 56 ) d efault: 18h (0db) volda2r[7:0]: rch digital volume setting o f dac2 ( table 56 ) d efault: 18h (0db)
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 126 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 005d dac mute & filter setting atspda da1mute da2mute 0 0 0 dasd dasl r/w r/w r/w r/w r/w r/w r/w r/w r/w d efault 0 0 0 0 0 0 0 0 atspda: d a c digital volume transition time setting ( table 57 ) 0: 4/fs (default) 1: 16/fs da1mute: dac1 soft mute enable 0: soft mute disable (default) 1: soft mute enable da2mute: dac 2 soft mute enable 0: soft mute disable (default) 1: soft mute enable dasd, dasl: dac digital filter select ( table 61 ) 00: sharp roll - off fi l ter (default) 01: slow roll - off filt er 10: short delay sharp roll - off filter 11: short delay slow roll - off filter addr register name d7 d6 d5 d4 d3 d2 d1 d0 005e dac de - emphasis setting 0 0 0 0 dem2[1:0] dem1[1:0] r/w r/w r/w r/w r/w r/w r/w r/w r/w d efault 0 0 0 0 0 1 0 1 dem2[1:0]: de - emphasis f i lter setting of dac2 ( table 62 ) 00: 44.1khz 01: off (default) 10: 48khz 11: 32khz dem1[1:0]: de - emphasis f i lter setting of dac 1 ( table 62 ) 00: 44.1khz 01: off (default) 10: 48khz 11: 32khz addr register name d7 d6 d5 d 4 d3 d2 d1 d0 0060 src fi l ter setting srcfec srcfaud 0 srcphgr 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w d efault 0 0 0 0 0 0 0 0 srcfec, srcfaud: src digital filter setting 00: voice mode (default) 01: aud i o mode 1x: echo canceller mode srcphgr: group delay matching function for multiple src s on the same sampling rate 0: disable (default) 1: enable
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 127 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 0061 src mute setting 0 0 0 0 smute1 smute2 sauto1 sauto2 r/w r/w r/w r/w r/w r/w r/w r/w r/w d efault 0 0 0 0 0 0 0 0 smute1: src1 soft mute enable 0: soft mute disable (default) 1: soft mute enable smute2: src 2 soft mute enable 0: soft mute disable (default) 1: soft mute enable sauto1: semi - auto mode setting of src1 soft mute function 0: manual mode (default) 1: semi - auto mode sauto2: semi - auto mode setting of src 2 soft mute function 0: manual mode (default) 1: semi - auto mode addr register name d7 d6 d5 d4 d3 d2 d1 d0 0064 dsp memory assignment dlramdiv[1:0] 0 0 cramdiv[1:0] dramdiv pramdiv r/w r/w r/w r/w r/w r/w r/w d efault 00 0 0 00 0 0 dlramdiv[1:0]: dl ram memory assignment for dsp1 and dsp2 ( table 38 ) d efault: 00 (dsp1 = 12288 words, dsp2 = not connected ) cramdiv[1:0]: cram memory assignment for dsp1 and dsp2 ( table 36 ) d efault: 00 (dsp1 = 4096 words, dsp2 = 2048 words) dramdiv: d ram memory assignment for dsp1 and dsp2 ( table 37 ) 0: dsp1 = 2048 words, dsp2 = 2048 words (default) 1: dsp1 = 4096 words, dsp2 = reset pramdiv: p ram memory assignment for dsp1 and dsp2 ( table 35 ) 0: dsp1 = 2048 words, dsp2 = 2048 words (default) 1: dsp1 = 4096 words, dsp2 = reset
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 128 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 0065 dsp1/2 dram setting d1drma[1:0] d1drmbk[1:0] d2drma[1:0] d2drmbk[1:0] r/w r/w r/w r/w r/w d efault 00 00 00 00 d1drma[1:0]: bank addressing mode setting of each bank of dram for dsp1 ( table 40 ) d efault: 00 (bank 1 = ring, bank 0 = ring) d1drmbk[1:0]: dram bank size setting of dsp1 ( table 39 ) d efault: 00 (bank 1 = 1024 words, bank 0 = dsp1 dram size C 1024 words) d2drma[1:0]: bank addressing mode setting of each bank of dram for dsp2 ( table 40 ) d efault: 00 (bank 1 = ring, bank 0 = ring) d2drmbk[1:0]: dram bank size setting of dsp2 ( table 39 ) d efault: 00 (bank 1 = 1024 words, bank 0 = dsp2 dram size C 1024 words) addr register name d7 d6 d5 d4 d3 d2 d1 d0 0066 dsp1 dlram setting d1ss[1:0] d1dlrma 0 0 d1dlrmbk[2:0] r/w r/w r/w r/w r/w r/w d efault 00 0 0 0 000 d1ss[1:0]: sampling mode setting of dlram bank 0 for dsp1 ( table 43 ) d efault: 00 ( update every sampling ) d1dlrma: dlram memory bank1 addressing mode setting of dsp1 ( table 42 ) 0: ring (default) 1: linear d1dlrmbk[2:0]: dlram bank size setting of dsp1 ( table 41 ) d efault: 000 (bank 1 = 0 word, bank 0 = dsp1 dlram size) addr register name d7 d6 d5 d4 d3 d2 d1 d0 0067 dsp2 dlram setting d2ss[1:0] d2dlrma 0 0 d2dlrmbk[2:0] r/w r/w r/w r/w r/w r/w d efault 00 0 0 0 000 d2ss[1:0]: sampling mode setting of dlram bank 0 for dsp2 ( table 43 ) d efault: 00 ( update every sampling ) d2dlrma: dlram memory bank1 addressing mode setting of dsp 2 ( table 42 ) 0: ring (default) 1: linear d2dlrmbk[2:0]: dlram bank size setting of dsp 2 ( table 41 ) d efault: 000 (bank 1 = 0 word, bank 0 = dsp 2 dlram size)
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 129 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 0068 wavp & dlp0 setting d1dlp0 d1wavp[2:0] d2dlp0 d2wavp[2:0] r/w r/w r/w r/w r/w d efault 0 000 0 000 d1dlp0: operation m o de setting of dlram pointer (dlp0) of dsp1 0: ofreg (default) 1: dbus immediate data d1wavp[2:0]: cycle resolution setting of trigonometric table for dsp1 ( table 44 ) d efault: 000 (128 points) d2dlp0: operation m o de setting of dlram pointer (dlp0) of dsp 2 0: ofreg (default) 1: dbus immediate data d2wavp[2:0]: cycle resolution setting of trigonometric table for dsp 2 ( table 44 ) d efault: 000 (128 points) addr register name d7 d6 d5 d4 d3 d2 d1 d0 0069 jx setting d1jx0e d1jx1e d1jx2e d1jx3e d2jx0e d2jx1e d2jx2e d2jx3e r/w r/w r/w r/w r/w r/w r/w r/w r/w d efault 0 0 0 0 0 0 0 0 d1jx0e: dsp1 jx0 enable 0: disable (default) 1: enable d1jx1e: dsp1 jx1 enable 0: disable (default) 1: enable d1jx2e: dsp1 jx2 enable 0: disable (default) 1: enable d1jx3e: dsp1 jx3 enable 0: disable (default) 1: enable d2jx0e: dsp2 jx0 enable 0: disable (default) 1: enable d2jx1e: dsp2 jx1 enable 0: disable (default) 1: enable d2jx2e: dsp2 jx2 enable 0: disable (default) 1: enable d2jx3e: dsp2 jx3 enable 0: disable (default) 1: enable
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 1 30 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 006c sto flag setting crce 0 0 plllocke srclocke1 srclocke2 d1wdten d2wdten r/w r/w r/w r/w r/w r/w r/w r/w r/w d efault 0 0 0 0 0 0 0 0 crce: sto pin output setting of cyclic redundancy check error signal 0: do not output to sto pin (default) 1: output to sto pin plllocke: sto pin output setting of pll lock signal 0: do not output to sto pin (default) 1: output to sto pin srclocke1: sto pin output setting of src1 lock signal 0: do not output to sto pin (default) 1: output to sto pin srclocke2: sto pin output setting of src2 lock signal 0: do not output to sto pin (default) 1: output to sto pin d1wdten: sto pin output setting of dsp1 watch d o g timer error signal 0: output to sto pin (default) 1: do not output to sto pin d2wdten: sto pin output setting of dsp2 watch dog time error signal 0: output to sto pin (default) 1: do not output to sto pin
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 131 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 006d power management 0 0 pmsrc1 pmsrc2 pmad1 pmad2 pmda1 pmda2 r/w r/w r/w r/w r/w r/w r/w r/w r/w d efault 0 0 0 0 0 0 0 0 pmsrc1: src1 power management setting 0: power - off (default) 1: normal operation pmsrc2: src2 power management setting 0: power - off (default) 1: normal operation pmad1: ad c1 power management setting 0: power - off (default) 1: normal operation pmad2: adc2 power management setting 0: power - off (default) 1: normal operation pmda1: dac1 power management setting 0: power - off (default) 1: normal operation pmda2: dac2 power management setting 0: power - off (default) 1: normal operat ion
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 132 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 006e reset control dlrdy 0 0 0 d1resetn d2resetn cresetn hresetn r/w r/w r/w r/w r/w r/w r/w r/w r/w d efault 0 0 0 0 0 0 0 0 dlrdy: dsp data downloading function without clock input 0: off , normal operation (default) 1: on , program downloading is available without inputting a clock. note * 84 . dsp programs and coefficient data can be downloaded while the main clock is stopped or during clock reset (ckresetn bit = 0) by setting this bit to 1. this bit must be set to 0 after downloading. d1resetn: dsp1 reset 0: dsp1 reset (default) 1: dsp1 reset release d1resetn: dsp2 reset 0: dsp2 reset (default) 1: dsp2 reset release cresetn: codec reset 0: codec reset (default) adc1, adc2, dac1 and dac2 are reset. 1: codec reset release hresetn: hub reset 0: hub reset (default) adc1, adc2, dac1, dac2 , src1 and src2 are reset. 1: hub reset release
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 133 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 0100 device id devid[7:0] r/w r fixed value 35h devid[7:0]: ak7735 s device id read fixed value : 35h addr register name d7 d6 d5 d4 d3 d2 d1 d0 0101 revision num revnum[7:0] r/w r fixed value 00h revnum[7:0]: ak7735 s device revision read fixed value : 00h addr register name d7 d6 d5 d4 d3 d2 d1 d0 0102 dsp error status crcerrn wdt1errn wdt2errn plllock 0 0 gpo2 gpo1 r/w r r r r r r r r d efault 1 1 1 0 0 0 0 0 crcerrn: cyclic redundancy c heck error status 0: error 1: normal operation (default) wdt1errn: dsp1 watchdog timer error status 0: error 1: normal operation (default) wdt2errn: dsp2 watchdog timer error status 0: error 1: normal operation (default) plllock: pll lock status 0: pll unlock (default) 1: pll lock gpo2: gpo output level status of dsp2 0: l output (default) 1: h output gpo1: gpo output level status of dsp1 0: l output (default) 1: h output
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 134 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 0103 src status 0 0 src2lock src1lock 0 0 0 0 r/w r r r r r r r r d ef a u lt 0 0 0 0 0 0 0 0 src2lock: src2 lock status read 0: unlock (default) 1: lock src1lock: src1 lock status read 0: unlock (default) 1: lock addr register name d7 d6 d5 d4 d3 d2 d1 d0 0104 sto read out sto 0 0 0 0 0 0 0 r/w r r r r r r r r d efault 1 0 0 0 0 0 0 0 sto: sto pin status read 0: error 1: normal operation (default)
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 135 - 13. recommended external circuits connection diagram 1. i 2 c interface figure 82 . i 2 c interface connection example sdout1/rdy 20 28 s da scl 26 25 up 45 pdn reset control ak77 35 vrefh audio i/f clock csn 24 h or l & 23 sto/ rdy/ sdout 2 sdin 1 17 42 analog +3.3 v avdd 10 ? 0.1 ? vcom 44 2.2 ? dvss 1/dvss2 /dvss3 10, 22 , 30 21 digital io 1.8 3.3 v t vdd 10 ? 0.1 ? 11 digital io 3.3 v vdd33 10 ? 0.1 ? 31 digital core 3.3 v lvdd 10 ? 0.1 ? vrefl avss avdrv 2.2 ? 2 aout1r 47 aout1l 48 aout2l aout2r 1 i2cfil 27 h or l sdin 2 /jx0 lrck 1 18 bick 1 19 lrck 2 /jx1 15 bick 2 /jx2 16 sdout 3/clko/gpo1 7 sdin 3 /jx3 sdin 4 9 sdout 4/ gpo 2 5 lrck 3 4 bick 3 6 audio i/f clock & testi 3 l 8 29 46 43 35 ain2lp/ain3l 34 ain2ln/ain4l 33 ain2rp/ain3r 32 ain2r n /ain4r 39 ain 1l /inp1 38 inn1 37 ain 1r / inp2 36 inn2 41 mpwr mpref 40 1 ? 4.7 k 4.7 k 4.7 k 4.7 k 10 ? 0.1 ? 1 ? 1 ? 1 ? 1 ? 100n 100n 100n 100n xto xti rd 12 13 14
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 136 - 2. spi interface figure 83 . spi interface connection e x ample sdout1/rdy 20 28 so sclk 26 25 up 45 pdn reset control ak77 35 vrefh audio i/f clock csn 24 & 23 sto/ rdy/ sdout 2 sdin 1 17 42 analog +3.3 v avdd 10 ? 0.1 ? vcom 44 2.2 ? dvss 1/dvss2 /dvss 3 10, 22 , 30 21 digital io 1.8 3.3 v t vdd 10 ? 0.1 ? 11 digital io 3.3 v vdd33 10 ? 0.1 ? 31 digital core 3.3 v lvdd 10 ? 0.1 ? vrefl avss avdrv 2.2 ? 2 aout1r 47 aout1l 48 aout2l aout2r 1 si 27 sdin 2 /jx0 lrck 1 18 bick 1 19 lrck 2 /jx1 15 bick 2 /jx2 1 6 sdout 3/clko/gpo1 7 sdin 3 /jx3 sdin 4 9 sdout 4/ gpo 2 5 lrck 3 4 bick 3 6 audio i/f clock & testi 3 l 8 29 46 43 35 ain2lp/ain3l 34 ain2ln/ain4l 33 ain2rp/ain3r 32 ain2r n /ain4r 39 ain 1l /inp1 38 inn1 37 ain 1r /inp2 36 inn2 41 mpwr mpref 40 1 ? 4.7 k 4.7 k 4.7 k 4.7 k 10 ? 0.1 ? 1 ? 1 ? 1 ? 1 ? 100n 100n 100n 100n xto xti rd 12 13 14
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 137 - peripheral circuit 1. ground avss, dvss1, dvss2 and dvss3 should be connected to the same ground. decoupling capacitors, pa rticularly ceramic capacitors of small capacity, should be placed at positions as close as possible to the ak77 35 . 2. reference voltage vcom is a common voltage of this chip and the vcom pin outputs avdd/2. a 2.2f ceramic capacitor should be connected between the vcom pin and a vss. do not connect the vcom pin to any external devices. digital signal lines, especially clock signal line should be kept away as far as possible from this pin in order to avo id unwanted coupling into the ak77 35 . 3. analog input the analog input signal is input to the analog modulator of the ak7735. the max imum input voltage at differential input pins is 2. 30vpp (typ.) or 2. 83vpp (typ.) . the maximum input voltage at single - ended input pins is 2. 30vpp (typ.) or 2. 83vpp (typ.) . the output code format is 2's complements. the internal hpf removes the dc offset . after power - down is released, the internal operating point level avdd/2 occurs on analog input pins of the ak77 35 . concerning the internal operating point formation circuit, each input pin has impedance of 2 5 k ? ( t yp . ). the pins that are connected to ac coupling capacitors require start - up time (time constant). the ak77 35 samples the analog inputs at 6.144 mhz when fs=48khz , 96khz or 192khz . the ak77 35 includes an anti - aliasing filter (rc filter) , and n o external low - pass filter is necessary in front of t he adc. however, an external low - pass filter should be connected before the adc for the signal which has large out - of - band noise such as d/a converted signals. the analog power supply to the ak77 35 is +3.3v (t yp .) . voltage of avdd + 0.3v or larger , voltage of a vss - 0.3v or smaller , and current of 10ma or larger must not be applied to analog input pins. excessive current will damage the internal protection circuit and will cause latch - up, damaging the ic. accordingly, if the e xternal analog circuit voltage is 15v, the analog input pins must be protected from signals which are equal or larger than absolute maximum rating s . when using differential input mode, it is prohibited to input signal to only one side like pseudo differential input. 4. analo g output the analog output is single - ended and the output signal range is typically 0. 857 x avdd vpp centered on v com . the digital input data format is two s compliment. positive full - scale output corre sponds to 7ffff ff fh (@ 32 bit) inpu t code, negative full scale is 80 00 0000h (@ 32 bit) and vcom voltage ideally is 000 00 000h (@ 32 bit) . the out - of - band noise (shaping noise) generated by the internal delta - sigma modulator is attenuated by an integrated switched capacitor filter (scf) and a con tinuous time filter (ctf).
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 138 - 5 . crystal oscillator the resistor and capacitor values for the oscillator rc circuit are shown blow. oscillator r1 ( max ) c0 ( max ) xti, xto pin capacity 12.288mhz 120 80
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 139 - 14. package outline dimensions material and lead finis h package: epoxy , halogen (br and ci) free lead frame: copper lead - finish: soldering (pb free) plate
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 140 - marking 1) pin #1 indication 2) date code: xxxxxxx (7 digits) 3) marking code: ak7735vq 1) pin #1 indication 2) date code: xxxxxxx (7 digits) 3) marking code: AK7735EQ ak77 35vq xxxxxxx 1 ak77 35 e q xxxxxxx 1
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 141 - 15. ordering guide ak7735vq - 40 ? +85 ? c 48 - pin lqfp (0.5mm pitch) ak7735 e q - 2 0 ? +85 ? c 48 - pin lqfp (0.5mm pitch) akd7735 evaluation board for ak7735 16. revision history date (y/m/d) revision reason page contents 16/ 12/01 00 first edition
[ ak 7735 ] 016014707 - e - 00 201 6 / 12 - 142 - important notice 0. asahi kasei microdevices corporation (akm) reserves the right to make changes to the information contained in this document without notice. when you consider any use or application of akm product stipulated in this document ( product ) , please make inquiries the sales office of akm or authorized d istributor s as to current status of the products. 1. all information included in this document are provided only to illustrate the operation and application examples of akm products . akm neither makes warranties or representations with respect to the accur acy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of akm or any third party with respect to the information in this document. you are fully responsible for use o f such information contained in this document in your product design or applications . akm assumes no liability for any losses incurred by you or third parties arising from the use of such information in your product design or applications. 2. the product is neither intended nor warranted for use in equipment or systems that require extraordinarily high levels of quality and/or reliability and/or a malfunction or failure of which may cause loss of human life, bodily injury, serious property damage or seriou s public impact , including but not limited to, equipment used in nuclear facilities, equipment used in the aerospace industry, medical equipment, equipment used for automobiles, trains, ships and other transportation, traffic signaling equipment, equipment used to control combustions or explosions, safety devices, elevators and escalators, devices related to electric power, and equipment used in finance - related fields. do not use product for the above use unless specifically agreed by akm in writing . 3. tho ugh akm works continually to improve the products quality and reliability, you are responsible for complying with safety standards and for providing adequate designs and safeguards for your hardware, software and systems which minimize risk and avoid situations in which a malfunction or failure of the product could cause loss of human life, bodily injury or damage to property, including data loss or corruption. 4. do not use or otherwise make available the product or related technology or any information contained in this document for any military purposes, including without limitation, for the design, development, use, stockpiling or manufacturing of nuclear, chemical, or biological weapons or missile technology pr oducts (mass destruction weapons). when exporting the p roducts or related technology or any information contained in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws an d regulations. the p roducts and related technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. 5. please contact akm sales repr esentative for details as to environmental matters such as the rohs compatibility of the product. please use the product in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without l imitation, the eu rohs directive. akm assumes no liability for damages or losses occurring as a result of noncompliance with applicable laws and regulations. 6. resale of the product with provisions different from the statement and/or technical features se t forth in this document shall immediately void any warranty granted by akm for the product and shall not create or extend in any manner whatsoever , any liability of akm. 7. this document may not be reproduced or duplicated, in any form, in whole or in par t, without prior written consent of akm .

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