1 ? fn6189.3 isl45041 tft-lcd i 2 c programmable vcom calibrator the v com voltage of an lcd panel needs to be adjusted to remove flicker. this part provid es a digital interface to control the sink-current output that at taches to an external voltage divider. the increase in output sink current lowers the voltage on the external divider, which is applied to an external v com buffer amplifier. the desired v com setting is loaded from an external source via a standard 2-wire i 2 c serial interface. at power up, the part automatically comes up at the last programmed eeprom setting. an external resistor attaches to the set pin and sets the full-scale sink current that det ermines the lowest voltage of the external voltage divider. the isl45041 is available in an 8 ld 3mmx3mm tdfn package with a maximum thickness of 0.8mm for ultra thin lcd panel design. an evaluation kit complete with software to control the dcp from a computer is available. reference application note an1275 and ?ordering information?. features ? 128-step adjustable sink current output ? 2.25v to 3.6v logic supply voltage operating range (2.25v minimum programming voltage) ? analog supply voltage range 4.5v to 18v for vdd from 2.6v to 3.6v; 4.5v to 13v for vdd from 2.25v to 2.6v ?i 2 c interface (slave and transmitter) - address: 1001111 ? on-board 7-bit eeprom ? output adjustment set pin ? output guaranteed monotonic over-temperature ? thin 8 ld 3mmx3mm dfn (0.8mm max) ? pb-free (rohs compliant) applications ? lcd panels pinout isl45041 (8 ld tdfn) top view ordering information part number (note) part marking temp. range (c) package (pb-free) pkg. dwg. # isl45041irz 041z 0 to +85 8 ld 3x3 tdfn l8.3x3a ISL45041IRZ-T* 041z 0 to +85 8 ld 3x3 tdfn tape and reel l8.3x3a isl45041eval1z evaluation board *please refer to tb347 for detai ls on reel specifications. note: these intersil pb-free pl astic packaged products employ special pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations). intersil pb-free products are msl classified at pb-free peak reflow te mperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. out avdd wp gnd 1 2 3 4 8 7 6 5 set scl sda vdd data sheet august 12, 2010 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2005, 2006, 2007, 2010. all rights reserved all other trademarks mentioned are the property of their respective owners.
2 fn6189.3 august 12, 2010 pin descriptions pin type pull u/d function out output adjustable sink current output pin. the current si nks into the out pin is equal to the dac setting times the maximum adjustable sink current di vided by 128. see set pin function description for the maximum adjustable sink current setting. avdd supply high-voltage analog supply. by pass to gnd with 0.1f capacitor. wp input pull-down write protect. active low. to enable programming, connect to 0.7*vdd supply or greater. the wp pin is designed for static control. it has an internal pull-dow n 150k resistor. to avoid possibly over-writing the eeprom contents, no frequency above 1hz should be applied to this input. care should be taken to avoid any glitches on the input. when removing or applying mec hanical jumpers, always ensure the vdd power is off. a high to low transition on the wp pin results in the register contents being loaded with eeprom data. gnd supply ground connection. vdd supply system power supply input. by pass to gnd with 0.1f capacitor. sda in/out i 2 c serial data input and output. scl input i 2 c clock input set analog maximum sink current adjustment point. connect a re sistor from set to gnd to set the maximum adjustable sink current of the out pin. the maximum adjustable sink current is equal to (avdd/20) divided by rset. block diagram isl45041 i 2 c interface analog dcp and current output block avdd out set sda vdd gnd d<7:0> scl 7-bit eeprom 128 data registers wp isl45041
3 fn6189.3 august 12, 2010 absolute maximum rati ngs thermal information v dd to gnd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+4v input voltages to gnd set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +4v avdd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +20v output voltages to gnd out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +20v esd rating hbm for device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2kv hbm for input pins (scl, sda) . . . . . . . . . . . . . . . . . . . . . . . .4kv operating conditions temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . 0c to +85c thermal resistance (typical, note 1) ja (c/w) 8 ld tdfn package. . . . . . . . . . . . . . . . . . . . . . . . . 170 moisture sensitivity (see technical brief tb363) all packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . level 2 maximum junction temperature (plastic package) . . . . . . +150c maximum storage temperature range . . . . . . . . . .-65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp caution: do not operate at or near the maximum ratings listed fo r extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. note: 1. ja is measured with the component mounted on a high effective therma l conductivity test board in free air. see tech brief tb379 f or details. electrical specifications test conditions: v dd = 3v, av dd = 10v, out = 5v, r set = 24.9k ; unless otherwise specified. typicals are at t a = +25c parameter symbol test conditions temp (c) min (note 7) typ max (note 7) units dc characteristics v dd supply range - operating v dd full 2.25 - 3.6 v v dd supply range - eeprom programming v dd full 2.25 - 3.6 v v dd supply current i dd (note 4) full - - 50 a avdd supply range avdd v dd range 2.6v to 3.6v full 4.5 - 18 v v dd range 2.25v to 2.6v full 4.5 - 13 v avdd supply current iavdd (note 2) full - - 25 a set voltage resolution set vr full 7 7 7 bits set differential nonlinearity set dn monotonic over-temperature full - - 1 lsb set zero-scale error set zse full - - 2 lsb set full-scale error set fse full - - 8 lsb set current iset through r set (note 5) full - 20 - a set external resistance set er to gnd, av dd = 20v full 10 - 200 k to gnd, av dd = 4.5v full 2.25 - 45 k avdd to set voltage attenuation avdd to set (note 3) full - 1:20 - v/v out settling time out st to 0.5 lsb error band (note 3) full - 8 - s out voltage range v out full vset + 0.5v - 13 v set voltage drift set vd (note 3) 25 to 55 - <10 - mv sda, scl, wp input logic high vih full 0.7*vdd - - v sda, scl, wp input logic low vil full - - 0.3*vdd v sda, scl, wp hysteresis (note 3) full - 0.22*vdd - v wp input current il wpn full 15 25 35 a sda, scl logic high voh s @ 3ma full 0.4 - - v sda, scl logic low vol s @ 3ma full - - 0.4 v isl45041
4 fn6189.3 august 12, 2010 i 2 c scl clock frequency f scl full 0 - 400 khz i 2 c clock high time t sch full 0.6 - - s i 2 c clock low time t scl full 1.3 - - s i 2 c spike rejection filter pulse width t dsp full 0 - 50 ns i 2 c data set-up time t sds full 100 - - ns i 2 c data hold time t sdh full 0 - 900 ns i 2 c sda, scl input rise time t icr dependent on load (note 6) full - 20 + 0.1*cb 1000 ns i 2 c sda, scl input fall time t icf (note 6) full - 20 + 0.1*cb 300 ns i 2 c bus free time between stop and start t buf full 1.3 - - s i 2 c repeated start condition set-up t sts full 0.6 - - s i 2 c repeated start condition hold t sth full 0.6 - - s i 2 c stop condition set-up t sps full 0.6 - - s i 2 c bus capacitive load cb full - - 400 pf capacitance on sda c sda full - - 10 pf capacitance on scl c s wp = 0 full - - 10 pf wp = 1 - - 22 pf write cycle time t w full - - 100 ms notes: 2. tested at av dd = 20v. 3. simulated and determined via design and not directly tested. 4. simulated maximum current draw when programming eeprom is 23ma, should be considered when designing power supply. 5. a typical current of 20a is calculated using the avdd = 10v and rset = 24.9k . reference ?rset resistor? on page 5. 6. simulated and designed according to i 2 c specifications. 7. parameters with min and/or max limits are 100% tested at +25 c, unless otherwise specified. temperature limits established by characterization and are not production tested. electrical specifications test conditions: v dd = 3v, av dd = 10v, out = 5v, r set = 24.9k ; unless otherwise specified. typicals are at t a = +25c (continued) parameter symbol test conditions temp (c) min (note 7) typ max (note 7) units isl45041
5 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn6189.3 august 12, 2010 application information this device provides the ability to reduce the flicker of an lcd panel by adjustment of the v com voltage during production test and alignment. a 128-step resolution is provided under digital control, which adjusts the sink current of the output. the output is connected to an external voltage divider, so that the device will have the capability to reduce the voltage on the output by increasing th e output sink current. the adjustment of the output is provided by the 2-wire i 2 c serial interface. expected output voltage the isl45041 provides an output sink current, which lowers the voltage on the external voltage divider (vcom output voltage). equation 1 and equation 2 can be used to calculate the output current (i out) and output voltage (v out ) values. note: where setting is an integer between 1 and 128. table 1 gives the calculated value of v out for the evaluation board using the on-board resistors values of: r set = 24.9k, r 1 = 200k, r 2 = 243k, and av dd = 10v. r set resistor the external r set resistor sets the full- scale sink current that determines the lowest voltage of the external voltage divider r 1 and r 2 (figure 1). the voltage difference between the out pin and set pin (figure 2) has to be greater than 1.75v. this will keep the output mos transistor in the saturation region. expected current settings and 7-bit accuracy occurs when the output mos transistor is oper ating in the saturation region. figure 2 shows the internal c onnection for the output mos transistor. the value of the av dd supply sets the voltage at the source of the output transistor . this voltage is equal to (setting/128) x (av dd /20). the i set current is therefore equal to (setting/128) x (av dd /20 x r set ). the value of the drain voltage is found using equation 2. the values of r 1 and r 2 (equation 2) should be determined (setting equal to 128) so the minimum value of v out is greater than 1.75v + av dd /20. ramp-up of the vdd power supply it is required that the ramp-up from 10% vdd to 90% vdd level be achieved in less than or equal to 10ms to assure that the eeprom and power-on-reset circuits are synchronized and the correct value is read from the eeprom memory. table 1. setting value v out 1 5.468 10 5.313 20 5.141 30 4.969 40 4.797 50 4.625 r set figure 1. output connection circuit example - + isl45041 set out avdd r 1 r 2 avdd i out i out setting 128 -------------------- - x av dd 20 r set () --------------------------- = v out r 2 r 1 r 2 + -------------------- - ?? ?? ?? av dd 1 setting 128 -------------------- - x r 1 20 r set () --------------------------- ? ?? ?? ?? = (eq. 1) (eq. 2) 60 4.453 70 4.281 80 4.109 90 3.936 100 3.764 110 3.592 128 3.282 table 1. (continued) setting value v out figure 2. output connection circuit example av dd = 15v rset out pin r1 r2 avdd vsat 0.5v set pin setting 128 ---------------------------- x av dd 20 ----------------- - isl45041
6 fn6189.3 august 12, 2010 i 2 c timing diagram figure 3 shows the i 2 c timing diagram and expected scope photos of sc l and sda when writing all zeros or all ones. figure 3. isl45041 i 2 c timing diagram 9 e 0 to write to eeprom 8-bit address 4 f 7-bit address i 2 c slave address isl45041
7 fn6189.3 august 12, 2010 isl45041 package outline drawing l8.3x3a 8 lead thin dual flat no-lead plastic package rev 4, 2/10 located within the zone indicated. the pin #1 identifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 id entifier is optional, but must be between 0.15mm and 0.20mm from the terminal tip. dimension applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing c onform to asme y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: bottom view detail "x" side view typical recommended land pattern top view c 0 . 2 ref 0 . 05 max. 0 . 02 nom. 5 3.00 a b 3.00 (4x) 0.15 6 pin 1 index area pin #1 6x 0.65 1.50 0.10 8 1 8x 0.30 0.10 6 0.75 0.05 see detail "x" 0.08 0.10 c c c ( 2.90 ) (1.50) ( 8 x 0.30) ( 8x 0.50) ( 2.30) ( 1.95) 2.30 0.10 0.10 8x 0.30 0.05 a mc b 4 2x 1.950 (6x 0.65) index area pin 1 compliant to jedec mo-229 weec-2 except for the foot length. 7.
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