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3.3 v, 4.25 gbps, limiting amplifier data sheet adn2892 rev. a document f eedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its us e. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2005 C 2013 analog devices, inc. all rights reserved. technical support www.analog.com f eatures input sensitivity: 3.5 mv p -p 70 ps rise/fall times cml outputs: 75 0 mv p - p differential bandwidth selectable for multirate 1 /2 /4 fc modules optional los output i nversion programmable los detector: 3.5 mv to 35 mv rx signal strength indicator ( r ssi) sff - 8472 - compliant average power measurement single - supply operation: 3.3 v low power dissipation: 160 mw available in space - saving , 3 mm 3 mm , 16 - lead lfcsp extended temperature r ange: ? 40 c to + 95 c sfp reference design available a pplications 1 , 2 , and 4 fc t ransceivers sf p/sff/gbic optical transceivers gbe transceivers backplane r eceivers g eneral d escription the adn2892 is a 4.25 gb p s limiting amplifier with integrated loss of s ignal (los) d etection circuitry and a received signal strength indica tor (rssi). this part is optimized for fibre channel (fc) and gigabit ethernet (gbe) optoelectronic conversion applications. the adn2892 has a dif fe rential input sensitivity of 3.5 mv p - p and accepts up to a 2.0 v p - p differential input overload voltage. the adn2892 ha s current mode logic (cml) outputs with controlled rise and fall times. the a dn2892 has a selectable low - pass filter with a ?3 db cutoff frequency of 1.5 ghz. by setting bw_ sel to l ogic 0, t he filter can limit the relaxation oscillation of a low cost cd laser used in a legacy 1 gbps fc transmitter. the limited bw also reduces the rms noise and in turn improves the receiver opti cal sensitivity for a lower data rate application, such as 1 fc and gbe. by monitoring the bias current through a photodiode, the on - chip rssi detector measures the average power received with 2% typical linearity over the entire valid input range of the photodiode. the on - chip rssi detector facilitates sff - 8472 - compliant optical transceivers by eliminating the need for external rssi detector circuitry. additional features include a programmable loss - of -signal (los) detector and output squelch. the adn2892 is available in a 3 mm 3 mm, 16 - lead lfcsp. f unctional b lock d iagram lpf adn2892 avcc avee bw_sel squelch drvcc drvee rssi/los detector adn2882 outp outn pin nin 50w 50w 3.5kw v ref 50w 50w pd_vcc pd_cathode los rssi_out v+ 10kw aduc7020 thradj los_inv 04986-001 figure 1. r ssi function capable applications setup block dia gram
adn2892 data sheet rev. a | page 2 of 16 table of contents specification s ..................................................................................... 3 absolute maximum ratings ............................................................ 5 thermal resistance ...................................................................... 5 esd caution .................................................................................. 5 pin configuration and function descriptions ............................. 6 typical performance characteristics ............................................. 7 theory of operation ...................................................................... 10 limiting amplifier ..................................................................... 10 loss - of - signal (los) detector ................................................. 10 received signal strength indicator (rssi) .............................. 10 squelch mode ............................................................................. 10 bw_sel (bandwidth selection) mo de ................................... 10 los_inv (lose of signal_invert) mode ................................ 10 applications ..................................................................................... 11 pc b design guidelines ............................................................. 11 pad coating and pb - free soldering ........................................ 12 outline dimensions ....................................................................... 13 ordering guide .......................................................................... 13 r evision h istory 7 /13 rev. 0 to rev. a change to output voltage swing parameter, table 1 ................... 3 changes to figure 2 ........................................................................... 6 updated outline dimensions ........................................................ 13 changes to ordering guide ........................................................... 13 4 /05 revision 0 : initial version
data sheet adn2892 rev. a | page 3 of 16 specifications test conditions: vcc = 2.9 v to 3.6 v, vee = 0 v, t a = ?40 c to +95 c , unless otherwise noted. table 1 . parameter min typ max unit test conditions/comments quantizer dc characteristics inp ut voltage range v cc ? 1.2 v cc ? 0.2 v at pin or nin, dc - coupled input common mode 2.1 2.7 v dc - coupled peak -to - peak differential input range 2.0 v p -p pin ? nin, ac - coupled input sensitivity 6.6 3.5 mv p -p pin ? nin, ber 1 10 ?10 input offset voltage 100 v input rms noise 2 3 5 v rms input resistance 50 ? single - ended input capacitance 0.65 pf quantizer ac characteristics input data rate 1.0 4.25 gbps small signal gain 51 db differential s11 ?10 db differential, f < 4.25 ghz s22 ?10 db differential, f < 4.25 ghz random jitter 3. 0 3.9 ps rms input 10 mv p - p, 4 fc , k 28.7 pattern deterministic jitter 10 21.0 ps p-p input 10 mv p - p, 4 fc, k 28.5 pattern low frequency cutoff 30 khz power supply rejection 45 db 100 khz < f < 10 mhz loss of signal detector (los) los assert level 2.9 3.5 4.8 mv p -p r thradj = 1 00 k ? 22.4 35 55.0 mv p -p r thradj = 1 k ? electrical hysteresis 2.5 5.0 db 1.0 gbps, prbs 2 23 ? 1 2.8 5.0 db 4 fc, prbs 2 23 ? 1 los as sert time 950 ns dc - coupled los deassert time 62 ns dc - coupled rssi input current range 5 1000 a rssi output linearity 2 % 5 a i in 1000 a gain 1.0 ma/ma i rssi /i pd_cathode offset 145 na compliance voltage (at pd_cathode) v cc ? 0.4 v i pd_cathode = 5 a v cc ? 0.9 v i pd_cathode = 1000 a bw_sel (bandwidth selection) channel bandwidth 1.5 ghz ?3 db cutoff frequency of the on - chip, two - pole , low - pass filter, when bw_sel = 0 power supplies v cc 2.9 3.3 3.6 v i cc 48 54 ma operating temperature range ?40 +25 +95 c t min to t max cml output characteristics output impedance 50 ? single - ended output voltage swing 600 750 940 m v p -p differential output rise and fall time 70 103 ps 20% to 80%
adn2892 data sheet rev. a | page 4 of 16 parameter min typ max unit test conditions/comments logic inputs (squelch, los_inv, and bw_sel) v ih , input high voltage 2.0 v v il , input low voltage 0.8 v input current ( squelch, los_inv) 39 a i inh , v in = 2.4 v, 100 k? pull - down, on - chip resistor input current ( bw_sel) ?38 a i inl , v in = 0.0 v, 100 k? pull - up, on - chip resistor logic outputs (los) v oh , output high voltage 2.4 v open drain output, 4.7 k? ? 10 k? pull - up resistor to vcc v ol , output low voltage 0.4 v open drain output, 4.7 k? ? 10 k? pull - up resistor to vcc
data sheet adn2892 rev. a | page 5 of 16 absolute maximum rat ings table 2 . parameter rating power supply voltage 4.2 v minimum voltage (all inputs and outputs) vee ? 0.4 v maximum voltage (all inputs and outputs) vcc + 0.4 v storage temperature ?65c to +150c operating temperature range ?40c to +95c production soldering temperature j - std -20 junction temperature 125c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and fun ctional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. therm al resistance ja is specified for 4 - layer pcb with exposed paddle soldered to gnd. table 3 . package type ja unit 3 mm 3 mm, 16 - lead lfcsp 28 c/w esd caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although this product features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discha rges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
adn2892 data sheet rev. a | page 6 of 16 pin configuration and function descripti ons 04986-002 notes 1. there is an exposed pad on the bottom of the package that must be connected to the gnd plane with filled vias. 1 avdd 2pin 3 nin 4avee 11 outp 12 drvcc 10 outn 9 drvee 5 thradj 6 bw_sel 7 los_inv 8 los 15 pv_vcc 16 pd_cathode 14 rssi_out 13 squelch top view (not to scale) adn2892 figure 2 . pin configuration table 4 . pin function descriptions pin o. neonic i/ tpe 1 description 1 avcc p analog power supply. 2 pin ai differential data input, positive port, 50 ? on- chip termination. 3 nin ai differential data input, negative port, 50 ? on- chip termination. 4 avee p a nalog ground. 5 thradj ao los threshold adjust resistor. 6 bw_sel di with one 100 k? on - chip , pull - up resistor, bw_sel = 0 for 1 /2 fc, bw_sel = 1 for 4 fc . 7 los_inv di with one 100 k? on - chip , pull - down resistor, los_inv = 1 inverts the los output to be active low for sff. 8 los do los detector output, open collector. 9 drvee p output buffer ground. 10 outn do differential data output, cml, negative port, 50 ? , on - chip termination. 11 outp do differential data output, cml, positive port, 50 ? , on- chip termination. 12 drvcc p output buffer power supply. 13 squelch di disable outputs, 100 k ? on - chip , p ull - down resistor. 14 rssi_out ao average current output. 15 pd_vcc p power input for rssi measurement. 16 pd_cathode ao photodiode bias voltage . exposed pad pad p connect to ground. 1 p = power; di = digital input; do = digital output; ai = analog input; and ao = analog output.
data sheet adn2892 rev. a | page 7 of 16 typical performance characteristics 50ps/div 150mv/div 04986-012 figure 3 . eye of adn2892 @ 25c, 4.25 gbps, and 10 mv input 50ps/div 150mv/div 04986-023 figure 4 . eye of adn2892 @ 95c, 4.25 gbps, and 10 mv input 200ps/div 150mv/div 04986-010 figure 5. eye of adn2892 at 25c, 1.0 63 gbps, and 10 mv input ( bw_sel = 0 ) 0 04986-026 r th ( w ) trip and release (v) 1k 100k 0.06 10k 0.05 0.04 0.03 0.02 0.01 ? 40 c +25 c +95 c assertion deassertion ? 40 c +25 c +95 c figure 6. los trip and release vs. r th at 4.25 gbps 0 04986-027 r th (w) electrical hysteresis (db) 1k 100k 8 10k 7 6 5 4 3 2 1 1gbps 4.25gbps figure 7. los electrical hysteresis vs. r th at 25c 16 0 04986-024 electrical hysteresis (db) samples 5.8 14 12 10 8 6 4 2 6.0 6.2 6.4 6.6 6.8 7.0 7.2 7.4 7.6 7.8 8.0 8.2 8.4 8.6 figure 8 . sample lot distribution worst - case condition: conditions = 4.25 gbps, 100 k? @ ?40c, 3.6 v
adn2892 data sheet rev. a | page 8 of 16 0 04986-028 rate (gbps) jitter (ps) 1.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 1.5 2.0 2.5 3.0 3.5 4.0 figure 9. random jitter vs. data rate 0 04986-029 rate (gbps) jitter (ps) 1.0 4.5 18 16 14 12 10 8 6 4 2 1.5 2.0 2.5 3.0 3.5 4.0 figure 10 . determ inistic jitter vs. data rate 70 0 100k 04986-016 supply-noise frequency power supply-noise rejection (db) 10m 60 50 40 30 20 10 1m figure 11 . psrr vs. supply - noise frequency 1200 0 0 04986-017 pd_cathode current (photodiode current) ( a) rssi output current ( a) 1000 800 600 400 200 200 400 600 800 1000 figure 12 . rssi output vs. average photodiode current 60 0 0 04986-020 pd_cathode current (photodiode current) ( a) rssi output current ( a) 50 40 30 20 10 10 20 30 40 50 figure 13 . rssi output vs. average photodio de current (zoomed) ? 0.15 ? 0.70 04986-018 input current ( a) compliance voltage referred to vcc (v) 0 1000 ? 0.20 ? 0.25 ? 0.30 ? 0.35 ? 0.40 ? 0.45 ? 0.50 ? 0.55 ? 0.60 ? 0.65 100 200 300 400 500 600 700 800 900 figure 14 . pd_cathode compliance voltage vs. input current rssi (refer to vcc)
data sheet adn2892 rev. a | page 9 of 16 0 04986-019 temperature (c) 5a referred offset (na) ?40 100 900 800 700 600 500 400 300 200 100 ?20 0 20 40 60 80 figure 15 . rssi offset difference between measured rssi output and pd_cathode (input) current of 5 a 5.0 0 04986-021 pd_cathode current ( a) rssi linearity (%) 0 1000 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 200 400 600 800 +100 c +30 c ? 40 c figure 16 . rssi linearity % vs. pd_cathode current 04986-025 46.0 temperature ( c) i cc (ma) 49.0 48.5 48.0 47.5 47.0 46.5 100 ? 40 ? 20 0 20 40 60 80 figure 17 . adn2892 i cc current vs. temperature
adn2892 data sheet rev. a | page 10 of 16 theory of operation limiting amplifier input buffer the adn2892 limiting amplifier provide s diffe rential inputs (pin/nin), each with a single - ended, on - chip 50 ? termination. the amplifier can accept either dc - coupled or ac - coupled signals; however, an ac - coupled signal is recommended. using a dc - coupled signal, the amplifier needs a nominal vcc ? 0.7 v common - mode voltage and 0.5 v h eadroom. if the input common - mode voltage is 2.4 v, the available headroom is reduce d down to 0.3 v. the adn2892 limiting amplifier is a high gain device. it is susceptible to dc offsets in the signal path. the pulse width distortion presented in the nrz data or a distortion generated by the tia may appear as dc offset or a corrupted signal to the adn2892 inputs. an internal offset correction loop can compensate for certain levels of offset. cml output buffer the adn2892 provides differential cml outputs, outp and outn. each output has an internal 50 ? termination to vcc. loss - of - signal (los) detecto r the on - chip los circuit drives los to logic high when the input signal level falls below a user - programmable threshold. the threshold level can be set anywhe re from 3.5 mv pp to 35 mv pp typical by a resistor connected between the thradj pin and vee. see figure 6 and figure 7 for the los threshold vs. thradj. the adn2892 los ci rcuit has an electrical hysteresis greater than 2.5 db to prevent chatter at the los s ignal. the los output is an open - collector output that must be pulled up externally with a 4.7 k? to 10 k? resistor. received signal stre ngth indicator (rssi ) the adn2892 has an on - chip, rssi circuit. by monitoring the current supplied to the photodiode, the rssi circuit provides an accurate, average power measurement. the output of the rssi is a current that is directly proportional to the average amount of pin photodiode current. placing a resistor between the rssi_out pin and gnd converts the current t o a gnd referenced voltage. this function eliminates the need for external rssi circuitry for sff - 8472- compliant optical receivers. for more information, see figure 12 to fi gure 16. connect the pd_vcc, pd_cathode, and rssi_out pins to avc c to disable the rssi feature. squelch mode driving the squelch input to logic high disables the limiting amplifier outputs. using los output to drive the squelch input, the limiting amplifi er outputs stop toggling anytime a signal input level to the limiting amplifier drops below the programmed los threshold. the squelch pin has a 100 k?, internal pull - down resistor. bw_sel (bandwidth selection ) m ode driving the bw_sel input signal to logic high , the amplifier provides a 3.8 ghz bandwidth. driving the bw_sel input signal to logic low , the amplifier accepts input si gnal s through a 1.5 ghz , 2 - pole , low - pass filter that improves receiving sensitivity. the low - pass filter reduces the possibl e relaxation oscillation of low speed, low cost laser source by limiting the input signal bandwidth. the bw_sel pin has a 100 k?, on - chip pull - up resistor. s etting the bw_sel pin open disables the low - pass filter . los _ inv (lose of signal_inve rt) m ode some applications , such as sff, need the los assertion and deassertion voltage reversed . when the los_inv pin is pulled to logic high , the los output assertion is pulled down to electrical low . the los_inv pin has a 100 k ? on - chip , pull - down resistor.
data sheet adn2892 rev. a | page 11 of 16 applications pcb design guidelines proper rf pcb design techniques must be used to ensure optimal performance. output buffer power supply and ground planes pin 9 (drvee) and pin 12 (drvcc) are the power supply and ground pins that provide current to the differential output buffer. to reduce possible series inductance, pin 9, which is the ground return of the output buffer, should connect to ground directly. if the ground plane is an internal plane and connections to the ground plane are vias, multiple vias in parallel to ground can reduce series inductance. similarly, to reduce the possible series inductance, pin 12, which supplies power to the high speed differential outp/outn output buffer, should connect to the power plane directly. if the power plane is an internal plane and connections to the power plane are vias, multiple vias in parallel can reduce the series inductance, especially on pin 12. see figure 18 for the recommended connections. the exposed pad should connect to the gnd plane using filled vias so that solder does not leak through the vias during reflow. using filled vias in parallel under the package greatly reduces the thermal resistance and enhances the reliability of the connectivity of the exposed pad to the gnd plane during reflow. to reduce power supply noise, a 10 f electrolytic decoupling capacitor between power and ground should be close to where the 3.3 v supply enters the pcb. the other 0.1 f and 1 nf ceramic chip decoupling capacitors should be close to the vcc and vee pins to provide optimal supply decoupling and a shorter current return loop. 04986-008 connect exposed pad to gnd avcc 1 thradj 5 bw_sel 6 los_inv 7 los 8 pd_cathode 16 pd_vcc 15 rssi_out 14 squelch 13 pin 2 nin 3 avee 4 drvcc 12 outn 10 drvee 9 outp c4 c3 11 c2 c1 to host board c7 c8 vcc c5 c6 vcc c12 r2 vcc r3 4.7k ? to 10k ? on host board vcc adn2882 0.1 ?f vcc c9 rssi measurement to adc r1 c10 c1?c4, c11: 0.01 ?f x5r/x7r dielectric, 0201 case c5, c7, c9, c10, c12: 0.1 ? f x5r/x7r dielectric, 0402 case c6, c8: 1nf x5r/x7r dielectric, 0201 case to aduc7020 adn2892 figure 18. typical adn2892 applications circuit
adn2892 data sheet rev. a | page 12 of 16 pcb layout figure 19 shows the recommended pcb layout. the 50 transmission lines are the traces that bring the high frequency input and output signals (pin, nin, outp, and outn) from a terminated source to a terminated load with minimum reflection. to avoid a signal skew between the differential traces, each differential pin/nin and outp/outn pair should have matched trace lengths from a differential source to a differential load. c1, c2, c3, and c4 are ac coupling capacitors in series with the high speed, signal input/output paths. to minimize the possible mismatch, the ac coupling capacitor pads should be the same width as the 50 transmission line trace width. to reduce supply noise, a 1 nf decoupling capacitor should be placed as close as possible to the vcc pins on the same layer and not through vias. a 0.1 f decoupling capacitor can be placed on the bottom of the pcb directly underneath the 1 nf capacitor. all high speed, cml outputs have internal 50 resistor termination between the output pin and vcc. the high speed inputs, pin and nin, also have the internal 50 termination to an internal reference voltage. as with any high speed, mixed-signal design, keep all high speed digital traces away from sensitive analog nodes. soldering guidelines for the lfcsp the lands on the 16-lead lfcsp are rectangular. the pcb pad for these should be 0.1 mm longer than the package land length and 0.05 mm wider than the package land width. the land should be centered on the pad. this ensures that the solder joint size is maximized. the bottom of the lfcsp has a central exposed pad. the pad on the printed circuit board should be at least as large as the exposed pad. users must connect the exposed pad to vee using filled vias so that solder does not leak through the vias during reflow. this ensures a solid connection from the exposed pad to vee. pad coating and pb-free soldering table 5. pad coating matt-tin pb-free reflow portfolio j-std-20b 04986-009 1 filled vias to gnd exposed pad pin nin via to c12, r2 on bottom vias to bottom double-via to gnd to reduce inductance c3 c8 c4 c1 c2 outp double-vias to reduce inductance to supply and gnd r1, c9, c10 on bottom to rosa place c7 on bottom of board underneath c8 outn place c5 on bottom of board underneath c6 ? 4mm transmission lines same width as ac coupling caps to reduce reflections gnd avcc dvcc gnd c6 figure 19. recommended adn2892 pcb layout (top view)
data sheet adn2892 rev. a | page 13 of 16 outline dimensions * compli ant to jedec standards mo-220-veed-2 except for expose d pad dim ension. 1 0.50 bsc 0.60 max pin 1 indicator 1.50 re f 0.50 0.40 0.30 0.25 min 0.45 2.75 bsc sq top view 12 max 0.80 max 0.65 typ seating plane pin 1 indicat or 0.90 0.85 0.80 0.30 0.23 0.18 0.05 ma x 0.02 nom 0.20 ref 3.00 bsc s q * 1.65 1.50 sq 1.35 16 5 13 8 9 12 4 exposed pad bottom view for prope r connec tion o f the exp osed pad, ref er to the pin c onfiguration and functio n descri ptions secti on of this data sheet. 07-1 7-2008 -a figure 20 . 16 - lead lead frame chip scale package [lfcsp_vq] 3 mm 3 mm body , very thin quad (cp - 16 - 3) dimensions shown in millimeters ordering guide model 1 temperature range package description package option branding adn2892acpz - 500rl7 C 40c to +95c 16 - lead lfcsp_vq, 500 pieces cp - 16 - 3 f05 adn2892acpz - rl7 C 40c to +95c 16- lead lfcsp_vq, 1,500 pieces cp -16 -3 f05 adn2892acpz -rl C 40c to +95c 16- lead lfcsp_vq, 5,000 pieces cp -16 -3 f05 eval - adn2892eb z evaluation board 1 z = rohs - compliant part.
adn2892 data sheet rev. a | page 14 of 16 notes
data sheet adn2892 rev. a | page 15 of 16 notes
adn2892 data sheet rev. a | page 16 of 16 notes ? 2005 C 2013 analog devices, in c. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d04986 - 0 - 7/13(a)

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