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1200/sec precision angular rate sensor data sheet adis16133 rev. d document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third p arties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their resp ective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2010C 2014 analog devices, inc. all rights reserved. technical support www.analog.com features d igital gyroscope system , 12 00/sec measurement range in - run bias stability, ~ 6 /hour ~11 /hour over temperature: ? 40c to +85c autonomous operation and data collection no external configuration commands required s tart - up time : 181 ms s leep mod e recovery: 4.7 ms factory calibrated sensitivity and bias c alibration temperature range : ? 40c to + 85c single serial peripheral interface, spi compatible wide bandwidth: 335 hz embedded temperature sensor programmable operation and control automatic and manual bias correction controls digital filters: bartlett fir, a verage/decimation internal sample rate: up to 2 048 sps digital i/o: data ready, alarm indicator, general - purpose alarms for condition monitoring sleep mode for power management ena ble input sy nc operation single - supply operation: 4. 85 v to 5.1 5 v 2000 g shock survivability operating temperature range: ?40c to +105c applications precision instrumentation platform stabilization and control industrial vehicle n avigation downhole instrumentation robotics general description the adis16133 i sensor? is a high performance, digital gyro - scope sensing system that operates autonomously and requires no user configuration to produ ce accurate rate sensing data. key performance advantages include low noise density, w ide b andwidth, low variation over temperature, and excellent in - run bias stability, all of which directly influence critical end perfor - mance goals for platform stabilization , navigation, roboti cs , and medical instrumentation syste ms. this sensor system combine s industry leading i mems? technology with signal conditioning that optimizes dynamic performance . the factory calibration characterizes the entire sensor signal chain for sensitivity and bias over a tempe rature range of ? 40 c to +85c. as a result, each adis16133 has its own unique correction for - mulas to produce accurate measurements upon installation . for some systems, the factory calibration eliminates the need for system level calibration and greatly simplifies it for others. the adis16133 s ample s data at rate s of up to 2 048 sps and offers an averaging/ decimation filter structure for optimizing noise /bandwidth trade - offs. the serial peripheral interface (spi) and user register structure provide easy access to configuration controls and calibrated sensor data for embedded processor platforms. the 36 mm 44 mm 14 mm package provides four holes for simple mechanical attach ment . use m2 (or 2 - 56 standard size ) machi ne screws along with a standard 24 - pin, dual row, 1 mm pitch connector to support electrical attachment to a printed circuit board (pcb) or cable system. the adis16133 provides an operating temperature range of ? 40c to +105c. functional block dia gram adis16133 calibration alarms i/o self-test user control registers spi port output data registers clock mems sensor temp sensor power management cs sclk din dout gnd vcc dio1 clkin dio2 rst controller filter 09231-001 f igure 1.
adis16133 data sheet rev. d | page 2 of 20 t able of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 timing specifications .................................................................. 4 absolute maximum ratings ............................................................ 5 esd caution .................................................................................. 5 pin configuration and function descriptions ............................. 6 typical performance characteristics ............................................. 7 basic operation ................................................................................. 8 reading se nsor data .................................................................... 8 output data registers .................................................................. 9 device configuration .................................................................. 9 user registers .................................................................................. 10 digital processing configuration ................................................. 11 calibration ....................................................................................... 12 alarms .............................................................................................. 13 system controls .............................................................................. 14 global commands ..................................................................... 14 memory managemen t ............................................................... 14 general - purpose input/output ................................................ 14 self - te st ....................................................................................... 15 power manageme nt ................................................................... 15 status ............................................................................................ 15 product identification ................................................................ 16 applications informati on .............................................................. 17 breakout board ........................................................................... 17 installation tips .......................................................................... 18 outline dimensions ....................................................................... 19 ordering guide .......................................................................... 19 revision history 2/14 rev. c to rev. d change to features section .............................................................. 1 changed conversion rate parameter to sample rate parameter, table 1 .............................................................................. 3 change to pin 2, table 5 ................................................................... 6 change to table 18 .......................................................................... 11 10/13 rev. b to rev. c deleted self - test change in output response parameter, table 1 ................................................................................................ 3 replaced adis16133/pcbz breakout b oard section with breakout board section ................................................................. 17 deleted legacy design section , fig ure 23, and figure 24; renumbered sequentially .............................................................. 17 changes to ordering guide .......................................................... 19 2/1 3 rev. a to rev. b changes to specifications section and table 1 .............................. 3 change to table 4 .............................................................................. 5 changes to table 31 ........................................................................ 15 5/12 rev. 0 to rev. a added 0x0c to 0x0f and 0x2a to 0x31 addre sses to table 14 .. 10 changes to alarm example section ............................................ 13 added adis16133/pcbz breakout board section and legacy design section ............................................................................... 17 9/10 revision 0: initial version
data sheet adis16133 rev. d | page 3 of 20 specifications t a = 2 5c, v cc = 5.0 v, angular rate = 0/s ec, dynamic range = 1200/s ec 1 g , unless otherwise noted. table 1. parameter test conditions/comments min typ max unit gyroscopes dynamic range 1200 1400 /sec initial sensitivity gyro_out register only 0.0495 0.05 0.0505 /sec/lsb repeatabil ity 1 ?40c t a +85c 1 % sensitivity temperature coefficient ?40c t a +85c 16 ppm/c nonlinearity best fit straight line 0.008 % of f s bias r epeatability 1 , 2 ?40c t a +85c, 1 1 /sec in- run bias stability +25c, smpl_prd = 0x001f 0.0017 /sec angular random walk 1 , +25c 0.75 /hr linear acceleration effect on bias 1 0.03 /sec/ g bias voltage sensitivity vcc = 4.85 v to 5.15 v 0.02 /sec/v output noise smpl_prd = 0x001f 0.27 /sec rms rate noise density f = 25 hz, smpl_prd = 0x001f 0.0122 /sec/hz rms bandwidth ?3 db 335 hz sensor resonant frequency 14.5 khz logic inputs 3 input high voltage, v ih 2.0 v input low voltage, v il 0.8 v logic 1 inp ut current, i ih v ih = 3.3 v 0.2 1 a logic 0 input current, i il v il = 0 v all pins except rst 40 60 a rst pin 80 a input capacitance, c in 10 pf digital outputs 3 output high voltage, v oh i source = 1.6 ma 2.4 v output low voltage, v ol i sink = 1.6 ma 0.4 v flash memory endurance 4 10,000 cycles data retention 4 t j = 85c 20 years functional times 5 time until data is available power - on start - up time 181 ms reset recovery time 71 ms sleep mode recovery time 4.7 ms flash memory self - test smpl_prd = 0x000f 16 ms automatic sensor self - test time smpl_prd = 0x000f 46 ms sample rate 680 2048 sps inte rnal sample rate accuracy smpl_prd = 0x001f 3 % input sync clock range smpl_prd = 0x0000 680 6 2048 hz power supply operati ng voltage range, vcc 4.85 5.0 5.15 v power supply current smpl_prd = 0x001f 88 ma sleep mode 1.4 ma 1 the r epeatability specifications represent analytical projections, which are based off of the following drift contributions and conditions: te mperature hysteresis (? 40c to +85c), electronics drift (high - temperature operating life test: +85c, 500 hours), drift from tempe rature cycling (jesd22, method a104 - c, method n, 500 cycles, ? 40c to +85c), rate random walk (10 year projection), and broadband noise . 2 bias repeatability describes a long - term behavior, over a variety of conditions. short - term repeatability is related to the in - run bias stability and noise density specifications. 3 the digital i/o signals are driven by an internal 3.3 v supply, and the inputs are 5 v tolerant. 4 jedec standard 22, method a117. endurance measured at ?40c, +25c, +85c, and +125c. 5 t hese times do not include thermal settling and internal filter response times, which may affect overall accuracy. 6 the sync input clock can function below the specified minimum value, but at reduced performance levels.
adis16133 data sheet rev. d | page 4 of 20 timing specifications t a = 25c, v cc = 5 v, unless otherwise noted. table 2. normal mode parameter description min 1 typ max unit f sclk serial clock 0.01 2.0 mhz t stall stall period between data 9 s t readrate read rate 25 s t cs chip select to clock edge 48.8 ns t dav dout valid after sclk edge 25 ns t dsu din setup time before sclk rising edge 24.4 ns t dhd din hold time after sclk rising edge 48.8 ns t sclkr , t sclkf sclk rise/fall times 5 12.5 ns t dr , t df d out rise/fall times 5 12.5 ns t sfs cs high after sclk edge 0 ns t 1 input sync positive pulse width 5 s t x input sync low time 100 s t 2 input sync to data ready output 360 s t 3 input sync period 488 s 1 guaranteed by design and character ization but not tested in production . timing diagrams cs sclk dout din 1 2 3 4 5 6 15 16 r/w a5 a6 a4 a3 a2 d2 msb db14 d1 lsb db13 db12 db10 db11 db2 lsb db1 t cs t sfs t dav t dhd t dsu 09231-002 figure 2 . spi timing and sequence cs sclk t readrate t stall 09231-003 figure 3 . stall time and data rate t 3 t x t 2 t 1 sync clock (clkin) data ready 09231-004 figure 4 . input clock timing diagram
data sheet adis16133 rev. d | page 5 of 20 absolute maximum rat ings table 3. parameter rating acceleration any axis, unpowered 2000 g any axis, powered 2000 g v cc to gnd ?0.3 v to + 7.0 v digital input voltage to gnd ?0.3 v to +5.3 v digital output voltage to gnd ?0.3 v to v cc + 0.3 v operating temperature range ?40c to +10 5c storage temperature range ?65c to + 125c 1, 2 1 extended exposure to temperatures outside t he specified temperature range of ?40c to + 10 5c can adversely affect the accuracy of the factory calibration. for best accuracy, store the parts within the specified operating range of ?40c to + 105c. 2 although the device is capable of withstanding sho rt - term exposure to 150c, long - term exposure threatens internal mechanical integrity. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. table 4 . packag e characteristics package type ja jc device weight 24- lead module ( ml - 24 -3) 15.7 c/w 1.48 c/w 31 g esd caution
adis16133 data sheet rev. d | page 6 of 20 pin configuration and function descripti ons 13 14 11 12 9 10 7 8 5 6 3 4 1 2 15 16 17 18 19 20 21 22 23 24 adis16133 top view notes 1. pins are not visible from this view. the pin assignments shown represent the mating connector assignments. 2. use samtec clm-112-02 or equivalent. 09231-005 figure 5 . mating connector pin assignments rate axis positive rotation direction + 09231-006 figure 6 . axial orientation (bottom side facing up) table 5 . pin function descriptions pin no. mnemonic type 1 description 2 clkin i clock input . 3 sclk i spi serial clock. 4 dout o spi data output. this pin c locks the output on the falling edge of sclk. 5 din i spi data input. this pin c locks the input on the rising edge of sclk. 6 cs i spi chip select. 7 dio1 i/o configurable digital input/output. 8 rst i reset. 9 dio2 i/ o configurable digital input/output. 10, 11, 12 v cc s power supply. 13, 14, 15 gnd s power ground. 1, 16 to 24 dnc n/a do not connect. 1 i is input, o is output, i/o is input/output, s is supply, and n/a is not applicable.
data sheet adis16133 rev. d | page 7 of 20 typical performance characteristics 0.100 0.010 0.001 1 10 100 1k root allan variance (/sec) tau (sec) 09231-007 vdd = 5v tempera ture = 25c +1 C1 figure 7 . gyroscope allan variance, +25c 0.100 0.010 0.001 1 10 100 1k root allan variance (/sec) integration time (sec) 09231-008 vdd = 5v tempera ture swee p ~1c/minute, 0c t o 50c +1 C1 f igure 8 . allan variance, 0c to 50c, 1c/min imum ramp rate 0.06 0.05 0.04 0.03 0.02 0.01 0 ?0.01 ?0.06 ?0.05 ?0.04 ?0.03 ?0.02 ?40 ?30 8070605040302010 0 ?10?20 output bias (/sec) temperature (c) 09231-009 figure 9 . bias vs. temperature, 0.1c/min imum ramp rate, autonull at 25c, smpl_prd = 0x001f, and dec_rate = 0x0010
adis16133 data sheet rev. d | page 8 of 20 basic operation the adis16133 is an autonomous system that requires no user initialization. as soon as it has a valid power supply, it initializes and starts sampling, processing, and loading sensor data into the output registers. dio1 pulses high after each sample cycle concludes. the spi interface enables simple integration with many embedded processor platforms, as shown in figure 10 (electrical connection diagram) and listed in table 6 (processor pin names and functions). system processor spi master adis16133 sclk cs din dout sclk ss mosi miso 5v irq dio1 vdd i/o lines are compatible with 3.3v or 5v logic levels 10 6 3 5 4 7 11 12 13 14 15 09231-010 figure 10. electrical connection diagram table 6. generic master processor pin names and functions pin name function ss slave select irq interrupt request mosi master output, slave input miso master input, slave output sclk serial clock the adis16133 spi interface supports full duplex serial com- munication (simultaneous transmit and receive) and uses the sequences shown in figure 13 for din/dout bit coding. table 7 provides a list of the most common settings that require attention to initialize a processor serial port for the adis16133 spi interface. table 7. generic master processor spi settings processor setting description master adis16133 operates as a slave sclk rate 2 mhz maximum serial clock rate spi mode 3 cpol = 1 (polarity), cpha = 1 (phase) msb-first mode bit sequence 16-bit mode shift register/data length reading sensor data a single register read requires two 16-bit spi cycles. the first cycle requests the contents of a register using the bit assignments in figure 13. the register contents follow on dout during the second sequence. figure 11 includes three single register reads in succession. in this example, the process begins with din = 0x0600 to request the contents of the gyro_out register, followed by 0x0400 to request the contents of the gyro_out2 register, and then 0x0200 to request the contents of the temp_out register. full duplex operation enables processors to use the same 16-bit spi cycle to read data from dout while requesting the next set of data on din. figure 12 provides an example of the four spi signals when reading gyro_out in a repeating pattern. note that dout starts to represent gyro_out during the second 16-bit spi cycle. din dout 0x0600 0x0400 0x0200 gyro_out gyro_out2 temp_out 09231-011 figure 11. spi read example sclk din dout cs 09231-025 din = 0000 0110 0000 0000 = 0x0600 dout = 1111 1100 0000 0001 = 0xfc18 = ?1000 lsbs ?50/sec figure 12. spi read example, second 16-bit sequence r/w r/w a6 a5 a4 a3 a2 a1 a0 dc7 dc6 dc5 dc4 dc3 dc2 dc1 dc0 d0 d1d2d3d4d5d6d7d8 d9d10 d11d12d13 d14 d15 cs sclk din dout a6 a5 d13 d14 d15 notes 1. dout bits are produced only when the previous 16-bit din sequence starts with r/w = 0. 2 . when cs is high, dout is in a three-state, high impedance mode, which allows multifunctional use of the line for other devices. 09231-013 figure 13. spi communication bit sequence
data sheet adis16133 rev. d | page 9 of 20 output data registers table 8. output data register formats register address measurement temp_out 0x02 internal temperature gyro_out2 0x04 gyroscope, lower 16 bits gyro_out 0x06 gyroscope, upper 16 bits rotation rate (gyroscope) gyro_out is the primary register for gyroscope output data and uses 16-bit twos complement format for its data. table 9 provides the numerical format for gyro_out, and table 10 provides several examples for converting digital data into /sec. table 9. gyro_out bit descriptions bits description [15:0] gyroscope data; twos complement, 0.05/sec per lsb (typical), 0/sec = 0x0000 table 10. gyro_out, twos complement format rotation rate decimal hex binary +1200/sec +24,000 0x5dc0 0101 1101 1100 0000 +0.1/sec +2 0x0002 0000 0000 0000 0010 +0.05/sec +1 0x0001 0000 0000 0000 0001 0/sec 0 0x0000 0000 0000 0000 0000 ?0.05/sec ?1 0xffff 1111 1111 1111 1111 ?0.1/sec ?2 0xfffe 1111 1111 1111 1110 ?1200/sec ?24,000 0xa240 1010 0010 0100 0000 the gyro_out2 register (see table 11) captures the bit growth associated with the decimation filter shown in figure 18, using an msb justified format. the bit growth starts with the msb (gyro_out2, bit 15) equal to the decimation rate setting in the dec_rate register, bits[4:0] (see table 18), and grows in the lsb direction as the decimation rate increases. see figure 14 for more details. table 11. gyro_out2 bit descriptions bits description [15:0] rotation rate data; resolution enhancement bits gyroscope data not used d 15 0 15 0 d = dec_rate[4:0] bit weight = 0.0125 2 d lsb = gyro_out2[16 ? d] /sec lsb gyro_out gyro_out2 09231-014 figure 14. gyroscope output format, dec_rate[4:0] > 0 internal temperature the temp_out register (see table 12) provides an internal temperature measurement that can be useful for observing relative temperature changes in the environment. table 13 provides several coding examples for converting the 16-bit twos complement number into units for temperature (c). table 12. temp_out bit descriptions bits description [15:0] temperature data; twos complement, 0.0058c per lsb (typical), 0c = 0x0000 table 13. temperature, twos complement format temperature decimal hex binary +105c +18,103 0x46b7 0100 0110 1011 0111 +0.0116c +2 0x0002 0000 0000 0000 0010 +0.0058c +1 0x0001 0000 0000 0000 0001 0c 0 0x0000 0000 0000 0000 0000 ?0.0058c ?1 0xffff 1111 1111 1111 1111 ?0.0116c ?2 0xfffe 1111 1111 1111 1110 ?40c ?6897 0xe50f 1110 0101 0000 1111 device configuration the registers listed in table 14 provide a variety of user confi- guration options. the spi provides access to these registers, one byte at a time, using the bit assignments shown in figure 13. each register has 16 bits, where bits[7:0] represent the lower address and bits[15:8] represent the upper address. figure 15 provides an example of writing 0x03 to address 0x22, which is the lower byte of the smpl_prd register (see table 16 and figure 18 for more information on the smpl_prd register). din = 1010 0010 0000 0011 = 0xa203, writes 0x03 to address 0x22 scl k din cs 09231-015 figure 15. spi sequence for setting th e decimate rate to 8 (din = 0xa203) dual memory structure writing configuration data to a control register updates its sram contents, which are volatile. after optimizing each relevant control register setting in a system, set glob_cmd[3] = 1 (din = 0xa808) to back up these settings in the nonvolatile flash memory. the flash back up process requires a valid power supply level for the entire 72 ms process time. table 14 provides a user register memory map that includes a column of flash backup information. a yes in this column indicates that a register has a mirror location in flash and, when backed up properly, automatically restores itself during startup or after a reset. figure 16 provides a diagram of the dual memory structure used to manage operation and store critical user settings. nonvolatile flash memory (no spi access) manual flash backup start-up reset volatile sram spi access 09231-016 figure 16. sram and flash memory diagram
adis16133 data sheet rev. d | page 10 of 20 u ser regi ster s table 14 . user register memory map name r/w 1 , 2 flash backup 2 address 3 default 2 register description bit function 2 flash_cnt r yes 0x00 n/a flash memory write count table 30 temp_out r no 0x02 n/a output, temperature (internal) table 12 gyro_out 2 r no 0x04 n/a output, g yroscope , l ower 16 bits table 11 gyro_out r no 0x06 n/a output, gyroscope , upper 16 bits table 9 gyro_off2 r/w yes 0x08 0x0000 gyroscope bias correction, lower 16 bits table 21 gyro_off r/w yes 0x0a 0x0000 gyroscope bias correction, upper 16 bits table 20 reserved n/a n/a 0x0c to 0x0f n/a reserved alm_mag1 r/w yes 0x 10 0x0000 alarm 1 trigger setting table 23 alm_mag2 r/w yes 0x12 0x0 000 alarm 2 trigger setting table 24 alm_smpl1 r/w yes 0x1 4 0x0000 alarm 1 sample period table 25 alm_smpl2 r/w yes 0x16 0x0000 alarm 2 sample period table 25 alm_ctrl r/w ye s 0x18 0x0 000 alarm configuration table 26 gpio_ctrl r/w yes 0x1 a 0x0000 general - purpose i/o control table 32 msc_ctrl r/w yes 0x1 c 0x0006 miscellaneous control: data ready, self - test table 31 smpl_prd r/w yes 0x1 e 0x001f internal sample period (rate) control table 16 avg_cnt r/w yes 0x20 0x0000 d igital filter control table 17 dec_rate r/w yes 0x22 0x0000 decimation rate se tting table 18 slp_ctrl w yes 0x24 0x0000 sleep mode control table 33 diag_stat r no 0x26 0x0000 system status table 34 glob_cmd w no 0x28 0x0000 system command table 29 reserved n/a n/a 0x2 a to 0x31 n/a reserved n/a lot_id1 r yes 0x32 n/a lot identification code 1 table 36 lot_id2 r yes 0x34 n/a lot identification code 2 table 36 lot_id3 r yes 0x36 n/a lot identification code 3 table 36 prod_id r yes 0x38 0x3f05 product id , binary number for 16 , 133 table 35 serial_num r yes 0x3a n/a serial number table 37 1 r means read, w means write. 2 n/a means not applicable. 3 each register contains two bytes. the address column in this table lists the address of the lower byte only; add 1 to it to calculate the address of the upper byte.
data sheet adis16133 rev. d | page 11 of 20 d igita l p rocessing configuration figure 18 provides a block diagram for the sampling and digital filter stages inside the adis16133 . table 15 provides a summary of digital processing registers for sample rate and filter control . table 15. digital p rocessing r egisters register name address description smpl_prd 0x1e sample rate control avg_cnt 0x20 digital filtering and r ange control dec_rate 0x22 decimation rate setting internal sample r ate the smpl_prd register in table 16 provides a programmable control for the internal sample rate. use the following formula to calculate the decimal numbe r for the c ode to write into this register: sps2048;1 768,32 _ ?= s s f f prd smpl the factory default setting for smpl_prd sets the internal sample rate to a rate of 1024 sps ; t he minimum setting for the smpl_prd register is 0x000f , which results in an internal sample rate of 2048 sps . table 16 . smpl_prd bit descriptions bits description (default = 0x00 1f) [15:0] clock setting bits ; sets f s in figure 18 input clock configuration set smpl_prd = 0x0000 (din = 0x9f00, then din = 0x9e00) to disable the internal clock and enable clkin as a clock input pin. digital filtering the avg_cnt register (see table 17 ) provides user controls for the lo w- pass filter. this filter contains two cascaded ave raging filters that provide a bartlett window fir filter response (see figure 17 ). for example, set avg_cnt [7 :0] = 0x04 (din = 0x a0 04) to set each stage to 16 taps. when used with the default sample rate of 1024 sps , this establis hes a ?3 db bandwidth of a pproximately 20 hz for this filter . 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 0.001 0.01 0.1 1 magnitude (db) frequency ( f / f s ) n = 2 n = 4 n = 16 n = 64 09231-017 figure 17 . bartlett window fir filter frequency response (phase delay = n samples) table 17. avg_cnt bit descriptions bits description (default = 0x0 000 ) [15:3] dont care [2:0] binary; b variable in figure 18; maximum setting = 110 (binary) = 6 (decimal) averaging/decimation filter the dec_rate register (see table 18 ) provides user control for t he final filter stage (see figure 18) , which averages and decimates the output data. for systems that value lower sample rates, this filter stage provides an opportunity to lower the sample rate while maintaining optimal bias sta bility performance. the ?3 db bandwidth of this filter stage is approximately one half the output data rate. for example, set dec_rate[7:0] = 0x04 (din = 0xa204) to reduce the sample rate by a factor of 16. when the factory default 1024 sps sample rate is used, this decimation setting reduces the output data rate to 64 sps and the sensor bandwidth to approximately 31 hz. table 18 . dec_rate bit descriptions bits description (default = 0x0000) [15:5] dont care [4:0] binary; d variab le in figure 18 ; m aximum setting = 10000 ( binary) = 16 (decimal ) mems gyro 402hz 819hz clock f s clkin n d ?3db bandwidth = 335hz b = avg_cnt[2:0] n b = 2 b n b = number of taps per stage 63? sp = smpl_prd d = dec_rate[4:0] n d = 2 d n d = number of taps n d = data rate divisor f s = 32,768 sp + 1 09231-018 figure 18 . sampling and frequency response block diagram
adis16133 data sheet rev. d | page 12 of 20 c alibration the adis16133 factory c alibration produces correction formulas for the gyroscope and programs them into the flash memory. table 19 contain s a list of user control registers that provide opportunity for user optimization after installation. figure 19 illustrates the summing function of the sensors offset correction register. table 19. registers for u ser c alibration register address description gyro_off2 0x08 gyro bias correction, lower 16 bits gyro_off 0x0a gyro bias correction, upper 16 bits glob_cmd 0x28 bias correction command mems gyro factory calibration and filtering adc gyro_out gyro_out2 gyro_off gyro_off2 09231-019 figure 19 . gyroscope bias cali bration user controls the factory calibration addresses initial and temperature d epen - dent bias errors in the gyroscopes, but some environmental conditions, such as temperature cycling and mechanical stress on the package , can cause bias shifts in mems gyroscope struc - tures. for systems that value absolute bias accuracy, there are two options for optimizing absolute bias accuracy: autonull and m anual correction. automatic bias correction set glob_cmd[0] = 1 (din = 0x a8 01) to start the automatic bias co rrection (abc) function, which uses the following internal sequence to calibrate each gyroscope for bias error: 1. w ait for a complete output data cycle to complete, which includes the entire average and decimation time in the dec_rate register . 2. read the output registers of the gyroscope . 3. multipl y the measurement by ?1 to change its polarity. 4. write the final value into the offset registers. 5. update the flash memory. the allan v ariance curve shown in figure 7 provide s a trade - off between bia s accuracy and averaging time. the dec_rate register p rovides a user control for averaging tim e when using the abc function. set dec_rate [7:0] = 0x10 (din = 0x a2 10) , which sets the decimation rate to 65,536 (2 16 ) and provides an averaging time of 64 seconds (65 , 536 1024 sps) for this function . then, set glo b_cmd[0] = 1 (din = 0x a8 01), and keep the platform stable for at least 65 seconds while the gyroscope bias data accumulates. after this completes, the adis16133 automatic ally updates the fl ash memory. the spi interface is inactive during the entire time it takes the abc function to complete. the only way to interrupt the abc function is to remove power or initiate a hardware reset using the rst pin. when using dec_rate = 0x00 10, the 1 accuracy for this correction is approximately 0.00 25 /sec for the gyroscope correction factor . for further optimization, use the manual bias correction function, with a 100 sec average for the bias estimate. see table 29 for mor e information on the glob_cmd register . manual bias correction the gyro_off and gyro_off2 registers (see table 20 and table 21 ) provide a bias adjustment function for the output of each sensor. gyro_off us es the same format as gyro_out , and gyro_off2 uses the same format as gyro_out2. table 20 . gyro_off bit descriptions bits description (default = 0x0000) [15:0] gyroscope offset correction ; t wos complement, 0.05 /sec per ls b , 0x0000 = 0/sec table 21. gyro_off2 bit descriptions bits description (default = 0x0000) [15:0] gyroscope offset correction, finer resolution ; uses the same format as gyro_out2 (s ee table 11 ) restori ng factory calibration set glob_cmd[1] = 1 (din = 0x a8 02) to execute the factory calibration restore function. the restore function resets each user calibration register to 0x0000, resets all sensor data to 0, and automatically updates the flash memory wit hin 72 ms . see table 29 for more information on glob_cmd.
data sheet adis16133 rev. d | page 13 of 20 alarms the alarm function provides monitoring for two independent conditions. tabl e 22 contains a list of registers that provide config uration and control inputs for the alarm function. table 22 . registers for alarm c onfigura tion register address description alm_mag1 0x10 alarm 1 trigger setting alm_mag2 0x12 alarm 2 trigger setting alm_smpl1 0x14 alarm 1 sample period alm_smpl2 0x16 alarm 2 sample period alm_ctrl 0x18 alarm configuration the alm_ctrl register (see table 26 ) provides data source selection (bits [15:8] ), rate - of - change enable (bits [7:6] ) , trigger polarity (bits [5:4] ), d ata source filtering (bit 3), and an alarm indicator signal (bits [2:0] ). static alarm use set the rate -of - change bits (alm_ctrl[7:6]) equal to zero for static alarm use, which compares the data source selection (alm_ctrl[15:8]) with the values in the alm_m agx registers in table 23 and table 24. the data format in these registers match es the format of the data selection in alm_ctrl[15:8] . alm_ctrl[5 :4] provide polarity settings. see table 27 for a static alarm configuration example. table 23 . alm_mag1 bit descriptions bits description (default = 0x0000) [15:0] t rigger setting ; m atches format of the alm_ctrl[11:8] selection table 24. alm_mag2 bit descriptions bits description (default = 0x0000) [15:0] t rigger setting ; m atches format of the alm_ctrl[15:12] selection dynamic alarm use set the rate - of - change bits (alm_ctrl[7:6]) equal to 1 to enable the dynamic alarm mode, which monitor s the data selection for a rate - of - change compariso n. the rate of change is represented by the magnitude in the alm_magx registers over the time represented by the number of samples setting in the alm_smplx register (see table 25 ) . see table 27 for a dynamic alarm configura - tion example. table 25 . alm_smpl1, alm_smpl2 bit descriptions bits description (default = 0x0000) [15:8] not used [7:0] b inary, number of samples (both 0x00 and 0x01 = 1) alarm r eporting diag_stat[9:8] provide error flags that indicate an alarm condition. alm_ctrl[2:0] provide controls for a hardware indicator using dio1 or dio2. table 26 . alm_ctrl bit descriptions bits description (default = 0x0000) [15:12] alarm 2 data source selection 0000 = disable 0001 = gyro_out (does not include gyro_out2) 0010 = temp_out 0011 = diag_stat [11:8] alarm 1 data source selection (same as alarm 2) [7] ra te - of - change enable for alarm 2 (1 = dynamic/ rate of change, 0 = static level) [6] rate - of - change enable for alarm 1 (1 = dynamic/ rate of change, 0 = static level) [5] trigger polarity for alarm 2 (1 specifies >alm_mag2, 0 specifies alm_mag1, 0 specifies alm_mag2 alarm 1: static; gyro_out < alm_mag1 set alarms to track filtered data dio2 = output indicator, positive polarity 0x930f alm_mag2 = 0x0fa0, ( 200/sec) 0x92a0 0x910f alm_mag1 = 0x0fa0, ( 200/sec) 0x90a0 0x9666 alm_smpl2[7:0] = 0x66 (102 samples)
adis16133 data sheet rev. d | page 14 of 20 s ystem control s the adis16133 provides a number of system l evel contr ols for managing its operation using the registers listed in table 28 . table 28 . system tool registers register name address description flash_cnt 0x00 flash write cycle counter gpio_ctrl 0x1a general - purpose i/o control msc_ctrl 0x1c self - test, calibration, data ready slp_ctrl 0x24 sleep mode control diag_stat 0x26 error flags glob_cmd 0x28 single command functions lot_id1 0x32 lot identification code 1 lot_id2 0x34 lot identification code 2 l ot_id3 0x36 lot identification code 3 prod_id 0x38 product identification serial_num 0x3a serial number g lobal c ommands the glob_cmd register (see table 29 ) provides trigger bits for several operations. write 1 to the appropriate bit in the glob_cmd register to start a function. after the function completes, the bit restores to 0. software reset set glob_cmd[7] = 1 (din = 0xa880) to reset the operation, which removes all data, initializes all registers from their flash sett ings, and starts data collection. this function provides a firmware alternative to the rst line ( s ee table 5 , p in 8). table 29 . glob_cmd bit descriptions bits description execution time 1 [15:8] not used n/a 2 [7] software reset 71 ms [6:4] not used n/a 2 [3] flash update 72 ms [2] not used n/a 2 [1] factory calibration restore 72 ms [0] automatic bias correction n/a 2 1 execution time is based on smpl_prd and dec_rate settings . this starts at the next data ready pulse, restarts the decimation cycle, and then writes to the flash 72 ms) after completing a decimation cycle. with respect to figure 18 , the decimation cycle time = n d f s . 2 n/a means not applic able. memory m anagement the data retention of the flash memory has a dependency on temperature, as shown in figure 20. the flash_cnt register (see table 30 ) provides a 16 - bit counter that helps track the number of write cycles to the nonvolatile flash memory, which helps manage the endurance rating. the flash updates every time any of the follow ing bits are set to 1: glob_cmd[ 3], glob _cmd [1] , and glob_ cmd[0] . table 30 . flash_cnt b it descriptions bits description [15:0] binary counter; number of flash updates 600 450 300 150 0 30 40 retention (years) junction temperature (c) 55 70 85 100 125 135 150 09231-113 figure 20 . flash memory retention checksum test set msc_ctrl[11] = 1 (din = 0x 9d 08 ) to perform a checksum verification of the internal program memory. this takes a sum - mation of the internal program memory and compares it with the original summation value for the same locations (from factory configuration). c heck the results in the diag_stat register (see table 34 ). diag _stat[6] equals 0 when the sum matches the correct value and it equals 1 when it does not. make sure that the power supply is within specification for the entire 20 ms that this function takes to complete. general - purpose i nput /o utput there are two general - purpose i/o lines, dio1 and dio2, which provide a number of useful functions. the msc_ctrl[2:0] bits (see table 31 ) control the data ready configuration and have the highest priority for sett ing either dio1 or dio2 (but not both) . the alm_ctrl[2:0] control bits (see table 26 ) provide the alarm indicator configuration control and have the seco nd highest priority for dio1 or dio2. when dio1 and dio2 are not in use as either data ready or alarm indicator sig nals, the gpio_ctrl register (see tabl e 32 ) provides the control and data bits for them. data ready i/o indicator the factory default setting for msc_ctrl[2:0] is 110, which con figures dio1 as a positive data ready indicator signa l. a common option for this function is msc_ctrl[2:0] = 100 (din = 0x9c04), which changes data ready to a negative polarity for processors that provide only negative triggered interrupt pins. the pulse width is between 100 s and 200 s over all conditions .
data sheet adis16133 rev. d | page 15 of 20 example i/o configuration for example, set gpio_ctrl[ 7 :0] = 0x02 (din = 0x9a02) to set dio 1 as an input and dio2 as an output. next , set gpio_ctrl[15:8] = 0x02 (din = 0x9b02) to set dio2 in a high output state. monitor dio1 by reading gpio_ctrl[ 15: 8 ] (di n = 0x1 b 00) and masking off the upper seven bits. table 31 . msc_ctrl bit descriptions bits description (default = 0x0006) [15:12] not used [11] memory test (cleared upon completion) (1 = enabled, 0 = disabled) [10] automatic self - test (cleared upon completion) (1 = enabled, 0 = disabled) [9 :8] do not use, always set this to 00 (binary) [7] disable sensor compensation (1 = disable compensation, 0 = enable compensation ) [6 :3] not used [2] data ready enable (1 = enabled, 0 = disabled) [1] data ready polarity (1 = active high, 0 = active low) [0] data ready line select (1 = dio2, 0 = dio1) table 32 . gpio_ctrl bit descriptions bits description (default = 0x0000) [15: 10 ] dont care [9] general - purpose i/o line 2 (dio2) data level [8] general - purpose i/o line 1 (dio1) data level [7:2] dont care [1] general - purpose i/o line 2 (dio2) direction control (1 = output, 0 = input) [0] general - purpose i/o line 1 (dio1) direction control (1 = out put, 0 = input) self - test the msc_ctrl bits (see table 31 ) provide a self - test function, which helps verify the mechanical integrity of the mems and signal processing circuit. when enabled, the self - test applies an electrosta tic force to the internal sensor element, which causes it to move in a manner that simulates its response to actual rotation. set msc_ctrl[10] = 1 (din = 0x9d 0 4) to run the self - test routine, which reports a pass/fail result in diag_stat[5]. msc_ctrl[ 10 ] r esets itself to 0 after completing this routine. this process takes approximately 46 ms. power management the slp_ctrl register (see table 33 ) provides two different sleep modes for system level management: normal and timed . set slp_ctrl[ 7:0 ] = 0xff (din = 0x a 4ff ) to start normal sleep mode . to awaken the device from sleep mode, use one of the following options to restore normal operation: assert cs from high to low, pulse rst low and then high again, or cycle the power. use slp_ctrl[7:0] to put the device in to sleep mode for a specified period. for example, slp_ctrl[7:0] = 0x 6 4 (din = 0x a4 64) puts the adis16133 to sleep for 50 sec. table 33 . slp_ctrl bit descriptions bits description [15:8] not used [7:0] 0xff: normal sleep mode 0x00 to 0xfe: programmable sleep time bits ; 0.5 sec/ lsb status the diag_stat register (see table 34 ) provides error flags for a number of functions. each flag uses a 1 to indicate an error con - dition and a 0 to indicate a normal condition. reading this register provides access to the status of each flag and resets all of the bits to 0 for mon itoring future operation. if the error condition remains, the error flag return s to 1 at the conclu sion of the next sample cycle. diag_stat[0] does not require a read of this register to return to 0. if the power supply voltage returns to within range, thi s flag clears automatically. the spi communication error flag in diag_stat[3] indicates that the number of sclks in a spi sequence did not equal a multiple of 16 sclks. table 34 . diag_stat bit descriptions bits description (default = 0x0000) [15:10] not used [9] alarm 2 status (1 = active, 0 = inactive) [8] alarm 1 status (1 = active, 0 = inactive) [7] not used [6] flash test, checksum flag (1 = fail, 0 = pass) [5] self - test diagnostic error flag (1 = fail, 0 = pass) [4] senso r over range (1 = overrange, 0 = normal) [3] spi communication failure (1 = fail, 0 = pass) [2] flash update failure (1 = fail, 0 = pass) [1] not used [0] power supply low, (1 = v cc < 4.75 v, 0 = v cc 4.75 v)
adis16133 data sheet rev. d | page 16 of 20 product identification the prod_id register (see table 35 ) contains 0x3 f 05 , which is the hexadecimal equivalent of 16,13 3. the lot_id1, lot_id2, and lot_id3 registers (see table 36 ) pr ovide manufacturing lot information. the serial_num register (see table 37 ) con - tains a binary number t h at represents the seri al number on the device label and is l ot specific. table 35 . prod_id bit des criptions bits description (default = 0x3f05) [15:0] product identification = 0x 3f05 table 36 . lot_id1, lot_id2 , lot_id3 bit descriptions bits description [15:0] lot identification, binary code table 37. serial_num bit descriptions bits description [15:14] not used [13:0] serial number, 1 to 9999 (0x270f)
data sheet adis16133 rev. d | page 17 of 20 applications information breakout b oard the adis16imu1/pcbz, sold separately, provides a breakout board function for the adis16133 bmlz. this interface printed circuit board (pcb) provides larger connectors than the adis16133 bmlz for simpler connection with a n spi - comp atible processor board. it also provides four tapped m2 holes for attachment of the adis16133 bmlz to the breakout board, and four holes (machine screw size m2.5 or #4) for mounting the brea kout board to a solid structure. j1 is a dual - row, 2 mm (pitch) connector that works with 1 mm ribbon cable systems. figure 21 provides the top level view of the interface board. install the adis16133 bmlz onto this board using the silk pattern as an orientation guide. figure 22 provides the pin assignments for j1 that match the adis16133 bmlz pin functions, which are listed in table 5 . the adis16133 does not require external capacitors for normal operation; therefore, the interface pcb does not use the c1 and c2 pads. 09231-200 i sensor adis16133 mounting holes figure 21 . physical diagram for the current adis16imu1/pcbz 1 rst 2 scl 3 cs 4 dout 5 dnc 6 din 7 gnd 8 gnd 9 gnd 10 vdd 11 vdd 12 vdd 13 dio1 14 dio2 15 dio3 16 dio4 j1 09231-201 figure 22 . adis16imu1/pcbz j1 pin assignments
adis16133 data sheet rev. d | page 18 of 20 installation tips use figure 23 and figure 24 as a starting point for a connector down mech anical design, where the mating connect or is soldered to a pcb. all of the evaluation tools for the adis16133 use the samtec clm - 112 - 02 series as the mating connector and assume use of two hol es for the connector alignment pins together with 24 holes for stress relief in those cases where the pin s of the adis16133 bottom out during insertion. when design ing a connector up system, use the mounting holes shown in figure 23 as a guide in designing the bulkhead mounting system , and use figure 24 as a guide in developing the mating connecto r interface on a flexible circuit or other connector system. 2x 0.560 bsc alignment holes for m a ting socket 5.00 bsc 39.60 bsc 19.800 bsc 31.200 bsc 15.600 bsc 5.00 bsc 4x 2.500 bsc 2.280 17.520 09231-022 figure 23 . suggested mounting hole locations, connector down 0.4334 [11.0] 0.0240 [0.610] 0.019685 [0.5000] (typ) 0.054 [1.37] 0.0394 [1.00] 0.0394 [1.00] 0.1800 [4.57] nonplated thru hole 2 0.022 dia (typ) 0.022 dia thru hole (typ) nonplated thru hole 09231-023 figure 24 . suggested layout and mechanical design for the mating connector
data sheet adis16133 re v. d | page 19 of 20 outline dimensions 01 09 08-a top view end view 35.854 35.600 35.346 31.350 31.200 31.050 15.700 15.600 15.500 44.25 4 44.000 43.746 39.7 50 39.600 39.450 1.00 bsc (lead pitch) 0.30 bsc sq (pin size) 2.200 typ 2.200 typ 2.400 thru hole (4 places) 5.50 bsc 3.27 3.07 2.87 14.054 13.80 0 13.546 19.900 19.80 0 19.700 17.6 70 17.520 17.370 figure 25 . 24 - lead module w ith connector interface (ml- 24 -3) dimensions shown in millimeters ordering guide model 1 temperature rang e package description package option adis16133 bmlz ?40c to +105c 24- lead module with connector interface ml -24-3 1 z = rohs compliant part.
adis16133 data sheet rev. d | page 20 of 20 notes ? 2010 C 2014 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d09231 -0- 2/14(d)

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